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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * drivers/pcmcia/m32r_cfc.c | |
3 | * | |
4 | * Device driver for the CFC functionality of M32R. | |
5 | * | |
6 | * Copyright (c) 2001, 2002, 2003, 2004 | |
7 | * Hiroyuki Kondo, Naoto Sugai, Hayato Fujiwara | |
8 | */ | |
9 | ||
10 | #include <linux/module.h> | |
11 | #include <linux/moduleparam.h> | |
12 | #include <linux/init.h> | |
1da177e4 LT |
13 | #include <linux/types.h> |
14 | #include <linux/fcntl.h> | |
15 | #include <linux/string.h> | |
16 | #include <linux/kernel.h> | |
17 | #include <linux/errno.h> | |
18 | #include <linux/timer.h> | |
1da177e4 LT |
19 | #include <linux/ioport.h> |
20 | #include <linux/delay.h> | |
21 | #include <linux/workqueue.h> | |
22 | #include <linux/interrupt.h> | |
d052d1be | 23 | #include <linux/platform_device.h> |
934bb7f8 | 24 | #include <linux/bitops.h> |
1da177e4 LT |
25 | #include <asm/irq.h> |
26 | #include <asm/io.h> | |
1da177e4 LT |
27 | #include <asm/system.h> |
28 | ||
1da177e4 LT |
29 | #include <pcmcia/cs_types.h> |
30 | #include <pcmcia/ss.h> | |
31 | #include <pcmcia/cs.h> | |
32 | ||
33 | #undef MAX_IO_WIN /* FIXME */ | |
34 | #define MAX_IO_WIN 1 | |
35 | #undef MAX_WIN /* FIXME */ | |
36 | #define MAX_WIN 1 | |
37 | ||
38 | #include "m32r_cfc.h" | |
39 | ||
1da177e4 LT |
40 | /* Poll status interval -- 0 means default to interrupt */ |
41 | static int poll_interval = 0; | |
42 | ||
43 | typedef enum pcc_space { as_none = 0, as_comm, as_attr, as_io } pcc_as_t; | |
44 | ||
45 | typedef struct pcc_socket { | |
46 | u_short type, flags; | |
47 | struct pcmcia_socket socket; | |
48 | unsigned int number; | |
906da809 | 49 | unsigned int ioaddr; |
1da177e4 LT |
50 | u_long mapaddr; |
51 | u_long base; /* PCC register base */ | |
52 | u_char cs_irq1, cs_irq2, intr; | |
53 | pccard_io_map io_map[MAX_IO_WIN]; | |
54 | pccard_mem_map mem_map[MAX_WIN]; | |
55 | u_char io_win; | |
56 | u_char mem_win; | |
57 | pcc_as_t current_space; | |
58 | u_char last_iodbex; | |
59 | #ifdef CONFIG_PROC_FS | |
60 | struct proc_dir_entry *proc; | |
61 | #endif | |
62 | } pcc_socket_t; | |
63 | ||
64 | static int pcc_sockets = 0; | |
65 | static pcc_socket_t socket[M32R_MAX_PCC] = { | |
66 | { 0, }, /* ... */ | |
67 | }; | |
68 | ||
69 | /*====================================================================*/ | |
70 | ||
71 | static unsigned int pcc_get(u_short, unsigned int); | |
72 | static void pcc_set(u_short, unsigned int , unsigned int ); | |
73 | ||
74 | static DEFINE_SPINLOCK(pcc_lock); | |
75 | ||
76 | #if !defined(CONFIG_PLAT_USRV) | |
77 | static inline u_long pcc_port2addr(unsigned long port, int size) { | |
78 | u_long addr = 0; | |
79 | u_long odd; | |
80 | ||
81 | if (size == 1) { /* byte access */ | |
82 | odd = (port&1) << 11; | |
83 | port -= port & 1; | |
84 | addr = CFC_IO_MAPBASE_BYTE - CFC_IOPORT_BASE + odd + port; | |
85 | } else if (size == 2) | |
86 | addr = CFC_IO_MAPBASE_WORD - CFC_IOPORT_BASE + port; | |
87 | ||
88 | return addr; | |
89 | } | |
90 | #else /* CONFIG_PLAT_USRV */ | |
91 | static inline u_long pcc_port2addr(unsigned long port, int size) { | |
92 | u_long odd; | |
93 | u_long addr = ((port - CFC_IOPORT_BASE) & 0xf000) << 8; | |
94 | ||
95 | if (size == 1) { /* byte access */ | |
96 | odd = port & 1; | |
97 | port -= odd; | |
98 | odd <<= 11; | |
99 | addr = (addr | CFC_IO_MAPBASE_BYTE) + odd + (port & 0xfff); | |
100 | } else if (size == 2) /* word access */ | |
101 | addr = (addr | CFC_IO_MAPBASE_WORD) + (port & 0xfff); | |
102 | ||
103 | return addr; | |
104 | } | |
105 | #endif /* CONFIG_PLAT_USRV */ | |
106 | ||
107 | void pcc_ioread_byte(int sock, unsigned long port, void *buf, size_t size, | |
108 | size_t nmemb, int flag) | |
109 | { | |
110 | u_long addr; | |
111 | unsigned char *bp = (unsigned char *)buf; | |
112 | unsigned long flags; | |
113 | ||
c9f50ddd | 114 | pr_debug("m32r_cfc: pcc_ioread_byte: sock=%d, port=%#lx, buf=%p, " |
1da177e4 LT |
115 | "size=%u, nmemb=%d, flag=%d\n", |
116 | sock, port, buf, size, nmemb, flag); | |
117 | ||
118 | addr = pcc_port2addr(port, 1); | |
119 | if (!addr) { | |
120 | printk("m32r_cfc:ioread_byte null port :%#lx\n",port); | |
121 | return; | |
122 | } | |
c9f50ddd | 123 | pr_debug("m32r_cfc: pcc_ioread_byte: addr=%#lx\n", addr); |
1da177e4 LT |
124 | |
125 | spin_lock_irqsave(&pcc_lock, flags); | |
126 | /* read Byte */ | |
127 | while (nmemb--) | |
128 | *bp++ = readb(addr); | |
129 | spin_unlock_irqrestore(&pcc_lock, flags); | |
130 | } | |
131 | ||
132 | void pcc_ioread_word(int sock, unsigned long port, void *buf, size_t size, | |
133 | size_t nmemb, int flag) | |
134 | { | |
135 | u_long addr; | |
136 | unsigned short *bp = (unsigned short *)buf; | |
137 | unsigned long flags; | |
138 | ||
c9f50ddd | 139 | pr_debug("m32r_cfc: pcc_ioread_word: sock=%d, port=%#lx, " |
1da177e4 LT |
140 | "buf=%p, size=%u, nmemb=%d, flag=%d\n", |
141 | sock, port, buf, size, nmemb, flag); | |
142 | ||
143 | if (size != 2) | |
144 | printk("m32r_cfc: ioread_word :illigal size %u : %#lx\n", size, | |
145 | port); | |
146 | if (size == 9) | |
147 | printk("m32r_cfc: ioread_word :insw \n"); | |
148 | ||
149 | addr = pcc_port2addr(port, 2); | |
150 | if (!addr) { | |
151 | printk("m32r_cfc:ioread_word null port :%#lx\n",port); | |
152 | return; | |
153 | } | |
c9f50ddd | 154 | pr_debug("m32r_cfc: pcc_ioread_word: addr=%#lx\n", addr); |
1da177e4 LT |
155 | |
156 | spin_lock_irqsave(&pcc_lock, flags); | |
157 | /* read Word */ | |
158 | while (nmemb--) | |
159 | *bp++ = readw(addr); | |
160 | spin_unlock_irqrestore(&pcc_lock, flags); | |
161 | } | |
162 | ||
163 | void pcc_iowrite_byte(int sock, unsigned long port, void *buf, size_t size, | |
164 | size_t nmemb, int flag) | |
165 | { | |
166 | u_long addr; | |
167 | unsigned char *bp = (unsigned char *)buf; | |
168 | unsigned long flags; | |
169 | ||
c9f50ddd | 170 | pr_debug("m32r_cfc: pcc_iowrite_byte: sock=%d, port=%#lx, " |
1da177e4 LT |
171 | "buf=%p, size=%u, nmemb=%d, flag=%d\n", |
172 | sock, port, buf, size, nmemb, flag); | |
173 | ||
174 | /* write Byte */ | |
175 | addr = pcc_port2addr(port, 1); | |
176 | if (!addr) { | |
177 | printk("m32r_cfc:iowrite_byte null port:%#lx\n",port); | |
178 | return; | |
179 | } | |
c9f50ddd | 180 | pr_debug("m32r_cfc: pcc_iowrite_byte: addr=%#lx\n", addr); |
1da177e4 LT |
181 | |
182 | spin_lock_irqsave(&pcc_lock, flags); | |
183 | while (nmemb--) | |
184 | writeb(*bp++, addr); | |
185 | spin_unlock_irqrestore(&pcc_lock, flags); | |
186 | } | |
187 | ||
188 | void pcc_iowrite_word(int sock, unsigned long port, void *buf, size_t size, | |
189 | size_t nmemb, int flag) | |
190 | { | |
191 | u_long addr; | |
192 | unsigned short *bp = (unsigned short *)buf; | |
193 | unsigned long flags; | |
194 | ||
c9f50ddd | 195 | pr_debug("m32r_cfc: pcc_iowrite_word: sock=%d, port=%#lx, " |
1da177e4 LT |
196 | "buf=%p, size=%u, nmemb=%d, flag=%d\n", |
197 | sock, port, buf, size, nmemb, flag); | |
198 | ||
199 | if(size != 2) | |
200 | printk("m32r_cfc: iowrite_word :illigal size %u : %#lx\n", | |
201 | size, port); | |
202 | if(size == 9) | |
203 | printk("m32r_cfc: iowrite_word :outsw \n"); | |
204 | ||
205 | addr = pcc_port2addr(port, 2); | |
206 | if (!addr) { | |
207 | printk("m32r_cfc:iowrite_word null addr :%#lx\n",port); | |
208 | return; | |
209 | } | |
210 | #if 1 | |
211 | if (addr & 1) { | |
212 | printk("m32r_cfc:iowrite_word port addr (%#lx):%#lx\n", port, | |
213 | addr); | |
214 | return; | |
215 | } | |
216 | #endif | |
c9f50ddd | 217 | pr_debug("m32r_cfc: pcc_iowrite_word: addr=%#lx\n", addr); |
1da177e4 LT |
218 | |
219 | spin_lock_irqsave(&pcc_lock, flags); | |
220 | while (nmemb--) | |
221 | writew(*bp++, addr); | |
222 | spin_unlock_irqrestore(&pcc_lock, flags); | |
223 | } | |
224 | ||
225 | /*====================================================================*/ | |
226 | ||
227 | #define IS_REGISTERED 0x2000 | |
228 | #define IS_ALIVE 0x8000 | |
229 | ||
230 | typedef struct pcc_t { | |
231 | char *name; | |
232 | u_short flags; | |
233 | } pcc_t; | |
234 | ||
235 | static pcc_t pcc[] = { | |
236 | #if !defined(CONFIG_PLAT_USRV) | |
237 | { "m32r_cfc", 0 }, { "", 0 }, | |
238 | #else /* CONFIG_PLAT_USRV */ | |
239 | { "m32r_cfc", 0 }, { "m32r_cfc", 0 }, { "m32r_cfc", 0 }, | |
240 | { "m32r_cfc", 0 }, { "m32r_cfc", 0 }, { "", 0 }, | |
241 | #endif /* CONFIG_PLAT_USRV */ | |
242 | }; | |
243 | ||
7d12e780 | 244 | static irqreturn_t pcc_interrupt(int, void *); |
1da177e4 LT |
245 | |
246 | /*====================================================================*/ | |
247 | ||
248 | static struct timer_list poll_timer; | |
249 | ||
250 | static unsigned int pcc_get(u_short sock, unsigned int reg) | |
251 | { | |
252 | unsigned int val = inw(reg); | |
c9f50ddd | 253 | pr_debug("m32r_cfc: pcc_get: reg(0x%08x)=0x%04x\n", reg, val); |
1da177e4 LT |
254 | return val; |
255 | } | |
256 | ||
257 | ||
258 | static void pcc_set(u_short sock, unsigned int reg, unsigned int data) | |
259 | { | |
260 | outw(data, reg); | |
c9f50ddd | 261 | pr_debug("m32r_cfc: pcc_set: reg(0x%08x)=0x%04x\n", reg, data); |
1da177e4 LT |
262 | } |
263 | ||
264 | /*====================================================================== | |
265 | ||
266 | See if a card is present, powered up, in IO mode, and already | |
267 | bound to a (non PC Card) Linux driver. We leave these alone. | |
268 | ||
269 | We make an exception for cards that seem to be serial devices. | |
270 | ||
271 | ======================================================================*/ | |
272 | ||
273 | static int __init is_alive(u_short sock) | |
274 | { | |
275 | unsigned int stat; | |
276 | ||
c9f50ddd | 277 | pr_debug("m32r_cfc: is_alive:\n"); |
1da177e4 LT |
278 | |
279 | printk("CF: "); | |
280 | stat = pcc_get(sock, (unsigned int)PLD_CFSTS); | |
281 | if (!stat) | |
282 | printk("No "); | |
283 | printk("Card is detected at socket %d : stat = 0x%08x\n", sock, stat); | |
c9f50ddd | 284 | pr_debug("m32r_cfc: is_alive: sock stat is 0x%04x\n", stat); |
1da177e4 LT |
285 | |
286 | return 0; | |
287 | } | |
288 | ||
906da809 OJ |
289 | static void add_pcc_socket(ulong base, int irq, ulong mapaddr, |
290 | unsigned int ioaddr) | |
1da177e4 LT |
291 | { |
292 | pcc_socket_t *t = &socket[pcc_sockets]; | |
293 | ||
c9f50ddd | 294 | pr_debug("m32r_cfc: add_pcc_socket: base=%#lx, irq=%d, " |
1da177e4 LT |
295 | "mapaddr=%#lx, ioaddr=%08x\n", |
296 | base, irq, mapaddr, ioaddr); | |
297 | ||
298 | /* add sockets */ | |
299 | t->ioaddr = ioaddr; | |
300 | t->mapaddr = mapaddr; | |
301 | #if !defined(CONFIG_PLAT_USRV) | |
302 | t->base = 0; | |
303 | t->flags = 0; | |
304 | t->cs_irq1 = irq; // insert irq | |
305 | t->cs_irq2 = irq + 1; // eject irq | |
306 | #else /* CONFIG_PLAT_USRV */ | |
307 | t->base = base; | |
308 | t->flags = 0; | |
309 | t->cs_irq1 = 0; // insert irq | |
310 | t->cs_irq2 = 0; // eject irq | |
311 | #endif /* CONFIG_PLAT_USRV */ | |
312 | ||
313 | if (is_alive(pcc_sockets)) | |
314 | t->flags |= IS_ALIVE; | |
315 | ||
316 | /* add pcc */ | |
317 | #if !defined(CONFIG_PLAT_USRV) | |
318 | request_region((unsigned int)PLD_CFRSTCR, 0x20, "m32r_cfc"); | |
319 | #else /* CONFIG_PLAT_USRV */ | |
320 | { | |
321 | unsigned int reg_base; | |
322 | ||
323 | reg_base = (unsigned int)PLD_CFRSTCR; | |
324 | reg_base |= pcc_sockets << 8; | |
325 | request_region(reg_base, 0x20, "m32r_cfc"); | |
326 | } | |
327 | #endif /* CONFIG_PLAT_USRV */ | |
328 | printk(KERN_INFO " %s ", pcc[pcc_sockets].name); | |
329 | printk("pcc at 0x%08lx\n", t->base); | |
330 | ||
331 | /* Update socket interrupt information, capabilities */ | |
332 | t->socket.features |= (SS_CAP_PCCARD | SS_CAP_STATIC_MAP); | |
333 | t->socket.map_size = M32R_PCC_MAPSIZE; | |
334 | t->socket.io_offset = ioaddr; /* use for io access offset */ | |
335 | t->socket.irq_mask = 0; | |
336 | #if !defined(CONFIG_PLAT_USRV) | |
337 | t->socket.pci_irq = PLD_IRQ_CFIREQ ; /* card interrupt */ | |
338 | #else /* CONFIG_PLAT_USRV */ | |
339 | t->socket.pci_irq = PLD_IRQ_CF0 + pcc_sockets; | |
340 | #endif /* CONFIG_PLAT_USRV */ | |
341 | ||
342 | #ifndef CONFIG_PLAT_USRV | |
343 | /* insert interrupt */ | |
344 | request_irq(irq, pcc_interrupt, 0, "m32r_cfc", pcc_interrupt); | |
ad09d583 | 345 | #ifndef CONFIG_PLAT_MAPPI3 |
1da177e4 LT |
346 | /* eject interrupt */ |
347 | request_irq(irq+1, pcc_interrupt, 0, "m32r_cfc", pcc_interrupt); | |
ad09d583 | 348 | #endif |
c9f50ddd | 349 | pr_debug("m32r_cfc: enable CFMSK, RDYSEL\n"); |
1da177e4 LT |
350 | pcc_set(pcc_sockets, (unsigned int)PLD_CFIMASK, 0x01); |
351 | #endif /* CONFIG_PLAT_USRV */ | |
352 | #if defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_USRV) || defined(CONFIG_PLAT_OPSPUT) | |
353 | pcc_set(pcc_sockets, (unsigned int)PLD_CFCR1, 0x0200); | |
354 | #endif | |
355 | pcc_sockets++; | |
356 | ||
357 | return; | |
358 | } | |
359 | ||
360 | ||
361 | /*====================================================================*/ | |
362 | ||
7d12e780 | 363 | static irqreturn_t pcc_interrupt(int irq, void *dev) |
1da177e4 LT |
364 | { |
365 | int i; | |
366 | u_int events = 0; | |
367 | int handled = 0; | |
368 | ||
c9f50ddd | 369 | pr_debug("m32r_cfc: pcc_interrupt: irq=%d, dev=%p\n", irq, dev); |
1da177e4 LT |
370 | for (i = 0; i < pcc_sockets; i++) { |
371 | if (socket[i].cs_irq1 != irq && socket[i].cs_irq2 != irq) | |
372 | continue; | |
373 | ||
374 | handled = 1; | |
c9f50ddd | 375 | pr_debug("m32r_cfc: pcc_interrupt: socket %d irq 0x%02x ", |
1da177e4 LT |
376 | i, irq); |
377 | events |= SS_DETECT; /* insert or eject */ | |
378 | if (events) | |
379 | pcmcia_parse_events(&socket[i].socket, events); | |
380 | } | |
c9f50ddd | 381 | pr_debug("m32r_cfc: pcc_interrupt: done\n"); |
1da177e4 LT |
382 | |
383 | return IRQ_RETVAL(handled); | |
384 | } /* pcc_interrupt */ | |
385 | ||
386 | static void pcc_interrupt_wrapper(u_long data) | |
387 | { | |
c9f50ddd | 388 | pr_debug("m32r_cfc: pcc_interrupt_wrapper:\n"); |
1dd997f8 | 389 | pcc_interrupt(0, NULL); |
1da177e4 LT |
390 | init_timer(&poll_timer); |
391 | poll_timer.expires = jiffies + poll_interval; | |
392 | add_timer(&poll_timer); | |
393 | } | |
394 | ||
395 | /*====================================================================*/ | |
396 | ||
397 | static int _pcc_get_status(u_short sock, u_int *value) | |
398 | { | |
399 | u_int status; | |
400 | ||
c9f50ddd | 401 | pr_debug("m32r_cfc: _pcc_get_status:\n"); |
1da177e4 LT |
402 | status = pcc_get(sock, (unsigned int)PLD_CFSTS); |
403 | *value = (status) ? SS_DETECT : 0; | |
c9f50ddd | 404 | pr_debug("m32r_cfc: _pcc_get_status: status=0x%08x\n", status); |
1da177e4 LT |
405 | |
406 | #if defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_USRV) || defined(CONFIG_PLAT_OPSPUT) | |
407 | if ( status ) { | |
408 | /* enable CF power */ | |
409 | status = inw((unsigned int)PLD_CPCR); | |
410 | if (!(status & PLD_CPCR_CF)) { | |
c9f50ddd | 411 | pr_debug("m32r_cfc: _pcc_get_status: " |
1da177e4 LT |
412 | "power on (CPCR=0x%08x)\n", status); |
413 | status |= PLD_CPCR_CF; | |
414 | outw(status, (unsigned int)PLD_CPCR); | |
415 | udelay(100); | |
416 | } | |
417 | *value |= SS_POWERON; | |
418 | ||
419 | pcc_set(sock, (unsigned int)PLD_CFBUFCR,0);/* enable buffer */ | |
420 | udelay(100); | |
421 | ||
422 | *value |= SS_READY; /* always ready */ | |
423 | *value |= SS_3VCARD; | |
424 | } else { | |
425 | /* disable CF power */ | |
426 | status = inw((unsigned int)PLD_CPCR); | |
427 | status &= ~PLD_CPCR_CF; | |
428 | outw(status, (unsigned int)PLD_CPCR); | |
429 | udelay(100); | |
c9f50ddd | 430 | pr_debug("m32r_cfc: _pcc_get_status: " |
1da177e4 LT |
431 | "power off (CPCR=0x%08x)\n", status); |
432 | } | |
934bb7f8 | 433 | #elif defined(CONFIG_PLAT_MAPPI2) || defined(CONFIG_PLAT_MAPPI3) |
1da177e4 LT |
434 | if ( status ) { |
435 | status = pcc_get(sock, (unsigned int)PLD_CPCR); | |
436 | if (status == 0) { /* power off */ | |
437 | pcc_set(sock, (unsigned int)PLD_CPCR, 1); | |
438 | pcc_set(sock, (unsigned int)PLD_CFBUFCR,0); /* force buffer off for ZA-36 */ | |
439 | udelay(50); | |
440 | } | |
934bb7f8 HT |
441 | *value |= SS_POWERON; |
442 | ||
443 | pcc_set(sock, (unsigned int)PLD_CFBUFCR,0); | |
444 | udelay(50); | |
445 | pcc_set(sock, (unsigned int)PLD_CFRSTCR, 0x0101); | |
446 | udelay(25); /* for IDE reset */ | |
447 | pcc_set(sock, (unsigned int)PLD_CFRSTCR, 0x0100); | |
448 | mdelay(2); /* for IDE reset */ | |
449 | ||
450 | *value |= SS_READY; | |
451 | *value |= SS_3VCARD; | |
452 | } else { | |
453 | /* disable CF power */ | |
454 | pcc_set(sock, (unsigned int)PLD_CPCR, 0); | |
455 | udelay(100); | |
c9f50ddd | 456 | pr_debug("m32r_cfc: _pcc_get_status: " |
934bb7f8 | 457 | "power off (CPCR=0x%08x)\n", status); |
1da177e4 LT |
458 | } |
459 | #else | |
460 | #error no platform configuration | |
461 | #endif | |
c9f50ddd | 462 | pr_debug("m32r_cfc: _pcc_get_status: GetStatus(%d) = %#4.4x\n", |
1da177e4 LT |
463 | sock, *value); |
464 | return 0; | |
465 | } /* _get_status */ | |
466 | ||
467 | /*====================================================================*/ | |
468 | ||
1da177e4 LT |
469 | static int _pcc_set_socket(u_short sock, socket_state_t *state) |
470 | { | |
c9f50ddd | 471 | pr_debug("m32r_cfc: SetSocket(%d, flags %#3.3x, Vcc %d, Vpp %d, " |
1da177e4 LT |
472 | "io_irq %d, csc_mask %#2.2x)\n", sock, state->flags, |
473 | state->Vcc, state->Vpp, state->io_irq, state->csc_mask); | |
474 | ||
934bb7f8 | 475 | #if defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_USRV) || defined(CONFIG_PLAT_OPSPUT) || defined(CONFIG_PLAT_MAPPI2) || defined(CONFIG_PLAT_MAPPI3) |
1da177e4 LT |
476 | if (state->Vcc) { |
477 | if ((state->Vcc != 50) && (state->Vcc != 33)) | |
478 | return -EINVAL; | |
479 | /* accept 5V and 3.3V */ | |
480 | } | |
1da177e4 | 481 | #endif |
1da177e4 | 482 | if (state->flags & SS_RESET) { |
c9f50ddd | 483 | pr_debug(":RESET\n"); |
1da177e4 LT |
484 | pcc_set(sock,(unsigned int)PLD_CFRSTCR,0x101); |
485 | }else{ | |
486 | pcc_set(sock,(unsigned int)PLD_CFRSTCR,0x100); | |
487 | } | |
488 | if (state->flags & SS_OUTPUT_ENA){ | |
c9f50ddd | 489 | pr_debug(":OUTPUT_ENA\n"); |
1da177e4 LT |
490 | /* bit clear */ |
491 | pcc_set(sock,(unsigned int)PLD_CFBUFCR,0); | |
492 | } else { | |
493 | pcc_set(sock,(unsigned int)PLD_CFBUFCR,1); | |
494 | } | |
495 | ||
1da177e4 | 496 | if(state->flags & SS_IOCARD){ |
c9f50ddd | 497 | pr_debug(":IOCARD"); |
1da177e4 LT |
498 | } |
499 | if (state->flags & SS_PWR_AUTO) { | |
c9f50ddd | 500 | pr_debug(":PWR_AUTO"); |
1da177e4 LT |
501 | } |
502 | if (state->csc_mask & SS_DETECT) | |
c9f50ddd | 503 | pr_debug(":csc-SS_DETECT"); |
1da177e4 LT |
504 | if (state->flags & SS_IOCARD) { |
505 | if (state->csc_mask & SS_STSCHG) | |
c9f50ddd | 506 | pr_debug(":STSCHG"); |
1da177e4 LT |
507 | } else { |
508 | if (state->csc_mask & SS_BATDEAD) | |
c9f50ddd | 509 | pr_debug(":BATDEAD"); |
1da177e4 | 510 | if (state->csc_mask & SS_BATWARN) |
c9f50ddd | 511 | pr_debug(":BATWARN"); |
1da177e4 | 512 | if (state->csc_mask & SS_READY) |
c9f50ddd | 513 | pr_debug(":READY"); |
1da177e4 | 514 | } |
c9f50ddd | 515 | pr_debug("\n"); |
1da177e4 LT |
516 | return 0; |
517 | } /* _set_socket */ | |
518 | ||
519 | /*====================================================================*/ | |
520 | ||
521 | static int _pcc_set_io_map(u_short sock, struct pccard_io_map *io) | |
522 | { | |
523 | u_char map; | |
524 | ||
c9f50ddd | 525 | pr_debug("m32r_cfc: SetIOMap(%d, %d, %#2.2x, %d ns, " |
5f784336 WS |
526 | "%#llx-%#llx)\n", sock, io->map, io->flags, |
527 | io->speed, (unsigned long long)io->start, | |
528 | (unsigned long long)io->stop); | |
1da177e4 LT |
529 | map = io->map; |
530 | ||
531 | return 0; | |
532 | } /* _set_io_map */ | |
533 | ||
534 | /*====================================================================*/ | |
535 | ||
536 | static int _pcc_set_mem_map(u_short sock, struct pccard_mem_map *mem) | |
537 | { | |
538 | ||
539 | u_char map = mem->map; | |
540 | u_long addr; | |
541 | pcc_socket_t *t = &socket[sock]; | |
542 | ||
c9f50ddd | 543 | pr_debug("m32r_cfc: SetMemMap(%d, %d, %#2.2x, %d ns, " |
5f784336 WS |
544 | "%#llx, %#x)\n", sock, map, mem->flags, |
545 | mem->speed, (unsigned long long)mem->static_start, | |
546 | mem->card_start); | |
1da177e4 LT |
547 | |
548 | /* | |
549 | * sanity check | |
550 | */ | |
551 | if ((map > MAX_WIN) || (mem->card_start > 0x3ffffff)){ | |
552 | return -EINVAL; | |
553 | } | |
554 | ||
555 | /* | |
556 | * de-activate | |
557 | */ | |
558 | if ((mem->flags & MAP_ACTIVE) == 0) { | |
559 | t->current_space = as_none; | |
560 | return 0; | |
561 | } | |
562 | ||
563 | /* | |
564 | * Set mode | |
565 | */ | |
566 | if (mem->flags & MAP_ATTRIB) { | |
567 | t->current_space = as_attr; | |
568 | } else { | |
569 | t->current_space = as_comm; | |
570 | } | |
571 | ||
572 | /* | |
573 | * Set address | |
574 | */ | |
575 | addr = t->mapaddr + (mem->card_start & M32R_PCC_MAPMASK); | |
576 | mem->static_start = addr + mem->card_start; | |
577 | ||
578 | return 0; | |
579 | ||
580 | } /* _set_mem_map */ | |
581 | ||
582 | #if 0 /* driver model ordering issue */ | |
583 | /*====================================================================== | |
584 | ||
585 | Routines for accessing socket information and register dumps via | |
586 | /proc/bus/pccard/... | |
587 | ||
588 | ======================================================================*/ | |
589 | ||
590 | static ssize_t show_info(struct class_device *class_dev, char *buf) | |
591 | { | |
592 | pcc_socket_t *s = container_of(class_dev, struct pcc_socket, | |
593 | socket.dev); | |
594 | ||
595 | return sprintf(buf, "type: %s\nbase addr: 0x%08lx\n", | |
596 | pcc[s->type].name, s->base); | |
597 | } | |
598 | ||
599 | static ssize_t show_exca(struct class_device *class_dev, char *buf) | |
600 | { | |
601 | /* FIXME */ | |
602 | ||
603 | return 0; | |
604 | } | |
605 | ||
606 | static CLASS_DEVICE_ATTR(info, S_IRUGO, show_info, NULL); | |
607 | static CLASS_DEVICE_ATTR(exca, S_IRUGO, show_exca, NULL); | |
608 | #endif | |
609 | ||
610 | /*====================================================================*/ | |
611 | ||
612 | /* this is horribly ugly... proper locking needs to be done here at | |
613 | * some time... */ | |
614 | #define LOCKED(x) do { \ | |
615 | int retval; \ | |
616 | unsigned long flags; \ | |
617 | spin_lock_irqsave(&pcc_lock, flags); \ | |
618 | retval = x; \ | |
619 | spin_unlock_irqrestore(&pcc_lock, flags); \ | |
620 | return retval; \ | |
621 | } while (0) | |
622 | ||
623 | ||
624 | static int pcc_get_status(struct pcmcia_socket *s, u_int *value) | |
625 | { | |
626 | unsigned int sock = container_of(s, struct pcc_socket, socket)->number; | |
627 | ||
628 | if (socket[sock].flags & IS_ALIVE) { | |
c9f50ddd | 629 | dev_dbg(&s->dev, "pcc_get_status: sock(%d) -EINVAL\n", sock); |
1da177e4 LT |
630 | *value = 0; |
631 | return -EINVAL; | |
632 | } | |
c9f50ddd | 633 | dev_dbg(&s->dev, "pcc_get_status: sock(%d)\n", sock); |
1da177e4 LT |
634 | LOCKED(_pcc_get_status(sock, value)); |
635 | } | |
636 | ||
1da177e4 LT |
637 | static int pcc_set_socket(struct pcmcia_socket *s, socket_state_t *state) |
638 | { | |
639 | unsigned int sock = container_of(s, struct pcc_socket, socket)->number; | |
640 | ||
641 | if (socket[sock].flags & IS_ALIVE) { | |
c9f50ddd | 642 | dev_dbg(&s->dev, "pcc_set_socket: sock(%d) -EINVAL\n", sock); |
1da177e4 LT |
643 | return -EINVAL; |
644 | } | |
c9f50ddd | 645 | dev_dbg(&s->dev, "pcc_set_socket: sock(%d)\n", sock); |
1da177e4 LT |
646 | LOCKED(_pcc_set_socket(sock, state)); |
647 | } | |
648 | ||
649 | static int pcc_set_io_map(struct pcmcia_socket *s, struct pccard_io_map *io) | |
650 | { | |
651 | unsigned int sock = container_of(s, struct pcc_socket, socket)->number; | |
652 | ||
653 | if (socket[sock].flags & IS_ALIVE) { | |
c9f50ddd | 654 | dev_dbg(&s->dev, "pcc_set_io_map: sock(%d) -EINVAL\n", sock); |
1da177e4 LT |
655 | return -EINVAL; |
656 | } | |
c9f50ddd | 657 | dev_dbg(&s->dev, "pcc_set_io_map: sock(%d)\n", sock); |
1da177e4 LT |
658 | LOCKED(_pcc_set_io_map(sock, io)); |
659 | } | |
660 | ||
661 | static int pcc_set_mem_map(struct pcmcia_socket *s, struct pccard_mem_map *mem) | |
662 | { | |
663 | unsigned int sock = container_of(s, struct pcc_socket, socket)->number; | |
664 | ||
665 | if (socket[sock].flags & IS_ALIVE) { | |
c9f50ddd | 666 | dev_dbg(&s->dev, "pcc_set_mem_map: sock(%d) -EINVAL\n", sock); |
1da177e4 LT |
667 | return -EINVAL; |
668 | } | |
c9f50ddd | 669 | dev_dbg(&s->dev, "pcc_set_mem_map: sock(%d)\n", sock); |
1da177e4 LT |
670 | LOCKED(_pcc_set_mem_map(sock, mem)); |
671 | } | |
672 | ||
673 | static int pcc_init(struct pcmcia_socket *s) | |
674 | { | |
c9f50ddd | 675 | dev_dbg(&s->dev, "pcc_init()\n"); |
1da177e4 LT |
676 | return 0; |
677 | } | |
678 | ||
679 | static struct pccard_operations pcc_operations = { | |
680 | .init = pcc_init, | |
681 | .get_status = pcc_get_status, | |
1da177e4 LT |
682 | .set_socket = pcc_set_socket, |
683 | .set_io_map = pcc_set_io_map, | |
684 | .set_mem_map = pcc_set_mem_map, | |
685 | }; | |
686 | ||
7a192ec3 | 687 | |
1da177e4 LT |
688 | /*====================================================================*/ |
689 | ||
7a192ec3 ML |
690 | static struct platform_driver pcc_driver = { |
691 | .driver = { | |
692 | .name = "cfc", | |
693 | .owner = THIS_MODULE, | |
694 | }, | |
1da177e4 LT |
695 | }; |
696 | ||
697 | static struct platform_device pcc_device = { | |
698 | .name = "cfc", | |
699 | .id = 0, | |
700 | }; | |
701 | ||
702 | /*====================================================================*/ | |
703 | ||
704 | static int __init init_m32r_pcc(void) | |
705 | { | |
706 | int i, ret; | |
707 | ||
7a192ec3 | 708 | ret = platform_driver_register(&pcc_driver); |
1da177e4 LT |
709 | if (ret) |
710 | return ret; | |
711 | ||
712 | ret = platform_device_register(&pcc_device); | |
713 | if (ret){ | |
7a192ec3 | 714 | platform_driver_unregister(&pcc_driver); |
1da177e4 LT |
715 | return ret; |
716 | } | |
717 | ||
934bb7f8 | 718 | #if defined(CONFIG_PLAT_MAPPI2) || defined(CONFIG_PLAT_MAPPI3) |
1da177e4 LT |
719 | pcc_set(0, (unsigned int)PLD_CFCR0, 0x0f0f); |
720 | pcc_set(0, (unsigned int)PLD_CFCR1, 0x0200); | |
721 | #endif | |
722 | ||
723 | pcc_sockets = 0; | |
724 | ||
725 | #if !defined(CONFIG_PLAT_USRV) | |
726 | add_pcc_socket(M32R_PCC0_BASE, PLD_IRQ_CFC_INSERT, CFC_ATTR_MAPBASE, | |
727 | CFC_IOPORT_BASE); | |
728 | #else /* CONFIG_PLAT_USRV */ | |
729 | { | |
730 | ulong base, mapaddr; | |
906da809 | 731 | unsigned int ioaddr; |
1da177e4 LT |
732 | |
733 | for (i = 0 ; i < M32R_MAX_PCC ; i++) { | |
734 | base = (ulong)PLD_CFRSTCR; | |
735 | base = base | (i << 8); | |
736 | ioaddr = (i + 1) << 12; | |
737 | mapaddr = CFC_ATTR_MAPBASE | (i << 20); | |
738 | add_pcc_socket(base, 0, mapaddr, ioaddr); | |
739 | } | |
740 | } | |
741 | #endif /* CONFIG_PLAT_USRV */ | |
742 | ||
743 | if (pcc_sockets == 0) { | |
744 | printk("socket is not found.\n"); | |
745 | platform_device_unregister(&pcc_device); | |
7a192ec3 | 746 | platform_driver_unregister(&pcc_driver); |
1da177e4 LT |
747 | return -ENODEV; |
748 | } | |
749 | ||
750 | /* Set up interrupt handler(s) */ | |
751 | ||
752 | for (i = 0 ; i < pcc_sockets ; i++) { | |
dfe461ae | 753 | socket[i].socket.dev.parent = &pcc_device.dev; |
1da177e4 | 754 | socket[i].socket.ops = &pcc_operations; |
a7eb169d | 755 | socket[i].socket.resource_ops = &pccard_static_ops; |
1da177e4 LT |
756 | socket[i].socket.owner = THIS_MODULE; |
757 | socket[i].number = i; | |
758 | ret = pcmcia_register_socket(&socket[i].socket); | |
759 | if (!ret) | |
760 | socket[i].flags |= IS_REGISTERED; | |
761 | ||
762 | #if 0 /* driver model ordering issue */ | |
763 | class_device_create_file(&socket[i].socket.dev, | |
764 | &class_device_attr_info); | |
765 | class_device_create_file(&socket[i].socket.dev, | |
766 | &class_device_attr_exca); | |
767 | #endif | |
768 | } | |
769 | ||
770 | /* Finally, schedule a polling interrupt */ | |
771 | if (poll_interval != 0) { | |
772 | poll_timer.function = pcc_interrupt_wrapper; | |
773 | poll_timer.data = 0; | |
774 | init_timer(&poll_timer); | |
775 | poll_timer.expires = jiffies + poll_interval; | |
776 | add_timer(&poll_timer); | |
777 | } | |
778 | ||
779 | return 0; | |
780 | } /* init_m32r_pcc */ | |
781 | ||
782 | static void __exit exit_m32r_pcc(void) | |
783 | { | |
784 | int i; | |
785 | ||
786 | for (i = 0; i < pcc_sockets; i++) | |
787 | if (socket[i].flags & IS_REGISTERED) | |
788 | pcmcia_unregister_socket(&socket[i].socket); | |
789 | ||
790 | platform_device_unregister(&pcc_device); | |
791 | if (poll_interval != 0) | |
792 | del_timer_sync(&poll_timer); | |
793 | ||
7a192ec3 | 794 | platform_driver_unregister(&pcc_driver); |
1da177e4 LT |
795 | } /* exit_m32r_pcc */ |
796 | ||
797 | module_init(init_m32r_pcc); | |
798 | module_exit(exit_m32r_pcc); | |
799 | MODULE_LICENSE("Dual MPL/GPL"); | |
800 | /*====================================================================*/ |