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Commit | Line | Data |
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de957c89 MT |
1 | /* |
2 | * m8xx_pcmcia.c - Linux PCMCIA socket driver for the mpc8xx series. | |
3 | * | |
cbba0de2 | 4 | * (C) 1999-2000 Magnus Damm <damm@opensource.se> |
de957c89 MT |
5 | * (C) 2001-2002 Montavista Software, Inc. |
6 | * <mlocke@mvista.com> | |
7 | * | |
8 | * Support for two slots by Cyclades Corporation | |
9 | * <oliver.kurth@cyclades.de> | |
10 | * Further fixes, v2.6 kernel port | |
11 | * <marcelo.tosatti@cyclades.com> | |
1371d3be | 12 | * |
80128ff7 | 13 | * Some fixes, additions (C) 2005-2007 Montavista Software, Inc. |
1371d3be | 14 | * <vbordug@ru.mvista.com> |
de957c89 MT |
15 | * |
16 | * "The ExCA standard specifies that socket controllers should provide | |
17 | * two IO and five memory windows per socket, which can be independently | |
18 | * configured and positioned in the host address space and mapped to | |
19 | * arbitrary segments of card address space. " - David A Hinds. 1999 | |
20 | * | |
21 | * This controller does _not_ meet the ExCA standard. | |
22 | * | |
23 | * m8xx pcmcia controller brief info: | |
24 | * + 8 windows (attrib, mem, i/o) | |
25 | * + up to two slots (SLOT_A and SLOT_B) | |
26 | * + inputpins, outputpins, event and mask registers. | |
27 | * - no offset register. sigh. | |
28 | * | |
29 | * Because of the lacking offset register we must map the whole card. | |
30 | * We assign each memory window PCMCIA_MEM_WIN_SIZE address space. | |
31 | * Make sure there is (PCMCIA_MEM_WIN_SIZE * PCMCIA_MEM_WIN_NO | |
32 | * * PCMCIA_SOCKETS_NO) bytes at PCMCIA_MEM_WIN_BASE. | |
33 | * The i/o windows are dynamically allocated at PCMCIA_IO_WIN_BASE. | |
34 | * They are maximum 64KByte each... | |
35 | */ | |
36 | ||
37 | #include <linux/module.h> | |
38 | #include <linux/init.h> | |
39 | #include <linux/types.h> | |
40 | #include <linux/fcntl.h> | |
41 | #include <linux/string.h> | |
42 | ||
de957c89 MT |
43 | #include <linux/kernel.h> |
44 | #include <linux/errno.h> | |
de957c89 MT |
45 | #include <linux/slab.h> |
46 | #include <linux/timer.h> | |
47 | #include <linux/ioport.h> | |
48 | #include <linux/delay.h> | |
49 | #include <linux/interrupt.h> | |
80128ff7 | 50 | #include <linux/fsl_devices.h> |
1977f032 | 51 | #include <linux/bitops.h> |
ad19dbdb SR |
52 | #include <linux/of_device.h> |
53 | #include <linux/of_platform.h> | |
de957c89 | 54 | |
80128ff7 | 55 | #include <asm/io.h> |
80128ff7 VB |
56 | #include <asm/system.h> |
57 | #include <asm/time.h> | |
de957c89 MT |
58 | #include <asm/mpc8xx.h> |
59 | #include <asm/8xx_immap.h> | |
60 | #include <asm/irq.h> | |
80128ff7 | 61 | #include <asm/fs_pd.h> |
de957c89 | 62 | |
de957c89 MT |
63 | #include <pcmcia/cs_types.h> |
64 | #include <pcmcia/cs.h> | |
65 | #include <pcmcia/ss.h> | |
66 | ||
de957c89 MT |
67 | #define pcmcia_info(args...) printk(KERN_INFO "m8xx_pcmcia: "args) |
68 | #define pcmcia_error(args...) printk(KERN_ERR "m8xx_pcmcia: "args) | |
69 | ||
70 | static const char *version = "Version 0.06, Aug 2005"; | |
71 | MODULE_LICENSE("Dual MPL/GPL"); | |
72 | ||
73 | #if !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B) | |
74 | ||
75 | /* The RPX series use SLOT_B */ | |
76 | #if defined(CONFIG_RPXCLASSIC) || defined(CONFIG_RPXLITE) | |
77 | #define CONFIG_PCMCIA_SLOT_B | |
78 | #define CONFIG_BD_IS_MHZ | |
79 | #endif | |
80 | ||
81 | /* The ADS board use SLOT_A */ | |
82 | #ifdef CONFIG_ADS | |
83 | #define CONFIG_PCMCIA_SLOT_A | |
84 | #define CONFIG_BD_IS_MHZ | |
85 | #endif | |
86 | ||
87 | /* The FADS series are a mess */ | |
88 | #ifdef CONFIG_FADS | |
89 | #if defined(CONFIG_MPC860T) || defined(CONFIG_MPC860) || defined(CONFIG_MPC821) | |
90 | #define CONFIG_PCMCIA_SLOT_A | |
91 | #else | |
92 | #define CONFIG_PCMCIA_SLOT_B | |
93 | #endif | |
94 | #endif | |
95 | ||
1371d3be VB |
96 | #if defined(CONFIG_MPC885ADS) |
97 | #define CONFIG_PCMCIA_SLOT_A | |
98 | #define PCMCIA_GLITCHY_CD | |
99 | #endif | |
100 | ||
de957c89 MT |
101 | /* Cyclades ACS uses both slots */ |
102 | #ifdef CONFIG_PRxK | |
103 | #define CONFIG_PCMCIA_SLOT_A | |
104 | #define CONFIG_PCMCIA_SLOT_B | |
105 | #endif | |
106 | ||
99121c0d | 107 | #endif /* !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B) */ |
de957c89 MT |
108 | |
109 | #if defined(CONFIG_PCMCIA_SLOT_A) && defined(CONFIG_PCMCIA_SLOT_B) | |
110 | ||
111 | #define PCMCIA_SOCKETS_NO 2 | |
112 | /* We have only 8 windows, dualsocket support will be limited. */ | |
113 | #define PCMCIA_MEM_WIN_NO 2 | |
114 | #define PCMCIA_IO_WIN_NO 2 | |
115 | #define PCMCIA_SLOT_MSG "SLOT_A and SLOT_B" | |
116 | ||
117 | #elif defined(CONFIG_PCMCIA_SLOT_A) || defined(CONFIG_PCMCIA_SLOT_B) | |
118 | ||
119 | #define PCMCIA_SOCKETS_NO 1 | |
120 | /* full support for one slot */ | |
121 | #define PCMCIA_MEM_WIN_NO 5 | |
122 | #define PCMCIA_IO_WIN_NO 2 | |
123 | ||
124 | /* define _slot_ to be able to optimize macros */ | |
125 | ||
126 | #ifdef CONFIG_PCMCIA_SLOT_A | |
127 | #define _slot_ 0 | |
128 | #define PCMCIA_SLOT_MSG "SLOT_A" | |
129 | #else | |
130 | #define _slot_ 1 | |
131 | #define PCMCIA_SLOT_MSG "SLOT_B" | |
132 | #endif | |
133 | ||
134 | #else | |
135 | #error m8xx_pcmcia: Bad configuration! | |
136 | #endif | |
137 | ||
138 | /* ------------------------------------------------------------------------- */ | |
139 | ||
99121c0d VB |
140 | #define PCMCIA_MEM_WIN_BASE 0xe0000000 /* base address for memory window 0 */ |
141 | #define PCMCIA_MEM_WIN_SIZE 0x04000000 /* each memory window is 64 MByte */ | |
142 | #define PCMCIA_IO_WIN_BASE _IO_BASE /* base address for io window 0 */ | |
de957c89 MT |
143 | /* ------------------------------------------------------------------------- */ |
144 | ||
80128ff7 | 145 | static int pcmcia_schlvl; |
de957c89 | 146 | |
34af946a | 147 | static DEFINE_SPINLOCK(events_lock); |
de957c89 | 148 | |
de957c89 MT |
149 | #define PCMCIA_SOCKET_KEY_5V 1 |
150 | #define PCMCIA_SOCKET_KEY_LV 2 | |
151 | ||
152 | /* look up table for pgcrx registers */ | |
80128ff7 | 153 | static u32 *m8xx_pgcrx[2]; |
de957c89 MT |
154 | |
155 | /* | |
156 | * This structure is used to address each window in the PCMCIA controller. | |
157 | * | |
158 | * Keep in mind that we assume that pcmcia_win[n+1] is mapped directly | |
159 | * after pcmcia_win[n]... | |
160 | */ | |
161 | ||
162 | struct pcmcia_win { | |
99121c0d VB |
163 | u32 br; |
164 | u32 or; | |
de957c89 MT |
165 | }; |
166 | ||
167 | /* | |
168 | * For some reason the hardware guys decided to make both slots share | |
169 | * some registers. | |
170 | * | |
171 | * Could someone invent object oriented hardware ? | |
172 | * | |
173 | * The macros are used to get the right bit from the registers. | |
174 | * SLOT_A : slot = 0 | |
175 | * SLOT_B : slot = 1 | |
176 | */ | |
177 | ||
178 | #define M8XX_PCMCIA_VS1(slot) (0x80000000 >> (slot << 4)) | |
179 | #define M8XX_PCMCIA_VS2(slot) (0x40000000 >> (slot << 4)) | |
180 | #define M8XX_PCMCIA_VS_MASK(slot) (0xc0000000 >> (slot << 4)) | |
181 | #define M8XX_PCMCIA_VS_SHIFT(slot) (30 - (slot << 4)) | |
182 | ||
183 | #define M8XX_PCMCIA_WP(slot) (0x20000000 >> (slot << 4)) | |
184 | #define M8XX_PCMCIA_CD2(slot) (0x10000000 >> (slot << 4)) | |
185 | #define M8XX_PCMCIA_CD1(slot) (0x08000000 >> (slot << 4)) | |
186 | #define M8XX_PCMCIA_BVD2(slot) (0x04000000 >> (slot << 4)) | |
187 | #define M8XX_PCMCIA_BVD1(slot) (0x02000000 >> (slot << 4)) | |
188 | #define M8XX_PCMCIA_RDY(slot) (0x01000000 >> (slot << 4)) | |
189 | #define M8XX_PCMCIA_RDY_L(slot) (0x00800000 >> (slot << 4)) | |
190 | #define M8XX_PCMCIA_RDY_H(slot) (0x00400000 >> (slot << 4)) | |
191 | #define M8XX_PCMCIA_RDY_R(slot) (0x00200000 >> (slot << 4)) | |
192 | #define M8XX_PCMCIA_RDY_F(slot) (0x00100000 >> (slot << 4)) | |
193 | #define M8XX_PCMCIA_MASK(slot) (0xFFFF0000 >> (slot << 4)) | |
194 | ||
195 | #define M8XX_PCMCIA_POR_VALID 0x00000001 | |
196 | #define M8XX_PCMCIA_POR_WRPROT 0x00000002 | |
197 | #define M8XX_PCMCIA_POR_ATTRMEM 0x00000010 | |
198 | #define M8XX_PCMCIA_POR_IO 0x00000018 | |
199 | #define M8XX_PCMCIA_POR_16BIT 0x00000040 | |
200 | ||
201 | #define M8XX_PGCRX(slot) m8xx_pgcrx[slot] | |
202 | ||
203 | #define M8XX_PGCRX_CXOE 0x00000080 | |
204 | #define M8XX_PGCRX_CXRESET 0x00000040 | |
205 | ||
206 | /* we keep one lookup table per socket to check flags */ | |
207 | ||
99121c0d | 208 | #define PCMCIA_EVENTS_MAX 5 /* 4 max at a time + termination */ |
de957c89 MT |
209 | |
210 | struct event_table { | |
211 | u32 regbit; | |
212 | u32 eventbit; | |
213 | }; | |
214 | ||
80128ff7 VB |
215 | static const char driver_name[] = "m8xx-pcmcia"; |
216 | ||
de957c89 | 217 | struct socket_info { |
99121c0d VB |
218 | void (*handler) (void *info, u32 events); |
219 | void *info; | |
de957c89 MT |
220 | |
221 | u32 slot; | |
80128ff7 VB |
222 | pcmconf8xx_t *pcmcia; |
223 | u32 bus_freq; | |
224 | int hwirq; | |
de957c89 MT |
225 | |
226 | socket_state_t state; | |
227 | struct pccard_mem_map mem_win[PCMCIA_MEM_WIN_NO]; | |
99121c0d | 228 | struct pccard_io_map io_win[PCMCIA_IO_WIN_NO]; |
de957c89 MT |
229 | struct event_table events[PCMCIA_EVENTS_MAX]; |
230 | struct pcmcia_socket socket; | |
231 | }; | |
232 | ||
233 | static struct socket_info socket[PCMCIA_SOCKETS_NO]; | |
234 | ||
235 | /* | |
236 | * Search this table to see if the windowsize is | |
237 | * supported... | |
238 | */ | |
239 | ||
240 | #define M8XX_SIZES_NO 32 | |
241 | ||
99121c0d | 242 | static const u32 m8xx_size_to_gray[M8XX_SIZES_NO] = { |
de957c89 MT |
243 | 0x00000001, 0x00000002, 0x00000008, 0x00000004, |
244 | 0x00000080, 0x00000040, 0x00000010, 0x00000020, | |
245 | 0x00008000, 0x00004000, 0x00001000, 0x00002000, | |
246 | 0x00000100, 0x00000200, 0x00000800, 0x00000400, | |
247 | ||
248 | 0x0fffffff, 0xffffffff, 0xffffffff, 0xffffffff, | |
249 | 0x01000000, 0x02000000, 0xffffffff, 0x04000000, | |
250 | 0x00010000, 0x00020000, 0x00080000, 0x00040000, | |
251 | 0x00800000, 0x00400000, 0x00100000, 0x00200000 | |
252 | }; | |
253 | ||
254 | /* ------------------------------------------------------------------------- */ | |
255 | ||
7d12e780 | 256 | static irqreturn_t m8xx_interrupt(int irq, void *dev); |
de957c89 | 257 | |
99121c0d | 258 | #define PCMCIA_BMT_LIMIT (15*4) /* Bus Monitor Timeout value */ |
de957c89 MT |
259 | |
260 | /* ------------------------------------------------------------------------- */ | |
261 | /* board specific stuff: */ | |
262 | /* voltage_set(), hardware_enable() and hardware_disable() */ | |
263 | /* ------------------------------------------------------------------------- */ | |
264 | /* RPX Boards from Embedded Planet */ | |
265 | ||
266 | #if defined(CONFIG_RPXCLASSIC) || defined(CONFIG_RPXLITE) | |
267 | ||
268 | /* The RPX boards seems to have it's bus monitor timeout set to 6*8 clocks. | |
269 | * SYPCR is write once only, therefore must the slowest memory be faster | |
270 | * than the bus monitor or we will get a machine check due to the bus timeout. | |
271 | */ | |
272 | ||
273 | #define PCMCIA_BOARD_MSG "RPX CLASSIC or RPX LITE" | |
274 | ||
275 | #undef PCMCIA_BMT_LIMIT | |
276 | #define PCMCIA_BMT_LIMIT (6*8) | |
277 | ||
278 | static int voltage_set(int slot, int vcc, int vpp) | |
279 | { | |
280 | u32 reg = 0; | |
281 | ||
99121c0d VB |
282 | switch (vcc) { |
283 | case 0: | |
284 | break; | |
de957c89 MT |
285 | case 33: |
286 | reg |= BCSR1_PCVCTL4; | |
287 | break; | |
288 | case 50: | |
289 | reg |= BCSR1_PCVCTL5; | |
290 | break; | |
291 | default: | |
292 | return 1; | |
293 | } | |
294 | ||
99121c0d VB |
295 | switch (vpp) { |
296 | case 0: | |
297 | break; | |
de957c89 MT |
298 | case 33: |
299 | case 50: | |
99121c0d | 300 | if (vcc == vpp) |
de957c89 MT |
301 | reg |= BCSR1_PCVCTL6; |
302 | else | |
303 | return 1; | |
304 | break; | |
305 | case 120: | |
306 | reg |= BCSR1_PCVCTL7; | |
307 | default: | |
308 | return 1; | |
309 | } | |
310 | ||
99121c0d | 311 | if (!((vcc == 50) || (vcc == 0))) |
de957c89 MT |
312 | return 1; |
313 | ||
314 | /* first, turn off all power */ | |
315 | ||
99121c0d VB |
316 | out_be32(((u32 *) RPX_CSR_ADDR), |
317 | in_be32(((u32 *) RPX_CSR_ADDR)) & ~(BCSR1_PCVCTL4 | | |
318 | BCSR1_PCVCTL5 | | |
319 | BCSR1_PCVCTL6 | | |
320 | BCSR1_PCVCTL7)); | |
de957c89 MT |
321 | |
322 | /* enable new powersettings */ | |
323 | ||
99121c0d | 324 | out_be32(((u32 *) RPX_CSR_ADDR), in_be32(((u32 *) RPX_CSR_ADDR)) | reg); |
de957c89 MT |
325 | |
326 | return 0; | |
327 | } | |
328 | ||
329 | #define socket_get(_slot_) PCMCIA_SOCKET_KEY_5V | |
99121c0d VB |
330 | #define hardware_enable(_slot_) /* No hardware to enable */ |
331 | #define hardware_disable(_slot_) /* No hardware to disable */ | |
de957c89 | 332 | |
99121c0d | 333 | #endif /* CONFIG_RPXCLASSIC */ |
de957c89 MT |
334 | |
335 | /* FADS Boards from Motorola */ | |
336 | ||
337 | #if defined(CONFIG_FADS) | |
338 | ||
339 | #define PCMCIA_BOARD_MSG "FADS" | |
340 | ||
341 | static int voltage_set(int slot, int vcc, int vpp) | |
342 | { | |
343 | u32 reg = 0; | |
344 | ||
99121c0d VB |
345 | switch (vcc) { |
346 | case 0: | |
347 | break; | |
348 | case 33: | |
349 | reg |= BCSR1_PCCVCC0; | |
350 | break; | |
351 | case 50: | |
352 | reg |= BCSR1_PCCVCC1; | |
353 | break; | |
354 | default: | |
355 | return 1; | |
de957c89 MT |
356 | } |
357 | ||
99121c0d VB |
358 | switch (vpp) { |
359 | case 0: | |
360 | break; | |
361 | case 33: | |
362 | case 50: | |
363 | if (vcc == vpp) | |
364 | reg |= BCSR1_PCCVPP1; | |
365 | else | |
de957c89 | 366 | return 1; |
99121c0d VB |
367 | break; |
368 | case 120: | |
369 | if ((vcc == 33) || (vcc == 50)) | |
370 | reg |= BCSR1_PCCVPP0; | |
371 | else | |
372 | return 1; | |
373 | default: | |
374 | return 1; | |
de957c89 MT |
375 | } |
376 | ||
377 | /* first, turn off all power */ | |
99121c0d VB |
378 | out_be32((u32 *) BCSR1, |
379 | in_be32((u32 *) BCSR1) & ~(BCSR1_PCCVCC_MASK | | |
380 | BCSR1_PCCVPP_MASK)); | |
1371d3be VB |
381 | |
382 | /* enable new powersettings */ | |
99121c0d | 383 | out_be32((u32 *) BCSR1, in_be32((u32 *) BCSR1) | reg); |
1371d3be VB |
384 | |
385 | return 0; | |
386 | } | |
387 | ||
388 | #define socket_get(_slot_) PCMCIA_SOCKET_KEY_5V | |
389 | ||
390 | static void hardware_enable(int slot) | |
391 | { | |
99121c0d | 392 | out_be32((u32 *) BCSR1, in_be32((u32 *) BCSR1) & ~BCSR1_PCCEN); |
1371d3be VB |
393 | } |
394 | ||
395 | static void hardware_disable(int slot) | |
396 | { | |
99121c0d | 397 | out_be32((u32 *) BCSR1, in_be32((u32 *) BCSR1) | BCSR1_PCCEN); |
1371d3be VB |
398 | } |
399 | ||
400 | #endif | |
401 | ||
402 | /* MPC885ADS Boards */ | |
403 | ||
404 | #if defined(CONFIG_MPC885ADS) | |
405 | ||
406 | #define PCMCIA_BOARD_MSG "MPC885ADS" | |
80128ff7 | 407 | #define socket_get(_slot_) PCMCIA_SOCKET_KEY_5V |
1371d3be | 408 | |
80128ff7 | 409 | static inline void hardware_enable(int slot) |
1371d3be | 410 | { |
99121c0d | 411 | m8xx_pcmcia_ops.hw_ctrl(slot, 1); |
de957c89 MT |
412 | } |
413 | ||
80128ff7 | 414 | static inline void hardware_disable(int slot) |
de957c89 | 415 | { |
80128ff7 | 416 | m8xx_pcmcia_ops.hw_ctrl(slot, 0); |
de957c89 MT |
417 | } |
418 | ||
80128ff7 | 419 | static inline int voltage_set(int slot, int vcc, int vpp) |
de957c89 | 420 | { |
80128ff7 | 421 | return m8xx_pcmcia_ops.voltage_set(slot, vcc, vpp); |
de957c89 MT |
422 | } |
423 | ||
424 | #endif | |
425 | ||
426 | /* ------------------------------------------------------------------------- */ | |
427 | /* Motorola MBX860 */ | |
428 | ||
429 | #if defined(CONFIG_MBX) | |
430 | ||
431 | #define PCMCIA_BOARD_MSG "MBX" | |
432 | ||
433 | static int voltage_set(int slot, int vcc, int vpp) | |
434 | { | |
435 | u8 reg = 0; | |
436 | ||
99121c0d VB |
437 | switch (vcc) { |
438 | case 0: | |
439 | break; | |
440 | case 33: | |
441 | reg |= CSR2_VCC_33; | |
442 | break; | |
443 | case 50: | |
444 | reg |= CSR2_VCC_50; | |
445 | break; | |
446 | default: | |
447 | return 1; | |
de957c89 MT |
448 | } |
449 | ||
99121c0d VB |
450 | switch (vpp) { |
451 | case 0: | |
452 | break; | |
453 | case 33: | |
454 | case 50: | |
455 | if (vcc == vpp) | |
456 | reg |= CSR2_VPP_VCC; | |
457 | else | |
458 | return 1; | |
459 | break; | |
460 | case 120: | |
461 | if ((vcc == 33) || (vcc == 50)) | |
462 | reg |= CSR2_VPP_12; | |
463 | else | |
de957c89 | 464 | return 1; |
99121c0d VB |
465 | default: |
466 | return 1; | |
de957c89 MT |
467 | } |
468 | ||
469 | /* first, turn off all power */ | |
99121c0d VB |
470 | out_8((u8 *) MBX_CSR2_ADDR, |
471 | in_8((u8 *) MBX_CSR2_ADDR) & ~(CSR2_VCC_MASK | CSR2_VPP_MASK)); | |
de957c89 MT |
472 | |
473 | /* enable new powersettings */ | |
99121c0d | 474 | out_8((u8 *) MBX_CSR2_ADDR, in_8((u8 *) MBX_CSR2_ADDR) | reg); |
de957c89 MT |
475 | |
476 | return 0; | |
477 | } | |
478 | ||
479 | #define socket_get(_slot_) PCMCIA_SOCKET_KEY_5V | |
99121c0d VB |
480 | #define hardware_enable(_slot_) /* No hardware to enable */ |
481 | #define hardware_disable(_slot_) /* No hardware to disable */ | |
de957c89 | 482 | |
99121c0d | 483 | #endif /* CONFIG_MBX */ |
de957c89 MT |
484 | |
485 | #if defined(CONFIG_PRxK) | |
486 | #include <asm/cpld.h> | |
487 | extern volatile fpga_pc_regs *fpga_pc; | |
488 | ||
489 | #define PCMCIA_BOARD_MSG "MPC855T" | |
490 | ||
491 | static int voltage_set(int slot, int vcc, int vpp) | |
492 | { | |
493 | u8 reg = 0; | |
494 | u8 regread; | |
495 | cpld_regs *ccpld = get_cpld(); | |
496 | ||
99121c0d VB |
497 | switch (vcc) { |
498 | case 0: | |
499 | break; | |
500 | case 33: | |
501 | reg |= PCMCIA_VCC_33; | |
502 | break; | |
503 | case 50: | |
504 | reg |= PCMCIA_VCC_50; | |
505 | break; | |
506 | default: | |
507 | return 1; | |
de957c89 MT |
508 | } |
509 | ||
99121c0d VB |
510 | switch (vpp) { |
511 | case 0: | |
512 | break; | |
513 | case 33: | |
514 | case 50: | |
515 | if (vcc == vpp) | |
516 | reg |= PCMCIA_VPP_VCC; | |
517 | else | |
de957c89 | 518 | return 1; |
99121c0d VB |
519 | break; |
520 | case 120: | |
521 | if ((vcc == 33) || (vcc == 50)) | |
522 | reg |= PCMCIA_VPP_12; | |
523 | else | |
524 | return 1; | |
525 | default: | |
526 | return 1; | |
de957c89 MT |
527 | } |
528 | ||
529 | reg = reg >> (slot << 2); | |
530 | regread = in_8(&ccpld->fpga_pc_ctl); | |
99121c0d VB |
531 | if (reg != |
532 | (regread & ((PCMCIA_VCC_MASK | PCMCIA_VPP_MASK) >> (slot << 2)))) { | |
de957c89 | 533 | /* enable new powersettings */ |
99121c0d VB |
534 | regread = |
535 | regread & ~((PCMCIA_VCC_MASK | PCMCIA_VPP_MASK) >> | |
536 | (slot << 2)); | |
de957c89 MT |
537 | out_8(&ccpld->fpga_pc_ctl, reg | regread); |
538 | msleep(100); | |
539 | } | |
540 | ||
541 | return 0; | |
542 | } | |
543 | ||
544 | #define socket_get(_slot_) PCMCIA_SOCKET_KEY_LV | |
99121c0d VB |
545 | #define hardware_enable(_slot_) /* No hardware to enable */ |
546 | #define hardware_disable(_slot_) /* No hardware to disable */ | |
de957c89 | 547 | |
99121c0d | 548 | #endif /* CONFIG_PRxK */ |
de957c89 | 549 | |
de957c89 | 550 | static u32 pending_events[PCMCIA_SOCKETS_NO]; |
34af946a | 551 | static DEFINE_SPINLOCK(pending_event_lock); |
de957c89 | 552 | |
7d12e780 | 553 | static irqreturn_t m8xx_interrupt(int irq, void *dev) |
de957c89 MT |
554 | { |
555 | struct socket_info *s; | |
556 | struct event_table *e; | |
557 | unsigned int i, events, pscr, pipr, per; | |
99121c0d | 558 | pcmconf8xx_t *pcmcia = socket[0].pcmcia; |
de957c89 | 559 | |
c9f50ddd | 560 | pr_debug("m8xx_pcmcia: Interrupt!\n"); |
de957c89 MT |
561 | /* get interrupt sources */ |
562 | ||
80128ff7 VB |
563 | pscr = in_be32(&pcmcia->pcmc_pscr); |
564 | pipr = in_be32(&pcmcia->pcmc_pipr); | |
565 | per = in_be32(&pcmcia->pcmc_per); | |
de957c89 | 566 | |
99121c0d | 567 | for (i = 0; i < PCMCIA_SOCKETS_NO; i++) { |
de957c89 MT |
568 | s = &socket[i]; |
569 | e = &s->events[0]; | |
570 | events = 0; | |
571 | ||
99121c0d VB |
572 | while (e->regbit) { |
573 | if (pscr & e->regbit) | |
de957c89 MT |
574 | events |= e->eventbit; |
575 | ||
99121c0d | 576 | e++; |
de957c89 MT |
577 | } |
578 | ||
579 | /* | |
580 | * report only if both card detect signals are the same | |
581 | * not too nice done, | |
582 | * we depend on that CD2 is the bit to the left of CD1... | |
583 | */ | |
99121c0d VB |
584 | if (events & SS_DETECT) |
585 | if (((pipr & M8XX_PCMCIA_CD2(i)) >> 1) ^ | |
586 | (pipr & M8XX_PCMCIA_CD1(i))) { | |
de957c89 MT |
587 | events &= ~SS_DETECT; |
588 | } | |
de957c89 MT |
589 | #ifdef PCMCIA_GLITCHY_CD |
590 | /* | |
591 | * I've experienced CD problems with my ADS board. | |
592 | * We make an extra check to see if there was a | |
593 | * real change of Card detection. | |
594 | */ | |
595 | ||
99121c0d VB |
596 | if ((events & SS_DETECT) && |
597 | ((pipr & | |
598 | (M8XX_PCMCIA_CD2(i) | M8XX_PCMCIA_CD1(i))) == 0) && | |
599 | (s->state.Vcc | s->state.Vpp)) { | |
de957c89 MT |
600 | events &= ~SS_DETECT; |
601 | /*printk( "CD glitch workaround - CD = 0x%08x!\n", | |
99121c0d VB |
602 | (pipr & (M8XX_PCMCIA_CD2(i) |
603 | | M8XX_PCMCIA_CD1(i)))); */ | |
de957c89 MT |
604 | } |
605 | #endif | |
606 | ||
607 | /* call the handler */ | |
608 | ||
c9f50ddd | 609 | pr_debug("m8xx_pcmcia: slot %u: events = 0x%02x, pscr = 0x%08x, " |
99121c0d | 610 | "pipr = 0x%08x\n", i, events, pscr, pipr); |
de957c89 | 611 | |
99121c0d | 612 | if (events) { |
de957c89 MT |
613 | spin_lock(&pending_event_lock); |
614 | pending_events[i] |= events; | |
615 | spin_unlock(&pending_event_lock); | |
616 | /* | |
617 | * Turn off RDY_L bits in the PER mask on | |
618 | * CD interrupt receival. | |
619 | * | |
620 | * They can generate bad interrupts on the | |
621 | * ACS4,8,16,32. - marcelo | |
622 | */ | |
623 | per &= ~M8XX_PCMCIA_RDY_L(0); | |
624 | per &= ~M8XX_PCMCIA_RDY_L(1); | |
625 | ||
80128ff7 | 626 | out_be32(&pcmcia->pcmc_per, per); |
de957c89 MT |
627 | |
628 | if (events) | |
629 | pcmcia_parse_events(&socket[i].socket, events); | |
630 | } | |
631 | } | |
632 | ||
633 | /* clear the interrupt sources */ | |
80128ff7 | 634 | out_be32(&pcmcia->pcmc_pscr, pscr); |
de957c89 | 635 | |
c9f50ddd | 636 | pr_debug("m8xx_pcmcia: Interrupt done.\n"); |
de957c89 MT |
637 | |
638 | return IRQ_HANDLED; | |
639 | } | |
640 | ||
641 | static u32 m8xx_get_graycode(u32 size) | |
642 | { | |
643 | u32 k; | |
644 | ||
99121c0d VB |
645 | for (k = 0; k < M8XX_SIZES_NO; k++) |
646 | if (m8xx_size_to_gray[k] == size) | |
de957c89 MT |
647 | break; |
648 | ||
99121c0d | 649 | if ((k == M8XX_SIZES_NO) || (m8xx_size_to_gray[k] == -1)) |
de957c89 MT |
650 | k = -1; |
651 | ||
652 | return k; | |
653 | } | |
654 | ||
80128ff7 | 655 | static u32 m8xx_get_speed(u32 ns, u32 is_io, u32 bus_freq) |
de957c89 MT |
656 | { |
657 | u32 reg, clocks, psst, psl, psht; | |
658 | ||
99121c0d | 659 | if (!ns) { |
de957c89 MT |
660 | |
661 | /* | |
662 | * We get called with IO maps setup to 0ns | |
663 | * if not specified by the user. | |
664 | * They should be 255ns. | |
665 | */ | |
666 | ||
99121c0d | 667 | if (is_io) |
de957c89 MT |
668 | ns = 255; |
669 | else | |
99121c0d | 670 | ns = 100; /* fast memory if 0 */ |
de957c89 MT |
671 | } |
672 | ||
673 | /* | |
674 | * In PSST, PSL, PSHT fields we tell the controller | |
675 | * timing parameters in CLKOUT clock cycles. | |
676 | * CLKOUT is the same as GCLK2_50. | |
677 | */ | |
678 | ||
679 | /* how we want to adjust the timing - in percent */ | |
680 | ||
99121c0d | 681 | #define ADJ 180 /* 80 % longer accesstime - to be sure */ |
de957c89 | 682 | |
80128ff7 | 683 | clocks = ((bus_freq / 1000) * ns) / 1000; |
99121c0d VB |
684 | clocks = (clocks * ADJ) / (100 * 1000); |
685 | if (clocks >= PCMCIA_BMT_LIMIT) { | |
686 | printk("Max access time limit reached\n"); | |
687 | clocks = PCMCIA_BMT_LIMIT - 1; | |
de957c89 MT |
688 | } |
689 | ||
99121c0d VB |
690 | psst = clocks / 7; /* setup time */ |
691 | psht = clocks / 7; /* hold time */ | |
692 | psl = (clocks * 5) / 7; /* strobe length */ | |
de957c89 MT |
693 | |
694 | psst += clocks - (psst + psht + psl); | |
695 | ||
99121c0d VB |
696 | reg = psst << 12; |
697 | reg |= psl << 7; | |
de957c89 MT |
698 | reg |= psht << 16; |
699 | ||
700 | return reg; | |
701 | } | |
702 | ||
703 | static int m8xx_get_status(struct pcmcia_socket *sock, unsigned int *value) | |
704 | { | |
705 | int lsock = container_of(sock, struct socket_info, socket)->slot; | |
706 | struct socket_info *s = &socket[lsock]; | |
707 | unsigned int pipr, reg; | |
80128ff7 | 708 | pcmconf8xx_t *pcmcia = s->pcmcia; |
de957c89 | 709 | |
80128ff7 | 710 | pipr = in_be32(&pcmcia->pcmc_pipr); |
de957c89 | 711 | |
99121c0d VB |
712 | *value = ((pipr & (M8XX_PCMCIA_CD1(lsock) |
713 | | M8XX_PCMCIA_CD2(lsock))) == 0) ? SS_DETECT : 0; | |
de957c89 MT |
714 | *value |= (pipr & M8XX_PCMCIA_WP(lsock)) ? SS_WRPROT : 0; |
715 | ||
716 | if (s->state.flags & SS_IOCARD) | |
717 | *value |= (pipr & M8XX_PCMCIA_BVD1(lsock)) ? SS_STSCHG : 0; | |
718 | else { | |
719 | *value |= (pipr & M8XX_PCMCIA_RDY(lsock)) ? SS_READY : 0; | |
720 | *value |= (pipr & M8XX_PCMCIA_BVD1(lsock)) ? SS_BATDEAD : 0; | |
721 | *value |= (pipr & M8XX_PCMCIA_BVD2(lsock)) ? SS_BATWARN : 0; | |
722 | } | |
723 | ||
724 | if (s->state.Vcc | s->state.Vpp) | |
725 | *value |= SS_POWERON; | |
726 | ||
727 | /* | |
728 | * Voltage detection: | |
729 | * This driver only supports 16-Bit pc-cards. | |
730 | * Cardbus is not handled here. | |
731 | * | |
732 | * To determine what voltage to use we must read the VS1 and VS2 pin. | |
733 | * Depending on what socket type is present, | |
734 | * different combinations mean different things. | |
735 | * | |
736 | * Card Key Socket Key VS1 VS2 Card Vcc for CIS parse | |
737 | * | |
738 | * 5V 5V, LV* NC NC 5V only 5V (if available) | |
739 | * | |
740 | * 5V 5V, LV* GND NC 5 or 3.3V as low as possible | |
741 | * | |
742 | * 5V 5V, LV* GND GND 5, 3.3, x.xV as low as possible | |
743 | * | |
744 | * LV* 5V - - shall not fit into socket | |
745 | * | |
746 | * LV* LV* GND NC 3.3V only 3.3V | |
747 | * | |
748 | * LV* LV* NC GND x.xV x.xV (if avail.) | |
749 | * | |
750 | * LV* LV* GND GND 3.3 or x.xV as low as possible | |
751 | * | |
752 | * *LV means Low Voltage | |
753 | * | |
754 | * | |
755 | * That gives us the following table: | |
756 | * | |
757 | * Socket VS1 VS2 Voltage | |
758 | * | |
759 | * 5V NC NC 5V | |
760 | * 5V NC GND none (should not be possible) | |
761 | * 5V GND NC >= 3.3V | |
762 | * 5V GND GND >= x.xV | |
763 | * | |
764 | * LV NC NC 5V (if available) | |
765 | * LV NC GND x.xV (if available) | |
766 | * LV GND NC 3.3V | |
767 | * LV GND GND >= x.xV | |
768 | * | |
769 | * So, how do I determine if I have a 5V or a LV | |
770 | * socket on my board? Look at the socket! | |
771 | * | |
772 | * | |
773 | * Socket with 5V key: | |
774 | * ++--------------------------------------------+ | |
775 | * || | | |
776 | * || || | |
777 | * || || | |
778 | * | | | |
779 | * +---------------------------------------------+ | |
780 | * | |
781 | * Socket with LV key: | |
782 | * ++--------------------------------------------+ | |
783 | * || | | |
784 | * | || | |
785 | * | || | |
786 | * | | | |
787 | * +---------------------------------------------+ | |
788 | * | |
789 | * | |
790 | * With other words - LV only cards does not fit | |
791 | * into the 5V socket! | |
792 | */ | |
793 | ||
794 | /* read out VS1 and VS2 */ | |
795 | ||
796 | reg = (pipr & M8XX_PCMCIA_VS_MASK(lsock)) | |
99121c0d | 797 | >> M8XX_PCMCIA_VS_SHIFT(lsock); |
de957c89 | 798 | |
99121c0d VB |
799 | if (socket_get(lsock) == PCMCIA_SOCKET_KEY_LV) { |
800 | switch (reg) { | |
de957c89 MT |
801 | case 1: |
802 | *value |= SS_3VCARD; | |
99121c0d | 803 | break; /* GND, NC - 3.3V only */ |
de957c89 MT |
804 | case 2: |
805 | *value |= SS_XVCARD; | |
99121c0d | 806 | break; /* NC. GND - x.xV only */ |
de957c89 MT |
807 | }; |
808 | } | |
809 | ||
c9f50ddd | 810 | pr_debug("m8xx_pcmcia: GetStatus(%d) = %#2.2x\n", lsock, *value); |
de957c89 MT |
811 | return 0; |
812 | } | |
813 | ||
99121c0d | 814 | static int m8xx_set_socket(struct pcmcia_socket *sock, socket_state_t * state) |
de957c89 MT |
815 | { |
816 | int lsock = container_of(sock, struct socket_info, socket)->slot; | |
817 | struct socket_info *s = &socket[lsock]; | |
818 | struct event_table *e; | |
819 | unsigned int reg; | |
820 | unsigned long flags; | |
80128ff7 | 821 | pcmconf8xx_t *pcmcia = socket[0].pcmcia; |
de957c89 | 822 | |
c9f50ddd | 823 | pr_debug("m8xx_pcmcia: SetSocket(%d, flags %#3.3x, Vcc %d, Vpp %d, " |
99121c0d VB |
824 | "io_irq %d, csc_mask %#2.2x)\n", lsock, state->flags, |
825 | state->Vcc, state->Vpp, state->io_irq, state->csc_mask); | |
de957c89 MT |
826 | |
827 | /* First, set voltage - bail out if invalid */ | |
99121c0d | 828 | if (voltage_set(lsock, state->Vcc, state->Vpp)) |
de957c89 MT |
829 | return -EINVAL; |
830 | ||
831 | /* Take care of reset... */ | |
99121c0d VB |
832 | if (state->flags & SS_RESET) |
833 | out_be32(M8XX_PGCRX(lsock), in_be32(M8XX_PGCRX(lsock)) | M8XX_PGCRX_CXRESET); /* active high */ | |
de957c89 | 834 | else |
99121c0d VB |
835 | out_be32(M8XX_PGCRX(lsock), |
836 | in_be32(M8XX_PGCRX(lsock)) & ~M8XX_PGCRX_CXRESET); | |
de957c89 MT |
837 | |
838 | /* ... and output enable. */ | |
839 | ||
840 | /* The CxOE signal is connected to a 74541 on the ADS. | |
841 | I guess most other boards used the ADS as a reference. | |
842 | I tried to control the CxOE signal with SS_OUTPUT_ENA, | |
843 | but the reset signal seems connected via the 541. | |
844 | If the CxOE is left high are some signals tristated and | |
f26fc4e0 | 845 | no pullups are present -> the cards act weird. |
de957c89 MT |
846 | So right now the buffers are enabled if the power is on. */ |
847 | ||
99121c0d VB |
848 | if (state->Vcc || state->Vpp) |
849 | out_be32(M8XX_PGCRX(lsock), in_be32(M8XX_PGCRX(lsock)) & ~M8XX_PGCRX_CXOE); /* active low */ | |
de957c89 | 850 | else |
99121c0d VB |
851 | out_be32(M8XX_PGCRX(lsock), |
852 | in_be32(M8XX_PGCRX(lsock)) | M8XX_PGCRX_CXOE); | |
de957c89 MT |
853 | |
854 | /* | |
855 | * We'd better turn off interrupts before | |
856 | * we mess with the events-table.. | |
857 | */ | |
858 | ||
859 | spin_lock_irqsave(&events_lock, flags); | |
860 | ||
861 | /* | |
862 | * Play around with the interrupt mask to be able to | |
863 | * give the events the generic pcmcia driver wants us to. | |
864 | */ | |
865 | ||
866 | e = &s->events[0]; | |
867 | reg = 0; | |
868 | ||
99121c0d | 869 | if (state->csc_mask & SS_DETECT) { |
de957c89 MT |
870 | e->eventbit = SS_DETECT; |
871 | reg |= e->regbit = (M8XX_PCMCIA_CD2(lsock) | |
872 | | M8XX_PCMCIA_CD1(lsock)); | |
873 | e++; | |
874 | } | |
99121c0d | 875 | if (state->flags & SS_IOCARD) { |
de957c89 MT |
876 | /* |
877 | * I/O card | |
878 | */ | |
99121c0d | 879 | if (state->csc_mask & SS_STSCHG) { |
de957c89 MT |
880 | e->eventbit = SS_STSCHG; |
881 | reg |= e->regbit = M8XX_PCMCIA_BVD1(lsock); | |
882 | e++; | |
883 | } | |
884 | /* | |
885 | * If io_irq is non-zero we should enable irq. | |
886 | */ | |
99121c0d | 887 | if (state->io_irq) { |
80128ff7 | 888 | out_be32(M8XX_PGCRX(lsock), |
99121c0d VB |
889 | in_be32(M8XX_PGCRX(lsock)) | |
890 | mk_int_int_mask(s->hwirq) << 24); | |
de957c89 MT |
891 | /* |
892 | * Strange thing here: | |
893 | * The manual does not tell us which interrupt | |
894 | * the sources generate. | |
895 | * Anyhow, I found out that RDY_L generates IREQLVL. | |
896 | * | |
897 | * We use level triggerd interrupts, and they don't | |
898 | * have to be cleared in PSCR in the interrupt handler. | |
899 | */ | |
900 | reg |= M8XX_PCMCIA_RDY_L(lsock); | |
99121c0d VB |
901 | } else |
902 | out_be32(M8XX_PGCRX(lsock), | |
903 | in_be32(M8XX_PGCRX(lsock)) & 0x00ffffff); | |
904 | } else { | |
de957c89 MT |
905 | /* |
906 | * Memory card | |
907 | */ | |
99121c0d | 908 | if (state->csc_mask & SS_BATDEAD) { |
de957c89 MT |
909 | e->eventbit = SS_BATDEAD; |
910 | reg |= e->regbit = M8XX_PCMCIA_BVD1(lsock); | |
911 | e++; | |
912 | } | |
99121c0d | 913 | if (state->csc_mask & SS_BATWARN) { |
de957c89 MT |
914 | e->eventbit = SS_BATWARN; |
915 | reg |= e->regbit = M8XX_PCMCIA_BVD2(lsock); | |
916 | e++; | |
917 | } | |
918 | /* What should I trigger on - low/high,raise,fall? */ | |
99121c0d | 919 | if (state->csc_mask & SS_READY) { |
de957c89 | 920 | e->eventbit = SS_READY; |
99121c0d | 921 | reg |= e->regbit = 0; //?? |
de957c89 MT |
922 | e++; |
923 | } | |
924 | } | |
925 | ||
99121c0d | 926 | e->regbit = 0; /* terminate list */ |
de957c89 MT |
927 | |
928 | /* | |
929 | * Clear the status changed . | |
930 | * Port A and Port B share the same port. | |
931 | * Writing ones will clear the bits. | |
932 | */ | |
933 | ||
80128ff7 | 934 | out_be32(&pcmcia->pcmc_pscr, reg); |
de957c89 MT |
935 | |
936 | /* | |
937 | * Write the mask. | |
938 | * Port A and Port B share the same port. | |
939 | * Need for read-modify-write. | |
940 | * Ones will enable the interrupt. | |
941 | */ | |
942 | ||
99121c0d VB |
943 | reg |= |
944 | in_be32(&pcmcia-> | |
945 | pcmc_per) & (M8XX_PCMCIA_MASK(0) | M8XX_PCMCIA_MASK(1)); | |
80128ff7 | 946 | out_be32(&pcmcia->pcmc_per, reg); |
de957c89 MT |
947 | |
948 | spin_unlock_irqrestore(&events_lock, flags); | |
949 | ||
950 | /* copy the struct and modify the copy */ | |
951 | ||
952 | s->state = *state; | |
953 | ||
954 | return 0; | |
955 | } | |
956 | ||
957 | static int m8xx_set_io_map(struct pcmcia_socket *sock, struct pccard_io_map *io) | |
958 | { | |
959 | int lsock = container_of(sock, struct socket_info, socket)->slot; | |
960 | ||
961 | struct socket_info *s = &socket[lsock]; | |
962 | struct pcmcia_win *w; | |
963 | unsigned int reg, winnr; | |
80128ff7 VB |
964 | pcmconf8xx_t *pcmcia = s->pcmcia; |
965 | ||
de957c89 MT |
966 | #define M8XX_SIZE (io->stop - io->start + 1) |
967 | #define M8XX_BASE (PCMCIA_IO_WIN_BASE + io->start) | |
968 | ||
c9f50ddd | 969 | pr_debug("m8xx_pcmcia: SetIOMap(%d, %d, %#2.2x, %d ns, " |
5f784336 WS |
970 | "%#4.4llx-%#4.4llx)\n", lsock, io->map, io->flags, |
971 | io->speed, (unsigned long long)io->start, | |
972 | (unsigned long long)io->stop); | |
de957c89 MT |
973 | |
974 | if ((io->map >= PCMCIA_IO_WIN_NO) || (io->start > 0xffff) | |
975 | || (io->stop > 0xffff) || (io->stop < io->start)) | |
976 | return -EINVAL; | |
977 | ||
99121c0d | 978 | if ((reg = m8xx_get_graycode(M8XX_SIZE)) == -1) |
de957c89 MT |
979 | return -EINVAL; |
980 | ||
99121c0d | 981 | if (io->flags & MAP_ACTIVE) { |
de957c89 | 982 | |
c9f50ddd | 983 | pr_debug("m8xx_pcmcia: io->flags & MAP_ACTIVE\n"); |
de957c89 MT |
984 | |
985 | winnr = (PCMCIA_MEM_WIN_NO * PCMCIA_SOCKETS_NO) | |
99121c0d | 986 | + (lsock * PCMCIA_IO_WIN_NO) + io->map; |
de957c89 MT |
987 | |
988 | /* setup registers */ | |
989 | ||
99121c0d | 990 | w = (void *)&pcmcia->pcmc_pbr0; |
de957c89 MT |
991 | w += winnr; |
992 | ||
99121c0d | 993 | out_be32(&w->or, 0); /* turn off window first */ |
de957c89 MT |
994 | out_be32(&w->br, M8XX_BASE); |
995 | ||
996 | reg <<= 27; | |
99121c0d | 997 | reg |= M8XX_PCMCIA_POR_IO | (lsock << 2); |
de957c89 | 998 | |
80128ff7 | 999 | reg |= m8xx_get_speed(io->speed, 1, s->bus_freq); |
de957c89 | 1000 | |
99121c0d | 1001 | if (io->flags & MAP_WRPROT) |
de957c89 MT |
1002 | reg |= M8XX_PCMCIA_POR_WRPROT; |
1003 | ||
99121c0d VB |
1004 | /*if(io->flags & (MAP_16BIT | MAP_AUTOSZ)) */ |
1005 | if (io->flags & MAP_16BIT) | |
de957c89 MT |
1006 | reg |= M8XX_PCMCIA_POR_16BIT; |
1007 | ||
99121c0d | 1008 | if (io->flags & MAP_ACTIVE) |
de957c89 MT |
1009 | reg |= M8XX_PCMCIA_POR_VALID; |
1010 | ||
1011 | out_be32(&w->or, reg); | |
1012 | ||
c9f50ddd DB |
1013 | pr_debug("m8xx_pcmcia: Socket %u: Mapped io window %u at " |
1014 | "%#8.8x, OR = %#8.8x.\n", lsock, io->map, w->br, w->or); | |
de957c89 MT |
1015 | } else { |
1016 | /* shutdown IO window */ | |
1017 | winnr = (PCMCIA_MEM_WIN_NO * PCMCIA_SOCKETS_NO) | |
99121c0d | 1018 | + (lsock * PCMCIA_IO_WIN_NO) + io->map; |
de957c89 MT |
1019 | |
1020 | /* setup registers */ | |
1021 | ||
99121c0d | 1022 | w = (void *)&pcmcia->pcmc_pbr0; |
de957c89 MT |
1023 | w += winnr; |
1024 | ||
99121c0d VB |
1025 | out_be32(&w->or, 0); /* turn off window */ |
1026 | out_be32(&w->br, 0); /* turn off base address */ | |
de957c89 | 1027 | |
c9f50ddd DB |
1028 | pr_debug("m8xx_pcmcia: Socket %u: Unmapped io window %u at " |
1029 | "%#8.8x, OR = %#8.8x.\n", lsock, io->map, w->br, w->or); | |
de957c89 MT |
1030 | } |
1031 | ||
1032 | /* copy the struct and modify the copy */ | |
1033 | s->io_win[io->map] = *io; | |
99121c0d | 1034 | s->io_win[io->map].flags &= (MAP_WRPROT | MAP_16BIT | MAP_ACTIVE); |
c9f50ddd | 1035 | pr_debug("m8xx_pcmcia: SetIOMap exit\n"); |
de957c89 MT |
1036 | |
1037 | return 0; | |
1038 | } | |
1039 | ||
99121c0d VB |
1040 | static int m8xx_set_mem_map(struct pcmcia_socket *sock, |
1041 | struct pccard_mem_map *mem) | |
de957c89 MT |
1042 | { |
1043 | int lsock = container_of(sock, struct socket_info, socket)->slot; | |
1044 | struct socket_info *s = &socket[lsock]; | |
1045 | struct pcmcia_win *w; | |
1046 | struct pccard_mem_map *old; | |
1047 | unsigned int reg, winnr; | |
80128ff7 | 1048 | pcmconf8xx_t *pcmcia = s->pcmcia; |
de957c89 | 1049 | |
c9f50ddd | 1050 | pr_debug("m8xx_pcmcia: SetMemMap(%d, %d, %#2.2x, %d ns, " |
5f784336 WS |
1051 | "%#5.5llx, %#5.5x)\n", lsock, mem->map, mem->flags, |
1052 | mem->speed, (unsigned long long)mem->static_start, | |
1053 | mem->card_start); | |
de957c89 MT |
1054 | |
1055 | if ((mem->map >= PCMCIA_MEM_WIN_NO) | |
99121c0d | 1056 | // || ((mem->s) >= PCMCIA_MEM_WIN_SIZE) |
de957c89 | 1057 | || (mem->card_start >= 0x04000000) |
99121c0d VB |
1058 | || (mem->static_start & 0xfff) /* 4KByte resolution */ |
1059 | ||(mem->card_start & 0xfff)) | |
de957c89 MT |
1060 | return -EINVAL; |
1061 | ||
99121c0d VB |
1062 | if ((reg = m8xx_get_graycode(PCMCIA_MEM_WIN_SIZE)) == -1) { |
1063 | printk("Cannot set size to 0x%08x.\n", PCMCIA_MEM_WIN_SIZE); | |
de957c89 MT |
1064 | return -EINVAL; |
1065 | } | |
1066 | reg <<= 27; | |
1067 | ||
1068 | winnr = (lsock * PCMCIA_MEM_WIN_NO) + mem->map; | |
1069 | ||
1070 | /* Setup the window in the pcmcia controller */ | |
1071 | ||
99121c0d | 1072 | w = (void *)&pcmcia->pcmc_pbr0; |
de957c89 MT |
1073 | w += winnr; |
1074 | ||
1075 | reg |= lsock << 2; | |
1076 | ||
80128ff7 | 1077 | reg |= m8xx_get_speed(mem->speed, 0, s->bus_freq); |
de957c89 | 1078 | |
99121c0d VB |
1079 | if (mem->flags & MAP_ATTRIB) |
1080 | reg |= M8XX_PCMCIA_POR_ATTRMEM; | |
de957c89 | 1081 | |
99121c0d | 1082 | if (mem->flags & MAP_WRPROT) |
de957c89 MT |
1083 | reg |= M8XX_PCMCIA_POR_WRPROT; |
1084 | ||
99121c0d | 1085 | if (mem->flags & MAP_16BIT) |
de957c89 MT |
1086 | reg |= M8XX_PCMCIA_POR_16BIT; |
1087 | ||
99121c0d | 1088 | if (mem->flags & MAP_ACTIVE) |
de957c89 MT |
1089 | reg |= M8XX_PCMCIA_POR_VALID; |
1090 | ||
1091 | out_be32(&w->or, reg); | |
1092 | ||
c9f50ddd | 1093 | pr_debug("m8xx_pcmcia: Socket %u: Mapped memory window %u at %#8.8x, " |
99121c0d | 1094 | "OR = %#8.8x.\n", lsock, mem->map, w->br, w->or); |
de957c89 | 1095 | |
99121c0d | 1096 | if (mem->flags & MAP_ACTIVE) { |
de957c89 MT |
1097 | /* get the new base address */ |
1098 | mem->static_start = PCMCIA_MEM_WIN_BASE + | |
99121c0d VB |
1099 | (PCMCIA_MEM_WIN_SIZE * winnr) |
1100 | + mem->card_start; | |
de957c89 MT |
1101 | } |
1102 | ||
c9f50ddd | 1103 | pr_debug("m8xx_pcmcia: SetMemMap(%d, %d, %#2.2x, %d ns, " |
5f784336 WS |
1104 | "%#5.5llx, %#5.5x)\n", lsock, mem->map, mem->flags, |
1105 | mem->speed, (unsigned long long)mem->static_start, | |
1106 | mem->card_start); | |
de957c89 MT |
1107 | |
1108 | /* copy the struct and modify the copy */ | |
1109 | ||
1110 | old = &s->mem_win[mem->map]; | |
1111 | ||
1112 | *old = *mem; | |
99121c0d | 1113 | old->flags &= (MAP_ATTRIB | MAP_WRPROT | MAP_16BIT | MAP_ACTIVE); |
de957c89 MT |
1114 | |
1115 | return 0; | |
1116 | } | |
1117 | ||
1118 | static int m8xx_sock_init(struct pcmcia_socket *sock) | |
1119 | { | |
1120 | int i; | |
1121 | pccard_io_map io = { 0, 0, 0, 0, 1 }; | |
1122 | pccard_mem_map mem = { 0, 0, 0, 0, 0, 0 }; | |
1123 | ||
c9f50ddd | 1124 | pr_debug("m8xx_pcmcia: sock_init(%d)\n", s); |
de957c89 MT |
1125 | |
1126 | m8xx_set_socket(sock, &dead_socket); | |
1127 | for (i = 0; i < PCMCIA_IO_WIN_NO; i++) { | |
1128 | io.map = i; | |
1129 | m8xx_set_io_map(sock, &io); | |
1130 | } | |
1131 | for (i = 0; i < PCMCIA_MEM_WIN_NO; i++) { | |
1132 | mem.map = i; | |
1133 | m8xx_set_mem_map(sock, &mem); | |
1134 | } | |
1135 | ||
1136 | return 0; | |
1137 | ||
1138 | } | |
1139 | ||
80128ff7 | 1140 | static int m8xx_sock_suspend(struct pcmcia_socket *sock) |
de957c89 MT |
1141 | { |
1142 | return m8xx_set_socket(sock, &dead_socket); | |
1143 | } | |
1144 | ||
1145 | static struct pccard_operations m8xx_services = { | |
99121c0d | 1146 | .init = m8xx_sock_init, |
80128ff7 | 1147 | .suspend = m8xx_sock_suspend, |
de957c89 | 1148 | .get_status = m8xx_get_status, |
de957c89 MT |
1149 | .set_socket = m8xx_set_socket, |
1150 | .set_io_map = m8xx_set_io_map, | |
1151 | .set_mem_map = m8xx_set_mem_map, | |
1152 | }; | |
1153 | ||
99121c0d VB |
1154 | static int __init m8xx_probe(struct of_device *ofdev, |
1155 | const struct of_device_id *match) | |
de957c89 MT |
1156 | { |
1157 | struct pcmcia_win *w; | |
80128ff7 VB |
1158 | unsigned int i, m, hwirq; |
1159 | pcmconf8xx_t *pcmcia; | |
1160 | int status; | |
1161 | struct device_node *np = ofdev->node; | |
de957c89 MT |
1162 | |
1163 | pcmcia_info("%s\n", version); | |
1164 | ||
80128ff7 | 1165 | pcmcia = of_iomap(np, 0); |
99121c0d | 1166 | if (pcmcia == NULL) |
80128ff7 VB |
1167 | return -EINVAL; |
1168 | ||
1169 | pcmcia_schlvl = irq_of_parse_and_map(np, 0); | |
99121c0d | 1170 | hwirq = irq_map[pcmcia_schlvl].hwirq; |
5a1c3e1a JL |
1171 | if (pcmcia_schlvl < 0) { |
1172 | iounmap(pcmcia); | |
80128ff7 | 1173 | return -EINVAL; |
5a1c3e1a | 1174 | } |
80128ff7 VB |
1175 | |
1176 | m8xx_pgcrx[0] = &pcmcia->pcmc_pgcra; | |
1177 | m8xx_pgcrx[1] = &pcmcia->pcmc_pgcrb; | |
1178 | ||
de957c89 | 1179 | pcmcia_info(PCMCIA_BOARD_MSG " using " PCMCIA_SLOT_MSG |
80128ff7 | 1180 | " with IRQ %u (%d). \n", pcmcia_schlvl, hwirq); |
de957c89 MT |
1181 | |
1182 | /* Configure Status change interrupt */ | |
1183 | ||
99121c0d VB |
1184 | if (request_irq(pcmcia_schlvl, m8xx_interrupt, IRQF_SHARED, |
1185 | driver_name, socket)) { | |
de957c89 MT |
1186 | pcmcia_error("Cannot allocate IRQ %u for SCHLVL!\n", |
1187 | pcmcia_schlvl); | |
5a1c3e1a | 1188 | iounmap(pcmcia); |
de957c89 MT |
1189 | return -1; |
1190 | } | |
1191 | ||
99121c0d | 1192 | w = (void *)&pcmcia->pcmc_pbr0; |
de957c89 | 1193 | |
99121c0d | 1194 | out_be32(&pcmcia->pcmc_pscr, M8XX_PCMCIA_MASK(0) | M8XX_PCMCIA_MASK(1)); |
80128ff7 | 1195 | clrbits32(&pcmcia->pcmc_per, M8XX_PCMCIA_MASK(0) | M8XX_PCMCIA_MASK(1)); |
de957c89 | 1196 | |
80128ff7 | 1197 | /* connect interrupt and disable CxOE */ |
de957c89 | 1198 | |
99121c0d VB |
1199 | out_be32(M8XX_PGCRX(0), |
1200 | M8XX_PGCRX_CXOE | (mk_int_int_mask(hwirq) << 16)); | |
1201 | out_be32(M8XX_PGCRX(1), | |
1202 | M8XX_PGCRX_CXOE | (mk_int_int_mask(hwirq) << 16)); | |
de957c89 | 1203 | |
80128ff7 | 1204 | /* intialize the fixed memory windows */ |
de957c89 | 1205 | |
99121c0d | 1206 | for (i = 0; i < PCMCIA_SOCKETS_NO; i++) { |
80128ff7 | 1207 | for (m = 0; m < PCMCIA_MEM_WIN_NO; m++) { |
de957c89 | 1208 | out_be32(&w->br, PCMCIA_MEM_WIN_BASE + |
99121c0d VB |
1209 | (PCMCIA_MEM_WIN_SIZE |
1210 | * (m + i * PCMCIA_MEM_WIN_NO))); | |
de957c89 | 1211 | |
99121c0d | 1212 | out_be32(&w->or, 0); /* set to not valid */ |
de957c89 MT |
1213 | |
1214 | w++; | |
1215 | } | |
1216 | } | |
1217 | ||
80128ff7 | 1218 | /* turn off voltage */ |
de957c89 MT |
1219 | voltage_set(0, 0, 0); |
1220 | voltage_set(1, 0, 0); | |
1221 | ||
80128ff7 | 1222 | /* Enable external hardware */ |
de957c89 MT |
1223 | hardware_enable(0); |
1224 | hardware_enable(1); | |
1225 | ||
99121c0d | 1226 | for (i = 0; i < PCMCIA_SOCKETS_NO; i++) { |
de957c89 MT |
1227 | socket[i].slot = i; |
1228 | socket[i].socket.owner = THIS_MODULE; | |
99121c0d VB |
1229 | socket[i].socket.features = |
1230 | SS_CAP_PCCARD | SS_CAP_MEM_ALIGN | SS_CAP_STATIC_MAP; | |
de957c89 MT |
1231 | socket[i].socket.irq_mask = 0x000; |
1232 | socket[i].socket.map_size = 0x1000; | |
1233 | socket[i].socket.io_offset = 0; | |
80128ff7 | 1234 | socket[i].socket.pci_irq = pcmcia_schlvl; |
de957c89 | 1235 | socket[i].socket.ops = &m8xx_services; |
80128ff7 | 1236 | socket[i].socket.resource_ops = &pccard_nonstatic_ops; |
de957c89 | 1237 | socket[i].socket.cb_dev = NULL; |
80128ff7 VB |
1238 | socket[i].socket.dev.parent = &ofdev->dev; |
1239 | socket[i].pcmcia = pcmcia; | |
1240 | socket[i].bus_freq = ppc_proc_freq; | |
1241 | socket[i].hwirq = hwirq; | |
1242 | ||
de957c89 MT |
1243 | } |
1244 | ||
80128ff7 VB |
1245 | for (i = 0; i < PCMCIA_SOCKETS_NO; i++) { |
1246 | status = pcmcia_register_socket(&socket[i].socket); | |
1247 | if (status < 0) | |
1248 | pcmcia_error("Socket register failed\n"); | |
1249 | } | |
de957c89 MT |
1250 | |
1251 | return 0; | |
1252 | } | |
1253 | ||
99121c0d | 1254 | static int m8xx_remove(struct of_device *ofdev) |
de957c89 | 1255 | { |
80128ff7 VB |
1256 | u32 m, i; |
1257 | struct pcmcia_win *w; | |
1258 | pcmconf8xx_t *pcmcia = socket[0].pcmcia; | |
1259 | ||
1260 | for (i = 0; i < PCMCIA_SOCKETS_NO; i++) { | |
99121c0d | 1261 | w = (void *)&pcmcia->pcmc_pbr0; |
80128ff7 VB |
1262 | |
1263 | out_be32(&pcmcia->pcmc_pscr, M8XX_PCMCIA_MASK(i)); | |
1264 | out_be32(&pcmcia->pcmc_per, | |
99121c0d | 1265 | in_be32(&pcmcia->pcmc_per) & ~M8XX_PCMCIA_MASK(i)); |
de957c89 | 1266 | |
80128ff7 VB |
1267 | /* turn off interrupt and disable CxOE */ |
1268 | out_be32(M8XX_PGCRX(i), M8XX_PGCRX_CXOE); | |
1269 | ||
1270 | /* turn off memory windows */ | |
1271 | for (m = 0; m < PCMCIA_MEM_WIN_NO; m++) { | |
99121c0d | 1272 | out_be32(&w->or, 0); /* set to not valid */ |
80128ff7 VB |
1273 | w++; |
1274 | } | |
1275 | ||
1276 | /* turn off voltage */ | |
1277 | voltage_set(i, 0, 0); | |
1278 | ||
1279 | /* disable external hardware */ | |
1280 | hardware_disable(i); | |
1281 | } | |
de957c89 MT |
1282 | for (i = 0; i < PCMCIA_SOCKETS_NO; i++) |
1283 | pcmcia_unregister_socket(&socket[i].socket); | |
5a1c3e1a | 1284 | iounmap(pcmcia); |
de957c89 | 1285 | |
80128ff7 | 1286 | free_irq(pcmcia_schlvl, NULL); |
de957c89 | 1287 | |
80128ff7 VB |
1288 | return 0; |
1289 | } | |
1290 | ||
1291 | #ifdef CONFIG_PM | |
1292 | static int m8xx_suspend(struct platform_device *pdev, pm_message_t state) | |
1293 | { | |
827b4649 | 1294 | return pcmcia_socket_dev_suspend(&pdev->dev); |
80128ff7 VB |
1295 | } |
1296 | ||
1297 | static int m8xx_resume(struct platform_device *pdev) | |
1298 | { | |
1299 | return pcmcia_socket_dev_resume(&pdev->dev); | |
1300 | } | |
1301 | #else | |
1302 | #define m8xx_suspend NULL | |
1303 | #define m8xx_resume NULL | |
1304 | #endif | |
1305 | ||
1306 | static struct of_device_id m8xx_pcmcia_match[] = { | |
1307 | { | |
99121c0d VB |
1308 | .type = "pcmcia", |
1309 | .compatible = "fsl,pq-pcmcia", | |
1310 | }, | |
80128ff7 VB |
1311 | {}, |
1312 | }; | |
1313 | ||
1314 | MODULE_DEVICE_TABLE(of, m8xx_pcmcia_match); | |
1315 | ||
1316 | static struct of_platform_driver m8xx_pcmcia_driver = { | |
8bf8df71 | 1317 | .name = driver_name, |
99121c0d VB |
1318 | .match_table = m8xx_pcmcia_match, |
1319 | .probe = m8xx_probe, | |
1320 | .remove = m8xx_remove, | |
1321 | .suspend = m8xx_suspend, | |
1322 | .resume = m8xx_resume, | |
80128ff7 VB |
1323 | }; |
1324 | ||
1325 | static int __init m8xx_init(void) | |
1326 | { | |
1327 | return of_register_platform_driver(&m8xx_pcmcia_driver); | |
1328 | } | |
1329 | ||
1330 | static void __exit m8xx_exit(void) | |
1331 | { | |
1332 | of_unregister_platform_driver(&m8xx_pcmcia_driver); | |
de957c89 MT |
1333 | } |
1334 | ||
1335 | module_init(m8xx_init); | |
1336 | module_exit(m8xx_exit); |