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Commit | Line | Data |
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1da177e4 LT |
1 | /*====================================================================== |
2 | ||
3 | Device driver for the PCMCIA control functionality of PXA2xx | |
4 | microprocessors. | |
5 | ||
6 | The contents of this file may be used under the | |
7 | terms of the GNU Public License version 2 (the "GPL") | |
8 | ||
9 | (c) Ian Molton (spyro@f2s.com) 2003 | |
10 | (c) Stefan Eletzhofer (stefan.eletzhofer@inquant.de) 2003,4 | |
11 | ||
12 | derived from sa11xx_base.c | |
13 | ||
14 | Portions created by John G. Dorsey are | |
15 | Copyright (C) 1999 John G. Dorsey. | |
16 | ||
17 | ======================================================================*/ | |
18 | ||
19 | #include <linux/module.h> | |
5a0e3ad6 | 20 | #include <linux/slab.h> |
1da177e4 | 21 | #include <linux/init.h> |
1da177e4 LT |
22 | #include <linux/cpufreq.h> |
23 | #include <linux/ioport.h> | |
24 | #include <linux/kernel.h> | |
25 | #include <linux/spinlock.h> | |
d052d1be | 26 | #include <linux/platform_device.h> |
1da177e4 | 27 | |
a09e64fb | 28 | #include <mach/hardware.h> |
ad68bb9f | 29 | #include <mach/smemc.h> |
1da177e4 LT |
30 | #include <asm/io.h> |
31 | #include <asm/irq.h> | |
a09e64fb | 32 | #include <mach/pxa2xx-regs.h> |
20f18ff3 | 33 | #include <asm/mach-types.h> |
1da177e4 | 34 | |
1da177e4 | 35 | #include <pcmcia/ss.h> |
1da177e4 LT |
36 | #include <pcmcia/cistpl.h> |
37 | ||
1da177e4 LT |
38 | #include "soc_common.h" |
39 | #include "pxa2xx_base.h" | |
40 | ||
b393c696 EM |
41 | /* |
42 | * Personal Computer Memory Card International Association (PCMCIA) sockets | |
43 | */ | |
44 | ||
45 | #define PCMCIAPrtSp 0x04000000 /* PCMCIA Partition Space [byte] */ | |
46 | #define PCMCIASp (4*PCMCIAPrtSp) /* PCMCIA Space [byte] */ | |
47 | #define PCMCIAIOSp PCMCIAPrtSp /* PCMCIA I/O Space [byte] */ | |
48 | #define PCMCIAAttrSp PCMCIAPrtSp /* PCMCIA Attribute Space [byte] */ | |
49 | #define PCMCIAMemSp PCMCIAPrtSp /* PCMCIA Memory Space [byte] */ | |
50 | ||
51 | #define PCMCIA0Sp PCMCIASp /* PCMCIA 0 Space [byte] */ | |
52 | #define PCMCIA0IOSp PCMCIAIOSp /* PCMCIA 0 I/O Space [byte] */ | |
53 | #define PCMCIA0AttrSp PCMCIAAttrSp /* PCMCIA 0 Attribute Space [byte] */ | |
54 | #define PCMCIA0MemSp PCMCIAMemSp /* PCMCIA 0 Memory Space [byte] */ | |
55 | ||
56 | #define PCMCIA1Sp PCMCIASp /* PCMCIA 1 Space [byte] */ | |
57 | #define PCMCIA1IOSp PCMCIAIOSp /* PCMCIA 1 I/O Space [byte] */ | |
58 | #define PCMCIA1AttrSp PCMCIAAttrSp /* PCMCIA 1 Attribute Space [byte] */ | |
59 | #define PCMCIA1MemSp PCMCIAMemSp /* PCMCIA 1 Memory Space [byte] */ | |
60 | ||
61 | #define _PCMCIA(Nb) /* PCMCIA [0..1] */ \ | |
62 | (0x20000000 + (Nb) * PCMCIASp) | |
63 | #define _PCMCIAIO(Nb) _PCMCIA(Nb) /* PCMCIA I/O [0..1] */ | |
64 | #define _PCMCIAAttr(Nb) /* PCMCIA Attribute [0..1] */ \ | |
65 | (_PCMCIA(Nb) + 2 * PCMCIAPrtSp) | |
66 | #define _PCMCIAMem(Nb) /* PCMCIA Memory [0..1] */ \ | |
67 | (_PCMCIA(Nb) + 3 * PCMCIAPrtSp) | |
68 | ||
69 | #define _PCMCIA0 _PCMCIA(0) /* PCMCIA 0 */ | |
70 | #define _PCMCIA0IO _PCMCIAIO(0) /* PCMCIA 0 I/O */ | |
71 | #define _PCMCIA0Attr _PCMCIAAttr(0) /* PCMCIA 0 Attribute */ | |
72 | #define _PCMCIA0Mem _PCMCIAMem(0) /* PCMCIA 0 Memory */ | |
73 | ||
74 | #define _PCMCIA1 _PCMCIA(1) /* PCMCIA 1 */ | |
75 | #define _PCMCIA1IO _PCMCIAIO(1) /* PCMCIA 1 I/O */ | |
76 | #define _PCMCIA1Attr _PCMCIAAttr(1) /* PCMCIA 1 Attribute */ | |
77 | #define _PCMCIA1Mem _PCMCIAMem(1) /* PCMCIA 1 Memory */ | |
78 | ||
1da177e4 LT |
79 | |
80 | #define MCXX_SETUP_MASK (0x7f) | |
81 | #define MCXX_ASST_MASK (0x1f) | |
82 | #define MCXX_HOLD_MASK (0x3f) | |
83 | #define MCXX_SETUP_SHIFT (0) | |
84 | #define MCXX_ASST_SHIFT (7) | |
85 | #define MCXX_HOLD_SHIFT (14) | |
86 | ||
87 | static inline u_int pxa2xx_mcxx_hold(u_int pcmcia_cycle_ns, | |
88 | u_int mem_clk_10khz) | |
89 | { | |
90 | u_int code = pcmcia_cycle_ns * mem_clk_10khz; | |
91 | return (code / 300000) + ((code % 300000) ? 1 : 0) - 1; | |
92 | } | |
93 | ||
94 | static inline u_int pxa2xx_mcxx_asst(u_int pcmcia_cycle_ns, | |
95 | u_int mem_clk_10khz) | |
96 | { | |
97 | u_int code = pcmcia_cycle_ns * mem_clk_10khz; | |
24d6572b | 98 | return (code / 300000) + ((code % 300000) ? 1 : 0) + 1; |
1da177e4 LT |
99 | } |
100 | ||
101 | static inline u_int pxa2xx_mcxx_setup(u_int pcmcia_cycle_ns, | |
102 | u_int mem_clk_10khz) | |
103 | { | |
104 | u_int code = pcmcia_cycle_ns * mem_clk_10khz; | |
105 | return (code / 100000) + ((code % 100000) ? 1 : 0) - 1; | |
106 | } | |
107 | ||
108 | /* This function returns the (approximate) command assertion period, in | |
109 | * nanoseconds, for a given CPU clock frequency and MCXX_ASST value: | |
110 | */ | |
111 | static inline u_int pxa2xx_pcmcia_cmd_time(u_int mem_clk_10khz, | |
112 | u_int pcmcia_mcxx_asst) | |
113 | { | |
114 | return (300000 * (pcmcia_mcxx_asst + 1) / mem_clk_10khz); | |
115 | } | |
116 | ||
117 | static int pxa2xx_pcmcia_set_mcmem( int sock, int speed, int clock ) | |
118 | { | |
ad68bb9f MV |
119 | uint32_t val; |
120 | ||
121 | val = ((pxa2xx_mcxx_setup(speed, clock) | |
1da177e4 LT |
122 | & MCXX_SETUP_MASK) << MCXX_SETUP_SHIFT) |
123 | | ((pxa2xx_mcxx_asst(speed, clock) | |
124 | & MCXX_ASST_MASK) << MCXX_ASST_SHIFT) | |
125 | | ((pxa2xx_mcxx_hold(speed, clock) | |
126 | & MCXX_HOLD_MASK) << MCXX_HOLD_SHIFT); | |
127 | ||
ad68bb9f MV |
128 | __raw_writel(val, MCMEM(sock)); |
129 | ||
1da177e4 LT |
130 | return 0; |
131 | } | |
132 | ||
133 | static int pxa2xx_pcmcia_set_mcio( int sock, int speed, int clock ) | |
134 | { | |
ad68bb9f MV |
135 | uint32_t val; |
136 | ||
137 | val = ((pxa2xx_mcxx_setup(speed, clock) | |
1da177e4 LT |
138 | & MCXX_SETUP_MASK) << MCXX_SETUP_SHIFT) |
139 | | ((pxa2xx_mcxx_asst(speed, clock) | |
140 | & MCXX_ASST_MASK) << MCXX_ASST_SHIFT) | |
141 | | ((pxa2xx_mcxx_hold(speed, clock) | |
142 | & MCXX_HOLD_MASK) << MCXX_HOLD_SHIFT); | |
143 | ||
ad68bb9f MV |
144 | __raw_writel(val, MCIO(sock)); |
145 | ||
1da177e4 LT |
146 | return 0; |
147 | } | |
148 | ||
149 | static int pxa2xx_pcmcia_set_mcatt( int sock, int speed, int clock ) | |
150 | { | |
ad68bb9f MV |
151 | uint32_t val; |
152 | ||
153 | val = ((pxa2xx_mcxx_setup(speed, clock) | |
1da177e4 LT |
154 | & MCXX_SETUP_MASK) << MCXX_SETUP_SHIFT) |
155 | | ((pxa2xx_mcxx_asst(speed, clock) | |
156 | & MCXX_ASST_MASK) << MCXX_ASST_SHIFT) | |
157 | | ((pxa2xx_mcxx_hold(speed, clock) | |
158 | & MCXX_HOLD_MASK) << MCXX_HOLD_SHIFT); | |
159 | ||
ad68bb9f MV |
160 | __raw_writel(val, MCATT(sock)); |
161 | ||
1da177e4 LT |
162 | return 0; |
163 | } | |
164 | ||
165 | static int pxa2xx_pcmcia_set_mcxx(struct soc_pcmcia_socket *skt, unsigned int clk) | |
166 | { | |
167 | struct soc_pcmcia_timing timing; | |
168 | int sock = skt->nr; | |
169 | ||
170 | soc_common_pcmcia_get_timing(skt, &timing); | |
171 | ||
172 | pxa2xx_pcmcia_set_mcmem(sock, timing.mem, clk); | |
173 | pxa2xx_pcmcia_set_mcatt(sock, timing.attr, clk); | |
174 | pxa2xx_pcmcia_set_mcio(sock, timing.io, clk); | |
175 | ||
176 | return 0; | |
177 | } | |
178 | ||
179 | static int pxa2xx_pcmcia_set_timing(struct soc_pcmcia_socket *skt) | |
180 | { | |
2a125dd5 EM |
181 | unsigned long clk = clk_get_rate(skt->clk); |
182 | return pxa2xx_pcmcia_set_mcxx(skt, clk / 10000); | |
1da177e4 LT |
183 | } |
184 | ||
185 | #ifdef CONFIG_CPU_FREQ | |
186 | ||
187 | static int | |
188 | pxa2xx_pcmcia_frequency_change(struct soc_pcmcia_socket *skt, | |
189 | unsigned long val, | |
190 | struct cpufreq_freqs *freqs) | |
191 | { | |
1da177e4 LT |
192 | switch (val) { |
193 | case CPUFREQ_PRECHANGE: | |
194 | if (freqs->new > freqs->old) { | |
195 | debug(skt, 2, "new frequency %u.%uMHz > %u.%uMHz, " | |
196 | "pre-updating\n", | |
197 | freqs->new / 1000, (freqs->new / 100) % 10, | |
198 | freqs->old / 1000, (freqs->old / 100) % 10); | |
d344a21a | 199 | pxa2xx_pcmcia_set_timing(skt); |
1da177e4 LT |
200 | } |
201 | break; | |
202 | ||
203 | case CPUFREQ_POSTCHANGE: | |
204 | if (freqs->new < freqs->old) { | |
205 | debug(skt, 2, "new frequency %u.%uMHz < %u.%uMHz, " | |
206 | "post-updating\n", | |
207 | freqs->new / 1000, (freqs->new / 100) % 10, | |
208 | freqs->old / 1000, (freqs->old / 100) % 10); | |
d344a21a | 209 | pxa2xx_pcmcia_set_timing(skt); |
1da177e4 LT |
210 | } |
211 | break; | |
212 | } | |
213 | return 0; | |
214 | } | |
215 | #endif | |
216 | ||
5b703683 | 217 | void pxa2xx_configure_sockets(struct device *dev) |
20f18ff3 MZ |
218 | { |
219 | struct pcmcia_low_level *ops = dev->platform_data; | |
20f18ff3 MZ |
220 | /* |
221 | * We have at least one socket, so set MECR:CIT | |
222 | * (Card Is There) | |
223 | */ | |
ad68bb9f | 224 | uint32_t mecr = MECR_CIT; |
20f18ff3 MZ |
225 | |
226 | /* Set MECR:NOS (Number Of Sockets) */ | |
c2de1c38 MZ |
227 | if ((ops->first + ops->nr) > 1 || |
228 | machine_is_viper() || machine_is_arcom_zeus()) | |
ad68bb9f MV |
229 | mecr |= MECR_NOS; |
230 | ||
231 | __raw_writel(mecr, MECR); | |
20f18ff3 | 232 | } |
d5240dfd | 233 | EXPORT_SYMBOL(pxa2xx_configure_sockets); |
20f18ff3 | 234 | |
b393c696 EM |
235 | static const char *skt_names[] = { |
236 | "PCMCIA socket 0", | |
237 | "PCMCIA socket 1", | |
238 | }; | |
239 | ||
240 | #define SKT_DEV_INFO_SIZE(n) \ | |
241 | (sizeof(struct skt_dev_info) + (n)*sizeof(struct soc_pcmcia_socket)) | |
242 | ||
701a5dc0 | 243 | int pxa2xx_drv_pcmcia_add_one(struct soc_pcmcia_socket *skt) |
da4f0073 RKAL |
244 | { |
245 | skt->res_skt.start = _PCMCIA(skt->nr); | |
246 | skt->res_skt.end = _PCMCIA(skt->nr) + PCMCIASp - 1; | |
247 | skt->res_skt.name = skt_names[skt->nr]; | |
248 | skt->res_skt.flags = IORESOURCE_MEM; | |
249 | ||
250 | skt->res_io.start = _PCMCIAIO(skt->nr); | |
251 | skt->res_io.end = _PCMCIAIO(skt->nr) + PCMCIAIOSp - 1; | |
252 | skt->res_io.name = "io"; | |
253 | skt->res_io.flags = IORESOURCE_MEM | IORESOURCE_BUSY; | |
254 | ||
255 | skt->res_mem.start = _PCMCIAMem(skt->nr); | |
256 | skt->res_mem.end = _PCMCIAMem(skt->nr) + PCMCIAMemSp - 1; | |
257 | skt->res_mem.name = "memory"; | |
258 | skt->res_mem.flags = IORESOURCE_MEM; | |
259 | ||
260 | skt->res_attr.start = _PCMCIAAttr(skt->nr); | |
261 | skt->res_attr.end = _PCMCIAAttr(skt->nr) + PCMCIAAttrSp - 1; | |
262 | skt->res_attr.name = "attribute"; | |
263 | skt->res_attr.flags = IORESOURCE_MEM; | |
264 | ||
265 | return soc_pcmcia_add_one(skt); | |
266 | } | |
d0d26c33 | 267 | EXPORT_SYMBOL(pxa2xx_drv_pcmcia_add_one); |
da4f0073 | 268 | |
701a5dc0 RKAL |
269 | void pxa2xx_drv_pcmcia_ops(struct pcmcia_low_level *ops) |
270 | { | |
271 | /* Provide our PXA2xx specific timing routines. */ | |
272 | ops->set_timing = pxa2xx_pcmcia_set_timing; | |
273 | #ifdef CONFIG_CPU_FREQ | |
274 | ops->frequency_change = pxa2xx_pcmcia_frequency_change; | |
275 | #endif | |
276 | } | |
d0d26c33 | 277 | EXPORT_SYMBOL(pxa2xx_drv_pcmcia_ops); |
701a5dc0 | 278 | |
d0d26c33 | 279 | static int pxa2xx_drv_pcmcia_probe(struct platform_device *dev) |
1da177e4 | 280 | { |
701a5dc0 | 281 | int i, ret = 0; |
1da177e4 | 282 | struct pcmcia_low_level *ops; |
b393c696 EM |
283 | struct skt_dev_info *sinfo; |
284 | struct soc_pcmcia_socket *skt; | |
2a125dd5 | 285 | struct clk *clk; |
1da177e4 | 286 | |
d0d26c33 | 287 | ops = (struct pcmcia_low_level *)dev->dev.platform_data; |
a4257af5 MV |
288 | if (!ops) { |
289 | ret = -ENODEV; | |
290 | goto err0; | |
291 | } | |
292 | ||
293 | if (cpu_is_pxa320() && ops->nr > 1) { | |
294 | dev_err(&dev->dev, "pxa320 supports only one pcmcia slot"); | |
295 | ret = -EINVAL; | |
296 | goto err0; | |
297 | } | |
1da177e4 | 298 | |
2a125dd5 | 299 | clk = clk_get(&dev->dev, NULL); |
e09a7164 | 300 | if (IS_ERR(clk)) |
2a125dd5 EM |
301 | return -ENODEV; |
302 | ||
701a5dc0 | 303 | pxa2xx_drv_pcmcia_ops(ops); |
da4f0073 | 304 | |
b393c696 | 305 | sinfo = kzalloc(SKT_DEV_INFO_SIZE(ops->nr), GFP_KERNEL); |
2a125dd5 EM |
306 | if (!sinfo) { |
307 | clk_put(clk); | |
b393c696 | 308 | return -ENOMEM; |
2a125dd5 | 309 | } |
b393c696 EM |
310 | |
311 | sinfo->nskt = ops->nr; | |
2a125dd5 | 312 | sinfo->clk = clk; |
b393c696 EM |
313 | |
314 | /* Initialize processor specific parameters */ | |
315 | for (i = 0; i < ops->nr; i++) { | |
316 | skt = &sinfo->skt[i]; | |
317 | ||
da4f0073 | 318 | skt->nr = ops->first + i; |
2a125dd5 | 319 | skt->clk = clk; |
e0d21178 | 320 | soc_pcmcia_init_one(skt, ops, &dev->dev); |
b393c696 | 321 | |
da4f0073 RKAL |
322 | ret = pxa2xx_drv_pcmcia_add_one(skt); |
323 | if (ret) | |
a4257af5 | 324 | goto err1; |
b393c696 EM |
325 | } |
326 | ||
8fb28231 AL |
327 | pxa2xx_configure_sockets(&dev->dev); |
328 | dev_set_drvdata(&dev->dev, sinfo); | |
1da177e4 | 329 | |
a4257af5 MV |
330 | return 0; |
331 | ||
332 | err1: | |
333 | while (--i >= 0) | |
334 | soc_pcmcia_remove_one(&sinfo->skt[i]); | |
8fb28231 | 335 | clk_put(clk); |
a4257af5 MV |
336 | kfree(sinfo); |
337 | err0: | |
1da177e4 LT |
338 | return ret; |
339 | } | |
9468613b RK |
340 | |
341 | static int pxa2xx_drv_pcmcia_remove(struct platform_device *dev) | |
342 | { | |
be85458e RKAL |
343 | struct skt_dev_info *sinfo = platform_get_drvdata(dev); |
344 | int i; | |
345 | ||
346 | platform_set_drvdata(dev, NULL); | |
347 | ||
348 | for (i = 0; i < sinfo->nskt; i++) | |
349 | soc_pcmcia_remove_one(&sinfo->skt[i]); | |
350 | ||
2a125dd5 | 351 | clk_put(sinfo->clk); |
be85458e RKAL |
352 | kfree(sinfo); |
353 | return 0; | |
9468613b RK |
354 | } |
355 | ||
85c61021 | 356 | static int pxa2xx_drv_pcmcia_resume(struct device *dev) |
1da177e4 | 357 | { |
85c61021 | 358 | pxa2xx_configure_sockets(dev); |
d7646f76 | 359 | return 0; |
1da177e4 LT |
360 | } |
361 | ||
47145210 | 362 | static const struct dev_pm_ops pxa2xx_drv_pcmcia_pm_ops = { |
85c61021 MR |
363 | .resume = pxa2xx_drv_pcmcia_resume, |
364 | }; | |
365 | ||
9468613b | 366 | static struct platform_driver pxa2xx_pcmcia_driver = { |
1da177e4 | 367 | .probe = pxa2xx_drv_pcmcia_probe, |
9468613b | 368 | .remove = pxa2xx_drv_pcmcia_remove, |
9468613b RK |
369 | .driver = { |
370 | .name = "pxa2xx-pcmcia", | |
85c61021 | 371 | .pm = &pxa2xx_drv_pcmcia_pm_ops, |
9468613b | 372 | }, |
1da177e4 LT |
373 | }; |
374 | ||
375 | static int __init pxa2xx_pcmcia_init(void) | |
376 | { | |
9468613b | 377 | return platform_driver_register(&pxa2xx_pcmcia_driver); |
1da177e4 LT |
378 | } |
379 | ||
380 | static void __exit pxa2xx_pcmcia_exit(void) | |
381 | { | |
9468613b | 382 | platform_driver_unregister(&pxa2xx_pcmcia_driver); |
1da177e4 LT |
383 | } |
384 | ||
f36598ae | 385 | fs_initcall(pxa2xx_pcmcia_init); |
1da177e4 LT |
386 | module_exit(pxa2xx_pcmcia_exit); |
387 | ||
388 | MODULE_AUTHOR("Stefan Eletzhofer <stefan.eletzhofer@inquant.de> and Ian Molton <spyro@f2s.com>"); | |
389 | MODULE_DESCRIPTION("Linux PCMCIA Card Services: PXA2xx core socket driver"); | |
390 | MODULE_LICENSE("GPL"); | |
12c2c019 | 391 | MODULE_ALIAS("platform:pxa2xx-pcmcia"); |