]>
Commit | Line | Data |
---|---|---|
1b8873a0 JI |
1 | #undef DEBUG |
2 | ||
3 | /* | |
4 | * ARM performance counter support. | |
5 | * | |
6 | * Copyright (C) 2009 picoChip Designs, Ltd., Jamie Iles | |
43eab878 | 7 | * Copyright (C) 2010 ARM Ltd., Will Deacon <will.deacon@arm.com> |
796d1295 | 8 | * |
1b8873a0 | 9 | * This code is based on the sparc64 perf event code, which is in turn based |
d39976f0 | 10 | * on the x86 code. |
1b8873a0 JI |
11 | */ |
12 | #define pr_fmt(fmt) "hw perfevents: " fmt | |
13 | ||
74cf0bc7 | 14 | #include <linux/bitmap.h> |
cc88116d | 15 | #include <linux/cpumask.h> |
da4e4f18 | 16 | #include <linux/cpu_pm.h> |
74cf0bc7 | 17 | #include <linux/export.h> |
1b8873a0 | 18 | #include <linux/kernel.h> |
fa8ad788 | 19 | #include <linux/perf/arm_pmu.h> |
49c006b9 | 20 | #include <linux/platform_device.h> |
74cf0bc7 MR |
21 | #include <linux/slab.h> |
22 | #include <linux/spinlock.h> | |
bbd64559 SB |
23 | #include <linux/irq.h> |
24 | #include <linux/irqdesc.h> | |
1b8873a0 | 25 | |
1b8873a0 | 26 | #include <asm/irq_regs.h> |
1b8873a0 | 27 | |
1b8873a0 | 28 | static int |
e1f431b5 MR |
29 | armpmu_map_cache_event(const unsigned (*cache_map) |
30 | [PERF_COUNT_HW_CACHE_MAX] | |
31 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
32 | [PERF_COUNT_HW_CACHE_RESULT_MAX], | |
33 | u64 config) | |
1b8873a0 JI |
34 | { |
35 | unsigned int cache_type, cache_op, cache_result, ret; | |
36 | ||
37 | cache_type = (config >> 0) & 0xff; | |
38 | if (cache_type >= PERF_COUNT_HW_CACHE_MAX) | |
39 | return -EINVAL; | |
40 | ||
41 | cache_op = (config >> 8) & 0xff; | |
42 | if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX) | |
43 | return -EINVAL; | |
44 | ||
45 | cache_result = (config >> 16) & 0xff; | |
46 | if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX) | |
47 | return -EINVAL; | |
48 | ||
e1f431b5 | 49 | ret = (int)(*cache_map)[cache_type][cache_op][cache_result]; |
1b8873a0 JI |
50 | |
51 | if (ret == CACHE_OP_UNSUPPORTED) | |
52 | return -ENOENT; | |
53 | ||
54 | return ret; | |
55 | } | |
56 | ||
84fee97a | 57 | static int |
6dbc0029 | 58 | armpmu_map_hw_event(const unsigned (*event_map)[PERF_COUNT_HW_MAX], u64 config) |
84fee97a | 59 | { |
d9f96635 SB |
60 | int mapping; |
61 | ||
62 | if (config >= PERF_COUNT_HW_MAX) | |
63 | return -EINVAL; | |
64 | ||
65 | mapping = (*event_map)[config]; | |
e1f431b5 | 66 | return mapping == HW_OP_UNSUPPORTED ? -ENOENT : mapping; |
84fee97a WD |
67 | } |
68 | ||
69 | static int | |
e1f431b5 | 70 | armpmu_map_raw_event(u32 raw_event_mask, u64 config) |
84fee97a | 71 | { |
e1f431b5 MR |
72 | return (int)(config & raw_event_mask); |
73 | } | |
74 | ||
6dbc0029 WD |
75 | int |
76 | armpmu_map_event(struct perf_event *event, | |
77 | const unsigned (*event_map)[PERF_COUNT_HW_MAX], | |
78 | const unsigned (*cache_map) | |
79 | [PERF_COUNT_HW_CACHE_MAX] | |
80 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
81 | [PERF_COUNT_HW_CACHE_RESULT_MAX], | |
82 | u32 raw_event_mask) | |
e1f431b5 MR |
83 | { |
84 | u64 config = event->attr.config; | |
67b4305a | 85 | int type = event->attr.type; |
e1f431b5 | 86 | |
67b4305a MR |
87 | if (type == event->pmu->type) |
88 | return armpmu_map_raw_event(raw_event_mask, config); | |
89 | ||
90 | switch (type) { | |
e1f431b5 | 91 | case PERF_TYPE_HARDWARE: |
6dbc0029 | 92 | return armpmu_map_hw_event(event_map, config); |
e1f431b5 MR |
93 | case PERF_TYPE_HW_CACHE: |
94 | return armpmu_map_cache_event(cache_map, config); | |
95 | case PERF_TYPE_RAW: | |
96 | return armpmu_map_raw_event(raw_event_mask, config); | |
97 | } | |
98 | ||
99 | return -ENOENT; | |
84fee97a WD |
100 | } |
101 | ||
ed6f2a52 | 102 | int armpmu_event_set_period(struct perf_event *event) |
1b8873a0 | 103 | { |
8a16b34e | 104 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
ed6f2a52 | 105 | struct hw_perf_event *hwc = &event->hw; |
e7850595 | 106 | s64 left = local64_read(&hwc->period_left); |
1b8873a0 JI |
107 | s64 period = hwc->sample_period; |
108 | int ret = 0; | |
109 | ||
110 | if (unlikely(left <= -period)) { | |
111 | left = period; | |
e7850595 | 112 | local64_set(&hwc->period_left, left); |
1b8873a0 JI |
113 | hwc->last_period = period; |
114 | ret = 1; | |
115 | } | |
116 | ||
117 | if (unlikely(left <= 0)) { | |
118 | left += period; | |
e7850595 | 119 | local64_set(&hwc->period_left, left); |
1b8873a0 JI |
120 | hwc->last_period = period; |
121 | ret = 1; | |
122 | } | |
123 | ||
2d9ed740 DT |
124 | /* |
125 | * Limit the maximum period to prevent the counter value | |
126 | * from overtaking the one we are about to program. In | |
127 | * effect we are reducing max_period to account for | |
128 | * interrupt latency (and we are being very conservative). | |
129 | */ | |
130 | if (left > (armpmu->max_period >> 1)) | |
131 | left = armpmu->max_period >> 1; | |
1b8873a0 | 132 | |
e7850595 | 133 | local64_set(&hwc->prev_count, (u64)-left); |
1b8873a0 | 134 | |
ed6f2a52 | 135 | armpmu->write_counter(event, (u64)(-left) & 0xffffffff); |
1b8873a0 JI |
136 | |
137 | perf_event_update_userpage(event); | |
138 | ||
139 | return ret; | |
140 | } | |
141 | ||
ed6f2a52 | 142 | u64 armpmu_event_update(struct perf_event *event) |
1b8873a0 | 143 | { |
8a16b34e | 144 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
ed6f2a52 | 145 | struct hw_perf_event *hwc = &event->hw; |
a737823d | 146 | u64 delta, prev_raw_count, new_raw_count; |
1b8873a0 JI |
147 | |
148 | again: | |
e7850595 | 149 | prev_raw_count = local64_read(&hwc->prev_count); |
ed6f2a52 | 150 | new_raw_count = armpmu->read_counter(event); |
1b8873a0 | 151 | |
e7850595 | 152 | if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, |
1b8873a0 JI |
153 | new_raw_count) != prev_raw_count) |
154 | goto again; | |
155 | ||
57273471 | 156 | delta = (new_raw_count - prev_raw_count) & armpmu->max_period; |
1b8873a0 | 157 | |
e7850595 PZ |
158 | local64_add(delta, &event->count); |
159 | local64_sub(delta, &hwc->period_left); | |
1b8873a0 JI |
160 | |
161 | return new_raw_count; | |
162 | } | |
163 | ||
164 | static void | |
a4eaf7f1 | 165 | armpmu_read(struct perf_event *event) |
1b8873a0 | 166 | { |
ed6f2a52 | 167 | armpmu_event_update(event); |
1b8873a0 JI |
168 | } |
169 | ||
170 | static void | |
a4eaf7f1 | 171 | armpmu_stop(struct perf_event *event, int flags) |
1b8873a0 | 172 | { |
8a16b34e | 173 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
1b8873a0 JI |
174 | struct hw_perf_event *hwc = &event->hw; |
175 | ||
a4eaf7f1 PZ |
176 | /* |
177 | * ARM pmu always has to update the counter, so ignore | |
178 | * PERF_EF_UPDATE, see comments in armpmu_start(). | |
179 | */ | |
180 | if (!(hwc->state & PERF_HES_STOPPED)) { | |
ed6f2a52 SH |
181 | armpmu->disable(event); |
182 | armpmu_event_update(event); | |
a4eaf7f1 PZ |
183 | hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE; |
184 | } | |
1b8873a0 JI |
185 | } |
186 | ||
ed6f2a52 | 187 | static void armpmu_start(struct perf_event *event, int flags) |
1b8873a0 | 188 | { |
8a16b34e | 189 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
1b8873a0 JI |
190 | struct hw_perf_event *hwc = &event->hw; |
191 | ||
a4eaf7f1 PZ |
192 | /* |
193 | * ARM pmu always has to reprogram the period, so ignore | |
194 | * PERF_EF_RELOAD, see the comment below. | |
195 | */ | |
196 | if (flags & PERF_EF_RELOAD) | |
197 | WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE)); | |
198 | ||
199 | hwc->state = 0; | |
1b8873a0 JI |
200 | /* |
201 | * Set the period again. Some counters can't be stopped, so when we | |
a4eaf7f1 | 202 | * were stopped we simply disabled the IRQ source and the counter |
1b8873a0 JI |
203 | * may have been left counting. If we don't do this step then we may |
204 | * get an interrupt too soon or *way* too late if the overflow has | |
205 | * happened since disabling. | |
206 | */ | |
ed6f2a52 SH |
207 | armpmu_event_set_period(event); |
208 | armpmu->enable(event); | |
1b8873a0 JI |
209 | } |
210 | ||
a4eaf7f1 PZ |
211 | static void |
212 | armpmu_del(struct perf_event *event, int flags) | |
213 | { | |
8a16b34e | 214 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
11679250 | 215 | struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events); |
a4eaf7f1 PZ |
216 | struct hw_perf_event *hwc = &event->hw; |
217 | int idx = hwc->idx; | |
218 | ||
a4eaf7f1 | 219 | armpmu_stop(event, PERF_EF_UPDATE); |
8be3f9a2 MR |
220 | hw_events->events[idx] = NULL; |
221 | clear_bit(idx, hw_events->used_mask); | |
eab443ef SB |
222 | if (armpmu->clear_event_idx) |
223 | armpmu->clear_event_idx(hw_events, event); | |
a4eaf7f1 PZ |
224 | |
225 | perf_event_update_userpage(event); | |
226 | } | |
227 | ||
1b8873a0 | 228 | static int |
a4eaf7f1 | 229 | armpmu_add(struct perf_event *event, int flags) |
1b8873a0 | 230 | { |
8a16b34e | 231 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
11679250 | 232 | struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events); |
1b8873a0 JI |
233 | struct hw_perf_event *hwc = &event->hw; |
234 | int idx; | |
1b8873a0 | 235 | |
cc88116d MR |
236 | /* An event following a process won't be stopped earlier */ |
237 | if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus)) | |
238 | return -ENOENT; | |
239 | ||
1b8873a0 | 240 | /* If we don't have a space for the counter then finish early. */ |
ed6f2a52 | 241 | idx = armpmu->get_event_idx(hw_events, event); |
528b0bcc MR |
242 | if (idx < 0) |
243 | return idx; | |
1b8873a0 JI |
244 | |
245 | /* | |
246 | * If there is an event in the counter we are going to use then make | |
247 | * sure it is disabled. | |
248 | */ | |
249 | event->hw.idx = idx; | |
ed6f2a52 | 250 | armpmu->disable(event); |
8be3f9a2 | 251 | hw_events->events[idx] = event; |
1b8873a0 | 252 | |
a4eaf7f1 PZ |
253 | hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE; |
254 | if (flags & PERF_EF_START) | |
255 | armpmu_start(event, PERF_EF_RELOAD); | |
1b8873a0 JI |
256 | |
257 | /* Propagate our changes to the userspace mapping. */ | |
258 | perf_event_update_userpage(event); | |
259 | ||
528b0bcc | 260 | return 0; |
1b8873a0 JI |
261 | } |
262 | ||
1b8873a0 | 263 | static int |
e429817b SP |
264 | validate_event(struct pmu *pmu, struct pmu_hw_events *hw_events, |
265 | struct perf_event *event) | |
1b8873a0 | 266 | { |
e429817b | 267 | struct arm_pmu *armpmu; |
1b8873a0 | 268 | |
c95eb318 WD |
269 | if (is_software_event(event)) |
270 | return 1; | |
271 | ||
e429817b SP |
272 | /* |
273 | * Reject groups spanning multiple HW PMUs (e.g. CPU + CCI). The | |
274 | * core perf code won't check that the pmu->ctx == leader->ctx | |
275 | * until after pmu->event_init(event). | |
276 | */ | |
277 | if (event->pmu != pmu) | |
278 | return 0; | |
279 | ||
2dfcb802 | 280 | if (event->state < PERF_EVENT_STATE_OFF) |
cb2d8b34 WD |
281 | return 1; |
282 | ||
283 | if (event->state == PERF_EVENT_STATE_OFF && !event->attr.enable_on_exec) | |
65b4711f | 284 | return 1; |
1b8873a0 | 285 | |
e429817b | 286 | armpmu = to_arm_pmu(event->pmu); |
ed6f2a52 | 287 | return armpmu->get_event_idx(hw_events, event) >= 0; |
1b8873a0 JI |
288 | } |
289 | ||
290 | static int | |
291 | validate_group(struct perf_event *event) | |
292 | { | |
293 | struct perf_event *sibling, *leader = event->group_leader; | |
8be3f9a2 | 294 | struct pmu_hw_events fake_pmu; |
1b8873a0 | 295 | |
bce34d14 WD |
296 | /* |
297 | * Initialise the fake PMU. We only need to populate the | |
298 | * used_mask for the purposes of validation. | |
299 | */ | |
a4560846 | 300 | memset(&fake_pmu.used_mask, 0, sizeof(fake_pmu.used_mask)); |
1b8873a0 | 301 | |
e429817b | 302 | if (!validate_event(event->pmu, &fake_pmu, leader)) |
aa2bc1ad | 303 | return -EINVAL; |
1b8873a0 JI |
304 | |
305 | list_for_each_entry(sibling, &leader->sibling_list, group_entry) { | |
e429817b | 306 | if (!validate_event(event->pmu, &fake_pmu, sibling)) |
aa2bc1ad | 307 | return -EINVAL; |
1b8873a0 JI |
308 | } |
309 | ||
e429817b | 310 | if (!validate_event(event->pmu, &fake_pmu, event)) |
aa2bc1ad | 311 | return -EINVAL; |
1b8873a0 JI |
312 | |
313 | return 0; | |
314 | } | |
315 | ||
e81ddde3 MR |
316 | static struct arm_pmu_platdata *armpmu_get_platdata(struct arm_pmu *armpmu) |
317 | { | |
318 | struct platform_device *pdev = armpmu->plat_device; | |
319 | ||
320 | return pdev ? dev_get_platdata(&pdev->dev) : NULL; | |
321 | } | |
322 | ||
051f1b13 | 323 | static irqreturn_t armpmu_dispatch_irq(int irq, void *dev) |
0e25a5c9 | 324 | { |
bbd64559 | 325 | struct arm_pmu *armpmu; |
bbd64559 | 326 | struct arm_pmu_platdata *plat; |
5f5092e7 WD |
327 | int ret; |
328 | u64 start_clock, finish_clock; | |
bbd64559 | 329 | |
5ebd9200 MR |
330 | /* |
331 | * we request the IRQ with a (possibly percpu) struct arm_pmu**, but | |
332 | * the handlers expect a struct arm_pmu*. The percpu_irq framework will | |
333 | * do any necessary shifting, we just need to perform the first | |
334 | * dereference. | |
335 | */ | |
336 | armpmu = *(void **)dev; | |
e81ddde3 MR |
337 | |
338 | plat = armpmu_get_platdata(armpmu); | |
0e25a5c9 | 339 | |
5f5092e7 | 340 | start_clock = sched_clock(); |
051f1b13 | 341 | if (plat && plat->handle_irq) |
5ebd9200 | 342 | ret = plat->handle_irq(irq, armpmu, armpmu->handle_irq); |
051f1b13 | 343 | else |
5ebd9200 | 344 | ret = armpmu->handle_irq(irq, armpmu); |
5f5092e7 WD |
345 | finish_clock = sched_clock(); |
346 | ||
347 | perf_sample_event_took(finish_clock - start_clock); | |
348 | return ret; | |
0e25a5c9 RV |
349 | } |
350 | ||
05d22fde WD |
351 | static int |
352 | event_requires_mode_exclusion(struct perf_event_attr *attr) | |
353 | { | |
354 | return attr->exclude_idle || attr->exclude_user || | |
355 | attr->exclude_kernel || attr->exclude_hv; | |
356 | } | |
357 | ||
1b8873a0 JI |
358 | static int |
359 | __hw_perf_event_init(struct perf_event *event) | |
360 | { | |
8a16b34e | 361 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
1b8873a0 | 362 | struct hw_perf_event *hwc = &event->hw; |
9dcbf466 | 363 | int mapping; |
1b8873a0 | 364 | |
e1f431b5 | 365 | mapping = armpmu->map_event(event); |
1b8873a0 JI |
366 | |
367 | if (mapping < 0) { | |
368 | pr_debug("event %x:%llx not supported\n", event->attr.type, | |
369 | event->attr.config); | |
370 | return mapping; | |
371 | } | |
372 | ||
05d22fde WD |
373 | /* |
374 | * We don't assign an index until we actually place the event onto | |
375 | * hardware. Use -1 to signify that we haven't decided where to put it | |
376 | * yet. For SMP systems, each core has it's own PMU so we can't do any | |
377 | * clever allocation or constraints checking at this point. | |
378 | */ | |
379 | hwc->idx = -1; | |
380 | hwc->config_base = 0; | |
381 | hwc->config = 0; | |
382 | hwc->event_base = 0; | |
383 | ||
1b8873a0 JI |
384 | /* |
385 | * Check whether we need to exclude the counter from certain modes. | |
1b8873a0 | 386 | */ |
05d22fde WD |
387 | if ((!armpmu->set_event_filter || |
388 | armpmu->set_event_filter(hwc, &event->attr)) && | |
389 | event_requires_mode_exclusion(&event->attr)) { | |
1b8873a0 JI |
390 | pr_debug("ARM performance counters do not support " |
391 | "mode exclusion\n"); | |
fdeb8e35 | 392 | return -EOPNOTSUPP; |
1b8873a0 JI |
393 | } |
394 | ||
395 | /* | |
05d22fde | 396 | * Store the event encoding into the config_base field. |
1b8873a0 | 397 | */ |
05d22fde | 398 | hwc->config_base |= (unsigned long)mapping; |
1b8873a0 | 399 | |
edcb4d3c | 400 | if (!is_sampling_event(event)) { |
57273471 WD |
401 | /* |
402 | * For non-sampling runs, limit the sample_period to half | |
403 | * of the counter width. That way, the new counter value | |
404 | * is far less likely to overtake the previous one unless | |
405 | * you have some serious IRQ latency issues. | |
406 | */ | |
407 | hwc->sample_period = armpmu->max_period >> 1; | |
1b8873a0 | 408 | hwc->last_period = hwc->sample_period; |
e7850595 | 409 | local64_set(&hwc->period_left, hwc->sample_period); |
1b8873a0 JI |
410 | } |
411 | ||
1b8873a0 | 412 | if (event->group_leader != event) { |
e595ede6 | 413 | if (validate_group(event) != 0) |
1b8873a0 JI |
414 | return -EINVAL; |
415 | } | |
416 | ||
9dcbf466 | 417 | return 0; |
1b8873a0 JI |
418 | } |
419 | ||
b0a873eb | 420 | static int armpmu_event_init(struct perf_event *event) |
1b8873a0 | 421 | { |
8a16b34e | 422 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
1b8873a0 | 423 | |
cc88116d MR |
424 | /* |
425 | * Reject CPU-affine events for CPUs that are of a different class to | |
426 | * that which this PMU handles. Process-following events (where | |
427 | * event->cpu == -1) can be migrated between CPUs, and thus we have to | |
428 | * reject them later (in armpmu_add) if they're scheduled on a | |
429 | * different class of CPU. | |
430 | */ | |
431 | if (event->cpu != -1 && | |
432 | !cpumask_test_cpu(event->cpu, &armpmu->supported_cpus)) | |
433 | return -ENOENT; | |
434 | ||
2481c5fa SE |
435 | /* does not support taken branch sampling */ |
436 | if (has_branch_stack(event)) | |
437 | return -EOPNOTSUPP; | |
438 | ||
e1f431b5 | 439 | if (armpmu->map_event(event) == -ENOENT) |
b0a873eb | 440 | return -ENOENT; |
b0a873eb | 441 | |
e16592b0 | 442 | return __hw_perf_event_init(event); |
1b8873a0 JI |
443 | } |
444 | ||
a4eaf7f1 | 445 | static void armpmu_enable(struct pmu *pmu) |
1b8873a0 | 446 | { |
8be3f9a2 | 447 | struct arm_pmu *armpmu = to_arm_pmu(pmu); |
11679250 | 448 | struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events); |
7325eaec | 449 | int enabled = bitmap_weight(hw_events->used_mask, armpmu->num_events); |
1b8873a0 | 450 | |
cc88116d MR |
451 | /* For task-bound events we may be called on other CPUs */ |
452 | if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus)) | |
453 | return; | |
454 | ||
f4f38430 | 455 | if (enabled) |
ed6f2a52 | 456 | armpmu->start(armpmu); |
1b8873a0 JI |
457 | } |
458 | ||
a4eaf7f1 | 459 | static void armpmu_disable(struct pmu *pmu) |
1b8873a0 | 460 | { |
8a16b34e | 461 | struct arm_pmu *armpmu = to_arm_pmu(pmu); |
cc88116d MR |
462 | |
463 | /* For task-bound events we may be called on other CPUs */ | |
464 | if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus)) | |
465 | return; | |
466 | ||
ed6f2a52 | 467 | armpmu->stop(armpmu); |
1b8873a0 JI |
468 | } |
469 | ||
c904e32a MR |
470 | /* |
471 | * In heterogeneous systems, events are specific to a particular | |
472 | * microarchitecture, and aren't suitable for another. Thus, only match CPUs of | |
473 | * the same microarchitecture. | |
474 | */ | |
475 | static int armpmu_filter_match(struct perf_event *event) | |
476 | { | |
477 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); | |
478 | unsigned int cpu = smp_processor_id(); | |
479 | return cpumask_test_cpu(cpu, &armpmu->supported_cpus); | |
480 | } | |
481 | ||
48538b58 MR |
482 | static ssize_t armpmu_cpumask_show(struct device *dev, |
483 | struct device_attribute *attr, char *buf) | |
484 | { | |
485 | struct arm_pmu *armpmu = to_arm_pmu(dev_get_drvdata(dev)); | |
486 | return cpumap_print_to_pagebuf(true, buf, &armpmu->supported_cpus); | |
487 | } | |
488 | ||
489 | static DEVICE_ATTR(cpus, S_IRUGO, armpmu_cpumask_show, NULL); | |
490 | ||
491 | static struct attribute *armpmu_common_attrs[] = { | |
492 | &dev_attr_cpus.attr, | |
493 | NULL, | |
494 | }; | |
495 | ||
496 | static struct attribute_group armpmu_common_attr_group = { | |
497 | .attrs = armpmu_common_attrs, | |
498 | }; | |
499 | ||
74cf0bc7 MR |
500 | /* Set at runtime when we know what CPU type we are. */ |
501 | static struct arm_pmu *__oprofile_cpu_pmu; | |
502 | ||
503 | /* | |
504 | * Despite the names, these two functions are CPU-specific and are used | |
505 | * by the OProfile/perf code. | |
506 | */ | |
507 | const char *perf_pmu_name(void) | |
508 | { | |
509 | if (!__oprofile_cpu_pmu) | |
510 | return NULL; | |
511 | ||
512 | return __oprofile_cpu_pmu->name; | |
513 | } | |
514 | EXPORT_SYMBOL_GPL(perf_pmu_name); | |
515 | ||
516 | int perf_num_counters(void) | |
517 | { | |
518 | int max_events = 0; | |
519 | ||
520 | if (__oprofile_cpu_pmu != NULL) | |
521 | max_events = __oprofile_cpu_pmu->num_events; | |
522 | ||
523 | return max_events; | |
524 | } | |
525 | EXPORT_SYMBOL_GPL(perf_num_counters); | |
526 | ||
ba123543 | 527 | void armpmu_free_irq(struct arm_pmu *armpmu, int cpu) |
74cf0bc7 | 528 | { |
84c2c9a0 | 529 | struct pmu_hw_events __percpu *hw_events = armpmu->hw_events; |
a5fca048 | 530 | int irq = per_cpu(hw_events->irq, cpu); |
74cf0bc7 | 531 | |
a5fca048 MR |
532 | if (!cpumask_test_and_clear_cpu(cpu, &armpmu->active_irqs)) |
533 | return; | |
ad092fd2 | 534 | |
a5fca048 MR |
535 | if (irq_is_percpu(irq)) { |
536 | free_percpu_irq(irq, &hw_events->percpu_pmu); | |
537 | cpumask_clear(&armpmu->active_irqs); | |
538 | return; | |
539 | } | |
ad092fd2 | 540 | |
a5fca048 MR |
541 | free_irq(irq, per_cpu_ptr(&hw_events->percpu_pmu, cpu)); |
542 | } | |
ad092fd2 | 543 | |
444ae70d | 544 | void armpmu_free_irqs(struct arm_pmu *armpmu) |
a5fca048 MR |
545 | { |
546 | int cpu; | |
547 | ||
548 | for_each_cpu(cpu, &armpmu->supported_cpus) | |
549 | armpmu_free_irq(armpmu, cpu); | |
74cf0bc7 MR |
550 | } |
551 | ||
ba123543 | 552 | int armpmu_request_irq(struct arm_pmu *armpmu, int cpu) |
74cf0bc7 | 553 | { |
a5fca048 | 554 | int err = 0; |
84c2c9a0 | 555 | struct pmu_hw_events __percpu *hw_events = armpmu->hw_events; |
5654f1f1 | 556 | const irq_handler_t handler = armpmu_dispatch_irq; |
a5fca048 MR |
557 | int irq = per_cpu(hw_events->irq, cpu); |
558 | if (!irq) | |
559 | return 0; | |
74cf0bc7 | 560 | |
a5fca048 MR |
561 | if (irq_is_percpu(irq) && cpumask_empty(&armpmu->active_irqs)) { |
562 | err = request_percpu_irq(irq, handler, "arm-pmu", | |
563 | &hw_events->percpu_pmu); | |
564 | } else if (irq_is_percpu(irq)) { | |
565 | int other_cpu = cpumask_first(&armpmu->active_irqs); | |
566 | int other_irq = per_cpu(hw_events->irq, other_cpu); | |
74cf0bc7 | 567 | |
a5fca048 MR |
568 | if (irq != other_irq) { |
569 | pr_warn("mismatched PPIs detected.\n"); | |
570 | err = -EINVAL; | |
ad092fd2 | 571 | } |
a5fca048 | 572 | } else { |
ad092fd2 MR |
573 | err = request_irq(irq, handler, |
574 | IRQF_NOBALANCING | IRQF_NO_THREAD, "arm-pmu", | |
575 | per_cpu_ptr(&hw_events->percpu_pmu, cpu)); | |
a5fca048 | 576 | } |
ad092fd2 | 577 | |
a5fca048 MR |
578 | if (err) { |
579 | pr_err("unable to request IRQ%d for ARM PMU counters\n", | |
580 | irq); | |
581 | return err; | |
74cf0bc7 MR |
582 | } |
583 | ||
a5fca048 MR |
584 | cpumask_set_cpu(cpu, &armpmu->active_irqs); |
585 | ||
74cf0bc7 MR |
586 | return 0; |
587 | } | |
588 | ||
444ae70d | 589 | int armpmu_request_irqs(struct arm_pmu *armpmu) |
a5fca048 MR |
590 | { |
591 | int cpu, err; | |
592 | ||
593 | for_each_cpu(cpu, &armpmu->supported_cpus) { | |
594 | err = armpmu_request_irq(armpmu, cpu); | |
595 | if (err) | |
596 | break; | |
597 | } | |
598 | ||
599 | return err; | |
600 | } | |
601 | ||
e16592b0 MR |
602 | static int armpmu_get_cpu_irq(struct arm_pmu *pmu, int cpu) |
603 | { | |
604 | struct pmu_hw_events __percpu *hw_events = pmu->hw_events; | |
605 | return per_cpu(hw_events->irq, cpu); | |
606 | } | |
607 | ||
74cf0bc7 MR |
608 | /* |
609 | * PMU hardware loses all context when a CPU goes offline. | |
610 | * When a CPU is hotplugged back in, since some hardware registers are | |
611 | * UNKNOWN at reset, the PMU must be explicitly reset to avoid reading | |
612 | * junk values out of them. | |
613 | */ | |
6e103c0c | 614 | static int arm_perf_starting_cpu(unsigned int cpu, struct hlist_node *node) |
74cf0bc7 | 615 | { |
6e103c0c | 616 | struct arm_pmu *pmu = hlist_entry_safe(node, struct arm_pmu, node); |
e16592b0 | 617 | int irq; |
74cf0bc7 | 618 | |
6e103c0c SAS |
619 | if (!cpumask_test_cpu(cpu, &pmu->supported_cpus)) |
620 | return 0; | |
621 | if (pmu->reset) | |
622 | pmu->reset(pmu); | |
e16592b0 MR |
623 | |
624 | irq = armpmu_get_cpu_irq(pmu, cpu); | |
625 | if (irq) { | |
626 | if (irq_is_percpu(irq)) { | |
627 | enable_percpu_irq(irq, IRQ_TYPE_NONE); | |
628 | return 0; | |
629 | } | |
630 | ||
631 | if (irq_force_affinity(irq, cpumask_of(cpu)) && | |
632 | num_possible_cpus() > 1) { | |
633 | pr_warn("unable to set irq affinity (irq=%d, cpu=%u)\n", | |
634 | irq, cpu); | |
635 | } | |
636 | } | |
637 | ||
638 | return 0; | |
639 | } | |
640 | ||
641 | static int arm_perf_teardown_cpu(unsigned int cpu, struct hlist_node *node) | |
642 | { | |
643 | struct arm_pmu *pmu = hlist_entry_safe(node, struct arm_pmu, node); | |
644 | int irq; | |
645 | ||
646 | if (!cpumask_test_cpu(cpu, &pmu->supported_cpus)) | |
647 | return 0; | |
648 | ||
649 | irq = armpmu_get_cpu_irq(pmu, cpu); | |
650 | if (irq && irq_is_percpu(irq)) | |
651 | disable_percpu_irq(irq); | |
652 | ||
7d88eb69 | 653 | return 0; |
74cf0bc7 MR |
654 | } |
655 | ||
da4e4f18 LP |
656 | #ifdef CONFIG_CPU_PM |
657 | static void cpu_pm_pmu_setup(struct arm_pmu *armpmu, unsigned long cmd) | |
658 | { | |
659 | struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events); | |
660 | struct perf_event *event; | |
661 | int idx; | |
662 | ||
663 | for (idx = 0; idx < armpmu->num_events; idx++) { | |
664 | /* | |
665 | * If the counter is not used skip it, there is no | |
666 | * need of stopping/restarting it. | |
667 | */ | |
668 | if (!test_bit(idx, hw_events->used_mask)) | |
669 | continue; | |
670 | ||
671 | event = hw_events->events[idx]; | |
672 | ||
673 | switch (cmd) { | |
674 | case CPU_PM_ENTER: | |
675 | /* | |
676 | * Stop and update the counter | |
677 | */ | |
678 | armpmu_stop(event, PERF_EF_UPDATE); | |
679 | break; | |
680 | case CPU_PM_EXIT: | |
681 | case CPU_PM_ENTER_FAILED: | |
cbcc72e0 LP |
682 | /* |
683 | * Restore and enable the counter. | |
684 | * armpmu_start() indirectly calls | |
685 | * | |
686 | * perf_event_update_userpage() | |
687 | * | |
688 | * that requires RCU read locking to be functional, | |
689 | * wrap the call within RCU_NONIDLE to make the | |
690 | * RCU subsystem aware this cpu is not idle from | |
691 | * an RCU perspective for the armpmu_start() call | |
692 | * duration. | |
693 | */ | |
694 | RCU_NONIDLE(armpmu_start(event, PERF_EF_RELOAD)); | |
da4e4f18 LP |
695 | break; |
696 | default: | |
697 | break; | |
698 | } | |
699 | } | |
700 | } | |
701 | ||
702 | static int cpu_pm_pmu_notify(struct notifier_block *b, unsigned long cmd, | |
703 | void *v) | |
704 | { | |
705 | struct arm_pmu *armpmu = container_of(b, struct arm_pmu, cpu_pm_nb); | |
706 | struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events); | |
707 | int enabled = bitmap_weight(hw_events->used_mask, armpmu->num_events); | |
708 | ||
709 | if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus)) | |
710 | return NOTIFY_DONE; | |
711 | ||
712 | /* | |
713 | * Always reset the PMU registers on power-up even if | |
714 | * there are no events running. | |
715 | */ | |
716 | if (cmd == CPU_PM_EXIT && armpmu->reset) | |
717 | armpmu->reset(armpmu); | |
718 | ||
719 | if (!enabled) | |
720 | return NOTIFY_OK; | |
721 | ||
722 | switch (cmd) { | |
723 | case CPU_PM_ENTER: | |
724 | armpmu->stop(armpmu); | |
725 | cpu_pm_pmu_setup(armpmu, cmd); | |
726 | break; | |
727 | case CPU_PM_EXIT: | |
728 | cpu_pm_pmu_setup(armpmu, cmd); | |
729 | case CPU_PM_ENTER_FAILED: | |
730 | armpmu->start(armpmu); | |
731 | break; | |
732 | default: | |
733 | return NOTIFY_DONE; | |
734 | } | |
735 | ||
736 | return NOTIFY_OK; | |
737 | } | |
738 | ||
739 | static int cpu_pm_pmu_register(struct arm_pmu *cpu_pmu) | |
740 | { | |
741 | cpu_pmu->cpu_pm_nb.notifier_call = cpu_pm_pmu_notify; | |
742 | return cpu_pm_register_notifier(&cpu_pmu->cpu_pm_nb); | |
743 | } | |
744 | ||
745 | static void cpu_pm_pmu_unregister(struct arm_pmu *cpu_pmu) | |
746 | { | |
747 | cpu_pm_unregister_notifier(&cpu_pmu->cpu_pm_nb); | |
748 | } | |
749 | #else | |
750 | static inline int cpu_pm_pmu_register(struct arm_pmu *cpu_pmu) { return 0; } | |
751 | static inline void cpu_pm_pmu_unregister(struct arm_pmu *cpu_pmu) { } | |
752 | #endif | |
753 | ||
74cf0bc7 MR |
754 | static int cpu_pmu_init(struct arm_pmu *cpu_pmu) |
755 | { | |
756 | int err; | |
74cf0bc7 | 757 | |
e16592b0 MR |
758 | err = cpuhp_state_add_instance(CPUHP_AP_PERF_ARM_STARTING, |
759 | &cpu_pmu->node); | |
6e103c0c | 760 | if (err) |
ef5eb2c7 | 761 | goto out; |
74cf0bc7 | 762 | |
da4e4f18 LP |
763 | err = cpu_pm_pmu_register(cpu_pmu); |
764 | if (err) | |
765 | goto out_unregister; | |
766 | ||
74cf0bc7 MR |
767 | return 0; |
768 | ||
da4e4f18 | 769 | out_unregister: |
6e103c0c SAS |
770 | cpuhp_state_remove_instance_nocalls(CPUHP_AP_PERF_ARM_STARTING, |
771 | &cpu_pmu->node); | |
ef5eb2c7 | 772 | out: |
74cf0bc7 MR |
773 | return err; |
774 | } | |
775 | ||
776 | static void cpu_pmu_destroy(struct arm_pmu *cpu_pmu) | |
777 | { | |
da4e4f18 | 778 | cpu_pm_pmu_unregister(cpu_pmu); |
6e103c0c SAS |
779 | cpuhp_state_remove_instance_nocalls(CPUHP_AP_PERF_ARM_STARTING, |
780 | &cpu_pmu->node); | |
74cf0bc7 MR |
781 | } |
782 | ||
444ae70d | 783 | struct arm_pmu *armpmu_alloc(void) |
ef5eb2c7 MR |
784 | { |
785 | struct arm_pmu *pmu; | |
786 | int cpu; | |
787 | ||
788 | pmu = kzalloc(sizeof(*pmu), GFP_KERNEL); | |
789 | if (!pmu) { | |
790 | pr_info("failed to allocate PMU device!\n"); | |
791 | goto out; | |
792 | } | |
793 | ||
794 | pmu->hw_events = alloc_percpu(struct pmu_hw_events); | |
795 | if (!pmu->hw_events) { | |
796 | pr_info("failed to allocate per-cpu PMU data.\n"); | |
797 | goto out_free_pmu; | |
798 | } | |
799 | ||
7ef92d79 MR |
800 | pmu->pmu = (struct pmu) { |
801 | .pmu_enable = armpmu_enable, | |
802 | .pmu_disable = armpmu_disable, | |
803 | .event_init = armpmu_event_init, | |
804 | .add = armpmu_add, | |
805 | .del = armpmu_del, | |
806 | .start = armpmu_start, | |
807 | .stop = armpmu_stop, | |
808 | .read = armpmu_read, | |
809 | .filter_match = armpmu_filter_match, | |
810 | .attr_groups = pmu->attr_groups, | |
811 | /* | |
812 | * This is a CPU PMU potentially in a heterogeneous | |
813 | * configuration (e.g. big.LITTLE). This is not an uncore PMU, | |
814 | * and we have taken ctx sharing into account (e.g. with our | |
815 | * pmu::filter_match callback and pmu::event_init group | |
816 | * validation). | |
817 | */ | |
818 | .capabilities = PERF_PMU_CAP_HETEROGENEOUS_CPUS, | |
819 | }; | |
820 | ||
821 | pmu->attr_groups[ARMPMU_ATTR_GROUP_COMMON] = | |
822 | &armpmu_common_attr_group; | |
823 | ||
ef5eb2c7 MR |
824 | for_each_possible_cpu(cpu) { |
825 | struct pmu_hw_events *events; | |
826 | ||
827 | events = per_cpu_ptr(pmu->hw_events, cpu); | |
828 | raw_spin_lock_init(&events->pmu_lock); | |
829 | events->percpu_pmu = pmu; | |
830 | } | |
831 | ||
832 | return pmu; | |
833 | ||
834 | out_free_pmu: | |
835 | kfree(pmu); | |
836 | out: | |
837 | return NULL; | |
838 | } | |
839 | ||
444ae70d | 840 | void armpmu_free(struct arm_pmu *pmu) |
ef5eb2c7 MR |
841 | { |
842 | free_percpu(pmu->hw_events); | |
843 | kfree(pmu); | |
844 | } | |
845 | ||
e29b5559 MR |
846 | int armpmu_register(struct arm_pmu *pmu) |
847 | { | |
848 | int ret; | |
849 | ||
850 | ret = cpu_pmu_init(pmu); | |
851 | if (ret) | |
852 | return ret; | |
853 | ||
854 | ret = perf_pmu_register(&pmu->pmu, pmu->name, -1); | |
855 | if (ret) | |
856 | goto out_destroy; | |
857 | ||
858 | if (!__oprofile_cpu_pmu) | |
859 | __oprofile_cpu_pmu = pmu; | |
860 | ||
861 | pr_info("enabled with %s PMU driver, %d counters available\n", | |
862 | pmu->name, pmu->num_events); | |
863 | ||
864 | return 0; | |
865 | ||
866 | out_destroy: | |
867 | cpu_pmu_destroy(pmu); | |
868 | return ret; | |
869 | } | |
870 | ||
37b502f1 SAS |
871 | static int arm_pmu_hp_init(void) |
872 | { | |
873 | int ret; | |
874 | ||
6e103c0c | 875 | ret = cpuhp_setup_state_multi(CPUHP_AP_PERF_ARM_STARTING, |
73c1b41e | 876 | "perf/arm/pmu:starting", |
e16592b0 MR |
877 | arm_perf_starting_cpu, |
878 | arm_perf_teardown_cpu); | |
37b502f1 SAS |
879 | if (ret) |
880 | pr_err("CPU hotplug notifier for ARM PMU could not be registered: %d\n", | |
881 | ret); | |
882 | return ret; | |
883 | } | |
884 | subsys_initcall(arm_pmu_hp_init); |