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Commit | Line | Data |
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1b8873a0 JI |
1 | #undef DEBUG |
2 | ||
3 | /* | |
4 | * ARM performance counter support. | |
5 | * | |
6 | * Copyright (C) 2009 picoChip Designs, Ltd., Jamie Iles | |
43eab878 | 7 | * Copyright (C) 2010 ARM Ltd., Will Deacon <will.deacon@arm.com> |
796d1295 | 8 | * |
1b8873a0 | 9 | * This code is based on the sparc64 perf event code, which is in turn based |
d39976f0 | 10 | * on the x86 code. |
1b8873a0 JI |
11 | */ |
12 | #define pr_fmt(fmt) "hw perfevents: " fmt | |
13 | ||
74cf0bc7 | 14 | #include <linux/bitmap.h> |
cc88116d | 15 | #include <linux/cpumask.h> |
da4e4f18 | 16 | #include <linux/cpu_pm.h> |
74cf0bc7 | 17 | #include <linux/export.h> |
1b8873a0 | 18 | #include <linux/kernel.h> |
bc1e3c46 | 19 | #include <linux/of_device.h> |
fa8ad788 | 20 | #include <linux/perf/arm_pmu.h> |
49c006b9 | 21 | #include <linux/platform_device.h> |
74cf0bc7 | 22 | #include <linux/slab.h> |
e6017571 | 23 | #include <linux/sched/clock.h> |
74cf0bc7 | 24 | #include <linux/spinlock.h> |
bbd64559 SB |
25 | #include <linux/irq.h> |
26 | #include <linux/irqdesc.h> | |
1b8873a0 | 27 | |
74cf0bc7 | 28 | #include <asm/cputype.h> |
1b8873a0 | 29 | #include <asm/irq_regs.h> |
1b8873a0 | 30 | |
1b8873a0 | 31 | static int |
e1f431b5 MR |
32 | armpmu_map_cache_event(const unsigned (*cache_map) |
33 | [PERF_COUNT_HW_CACHE_MAX] | |
34 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
35 | [PERF_COUNT_HW_CACHE_RESULT_MAX], | |
36 | u64 config) | |
1b8873a0 JI |
37 | { |
38 | unsigned int cache_type, cache_op, cache_result, ret; | |
39 | ||
40 | cache_type = (config >> 0) & 0xff; | |
41 | if (cache_type >= PERF_COUNT_HW_CACHE_MAX) | |
42 | return -EINVAL; | |
43 | ||
44 | cache_op = (config >> 8) & 0xff; | |
45 | if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX) | |
46 | return -EINVAL; | |
47 | ||
48 | cache_result = (config >> 16) & 0xff; | |
49 | if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX) | |
50 | return -EINVAL; | |
51 | ||
e1f431b5 | 52 | ret = (int)(*cache_map)[cache_type][cache_op][cache_result]; |
1b8873a0 JI |
53 | |
54 | if (ret == CACHE_OP_UNSUPPORTED) | |
55 | return -ENOENT; | |
56 | ||
57 | return ret; | |
58 | } | |
59 | ||
84fee97a | 60 | static int |
6dbc0029 | 61 | armpmu_map_hw_event(const unsigned (*event_map)[PERF_COUNT_HW_MAX], u64 config) |
84fee97a | 62 | { |
d9f96635 SB |
63 | int mapping; |
64 | ||
65 | if (config >= PERF_COUNT_HW_MAX) | |
66 | return -EINVAL; | |
67 | ||
68 | mapping = (*event_map)[config]; | |
e1f431b5 | 69 | return mapping == HW_OP_UNSUPPORTED ? -ENOENT : mapping; |
84fee97a WD |
70 | } |
71 | ||
72 | static int | |
e1f431b5 | 73 | armpmu_map_raw_event(u32 raw_event_mask, u64 config) |
84fee97a | 74 | { |
e1f431b5 MR |
75 | return (int)(config & raw_event_mask); |
76 | } | |
77 | ||
6dbc0029 WD |
78 | int |
79 | armpmu_map_event(struct perf_event *event, | |
80 | const unsigned (*event_map)[PERF_COUNT_HW_MAX], | |
81 | const unsigned (*cache_map) | |
82 | [PERF_COUNT_HW_CACHE_MAX] | |
83 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
84 | [PERF_COUNT_HW_CACHE_RESULT_MAX], | |
85 | u32 raw_event_mask) | |
e1f431b5 MR |
86 | { |
87 | u64 config = event->attr.config; | |
67b4305a | 88 | int type = event->attr.type; |
e1f431b5 | 89 | |
67b4305a MR |
90 | if (type == event->pmu->type) |
91 | return armpmu_map_raw_event(raw_event_mask, config); | |
92 | ||
93 | switch (type) { | |
e1f431b5 | 94 | case PERF_TYPE_HARDWARE: |
6dbc0029 | 95 | return armpmu_map_hw_event(event_map, config); |
e1f431b5 MR |
96 | case PERF_TYPE_HW_CACHE: |
97 | return armpmu_map_cache_event(cache_map, config); | |
98 | case PERF_TYPE_RAW: | |
99 | return armpmu_map_raw_event(raw_event_mask, config); | |
100 | } | |
101 | ||
102 | return -ENOENT; | |
84fee97a WD |
103 | } |
104 | ||
ed6f2a52 | 105 | int armpmu_event_set_period(struct perf_event *event) |
1b8873a0 | 106 | { |
8a16b34e | 107 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
ed6f2a52 | 108 | struct hw_perf_event *hwc = &event->hw; |
e7850595 | 109 | s64 left = local64_read(&hwc->period_left); |
1b8873a0 JI |
110 | s64 period = hwc->sample_period; |
111 | int ret = 0; | |
112 | ||
113 | if (unlikely(left <= -period)) { | |
114 | left = period; | |
e7850595 | 115 | local64_set(&hwc->period_left, left); |
1b8873a0 JI |
116 | hwc->last_period = period; |
117 | ret = 1; | |
118 | } | |
119 | ||
120 | if (unlikely(left <= 0)) { | |
121 | left += period; | |
e7850595 | 122 | local64_set(&hwc->period_left, left); |
1b8873a0 JI |
123 | hwc->last_period = period; |
124 | ret = 1; | |
125 | } | |
126 | ||
2d9ed740 DT |
127 | /* |
128 | * Limit the maximum period to prevent the counter value | |
129 | * from overtaking the one we are about to program. In | |
130 | * effect we are reducing max_period to account for | |
131 | * interrupt latency (and we are being very conservative). | |
132 | */ | |
133 | if (left > (armpmu->max_period >> 1)) | |
134 | left = armpmu->max_period >> 1; | |
1b8873a0 | 135 | |
e7850595 | 136 | local64_set(&hwc->prev_count, (u64)-left); |
1b8873a0 | 137 | |
ed6f2a52 | 138 | armpmu->write_counter(event, (u64)(-left) & 0xffffffff); |
1b8873a0 JI |
139 | |
140 | perf_event_update_userpage(event); | |
141 | ||
142 | return ret; | |
143 | } | |
144 | ||
ed6f2a52 | 145 | u64 armpmu_event_update(struct perf_event *event) |
1b8873a0 | 146 | { |
8a16b34e | 147 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
ed6f2a52 | 148 | struct hw_perf_event *hwc = &event->hw; |
a737823d | 149 | u64 delta, prev_raw_count, new_raw_count; |
1b8873a0 JI |
150 | |
151 | again: | |
e7850595 | 152 | prev_raw_count = local64_read(&hwc->prev_count); |
ed6f2a52 | 153 | new_raw_count = armpmu->read_counter(event); |
1b8873a0 | 154 | |
e7850595 | 155 | if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, |
1b8873a0 JI |
156 | new_raw_count) != prev_raw_count) |
157 | goto again; | |
158 | ||
57273471 | 159 | delta = (new_raw_count - prev_raw_count) & armpmu->max_period; |
1b8873a0 | 160 | |
e7850595 PZ |
161 | local64_add(delta, &event->count); |
162 | local64_sub(delta, &hwc->period_left); | |
1b8873a0 JI |
163 | |
164 | return new_raw_count; | |
165 | } | |
166 | ||
167 | static void | |
a4eaf7f1 | 168 | armpmu_read(struct perf_event *event) |
1b8873a0 | 169 | { |
ed6f2a52 | 170 | armpmu_event_update(event); |
1b8873a0 JI |
171 | } |
172 | ||
173 | static void | |
a4eaf7f1 | 174 | armpmu_stop(struct perf_event *event, int flags) |
1b8873a0 | 175 | { |
8a16b34e | 176 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
1b8873a0 JI |
177 | struct hw_perf_event *hwc = &event->hw; |
178 | ||
a4eaf7f1 PZ |
179 | /* |
180 | * ARM pmu always has to update the counter, so ignore | |
181 | * PERF_EF_UPDATE, see comments in armpmu_start(). | |
182 | */ | |
183 | if (!(hwc->state & PERF_HES_STOPPED)) { | |
ed6f2a52 SH |
184 | armpmu->disable(event); |
185 | armpmu_event_update(event); | |
a4eaf7f1 PZ |
186 | hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE; |
187 | } | |
1b8873a0 JI |
188 | } |
189 | ||
ed6f2a52 | 190 | static void armpmu_start(struct perf_event *event, int flags) |
1b8873a0 | 191 | { |
8a16b34e | 192 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
1b8873a0 JI |
193 | struct hw_perf_event *hwc = &event->hw; |
194 | ||
a4eaf7f1 PZ |
195 | /* |
196 | * ARM pmu always has to reprogram the period, so ignore | |
197 | * PERF_EF_RELOAD, see the comment below. | |
198 | */ | |
199 | if (flags & PERF_EF_RELOAD) | |
200 | WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE)); | |
201 | ||
202 | hwc->state = 0; | |
1b8873a0 JI |
203 | /* |
204 | * Set the period again. Some counters can't be stopped, so when we | |
a4eaf7f1 | 205 | * were stopped we simply disabled the IRQ source and the counter |
1b8873a0 JI |
206 | * may have been left counting. If we don't do this step then we may |
207 | * get an interrupt too soon or *way* too late if the overflow has | |
208 | * happened since disabling. | |
209 | */ | |
ed6f2a52 SH |
210 | armpmu_event_set_period(event); |
211 | armpmu->enable(event); | |
1b8873a0 JI |
212 | } |
213 | ||
a4eaf7f1 PZ |
214 | static void |
215 | armpmu_del(struct perf_event *event, int flags) | |
216 | { | |
8a16b34e | 217 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
11679250 | 218 | struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events); |
a4eaf7f1 PZ |
219 | struct hw_perf_event *hwc = &event->hw; |
220 | int idx = hwc->idx; | |
221 | ||
a4eaf7f1 | 222 | armpmu_stop(event, PERF_EF_UPDATE); |
8be3f9a2 MR |
223 | hw_events->events[idx] = NULL; |
224 | clear_bit(idx, hw_events->used_mask); | |
eab443ef SB |
225 | if (armpmu->clear_event_idx) |
226 | armpmu->clear_event_idx(hw_events, event); | |
a4eaf7f1 PZ |
227 | |
228 | perf_event_update_userpage(event); | |
229 | } | |
230 | ||
1b8873a0 | 231 | static int |
a4eaf7f1 | 232 | armpmu_add(struct perf_event *event, int flags) |
1b8873a0 | 233 | { |
8a16b34e | 234 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
11679250 | 235 | struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events); |
1b8873a0 JI |
236 | struct hw_perf_event *hwc = &event->hw; |
237 | int idx; | |
238 | int err = 0; | |
239 | ||
cc88116d MR |
240 | /* An event following a process won't be stopped earlier */ |
241 | if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus)) | |
242 | return -ENOENT; | |
243 | ||
33696fc0 | 244 | perf_pmu_disable(event->pmu); |
24cd7f54 | 245 | |
1b8873a0 | 246 | /* If we don't have a space for the counter then finish early. */ |
ed6f2a52 | 247 | idx = armpmu->get_event_idx(hw_events, event); |
1b8873a0 JI |
248 | if (idx < 0) { |
249 | err = idx; | |
250 | goto out; | |
251 | } | |
252 | ||
253 | /* | |
254 | * If there is an event in the counter we are going to use then make | |
255 | * sure it is disabled. | |
256 | */ | |
257 | event->hw.idx = idx; | |
ed6f2a52 | 258 | armpmu->disable(event); |
8be3f9a2 | 259 | hw_events->events[idx] = event; |
1b8873a0 | 260 | |
a4eaf7f1 PZ |
261 | hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE; |
262 | if (flags & PERF_EF_START) | |
263 | armpmu_start(event, PERF_EF_RELOAD); | |
1b8873a0 JI |
264 | |
265 | /* Propagate our changes to the userspace mapping. */ | |
266 | perf_event_update_userpage(event); | |
267 | ||
268 | out: | |
33696fc0 | 269 | perf_pmu_enable(event->pmu); |
1b8873a0 JI |
270 | return err; |
271 | } | |
272 | ||
1b8873a0 | 273 | static int |
e429817b SP |
274 | validate_event(struct pmu *pmu, struct pmu_hw_events *hw_events, |
275 | struct perf_event *event) | |
1b8873a0 | 276 | { |
e429817b | 277 | struct arm_pmu *armpmu; |
1b8873a0 | 278 | |
c95eb318 WD |
279 | if (is_software_event(event)) |
280 | return 1; | |
281 | ||
e429817b SP |
282 | /* |
283 | * Reject groups spanning multiple HW PMUs (e.g. CPU + CCI). The | |
284 | * core perf code won't check that the pmu->ctx == leader->ctx | |
285 | * until after pmu->event_init(event). | |
286 | */ | |
287 | if (event->pmu != pmu) | |
288 | return 0; | |
289 | ||
2dfcb802 | 290 | if (event->state < PERF_EVENT_STATE_OFF) |
cb2d8b34 WD |
291 | return 1; |
292 | ||
293 | if (event->state == PERF_EVENT_STATE_OFF && !event->attr.enable_on_exec) | |
65b4711f | 294 | return 1; |
1b8873a0 | 295 | |
e429817b | 296 | armpmu = to_arm_pmu(event->pmu); |
ed6f2a52 | 297 | return armpmu->get_event_idx(hw_events, event) >= 0; |
1b8873a0 JI |
298 | } |
299 | ||
300 | static int | |
301 | validate_group(struct perf_event *event) | |
302 | { | |
303 | struct perf_event *sibling, *leader = event->group_leader; | |
8be3f9a2 | 304 | struct pmu_hw_events fake_pmu; |
1b8873a0 | 305 | |
bce34d14 WD |
306 | /* |
307 | * Initialise the fake PMU. We only need to populate the | |
308 | * used_mask for the purposes of validation. | |
309 | */ | |
a4560846 | 310 | memset(&fake_pmu.used_mask, 0, sizeof(fake_pmu.used_mask)); |
1b8873a0 | 311 | |
e429817b | 312 | if (!validate_event(event->pmu, &fake_pmu, leader)) |
aa2bc1ad | 313 | return -EINVAL; |
1b8873a0 JI |
314 | |
315 | list_for_each_entry(sibling, &leader->sibling_list, group_entry) { | |
e429817b | 316 | if (!validate_event(event->pmu, &fake_pmu, sibling)) |
aa2bc1ad | 317 | return -EINVAL; |
1b8873a0 JI |
318 | } |
319 | ||
e429817b | 320 | if (!validate_event(event->pmu, &fake_pmu, event)) |
aa2bc1ad | 321 | return -EINVAL; |
1b8873a0 JI |
322 | |
323 | return 0; | |
324 | } | |
325 | ||
051f1b13 | 326 | static irqreturn_t armpmu_dispatch_irq(int irq, void *dev) |
0e25a5c9 | 327 | { |
bbd64559 SB |
328 | struct arm_pmu *armpmu; |
329 | struct platform_device *plat_device; | |
330 | struct arm_pmu_platdata *plat; | |
5f5092e7 WD |
331 | int ret; |
332 | u64 start_clock, finish_clock; | |
bbd64559 | 333 | |
5ebd9200 MR |
334 | /* |
335 | * we request the IRQ with a (possibly percpu) struct arm_pmu**, but | |
336 | * the handlers expect a struct arm_pmu*. The percpu_irq framework will | |
337 | * do any necessary shifting, we just need to perform the first | |
338 | * dereference. | |
339 | */ | |
340 | armpmu = *(void **)dev; | |
bbd64559 SB |
341 | plat_device = armpmu->plat_device; |
342 | plat = dev_get_platdata(&plat_device->dev); | |
0e25a5c9 | 343 | |
5f5092e7 | 344 | start_clock = sched_clock(); |
051f1b13 | 345 | if (plat && plat->handle_irq) |
5ebd9200 | 346 | ret = plat->handle_irq(irq, armpmu, armpmu->handle_irq); |
051f1b13 | 347 | else |
5ebd9200 | 348 | ret = armpmu->handle_irq(irq, armpmu); |
5f5092e7 WD |
349 | finish_clock = sched_clock(); |
350 | ||
351 | perf_sample_event_took(finish_clock - start_clock); | |
352 | return ret; | |
0e25a5c9 RV |
353 | } |
354 | ||
0b390e21 | 355 | static void |
8a16b34e | 356 | armpmu_release_hardware(struct arm_pmu *armpmu) |
0b390e21 | 357 | { |
ed6f2a52 | 358 | armpmu->free_irq(armpmu); |
0b390e21 WD |
359 | } |
360 | ||
1b8873a0 | 361 | static int |
8a16b34e | 362 | armpmu_reserve_hardware(struct arm_pmu *armpmu) |
1b8873a0 | 363 | { |
ed61f985 | 364 | int err = armpmu->request_irq(armpmu, armpmu_dispatch_irq); |
051f1b13 SH |
365 | if (err) { |
366 | armpmu_release_hardware(armpmu); | |
367 | return err; | |
49c006b9 | 368 | } |
1b8873a0 | 369 | |
0b390e21 | 370 | return 0; |
1b8873a0 JI |
371 | } |
372 | ||
1b8873a0 JI |
373 | static void |
374 | hw_perf_event_destroy(struct perf_event *event) | |
375 | { | |
8a16b34e | 376 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
03b7898d MR |
377 | atomic_t *active_events = &armpmu->active_events; |
378 | struct mutex *pmu_reserve_mutex = &armpmu->reserve_mutex; | |
379 | ||
380 | if (atomic_dec_and_mutex_lock(active_events, pmu_reserve_mutex)) { | |
8a16b34e | 381 | armpmu_release_hardware(armpmu); |
03b7898d | 382 | mutex_unlock(pmu_reserve_mutex); |
1b8873a0 JI |
383 | } |
384 | } | |
385 | ||
05d22fde WD |
386 | static int |
387 | event_requires_mode_exclusion(struct perf_event_attr *attr) | |
388 | { | |
389 | return attr->exclude_idle || attr->exclude_user || | |
390 | attr->exclude_kernel || attr->exclude_hv; | |
391 | } | |
392 | ||
1b8873a0 JI |
393 | static int |
394 | __hw_perf_event_init(struct perf_event *event) | |
395 | { | |
8a16b34e | 396 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
1b8873a0 | 397 | struct hw_perf_event *hwc = &event->hw; |
9dcbf466 | 398 | int mapping; |
1b8873a0 | 399 | |
e1f431b5 | 400 | mapping = armpmu->map_event(event); |
1b8873a0 JI |
401 | |
402 | if (mapping < 0) { | |
403 | pr_debug("event %x:%llx not supported\n", event->attr.type, | |
404 | event->attr.config); | |
405 | return mapping; | |
406 | } | |
407 | ||
05d22fde WD |
408 | /* |
409 | * We don't assign an index until we actually place the event onto | |
410 | * hardware. Use -1 to signify that we haven't decided where to put it | |
411 | * yet. For SMP systems, each core has it's own PMU so we can't do any | |
412 | * clever allocation or constraints checking at this point. | |
413 | */ | |
414 | hwc->idx = -1; | |
415 | hwc->config_base = 0; | |
416 | hwc->config = 0; | |
417 | hwc->event_base = 0; | |
418 | ||
1b8873a0 JI |
419 | /* |
420 | * Check whether we need to exclude the counter from certain modes. | |
1b8873a0 | 421 | */ |
05d22fde WD |
422 | if ((!armpmu->set_event_filter || |
423 | armpmu->set_event_filter(hwc, &event->attr)) && | |
424 | event_requires_mode_exclusion(&event->attr)) { | |
1b8873a0 JI |
425 | pr_debug("ARM performance counters do not support " |
426 | "mode exclusion\n"); | |
fdeb8e35 | 427 | return -EOPNOTSUPP; |
1b8873a0 JI |
428 | } |
429 | ||
430 | /* | |
05d22fde | 431 | * Store the event encoding into the config_base field. |
1b8873a0 | 432 | */ |
05d22fde | 433 | hwc->config_base |= (unsigned long)mapping; |
1b8873a0 | 434 | |
edcb4d3c | 435 | if (!is_sampling_event(event)) { |
57273471 WD |
436 | /* |
437 | * For non-sampling runs, limit the sample_period to half | |
438 | * of the counter width. That way, the new counter value | |
439 | * is far less likely to overtake the previous one unless | |
440 | * you have some serious IRQ latency issues. | |
441 | */ | |
442 | hwc->sample_period = armpmu->max_period >> 1; | |
1b8873a0 | 443 | hwc->last_period = hwc->sample_period; |
e7850595 | 444 | local64_set(&hwc->period_left, hwc->sample_period); |
1b8873a0 JI |
445 | } |
446 | ||
1b8873a0 | 447 | if (event->group_leader != event) { |
e595ede6 | 448 | if (validate_group(event) != 0) |
1b8873a0 JI |
449 | return -EINVAL; |
450 | } | |
451 | ||
9dcbf466 | 452 | return 0; |
1b8873a0 JI |
453 | } |
454 | ||
b0a873eb | 455 | static int armpmu_event_init(struct perf_event *event) |
1b8873a0 | 456 | { |
8a16b34e | 457 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
1b8873a0 | 458 | int err = 0; |
03b7898d | 459 | atomic_t *active_events = &armpmu->active_events; |
1b8873a0 | 460 | |
cc88116d MR |
461 | /* |
462 | * Reject CPU-affine events for CPUs that are of a different class to | |
463 | * that which this PMU handles. Process-following events (where | |
464 | * event->cpu == -1) can be migrated between CPUs, and thus we have to | |
465 | * reject them later (in armpmu_add) if they're scheduled on a | |
466 | * different class of CPU. | |
467 | */ | |
468 | if (event->cpu != -1 && | |
469 | !cpumask_test_cpu(event->cpu, &armpmu->supported_cpus)) | |
470 | return -ENOENT; | |
471 | ||
2481c5fa SE |
472 | /* does not support taken branch sampling */ |
473 | if (has_branch_stack(event)) | |
474 | return -EOPNOTSUPP; | |
475 | ||
e1f431b5 | 476 | if (armpmu->map_event(event) == -ENOENT) |
b0a873eb | 477 | return -ENOENT; |
b0a873eb | 478 | |
1b8873a0 JI |
479 | event->destroy = hw_perf_event_destroy; |
480 | ||
03b7898d MR |
481 | if (!atomic_inc_not_zero(active_events)) { |
482 | mutex_lock(&armpmu->reserve_mutex); | |
483 | if (atomic_read(active_events) == 0) | |
8a16b34e | 484 | err = armpmu_reserve_hardware(armpmu); |
1b8873a0 JI |
485 | |
486 | if (!err) | |
03b7898d MR |
487 | atomic_inc(active_events); |
488 | mutex_unlock(&armpmu->reserve_mutex); | |
1b8873a0 JI |
489 | } |
490 | ||
491 | if (err) | |
b0a873eb | 492 | return err; |
1b8873a0 JI |
493 | |
494 | err = __hw_perf_event_init(event); | |
495 | if (err) | |
496 | hw_perf_event_destroy(event); | |
497 | ||
b0a873eb | 498 | return err; |
1b8873a0 JI |
499 | } |
500 | ||
a4eaf7f1 | 501 | static void armpmu_enable(struct pmu *pmu) |
1b8873a0 | 502 | { |
8be3f9a2 | 503 | struct arm_pmu *armpmu = to_arm_pmu(pmu); |
11679250 | 504 | struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events); |
7325eaec | 505 | int enabled = bitmap_weight(hw_events->used_mask, armpmu->num_events); |
1b8873a0 | 506 | |
cc88116d MR |
507 | /* For task-bound events we may be called on other CPUs */ |
508 | if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus)) | |
509 | return; | |
510 | ||
f4f38430 | 511 | if (enabled) |
ed6f2a52 | 512 | armpmu->start(armpmu); |
1b8873a0 JI |
513 | } |
514 | ||
a4eaf7f1 | 515 | static void armpmu_disable(struct pmu *pmu) |
1b8873a0 | 516 | { |
8a16b34e | 517 | struct arm_pmu *armpmu = to_arm_pmu(pmu); |
cc88116d MR |
518 | |
519 | /* For task-bound events we may be called on other CPUs */ | |
520 | if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus)) | |
521 | return; | |
522 | ||
ed6f2a52 | 523 | armpmu->stop(armpmu); |
1b8873a0 JI |
524 | } |
525 | ||
c904e32a MR |
526 | /* |
527 | * In heterogeneous systems, events are specific to a particular | |
528 | * microarchitecture, and aren't suitable for another. Thus, only match CPUs of | |
529 | * the same microarchitecture. | |
530 | */ | |
531 | static int armpmu_filter_match(struct perf_event *event) | |
532 | { | |
533 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); | |
534 | unsigned int cpu = smp_processor_id(); | |
535 | return cpumask_test_cpu(cpu, &armpmu->supported_cpus); | |
536 | } | |
537 | ||
48538b58 MR |
538 | static ssize_t armpmu_cpumask_show(struct device *dev, |
539 | struct device_attribute *attr, char *buf) | |
540 | { | |
541 | struct arm_pmu *armpmu = to_arm_pmu(dev_get_drvdata(dev)); | |
542 | return cpumap_print_to_pagebuf(true, buf, &armpmu->supported_cpus); | |
543 | } | |
544 | ||
545 | static DEVICE_ATTR(cpus, S_IRUGO, armpmu_cpumask_show, NULL); | |
546 | ||
547 | static struct attribute *armpmu_common_attrs[] = { | |
548 | &dev_attr_cpus.attr, | |
549 | NULL, | |
550 | }; | |
551 | ||
552 | static struct attribute_group armpmu_common_attr_group = { | |
553 | .attrs = armpmu_common_attrs, | |
554 | }; | |
555 | ||
44d6b1fc | 556 | static void armpmu_init(struct arm_pmu *armpmu) |
03b7898d MR |
557 | { |
558 | atomic_set(&armpmu->active_events, 0); | |
559 | mutex_init(&armpmu->reserve_mutex); | |
8a16b34e MR |
560 | |
561 | armpmu->pmu = (struct pmu) { | |
562 | .pmu_enable = armpmu_enable, | |
563 | .pmu_disable = armpmu_disable, | |
564 | .event_init = armpmu_event_init, | |
565 | .add = armpmu_add, | |
566 | .del = armpmu_del, | |
567 | .start = armpmu_start, | |
568 | .stop = armpmu_stop, | |
569 | .read = armpmu_read, | |
c904e32a | 570 | .filter_match = armpmu_filter_match, |
1589680d | 571 | .attr_groups = armpmu->attr_groups, |
8a16b34e | 572 | }; |
48538b58 MR |
573 | armpmu->attr_groups[ARMPMU_ATTR_GROUP_COMMON] = |
574 | &armpmu_common_attr_group; | |
8a16b34e MR |
575 | } |
576 | ||
74cf0bc7 MR |
577 | /* Set at runtime when we know what CPU type we are. */ |
578 | static struct arm_pmu *__oprofile_cpu_pmu; | |
579 | ||
580 | /* | |
581 | * Despite the names, these two functions are CPU-specific and are used | |
582 | * by the OProfile/perf code. | |
583 | */ | |
584 | const char *perf_pmu_name(void) | |
585 | { | |
586 | if (!__oprofile_cpu_pmu) | |
587 | return NULL; | |
588 | ||
589 | return __oprofile_cpu_pmu->name; | |
590 | } | |
591 | EXPORT_SYMBOL_GPL(perf_pmu_name); | |
592 | ||
593 | int perf_num_counters(void) | |
594 | { | |
595 | int max_events = 0; | |
596 | ||
597 | if (__oprofile_cpu_pmu != NULL) | |
598 | max_events = __oprofile_cpu_pmu->num_events; | |
599 | ||
600 | return max_events; | |
601 | } | |
602 | EXPORT_SYMBOL_GPL(perf_num_counters); | |
603 | ||
604 | static void cpu_pmu_enable_percpu_irq(void *data) | |
605 | { | |
606 | int irq = *(int *)data; | |
607 | ||
608 | enable_percpu_irq(irq, IRQ_TYPE_NONE); | |
609 | } | |
610 | ||
611 | static void cpu_pmu_disable_percpu_irq(void *data) | |
612 | { | |
613 | int irq = *(int *)data; | |
614 | ||
615 | disable_percpu_irq(irq); | |
616 | } | |
617 | ||
618 | static void cpu_pmu_free_irq(struct arm_pmu *cpu_pmu) | |
619 | { | |
620 | int i, irq, irqs; | |
621 | struct platform_device *pmu_device = cpu_pmu->plat_device; | |
622 | struct pmu_hw_events __percpu *hw_events = cpu_pmu->hw_events; | |
623 | ||
624 | irqs = min(pmu_device->num_resources, num_possible_cpus()); | |
625 | ||
626 | irq = platform_get_irq(pmu_device, 0); | |
282b8796 | 627 | if (irq > 0 && irq_is_percpu(irq)) { |
19a469a5 MZ |
628 | on_each_cpu_mask(&cpu_pmu->supported_cpus, |
629 | cpu_pmu_disable_percpu_irq, &irq, 1); | |
74cf0bc7 MR |
630 | free_percpu_irq(irq, &hw_events->percpu_pmu); |
631 | } else { | |
632 | for (i = 0; i < irqs; ++i) { | |
633 | int cpu = i; | |
634 | ||
635 | if (cpu_pmu->irq_affinity) | |
636 | cpu = cpu_pmu->irq_affinity[i]; | |
637 | ||
638 | if (!cpumask_test_and_clear_cpu(cpu, &cpu_pmu->active_irqs)) | |
639 | continue; | |
640 | irq = platform_get_irq(pmu_device, i); | |
282b8796 | 641 | if (irq > 0) |
74cf0bc7 MR |
642 | free_irq(irq, per_cpu_ptr(&hw_events->percpu_pmu, cpu)); |
643 | } | |
644 | } | |
645 | } | |
646 | ||
647 | static int cpu_pmu_request_irq(struct arm_pmu *cpu_pmu, irq_handler_t handler) | |
648 | { | |
649 | int i, err, irq, irqs; | |
650 | struct platform_device *pmu_device = cpu_pmu->plat_device; | |
651 | struct pmu_hw_events __percpu *hw_events = cpu_pmu->hw_events; | |
652 | ||
653 | if (!pmu_device) | |
654 | return -ENODEV; | |
655 | ||
656 | irqs = min(pmu_device->num_resources, num_possible_cpus()); | |
657 | if (irqs < 1) { | |
658 | pr_warn_once("perf/ARM: No irqs for PMU defined, sampling events not supported\n"); | |
659 | return 0; | |
660 | } | |
661 | ||
662 | irq = platform_get_irq(pmu_device, 0); | |
282b8796 | 663 | if (irq > 0 && irq_is_percpu(irq)) { |
74cf0bc7 MR |
664 | err = request_percpu_irq(irq, handler, "arm-pmu", |
665 | &hw_events->percpu_pmu); | |
666 | if (err) { | |
667 | pr_err("unable to request IRQ%d for ARM PMU counters\n", | |
668 | irq); | |
669 | return err; | |
670 | } | |
19a469a5 MZ |
671 | |
672 | on_each_cpu_mask(&cpu_pmu->supported_cpus, | |
673 | cpu_pmu_enable_percpu_irq, &irq, 1); | |
74cf0bc7 MR |
674 | } else { |
675 | for (i = 0; i < irqs; ++i) { | |
676 | int cpu = i; | |
677 | ||
678 | err = 0; | |
679 | irq = platform_get_irq(pmu_device, i); | |
680 | if (irq < 0) | |
681 | continue; | |
682 | ||
683 | if (cpu_pmu->irq_affinity) | |
684 | cpu = cpu_pmu->irq_affinity[i]; | |
685 | ||
686 | /* | |
687 | * If we have a single PMU interrupt that we can't shift, | |
688 | * assume that we're running on a uniprocessor machine and | |
689 | * continue. Otherwise, continue without this interrupt. | |
690 | */ | |
691 | if (irq_set_affinity(irq, cpumask_of(cpu)) && irqs > 1) { | |
692 | pr_warn("unable to set irq affinity (irq=%d, cpu=%u)\n", | |
693 | irq, cpu); | |
694 | continue; | |
695 | } | |
696 | ||
697 | err = request_irq(irq, handler, | |
698 | IRQF_NOBALANCING | IRQF_NO_THREAD, "arm-pmu", | |
699 | per_cpu_ptr(&hw_events->percpu_pmu, cpu)); | |
700 | if (err) { | |
701 | pr_err("unable to request IRQ%d for ARM PMU counters\n", | |
702 | irq); | |
703 | return err; | |
704 | } | |
705 | ||
706 | cpumask_set_cpu(cpu, &cpu_pmu->active_irqs); | |
707 | } | |
708 | } | |
709 | ||
710 | return 0; | |
711 | } | |
712 | ||
713 | /* | |
714 | * PMU hardware loses all context when a CPU goes offline. | |
715 | * When a CPU is hotplugged back in, since some hardware registers are | |
716 | * UNKNOWN at reset, the PMU must be explicitly reset to avoid reading | |
717 | * junk values out of them. | |
718 | */ | |
6e103c0c | 719 | static int arm_perf_starting_cpu(unsigned int cpu, struct hlist_node *node) |
74cf0bc7 | 720 | { |
6e103c0c | 721 | struct arm_pmu *pmu = hlist_entry_safe(node, struct arm_pmu, node); |
74cf0bc7 | 722 | |
6e103c0c SAS |
723 | if (!cpumask_test_cpu(cpu, &pmu->supported_cpus)) |
724 | return 0; | |
725 | if (pmu->reset) | |
726 | pmu->reset(pmu); | |
7d88eb69 | 727 | return 0; |
74cf0bc7 MR |
728 | } |
729 | ||
da4e4f18 LP |
730 | #ifdef CONFIG_CPU_PM |
731 | static void cpu_pm_pmu_setup(struct arm_pmu *armpmu, unsigned long cmd) | |
732 | { | |
733 | struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events); | |
734 | struct perf_event *event; | |
735 | int idx; | |
736 | ||
737 | for (idx = 0; idx < armpmu->num_events; idx++) { | |
738 | /* | |
739 | * If the counter is not used skip it, there is no | |
740 | * need of stopping/restarting it. | |
741 | */ | |
742 | if (!test_bit(idx, hw_events->used_mask)) | |
743 | continue; | |
744 | ||
745 | event = hw_events->events[idx]; | |
746 | ||
747 | switch (cmd) { | |
748 | case CPU_PM_ENTER: | |
749 | /* | |
750 | * Stop and update the counter | |
751 | */ | |
752 | armpmu_stop(event, PERF_EF_UPDATE); | |
753 | break; | |
754 | case CPU_PM_EXIT: | |
755 | case CPU_PM_ENTER_FAILED: | |
cbcc72e0 LP |
756 | /* |
757 | * Restore and enable the counter. | |
758 | * armpmu_start() indirectly calls | |
759 | * | |
760 | * perf_event_update_userpage() | |
761 | * | |
762 | * that requires RCU read locking to be functional, | |
763 | * wrap the call within RCU_NONIDLE to make the | |
764 | * RCU subsystem aware this cpu is not idle from | |
765 | * an RCU perspective for the armpmu_start() call | |
766 | * duration. | |
767 | */ | |
768 | RCU_NONIDLE(armpmu_start(event, PERF_EF_RELOAD)); | |
da4e4f18 LP |
769 | break; |
770 | default: | |
771 | break; | |
772 | } | |
773 | } | |
774 | } | |
775 | ||
776 | static int cpu_pm_pmu_notify(struct notifier_block *b, unsigned long cmd, | |
777 | void *v) | |
778 | { | |
779 | struct arm_pmu *armpmu = container_of(b, struct arm_pmu, cpu_pm_nb); | |
780 | struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events); | |
781 | int enabled = bitmap_weight(hw_events->used_mask, armpmu->num_events); | |
782 | ||
783 | if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus)) | |
784 | return NOTIFY_DONE; | |
785 | ||
786 | /* | |
787 | * Always reset the PMU registers on power-up even if | |
788 | * there are no events running. | |
789 | */ | |
790 | if (cmd == CPU_PM_EXIT && armpmu->reset) | |
791 | armpmu->reset(armpmu); | |
792 | ||
793 | if (!enabled) | |
794 | return NOTIFY_OK; | |
795 | ||
796 | switch (cmd) { | |
797 | case CPU_PM_ENTER: | |
798 | armpmu->stop(armpmu); | |
799 | cpu_pm_pmu_setup(armpmu, cmd); | |
800 | break; | |
801 | case CPU_PM_EXIT: | |
802 | cpu_pm_pmu_setup(armpmu, cmd); | |
803 | case CPU_PM_ENTER_FAILED: | |
804 | armpmu->start(armpmu); | |
805 | break; | |
806 | default: | |
807 | return NOTIFY_DONE; | |
808 | } | |
809 | ||
810 | return NOTIFY_OK; | |
811 | } | |
812 | ||
813 | static int cpu_pm_pmu_register(struct arm_pmu *cpu_pmu) | |
814 | { | |
815 | cpu_pmu->cpu_pm_nb.notifier_call = cpu_pm_pmu_notify; | |
816 | return cpu_pm_register_notifier(&cpu_pmu->cpu_pm_nb); | |
817 | } | |
818 | ||
819 | static void cpu_pm_pmu_unregister(struct arm_pmu *cpu_pmu) | |
820 | { | |
821 | cpu_pm_unregister_notifier(&cpu_pmu->cpu_pm_nb); | |
822 | } | |
823 | #else | |
824 | static inline int cpu_pm_pmu_register(struct arm_pmu *cpu_pmu) { return 0; } | |
825 | static inline void cpu_pm_pmu_unregister(struct arm_pmu *cpu_pmu) { } | |
826 | #endif | |
827 | ||
74cf0bc7 MR |
828 | static int cpu_pmu_init(struct arm_pmu *cpu_pmu) |
829 | { | |
830 | int err; | |
831 | int cpu; | |
832 | struct pmu_hw_events __percpu *cpu_hw_events; | |
833 | ||
834 | cpu_hw_events = alloc_percpu(struct pmu_hw_events); | |
835 | if (!cpu_hw_events) | |
836 | return -ENOMEM; | |
837 | ||
6e103c0c SAS |
838 | err = cpuhp_state_add_instance_nocalls(CPUHP_AP_PERF_ARM_STARTING, |
839 | &cpu_pmu->node); | |
840 | if (err) | |
841 | goto out_free; | |
74cf0bc7 | 842 | |
da4e4f18 LP |
843 | err = cpu_pm_pmu_register(cpu_pmu); |
844 | if (err) | |
845 | goto out_unregister; | |
846 | ||
74cf0bc7 MR |
847 | for_each_possible_cpu(cpu) { |
848 | struct pmu_hw_events *events = per_cpu_ptr(cpu_hw_events, cpu); | |
849 | raw_spin_lock_init(&events->pmu_lock); | |
850 | events->percpu_pmu = cpu_pmu; | |
851 | } | |
852 | ||
853 | cpu_pmu->hw_events = cpu_hw_events; | |
854 | cpu_pmu->request_irq = cpu_pmu_request_irq; | |
855 | cpu_pmu->free_irq = cpu_pmu_free_irq; | |
856 | ||
857 | /* Ensure the PMU has sane values out of reset. */ | |
858 | if (cpu_pmu->reset) | |
859 | on_each_cpu_mask(&cpu_pmu->supported_cpus, cpu_pmu->reset, | |
860 | cpu_pmu, 1); | |
861 | ||
862 | /* If no interrupts available, set the corresponding capability flag */ | |
863 | if (!platform_get_irq(cpu_pmu->plat_device, 0)) | |
864 | cpu_pmu->pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT; | |
865 | ||
5101ef20 MR |
866 | /* |
867 | * This is a CPU PMU potentially in a heterogeneous configuration (e.g. | |
868 | * big.LITTLE). This is not an uncore PMU, and we have taken ctx | |
869 | * sharing into account (e.g. with our pmu::filter_match callback and | |
870 | * pmu::event_init group validation). | |
871 | */ | |
872 | cpu_pmu->pmu.capabilities |= PERF_PMU_CAP_HETEROGENEOUS_CPUS; | |
873 | ||
74cf0bc7 MR |
874 | return 0; |
875 | ||
da4e4f18 | 876 | out_unregister: |
6e103c0c SAS |
877 | cpuhp_state_remove_instance_nocalls(CPUHP_AP_PERF_ARM_STARTING, |
878 | &cpu_pmu->node); | |
879 | out_free: | |
74cf0bc7 MR |
880 | free_percpu(cpu_hw_events); |
881 | return err; | |
882 | } | |
883 | ||
884 | static void cpu_pmu_destroy(struct arm_pmu *cpu_pmu) | |
885 | { | |
da4e4f18 | 886 | cpu_pm_pmu_unregister(cpu_pmu); |
6e103c0c SAS |
887 | cpuhp_state_remove_instance_nocalls(CPUHP_AP_PERF_ARM_STARTING, |
888 | &cpu_pmu->node); | |
74cf0bc7 MR |
889 | free_percpu(cpu_pmu->hw_events); |
890 | } | |
891 | ||
892 | /* | |
893 | * CPU PMU identification and probing. | |
894 | */ | |
895 | static int probe_current_pmu(struct arm_pmu *pmu, | |
896 | const struct pmu_probe_info *info) | |
897 | { | |
898 | int cpu = get_cpu(); | |
899 | unsigned int cpuid = read_cpuid_id(); | |
900 | int ret = -ENODEV; | |
901 | ||
902 | pr_info("probing PMU on CPU %d\n", cpu); | |
903 | ||
904 | for (; info->init != NULL; info++) { | |
905 | if ((cpuid & info->mask) != info->cpuid) | |
906 | continue; | |
907 | ret = info->init(pmu); | |
908 | break; | |
909 | } | |
910 | ||
911 | put_cpu(); | |
912 | return ret; | |
913 | } | |
914 | ||
915 | static int of_pmu_irq_cfg(struct arm_pmu *pmu) | |
916 | { | |
b6c084d7 WD |
917 | int *irqs, i = 0; |
918 | bool using_spi = false; | |
74cf0bc7 MR |
919 | struct platform_device *pdev = pmu->plat_device; |
920 | ||
74cf0bc7 MR |
921 | irqs = kcalloc(pdev->num_resources, sizeof(*irqs), GFP_KERNEL); |
922 | if (!irqs) | |
923 | return -ENOMEM; | |
924 | ||
b6c084d7 | 925 | do { |
74cf0bc7 | 926 | struct device_node *dn; |
b6c084d7 | 927 | int cpu, irq; |
74cf0bc7 | 928 | |
b6c084d7 WD |
929 | /* See if we have an affinity entry */ |
930 | dn = of_parse_phandle(pdev->dev.of_node, "interrupt-affinity", i); | |
931 | if (!dn) | |
74cf0bc7 | 932 | break; |
b6c084d7 WD |
933 | |
934 | /* Check the IRQ type and prohibit a mix of PPIs and SPIs */ | |
935 | irq = platform_get_irq(pdev, i); | |
282b8796 | 936 | if (irq > 0) { |
b6c084d7 WD |
937 | bool spi = !irq_is_percpu(irq); |
938 | ||
939 | if (i > 0 && spi != using_spi) { | |
940 | pr_err("PPI/SPI IRQ type mismatch for %s!\n", | |
941 | dn->name); | |
75324684 | 942 | of_node_put(dn); |
b6c084d7 WD |
943 | kfree(irqs); |
944 | return -EINVAL; | |
945 | } | |
946 | ||
947 | using_spi = spi; | |
74cf0bc7 MR |
948 | } |
949 | ||
b6c084d7 | 950 | /* Now look up the logical CPU number */ |
fb659882 WD |
951 | for_each_possible_cpu(cpu) { |
952 | struct device_node *cpu_dn; | |
953 | ||
954 | cpu_dn = of_cpu_device_node_get(cpu); | |
955 | of_node_put(cpu_dn); | |
956 | ||
957 | if (dn == cpu_dn) | |
74cf0bc7 | 958 | break; |
fb659882 | 959 | } |
74cf0bc7 | 960 | |
74cf0bc7 MR |
961 | if (cpu >= nr_cpu_ids) { |
962 | pr_warn("Failed to find logical CPU for %s\n", | |
963 | dn->name); | |
8e0c34b0 | 964 | of_node_put(dn); |
b6c084d7 | 965 | cpumask_setall(&pmu->supported_cpus); |
74cf0bc7 MR |
966 | break; |
967 | } | |
8e0c34b0 | 968 | of_node_put(dn); |
74cf0bc7 | 969 | |
b6c084d7 WD |
970 | /* For SPIs, we need to track the affinity per IRQ */ |
971 | if (using_spi) { | |
121323ae | 972 | if (i >= pdev->num_resources) |
b6c084d7 | 973 | break; |
b6c084d7 WD |
974 | |
975 | irqs[i] = cpu; | |
976 | } | |
977 | ||
978 | /* Keep track of the CPUs containing this PMU type */ | |
74cf0bc7 | 979 | cpumask_set_cpu(cpu, &pmu->supported_cpus); |
b6c084d7 WD |
980 | i++; |
981 | } while (1); | |
74cf0bc7 | 982 | |
19a469a5 MZ |
983 | /* If we didn't manage to parse anything, try the interrupt affinity */ |
984 | if (cpumask_weight(&pmu->supported_cpus) == 0) { | |
7f1d642f MZ |
985 | int irq = platform_get_irq(pdev, 0); |
986 | ||
282b8796 | 987 | if (irq > 0 && irq_is_percpu(irq)) { |
19a469a5 | 988 | /* If using PPIs, check the affinity of the partition */ |
7f1d642f | 989 | int ret; |
19a469a5 | 990 | |
19a469a5 MZ |
991 | ret = irq_get_percpu_devid_partition(irq, &pmu->supported_cpus); |
992 | if (ret) { | |
993 | kfree(irqs); | |
994 | return ret; | |
995 | } | |
996 | } else { | |
997 | /* Otherwise default to all CPUs */ | |
998 | cpumask_setall(&pmu->supported_cpus); | |
999 | } | |
1000 | } | |
b6c084d7 WD |
1001 | |
1002 | /* If we matched up the IRQ affinities, use them to route the SPIs */ | |
1003 | if (using_spi && i == pdev->num_resources) | |
74cf0bc7 | 1004 | pmu->irq_affinity = irqs; |
b6c084d7 | 1005 | else |
74cf0bc7 | 1006 | kfree(irqs); |
74cf0bc7 MR |
1007 | |
1008 | return 0; | |
1009 | } | |
1010 | ||
1011 | int arm_pmu_device_probe(struct platform_device *pdev, | |
1012 | const struct of_device_id *of_table, | |
1013 | const struct pmu_probe_info *probe_table) | |
1014 | { | |
1015 | const struct of_device_id *of_id; | |
1016 | const int (*init_fn)(struct arm_pmu *); | |
1017 | struct device_node *node = pdev->dev.of_node; | |
1018 | struct arm_pmu *pmu; | |
1019 | int ret = -ENODEV; | |
1020 | ||
1021 | pmu = kzalloc(sizeof(struct arm_pmu), GFP_KERNEL); | |
1022 | if (!pmu) { | |
1023 | pr_info("failed to allocate PMU device!\n"); | |
1024 | return -ENOMEM; | |
1025 | } | |
1026 | ||
b916b785 MR |
1027 | armpmu_init(pmu); |
1028 | ||
74cf0bc7 MR |
1029 | pmu->plat_device = pdev; |
1030 | ||
1031 | if (node && (of_id = of_match_node(of_table, pdev->dev.of_node))) { | |
1032 | init_fn = of_id->data; | |
1033 | ||
8d1a0ae7 MF |
1034 | pmu->secure_access = of_property_read_bool(pdev->dev.of_node, |
1035 | "secure-reg-access"); | |
1036 | ||
1037 | /* arm64 systems boot only as non-secure */ | |
1038 | if (IS_ENABLED(CONFIG_ARM64) && pmu->secure_access) { | |
1039 | pr_warn("ignoring \"secure-reg-access\" property for arm64\n"); | |
1040 | pmu->secure_access = false; | |
1041 | } | |
1042 | ||
74cf0bc7 MR |
1043 | ret = of_pmu_irq_cfg(pmu); |
1044 | if (!ret) | |
1045 | ret = init_fn(pmu); | |
dbee3a74 | 1046 | } else if (probe_table) { |
74cf0bc7 | 1047 | cpumask_setall(&pmu->supported_cpus); |
f7a6c149 | 1048 | ret = probe_current_pmu(pmu, probe_table); |
74cf0bc7 MR |
1049 | } |
1050 | ||
1051 | if (ret) { | |
357b565d | 1052 | pr_info("%s: failed to probe PMU!\n", of_node_full_name(node)); |
74cf0bc7 MR |
1053 | goto out_free; |
1054 | } | |
1055 | ||
86cdd72a | 1056 | |
74cf0bc7 MR |
1057 | ret = cpu_pmu_init(pmu); |
1058 | if (ret) | |
1059 | goto out_free; | |
1060 | ||
b916b785 | 1061 | ret = perf_pmu_register(&pmu->pmu, pmu->name, -1); |
74cf0bc7 MR |
1062 | if (ret) |
1063 | goto out_destroy; | |
1064 | ||
0f254c76 JG |
1065 | if (!__oprofile_cpu_pmu) |
1066 | __oprofile_cpu_pmu = pmu; | |
1067 | ||
b916b785 MR |
1068 | pr_info("enabled with %s PMU driver, %d counters available\n", |
1069 | pmu->name, pmu->num_events); | |
1070 | ||
74cf0bc7 MR |
1071 | return 0; |
1072 | ||
1073 | out_destroy: | |
1074 | cpu_pmu_destroy(pmu); | |
1075 | out_free: | |
357b565d WD |
1076 | pr_info("%s: failed to register PMU devices!\n", |
1077 | of_node_full_name(node)); | |
5988a363 | 1078 | kfree(pmu->irq_affinity); |
74cf0bc7 MR |
1079 | kfree(pmu); |
1080 | return ret; | |
1081 | } | |
37b502f1 SAS |
1082 | |
1083 | static int arm_pmu_hp_init(void) | |
1084 | { | |
1085 | int ret; | |
1086 | ||
6e103c0c | 1087 | ret = cpuhp_setup_state_multi(CPUHP_AP_PERF_ARM_STARTING, |
73c1b41e | 1088 | "perf/arm/pmu:starting", |
6e103c0c | 1089 | arm_perf_starting_cpu, NULL); |
37b502f1 SAS |
1090 | if (ret) |
1091 | pr_err("CPU hotplug notifier for ARM PMU could not be registered: %d\n", | |
1092 | ret); | |
1093 | return ret; | |
1094 | } | |
1095 | subsys_initcall(arm_pmu_hp_init); |