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Commit | Line | Data |
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1b8873a0 JI |
1 | #undef DEBUG |
2 | ||
3 | /* | |
4 | * ARM performance counter support. | |
5 | * | |
6 | * Copyright (C) 2009 picoChip Designs, Ltd., Jamie Iles | |
43eab878 | 7 | * Copyright (C) 2010 ARM Ltd., Will Deacon <will.deacon@arm.com> |
796d1295 | 8 | * |
1b8873a0 | 9 | * This code is based on the sparc64 perf event code, which is in turn based |
d39976f0 | 10 | * on the x86 code. |
1b8873a0 JI |
11 | */ |
12 | #define pr_fmt(fmt) "hw perfevents: " fmt | |
13 | ||
74cf0bc7 | 14 | #include <linux/bitmap.h> |
cc88116d | 15 | #include <linux/cpumask.h> |
da4e4f18 | 16 | #include <linux/cpu_pm.h> |
74cf0bc7 | 17 | #include <linux/export.h> |
1b8873a0 | 18 | #include <linux/kernel.h> |
fa8ad788 | 19 | #include <linux/perf/arm_pmu.h> |
74cf0bc7 | 20 | #include <linux/slab.h> |
e6017571 | 21 | #include <linux/sched/clock.h> |
74cf0bc7 | 22 | #include <linux/spinlock.h> |
bbd64559 SB |
23 | #include <linux/irq.h> |
24 | #include <linux/irqdesc.h> | |
1b8873a0 | 25 | |
1b8873a0 | 26 | #include <asm/irq_regs.h> |
1b8873a0 | 27 | |
84b4be57 MR |
28 | static DEFINE_PER_CPU(struct arm_pmu *, cpu_armpmu); |
29 | static DEFINE_PER_CPU(int, cpu_irq); | |
30 | ||
8d3e9942 SP |
31 | static inline u64 arm_pmu_max_period(void) |
32 | { | |
33 | return (1ULL << 32) - 1; | |
34 | } | |
35 | ||
1b8873a0 | 36 | static int |
e1f431b5 MR |
37 | armpmu_map_cache_event(const unsigned (*cache_map) |
38 | [PERF_COUNT_HW_CACHE_MAX] | |
39 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
40 | [PERF_COUNT_HW_CACHE_RESULT_MAX], | |
41 | u64 config) | |
1b8873a0 JI |
42 | { |
43 | unsigned int cache_type, cache_op, cache_result, ret; | |
44 | ||
45 | cache_type = (config >> 0) & 0xff; | |
46 | if (cache_type >= PERF_COUNT_HW_CACHE_MAX) | |
47 | return -EINVAL; | |
48 | ||
49 | cache_op = (config >> 8) & 0xff; | |
50 | if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX) | |
51 | return -EINVAL; | |
52 | ||
53 | cache_result = (config >> 16) & 0xff; | |
54 | if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX) | |
55 | return -EINVAL; | |
56 | ||
6c833bb9 WD |
57 | if (!cache_map) |
58 | return -ENOENT; | |
59 | ||
e1f431b5 | 60 | ret = (int)(*cache_map)[cache_type][cache_op][cache_result]; |
1b8873a0 JI |
61 | |
62 | if (ret == CACHE_OP_UNSUPPORTED) | |
63 | return -ENOENT; | |
64 | ||
65 | return ret; | |
66 | } | |
67 | ||
84fee97a | 68 | static int |
6dbc0029 | 69 | armpmu_map_hw_event(const unsigned (*event_map)[PERF_COUNT_HW_MAX], u64 config) |
84fee97a | 70 | { |
d9f96635 SB |
71 | int mapping; |
72 | ||
73 | if (config >= PERF_COUNT_HW_MAX) | |
74 | return -EINVAL; | |
75 | ||
6c833bb9 WD |
76 | if (!event_map) |
77 | return -ENOENT; | |
78 | ||
d9f96635 | 79 | mapping = (*event_map)[config]; |
e1f431b5 | 80 | return mapping == HW_OP_UNSUPPORTED ? -ENOENT : mapping; |
84fee97a WD |
81 | } |
82 | ||
83 | static int | |
e1f431b5 | 84 | armpmu_map_raw_event(u32 raw_event_mask, u64 config) |
84fee97a | 85 | { |
e1f431b5 MR |
86 | return (int)(config & raw_event_mask); |
87 | } | |
88 | ||
6dbc0029 WD |
89 | int |
90 | armpmu_map_event(struct perf_event *event, | |
91 | const unsigned (*event_map)[PERF_COUNT_HW_MAX], | |
92 | const unsigned (*cache_map) | |
93 | [PERF_COUNT_HW_CACHE_MAX] | |
94 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
95 | [PERF_COUNT_HW_CACHE_RESULT_MAX], | |
96 | u32 raw_event_mask) | |
e1f431b5 MR |
97 | { |
98 | u64 config = event->attr.config; | |
67b4305a | 99 | int type = event->attr.type; |
e1f431b5 | 100 | |
67b4305a MR |
101 | if (type == event->pmu->type) |
102 | return armpmu_map_raw_event(raw_event_mask, config); | |
103 | ||
104 | switch (type) { | |
e1f431b5 | 105 | case PERF_TYPE_HARDWARE: |
6dbc0029 | 106 | return armpmu_map_hw_event(event_map, config); |
e1f431b5 MR |
107 | case PERF_TYPE_HW_CACHE: |
108 | return armpmu_map_cache_event(cache_map, config); | |
109 | case PERF_TYPE_RAW: | |
110 | return armpmu_map_raw_event(raw_event_mask, config); | |
111 | } | |
112 | ||
113 | return -ENOENT; | |
84fee97a WD |
114 | } |
115 | ||
ed6f2a52 | 116 | int armpmu_event_set_period(struct perf_event *event) |
1b8873a0 | 117 | { |
8a16b34e | 118 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
ed6f2a52 | 119 | struct hw_perf_event *hwc = &event->hw; |
e7850595 | 120 | s64 left = local64_read(&hwc->period_left); |
1b8873a0 | 121 | s64 period = hwc->sample_period; |
8d3e9942 | 122 | u64 max_period; |
1b8873a0 JI |
123 | int ret = 0; |
124 | ||
8d3e9942 | 125 | max_period = arm_pmu_max_period(); |
1b8873a0 JI |
126 | if (unlikely(left <= -period)) { |
127 | left = period; | |
e7850595 | 128 | local64_set(&hwc->period_left, left); |
1b8873a0 JI |
129 | hwc->last_period = period; |
130 | ret = 1; | |
131 | } | |
132 | ||
133 | if (unlikely(left <= 0)) { | |
134 | left += period; | |
e7850595 | 135 | local64_set(&hwc->period_left, left); |
1b8873a0 JI |
136 | hwc->last_period = period; |
137 | ret = 1; | |
138 | } | |
139 | ||
2d9ed740 DT |
140 | /* |
141 | * Limit the maximum period to prevent the counter value | |
142 | * from overtaking the one we are about to program. In | |
143 | * effect we are reducing max_period to account for | |
144 | * interrupt latency (and we are being very conservative). | |
145 | */ | |
8d3e9942 SP |
146 | if (left > (max_period >> 1)) |
147 | left = (max_period >> 1); | |
1b8873a0 | 148 | |
e7850595 | 149 | local64_set(&hwc->prev_count, (u64)-left); |
1b8873a0 | 150 | |
ed6f2a52 | 151 | armpmu->write_counter(event, (u64)(-left) & 0xffffffff); |
1b8873a0 JI |
152 | |
153 | perf_event_update_userpage(event); | |
154 | ||
155 | return ret; | |
156 | } | |
157 | ||
ed6f2a52 | 158 | u64 armpmu_event_update(struct perf_event *event) |
1b8873a0 | 159 | { |
8a16b34e | 160 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
ed6f2a52 | 161 | struct hw_perf_event *hwc = &event->hw; |
a737823d | 162 | u64 delta, prev_raw_count, new_raw_count; |
8d3e9942 | 163 | u64 max_period = arm_pmu_max_period(); |
1b8873a0 JI |
164 | |
165 | again: | |
e7850595 | 166 | prev_raw_count = local64_read(&hwc->prev_count); |
ed6f2a52 | 167 | new_raw_count = armpmu->read_counter(event); |
1b8873a0 | 168 | |
e7850595 | 169 | if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, |
1b8873a0 JI |
170 | new_raw_count) != prev_raw_count) |
171 | goto again; | |
172 | ||
8d3e9942 | 173 | delta = (new_raw_count - prev_raw_count) & max_period; |
1b8873a0 | 174 | |
e7850595 PZ |
175 | local64_add(delta, &event->count); |
176 | local64_sub(delta, &hwc->period_left); | |
1b8873a0 JI |
177 | |
178 | return new_raw_count; | |
179 | } | |
180 | ||
181 | static void | |
a4eaf7f1 | 182 | armpmu_read(struct perf_event *event) |
1b8873a0 | 183 | { |
ed6f2a52 | 184 | armpmu_event_update(event); |
1b8873a0 JI |
185 | } |
186 | ||
187 | static void | |
a4eaf7f1 | 188 | armpmu_stop(struct perf_event *event, int flags) |
1b8873a0 | 189 | { |
8a16b34e | 190 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
1b8873a0 JI |
191 | struct hw_perf_event *hwc = &event->hw; |
192 | ||
a4eaf7f1 PZ |
193 | /* |
194 | * ARM pmu always has to update the counter, so ignore | |
195 | * PERF_EF_UPDATE, see comments in armpmu_start(). | |
196 | */ | |
197 | if (!(hwc->state & PERF_HES_STOPPED)) { | |
ed6f2a52 SH |
198 | armpmu->disable(event); |
199 | armpmu_event_update(event); | |
a4eaf7f1 PZ |
200 | hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE; |
201 | } | |
1b8873a0 JI |
202 | } |
203 | ||
ed6f2a52 | 204 | static void armpmu_start(struct perf_event *event, int flags) |
1b8873a0 | 205 | { |
8a16b34e | 206 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
1b8873a0 JI |
207 | struct hw_perf_event *hwc = &event->hw; |
208 | ||
a4eaf7f1 PZ |
209 | /* |
210 | * ARM pmu always has to reprogram the period, so ignore | |
211 | * PERF_EF_RELOAD, see the comment below. | |
212 | */ | |
213 | if (flags & PERF_EF_RELOAD) | |
214 | WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE)); | |
215 | ||
216 | hwc->state = 0; | |
1b8873a0 JI |
217 | /* |
218 | * Set the period again. Some counters can't be stopped, so when we | |
a4eaf7f1 | 219 | * were stopped we simply disabled the IRQ source and the counter |
1b8873a0 JI |
220 | * may have been left counting. If we don't do this step then we may |
221 | * get an interrupt too soon or *way* too late if the overflow has | |
222 | * happened since disabling. | |
223 | */ | |
ed6f2a52 SH |
224 | armpmu_event_set_period(event); |
225 | armpmu->enable(event); | |
1b8873a0 JI |
226 | } |
227 | ||
a4eaf7f1 PZ |
228 | static void |
229 | armpmu_del(struct perf_event *event, int flags) | |
230 | { | |
8a16b34e | 231 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
11679250 | 232 | struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events); |
a4eaf7f1 PZ |
233 | struct hw_perf_event *hwc = &event->hw; |
234 | int idx = hwc->idx; | |
235 | ||
a4eaf7f1 | 236 | armpmu_stop(event, PERF_EF_UPDATE); |
8be3f9a2 MR |
237 | hw_events->events[idx] = NULL; |
238 | clear_bit(idx, hw_events->used_mask); | |
eab443ef SB |
239 | if (armpmu->clear_event_idx) |
240 | armpmu->clear_event_idx(hw_events, event); | |
a4eaf7f1 PZ |
241 | |
242 | perf_event_update_userpage(event); | |
243 | } | |
244 | ||
1b8873a0 | 245 | static int |
a4eaf7f1 | 246 | armpmu_add(struct perf_event *event, int flags) |
1b8873a0 | 247 | { |
8a16b34e | 248 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
11679250 | 249 | struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events); |
1b8873a0 JI |
250 | struct hw_perf_event *hwc = &event->hw; |
251 | int idx; | |
1b8873a0 | 252 | |
cc88116d MR |
253 | /* An event following a process won't be stopped earlier */ |
254 | if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus)) | |
255 | return -ENOENT; | |
256 | ||
1b8873a0 | 257 | /* If we don't have a space for the counter then finish early. */ |
ed6f2a52 | 258 | idx = armpmu->get_event_idx(hw_events, event); |
a9e469d1 MR |
259 | if (idx < 0) |
260 | return idx; | |
1b8873a0 JI |
261 | |
262 | /* | |
263 | * If there is an event in the counter we are going to use then make | |
264 | * sure it is disabled. | |
265 | */ | |
266 | event->hw.idx = idx; | |
ed6f2a52 | 267 | armpmu->disable(event); |
8be3f9a2 | 268 | hw_events->events[idx] = event; |
1b8873a0 | 269 | |
a4eaf7f1 PZ |
270 | hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE; |
271 | if (flags & PERF_EF_START) | |
272 | armpmu_start(event, PERF_EF_RELOAD); | |
1b8873a0 JI |
273 | |
274 | /* Propagate our changes to the userspace mapping. */ | |
275 | perf_event_update_userpage(event); | |
276 | ||
a9e469d1 | 277 | return 0; |
1b8873a0 JI |
278 | } |
279 | ||
1b8873a0 | 280 | static int |
e429817b SP |
281 | validate_event(struct pmu *pmu, struct pmu_hw_events *hw_events, |
282 | struct perf_event *event) | |
1b8873a0 | 283 | { |
e429817b | 284 | struct arm_pmu *armpmu; |
1b8873a0 | 285 | |
c95eb318 WD |
286 | if (is_software_event(event)) |
287 | return 1; | |
288 | ||
e429817b SP |
289 | /* |
290 | * Reject groups spanning multiple HW PMUs (e.g. CPU + CCI). The | |
291 | * core perf code won't check that the pmu->ctx == leader->ctx | |
292 | * until after pmu->event_init(event). | |
293 | */ | |
294 | if (event->pmu != pmu) | |
295 | return 0; | |
296 | ||
2dfcb802 | 297 | if (event->state < PERF_EVENT_STATE_OFF) |
cb2d8b34 WD |
298 | return 1; |
299 | ||
300 | if (event->state == PERF_EVENT_STATE_OFF && !event->attr.enable_on_exec) | |
65b4711f | 301 | return 1; |
1b8873a0 | 302 | |
e429817b | 303 | armpmu = to_arm_pmu(event->pmu); |
ed6f2a52 | 304 | return armpmu->get_event_idx(hw_events, event) >= 0; |
1b8873a0 JI |
305 | } |
306 | ||
307 | static int | |
308 | validate_group(struct perf_event *event) | |
309 | { | |
310 | struct perf_event *sibling, *leader = event->group_leader; | |
8be3f9a2 | 311 | struct pmu_hw_events fake_pmu; |
1b8873a0 | 312 | |
bce34d14 WD |
313 | /* |
314 | * Initialise the fake PMU. We only need to populate the | |
315 | * used_mask for the purposes of validation. | |
316 | */ | |
a4560846 | 317 | memset(&fake_pmu.used_mask, 0, sizeof(fake_pmu.used_mask)); |
1b8873a0 | 318 | |
e429817b | 319 | if (!validate_event(event->pmu, &fake_pmu, leader)) |
aa2bc1ad | 320 | return -EINVAL; |
1b8873a0 | 321 | |
edb39592 | 322 | for_each_sibling_event(sibling, leader) { |
e429817b | 323 | if (!validate_event(event->pmu, &fake_pmu, sibling)) |
aa2bc1ad | 324 | return -EINVAL; |
1b8873a0 JI |
325 | } |
326 | ||
e429817b | 327 | if (!validate_event(event->pmu, &fake_pmu, event)) |
aa2bc1ad | 328 | return -EINVAL; |
1b8873a0 JI |
329 | |
330 | return 0; | |
331 | } | |
332 | ||
051f1b13 | 333 | static irqreturn_t armpmu_dispatch_irq(int irq, void *dev) |
0e25a5c9 | 334 | { |
bbd64559 | 335 | struct arm_pmu *armpmu; |
5f5092e7 WD |
336 | int ret; |
337 | u64 start_clock, finish_clock; | |
bbd64559 | 338 | |
5ebd9200 MR |
339 | /* |
340 | * we request the IRQ with a (possibly percpu) struct arm_pmu**, but | |
341 | * the handlers expect a struct arm_pmu*. The percpu_irq framework will | |
342 | * do any necessary shifting, we just need to perform the first | |
343 | * dereference. | |
344 | */ | |
345 | armpmu = *(void **)dev; | |
84b4be57 MR |
346 | if (WARN_ON_ONCE(!armpmu)) |
347 | return IRQ_NONE; | |
76541370 | 348 | |
5f5092e7 | 349 | start_clock = sched_clock(); |
0788f1e9 | 350 | ret = armpmu->handle_irq(armpmu); |
5f5092e7 WD |
351 | finish_clock = sched_clock(); |
352 | ||
353 | perf_sample_event_took(finish_clock - start_clock); | |
354 | return ret; | |
0e25a5c9 RV |
355 | } |
356 | ||
05d22fde WD |
357 | static int |
358 | event_requires_mode_exclusion(struct perf_event_attr *attr) | |
359 | { | |
360 | return attr->exclude_idle || attr->exclude_user || | |
361 | attr->exclude_kernel || attr->exclude_hv; | |
362 | } | |
363 | ||
1b8873a0 JI |
364 | static int |
365 | __hw_perf_event_init(struct perf_event *event) | |
366 | { | |
8a16b34e | 367 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
1b8873a0 | 368 | struct hw_perf_event *hwc = &event->hw; |
9dcbf466 | 369 | int mapping; |
1b8873a0 | 370 | |
e1f431b5 | 371 | mapping = armpmu->map_event(event); |
1b8873a0 JI |
372 | |
373 | if (mapping < 0) { | |
374 | pr_debug("event %x:%llx not supported\n", event->attr.type, | |
375 | event->attr.config); | |
376 | return mapping; | |
377 | } | |
378 | ||
05d22fde WD |
379 | /* |
380 | * We don't assign an index until we actually place the event onto | |
381 | * hardware. Use -1 to signify that we haven't decided where to put it | |
382 | * yet. For SMP systems, each core has it's own PMU so we can't do any | |
383 | * clever allocation or constraints checking at this point. | |
384 | */ | |
385 | hwc->idx = -1; | |
386 | hwc->config_base = 0; | |
387 | hwc->config = 0; | |
388 | hwc->event_base = 0; | |
389 | ||
1b8873a0 JI |
390 | /* |
391 | * Check whether we need to exclude the counter from certain modes. | |
1b8873a0 | 392 | */ |
05d22fde WD |
393 | if ((!armpmu->set_event_filter || |
394 | armpmu->set_event_filter(hwc, &event->attr)) && | |
395 | event_requires_mode_exclusion(&event->attr)) { | |
1b8873a0 JI |
396 | pr_debug("ARM performance counters do not support " |
397 | "mode exclusion\n"); | |
fdeb8e35 | 398 | return -EOPNOTSUPP; |
1b8873a0 JI |
399 | } |
400 | ||
401 | /* | |
05d22fde | 402 | * Store the event encoding into the config_base field. |
1b8873a0 | 403 | */ |
05d22fde | 404 | hwc->config_base |= (unsigned long)mapping; |
1b8873a0 | 405 | |
edcb4d3c | 406 | if (!is_sampling_event(event)) { |
57273471 WD |
407 | /* |
408 | * For non-sampling runs, limit the sample_period to half | |
409 | * of the counter width. That way, the new counter value | |
410 | * is far less likely to overtake the previous one unless | |
411 | * you have some serious IRQ latency issues. | |
412 | */ | |
8d3e9942 | 413 | hwc->sample_period = arm_pmu_max_period() >> 1; |
1b8873a0 | 414 | hwc->last_period = hwc->sample_period; |
e7850595 | 415 | local64_set(&hwc->period_left, hwc->sample_period); |
1b8873a0 JI |
416 | } |
417 | ||
1b8873a0 | 418 | if (event->group_leader != event) { |
e595ede6 | 419 | if (validate_group(event) != 0) |
1b8873a0 JI |
420 | return -EINVAL; |
421 | } | |
422 | ||
9dcbf466 | 423 | return 0; |
1b8873a0 JI |
424 | } |
425 | ||
b0a873eb | 426 | static int armpmu_event_init(struct perf_event *event) |
1b8873a0 | 427 | { |
8a16b34e | 428 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
1b8873a0 | 429 | |
cc88116d MR |
430 | /* |
431 | * Reject CPU-affine events for CPUs that are of a different class to | |
432 | * that which this PMU handles. Process-following events (where | |
433 | * event->cpu == -1) can be migrated between CPUs, and thus we have to | |
434 | * reject them later (in armpmu_add) if they're scheduled on a | |
435 | * different class of CPU. | |
436 | */ | |
437 | if (event->cpu != -1 && | |
438 | !cpumask_test_cpu(event->cpu, &armpmu->supported_cpus)) | |
439 | return -ENOENT; | |
440 | ||
2481c5fa SE |
441 | /* does not support taken branch sampling */ |
442 | if (has_branch_stack(event)) | |
443 | return -EOPNOTSUPP; | |
444 | ||
e1f431b5 | 445 | if (armpmu->map_event(event) == -ENOENT) |
b0a873eb | 446 | return -ENOENT; |
b0a873eb | 447 | |
c09adab0 | 448 | return __hw_perf_event_init(event); |
1b8873a0 JI |
449 | } |
450 | ||
a4eaf7f1 | 451 | static void armpmu_enable(struct pmu *pmu) |
1b8873a0 | 452 | { |
8be3f9a2 | 453 | struct arm_pmu *armpmu = to_arm_pmu(pmu); |
11679250 | 454 | struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events); |
7325eaec | 455 | int enabled = bitmap_weight(hw_events->used_mask, armpmu->num_events); |
1b8873a0 | 456 | |
cc88116d MR |
457 | /* For task-bound events we may be called on other CPUs */ |
458 | if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus)) | |
459 | return; | |
460 | ||
f4f38430 | 461 | if (enabled) |
ed6f2a52 | 462 | armpmu->start(armpmu); |
1b8873a0 JI |
463 | } |
464 | ||
a4eaf7f1 | 465 | static void armpmu_disable(struct pmu *pmu) |
1b8873a0 | 466 | { |
8a16b34e | 467 | struct arm_pmu *armpmu = to_arm_pmu(pmu); |
cc88116d MR |
468 | |
469 | /* For task-bound events we may be called on other CPUs */ | |
470 | if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus)) | |
471 | return; | |
472 | ||
ed6f2a52 | 473 | armpmu->stop(armpmu); |
1b8873a0 JI |
474 | } |
475 | ||
c904e32a MR |
476 | /* |
477 | * In heterogeneous systems, events are specific to a particular | |
478 | * microarchitecture, and aren't suitable for another. Thus, only match CPUs of | |
479 | * the same microarchitecture. | |
480 | */ | |
481 | static int armpmu_filter_match(struct perf_event *event) | |
482 | { | |
483 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); | |
484 | unsigned int cpu = smp_processor_id(); | |
485 | return cpumask_test_cpu(cpu, &armpmu->supported_cpus); | |
486 | } | |
487 | ||
48538b58 MR |
488 | static ssize_t armpmu_cpumask_show(struct device *dev, |
489 | struct device_attribute *attr, char *buf) | |
490 | { | |
491 | struct arm_pmu *armpmu = to_arm_pmu(dev_get_drvdata(dev)); | |
492 | return cpumap_print_to_pagebuf(true, buf, &armpmu->supported_cpus); | |
493 | } | |
494 | ||
495 | static DEVICE_ATTR(cpus, S_IRUGO, armpmu_cpumask_show, NULL); | |
496 | ||
497 | static struct attribute *armpmu_common_attrs[] = { | |
498 | &dev_attr_cpus.attr, | |
499 | NULL, | |
500 | }; | |
501 | ||
502 | static struct attribute_group armpmu_common_attr_group = { | |
503 | .attrs = armpmu_common_attrs, | |
504 | }; | |
505 | ||
74cf0bc7 MR |
506 | /* Set at runtime when we know what CPU type we are. */ |
507 | static struct arm_pmu *__oprofile_cpu_pmu; | |
508 | ||
509 | /* | |
510 | * Despite the names, these two functions are CPU-specific and are used | |
511 | * by the OProfile/perf code. | |
512 | */ | |
513 | const char *perf_pmu_name(void) | |
514 | { | |
515 | if (!__oprofile_cpu_pmu) | |
516 | return NULL; | |
517 | ||
518 | return __oprofile_cpu_pmu->name; | |
519 | } | |
520 | EXPORT_SYMBOL_GPL(perf_pmu_name); | |
521 | ||
522 | int perf_num_counters(void) | |
523 | { | |
524 | int max_events = 0; | |
525 | ||
526 | if (__oprofile_cpu_pmu != NULL) | |
527 | max_events = __oprofile_cpu_pmu->num_events; | |
528 | ||
529 | return max_events; | |
530 | } | |
531 | EXPORT_SYMBOL_GPL(perf_num_counters); | |
532 | ||
84b4be57 | 533 | static int armpmu_count_irq_users(const int irq) |
74cf0bc7 | 534 | { |
84b4be57 | 535 | int cpu, count = 0; |
74cf0bc7 | 536 | |
84b4be57 MR |
537 | for_each_possible_cpu(cpu) { |
538 | if (per_cpu(cpu_irq, cpu) == irq) | |
539 | count++; | |
540 | } | |
541 | ||
542 | return count; | |
543 | } | |
7ed98e01 | 544 | |
167e6143 | 545 | void armpmu_free_irq(int irq, int cpu) |
84b4be57 MR |
546 | { |
547 | if (per_cpu(cpu_irq, cpu) == 0) | |
548 | return; | |
549 | if (WARN_ON(irq != per_cpu(cpu_irq, cpu))) | |
0e2663d9 | 550 | return; |
7ed98e01 | 551 | |
84b4be57 MR |
552 | if (!irq_is_percpu_devid(irq)) |
553 | free_irq(irq, per_cpu_ptr(&cpu_armpmu, cpu)); | |
554 | else if (armpmu_count_irq_users(irq) == 1) | |
555 | free_percpu_irq(irq, &cpu_armpmu); | |
556 | ||
557 | per_cpu(cpu_irq, cpu) = 0; | |
0e2663d9 | 558 | } |
7ed98e01 | 559 | |
167e6143 | 560 | int armpmu_request_irq(int irq, int cpu) |
84b4be57 MR |
561 | { |
562 | int err = 0; | |
563 | const irq_handler_t handler = armpmu_dispatch_irq; | |
0e2663d9 MR |
564 | if (!irq) |
565 | return 0; | |
74cf0bc7 | 566 | |
43fc9a2f | 567 | if (!irq_is_percpu_devid(irq)) { |
a3287c41 WD |
568 | unsigned long irq_flags; |
569 | ||
570 | err = irq_force_affinity(irq, cpumask_of(cpu)); | |
571 | ||
572 | if (err && num_possible_cpus() > 1) { | |
573 | pr_warn("unable to set irq affinity (irq=%d, cpu=%u)\n", | |
574 | irq, cpu); | |
575 | goto err_out; | |
576 | } | |
577 | ||
c0248c96 MR |
578 | irq_flags = IRQF_PERCPU | |
579 | IRQF_NOBALANCING | | |
580 | IRQF_NO_THREAD; | |
a3287c41 | 581 | |
6de3f791 | 582 | irq_set_status_flags(irq, IRQ_NOAUTOEN); |
a3287c41 | 583 | err = request_irq(irq, handler, irq_flags, "arm-pmu", |
84b4be57 MR |
584 | per_cpu_ptr(&cpu_armpmu, cpu)); |
585 | } else if (armpmu_count_irq_users(irq) == 0) { | |
43fc9a2f | 586 | err = request_percpu_irq(irq, handler, "arm-pmu", |
84b4be57 | 587 | &cpu_armpmu); |
0e2663d9 | 588 | } |
7ed98e01 | 589 | |
a3287c41 WD |
590 | if (err) |
591 | goto err_out; | |
74cf0bc7 | 592 | |
84b4be57 | 593 | per_cpu(cpu_irq, cpu) = irq; |
74cf0bc7 | 594 | return 0; |
a3287c41 WD |
595 | |
596 | err_out: | |
597 | pr_err("unable to request IRQ%d for ARM PMU counters\n", irq); | |
598 | return err; | |
74cf0bc7 MR |
599 | } |
600 | ||
c09adab0 MR |
601 | static int armpmu_get_cpu_irq(struct arm_pmu *pmu, int cpu) |
602 | { | |
603 | struct pmu_hw_events __percpu *hw_events = pmu->hw_events; | |
604 | return per_cpu(hw_events->irq, cpu); | |
605 | } | |
606 | ||
74cf0bc7 MR |
607 | /* |
608 | * PMU hardware loses all context when a CPU goes offline. | |
609 | * When a CPU is hotplugged back in, since some hardware registers are | |
610 | * UNKNOWN at reset, the PMU must be explicitly reset to avoid reading | |
611 | * junk values out of them. | |
612 | */ | |
6e103c0c | 613 | static int arm_perf_starting_cpu(unsigned int cpu, struct hlist_node *node) |
74cf0bc7 | 614 | { |
6e103c0c | 615 | struct arm_pmu *pmu = hlist_entry_safe(node, struct arm_pmu, node); |
c09adab0 | 616 | int irq; |
74cf0bc7 | 617 | |
6e103c0c SAS |
618 | if (!cpumask_test_cpu(cpu, &pmu->supported_cpus)) |
619 | return 0; | |
620 | if (pmu->reset) | |
621 | pmu->reset(pmu); | |
c09adab0 | 622 | |
84b4be57 MR |
623 | per_cpu(cpu_armpmu, cpu) = pmu; |
624 | ||
c09adab0 MR |
625 | irq = armpmu_get_cpu_irq(pmu, cpu); |
626 | if (irq) { | |
6de3f791 | 627 | if (irq_is_percpu_devid(irq)) |
c09adab0 | 628 | enable_percpu_irq(irq, IRQ_TYPE_NONE); |
6de3f791 MR |
629 | else |
630 | enable_irq(irq); | |
c09adab0 MR |
631 | } |
632 | ||
633 | return 0; | |
634 | } | |
635 | ||
636 | static int arm_perf_teardown_cpu(unsigned int cpu, struct hlist_node *node) | |
637 | { | |
638 | struct arm_pmu *pmu = hlist_entry_safe(node, struct arm_pmu, node); | |
639 | int irq; | |
640 | ||
641 | if (!cpumask_test_cpu(cpu, &pmu->supported_cpus)) | |
642 | return 0; | |
643 | ||
644 | irq = armpmu_get_cpu_irq(pmu, cpu); | |
6de3f791 MR |
645 | if (irq) { |
646 | if (irq_is_percpu_devid(irq)) | |
647 | disable_percpu_irq(irq); | |
648 | else | |
b08e5fd9 | 649 | disable_irq_nosync(irq); |
6de3f791 | 650 | } |
c09adab0 | 651 | |
84b4be57 MR |
652 | per_cpu(cpu_armpmu, cpu) = NULL; |
653 | ||
7d88eb69 | 654 | return 0; |
74cf0bc7 MR |
655 | } |
656 | ||
da4e4f18 LP |
657 | #ifdef CONFIG_CPU_PM |
658 | static void cpu_pm_pmu_setup(struct arm_pmu *armpmu, unsigned long cmd) | |
659 | { | |
660 | struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events); | |
661 | struct perf_event *event; | |
662 | int idx; | |
663 | ||
664 | for (idx = 0; idx < armpmu->num_events; idx++) { | |
665 | /* | |
666 | * If the counter is not used skip it, there is no | |
667 | * need of stopping/restarting it. | |
668 | */ | |
669 | if (!test_bit(idx, hw_events->used_mask)) | |
670 | continue; | |
671 | ||
672 | event = hw_events->events[idx]; | |
673 | ||
674 | switch (cmd) { | |
675 | case CPU_PM_ENTER: | |
676 | /* | |
677 | * Stop and update the counter | |
678 | */ | |
679 | armpmu_stop(event, PERF_EF_UPDATE); | |
680 | break; | |
681 | case CPU_PM_EXIT: | |
682 | case CPU_PM_ENTER_FAILED: | |
cbcc72e0 LP |
683 | /* |
684 | * Restore and enable the counter. | |
685 | * armpmu_start() indirectly calls | |
686 | * | |
687 | * perf_event_update_userpage() | |
688 | * | |
689 | * that requires RCU read locking to be functional, | |
690 | * wrap the call within RCU_NONIDLE to make the | |
691 | * RCU subsystem aware this cpu is not idle from | |
692 | * an RCU perspective for the armpmu_start() call | |
693 | * duration. | |
694 | */ | |
695 | RCU_NONIDLE(armpmu_start(event, PERF_EF_RELOAD)); | |
da4e4f18 LP |
696 | break; |
697 | default: | |
698 | break; | |
699 | } | |
700 | } | |
701 | } | |
702 | ||
703 | static int cpu_pm_pmu_notify(struct notifier_block *b, unsigned long cmd, | |
704 | void *v) | |
705 | { | |
706 | struct arm_pmu *armpmu = container_of(b, struct arm_pmu, cpu_pm_nb); | |
707 | struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events); | |
708 | int enabled = bitmap_weight(hw_events->used_mask, armpmu->num_events); | |
709 | ||
710 | if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus)) | |
711 | return NOTIFY_DONE; | |
712 | ||
713 | /* | |
714 | * Always reset the PMU registers on power-up even if | |
715 | * there are no events running. | |
716 | */ | |
717 | if (cmd == CPU_PM_EXIT && armpmu->reset) | |
718 | armpmu->reset(armpmu); | |
719 | ||
720 | if (!enabled) | |
721 | return NOTIFY_OK; | |
722 | ||
723 | switch (cmd) { | |
724 | case CPU_PM_ENTER: | |
725 | armpmu->stop(armpmu); | |
726 | cpu_pm_pmu_setup(armpmu, cmd); | |
727 | break; | |
728 | case CPU_PM_EXIT: | |
729 | cpu_pm_pmu_setup(armpmu, cmd); | |
730 | case CPU_PM_ENTER_FAILED: | |
731 | armpmu->start(armpmu); | |
732 | break; | |
733 | default: | |
734 | return NOTIFY_DONE; | |
735 | } | |
736 | ||
737 | return NOTIFY_OK; | |
738 | } | |
739 | ||
740 | static int cpu_pm_pmu_register(struct arm_pmu *cpu_pmu) | |
741 | { | |
742 | cpu_pmu->cpu_pm_nb.notifier_call = cpu_pm_pmu_notify; | |
743 | return cpu_pm_register_notifier(&cpu_pmu->cpu_pm_nb); | |
744 | } | |
745 | ||
746 | static void cpu_pm_pmu_unregister(struct arm_pmu *cpu_pmu) | |
747 | { | |
748 | cpu_pm_unregister_notifier(&cpu_pmu->cpu_pm_nb); | |
749 | } | |
750 | #else | |
751 | static inline int cpu_pm_pmu_register(struct arm_pmu *cpu_pmu) { return 0; } | |
752 | static inline void cpu_pm_pmu_unregister(struct arm_pmu *cpu_pmu) { } | |
753 | #endif | |
754 | ||
74cf0bc7 MR |
755 | static int cpu_pmu_init(struct arm_pmu *cpu_pmu) |
756 | { | |
757 | int err; | |
74cf0bc7 | 758 | |
c09adab0 MR |
759 | err = cpuhp_state_add_instance(CPUHP_AP_PERF_ARM_STARTING, |
760 | &cpu_pmu->node); | |
6e103c0c | 761 | if (err) |
2681f018 | 762 | goto out; |
74cf0bc7 | 763 | |
da4e4f18 LP |
764 | err = cpu_pm_pmu_register(cpu_pmu); |
765 | if (err) | |
766 | goto out_unregister; | |
767 | ||
74cf0bc7 MR |
768 | return 0; |
769 | ||
da4e4f18 | 770 | out_unregister: |
6e103c0c SAS |
771 | cpuhp_state_remove_instance_nocalls(CPUHP_AP_PERF_ARM_STARTING, |
772 | &cpu_pmu->node); | |
2681f018 | 773 | out: |
74cf0bc7 MR |
774 | return err; |
775 | } | |
776 | ||
777 | static void cpu_pmu_destroy(struct arm_pmu *cpu_pmu) | |
778 | { | |
da4e4f18 | 779 | cpu_pm_pmu_unregister(cpu_pmu); |
6e103c0c SAS |
780 | cpuhp_state_remove_instance_nocalls(CPUHP_AP_PERF_ARM_STARTING, |
781 | &cpu_pmu->node); | |
74cf0bc7 MR |
782 | } |
783 | ||
0dc1a185 | 784 | static struct arm_pmu *__armpmu_alloc(gfp_t flags) |
2681f018 MR |
785 | { |
786 | struct arm_pmu *pmu; | |
787 | int cpu; | |
788 | ||
0dc1a185 | 789 | pmu = kzalloc(sizeof(*pmu), flags); |
2681f018 MR |
790 | if (!pmu) { |
791 | pr_info("failed to allocate PMU device!\n"); | |
792 | goto out; | |
793 | } | |
794 | ||
0dc1a185 | 795 | pmu->hw_events = alloc_percpu_gfp(struct pmu_hw_events, flags); |
2681f018 MR |
796 | if (!pmu->hw_events) { |
797 | pr_info("failed to allocate per-cpu PMU data.\n"); | |
798 | goto out_free_pmu; | |
799 | } | |
800 | ||
70cd908a MR |
801 | pmu->pmu = (struct pmu) { |
802 | .pmu_enable = armpmu_enable, | |
803 | .pmu_disable = armpmu_disable, | |
804 | .event_init = armpmu_event_init, | |
805 | .add = armpmu_add, | |
806 | .del = armpmu_del, | |
807 | .start = armpmu_start, | |
808 | .stop = armpmu_stop, | |
809 | .read = armpmu_read, | |
810 | .filter_match = armpmu_filter_match, | |
811 | .attr_groups = pmu->attr_groups, | |
812 | /* | |
813 | * This is a CPU PMU potentially in a heterogeneous | |
814 | * configuration (e.g. big.LITTLE). This is not an uncore PMU, | |
815 | * and we have taken ctx sharing into account (e.g. with our | |
816 | * pmu::filter_match callback and pmu::event_init group | |
817 | * validation). | |
818 | */ | |
819 | .capabilities = PERF_PMU_CAP_HETEROGENEOUS_CPUS, | |
820 | }; | |
821 | ||
822 | pmu->attr_groups[ARMPMU_ATTR_GROUP_COMMON] = | |
823 | &armpmu_common_attr_group; | |
824 | ||
2681f018 MR |
825 | for_each_possible_cpu(cpu) { |
826 | struct pmu_hw_events *events; | |
827 | ||
828 | events = per_cpu_ptr(pmu->hw_events, cpu); | |
829 | raw_spin_lock_init(&events->pmu_lock); | |
830 | events->percpu_pmu = pmu; | |
831 | } | |
832 | ||
833 | return pmu; | |
834 | ||
835 | out_free_pmu: | |
836 | kfree(pmu); | |
837 | out: | |
838 | return NULL; | |
839 | } | |
840 | ||
0dc1a185 MR |
841 | struct arm_pmu *armpmu_alloc(void) |
842 | { | |
843 | return __armpmu_alloc(GFP_KERNEL); | |
844 | } | |
845 | ||
846 | struct arm_pmu *armpmu_alloc_atomic(void) | |
847 | { | |
848 | return __armpmu_alloc(GFP_ATOMIC); | |
849 | } | |
850 | ||
851 | ||
18bfcfe5 | 852 | void armpmu_free(struct arm_pmu *pmu) |
2681f018 MR |
853 | { |
854 | free_percpu(pmu->hw_events); | |
855 | kfree(pmu); | |
856 | } | |
857 | ||
74a2b3ea MR |
858 | int armpmu_register(struct arm_pmu *pmu) |
859 | { | |
860 | int ret; | |
861 | ||
862 | ret = cpu_pmu_init(pmu); | |
863 | if (ret) | |
864 | return ret; | |
865 | ||
866 | ret = perf_pmu_register(&pmu->pmu, pmu->name, -1); | |
867 | if (ret) | |
868 | goto out_destroy; | |
869 | ||
870 | if (!__oprofile_cpu_pmu) | |
871 | __oprofile_cpu_pmu = pmu; | |
872 | ||
873 | pr_info("enabled with %s PMU driver, %d counters available\n", | |
874 | pmu->name, pmu->num_events); | |
875 | ||
876 | return 0; | |
877 | ||
878 | out_destroy: | |
879 | cpu_pmu_destroy(pmu); | |
880 | return ret; | |
881 | } | |
882 | ||
37b502f1 SAS |
883 | static int arm_pmu_hp_init(void) |
884 | { | |
885 | int ret; | |
886 | ||
6e103c0c | 887 | ret = cpuhp_setup_state_multi(CPUHP_AP_PERF_ARM_STARTING, |
73c1b41e | 888 | "perf/arm/pmu:starting", |
c09adab0 MR |
889 | arm_perf_starting_cpu, |
890 | arm_perf_teardown_cpu); | |
37b502f1 SAS |
891 | if (ret) |
892 | pr_err("CPU hotplug notifier for ARM PMU could not be registered: %d\n", | |
893 | ret); | |
894 | return ret; | |
895 | } | |
896 | subsys_initcall(arm_pmu_hp_init); |