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e1000e: Fix e1000_check_for_copper_link_ich8lan return value.
[mirror_ubuntu-artful-kernel.git] / drivers / perf / xgene_pmu.c
CommitLineData
832c927d
TN		 1/*
2 * APM X-Gene SoC PMU (Performance Monitor Unit)
3 *
4 * Copyright (c) 2016, Applied Micro Circuits Corporation
5 * Author: Hoan Tran <hotran@apm.com>
6 * Tai Nguyen <ttnguyen@apm.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22#include <linux/acpi.h>
23#include <linux/clk.h>
24#include <linux/cpumask.h>
25#include <linux/interrupt.h>
26#include <linux/io.h>
27#include <linux/mfd/syscon.h>
c0bfc549 28#include <linux/module.h>
832c927d
TN		 29#include <linux/of_address.h>
30#include <linux/of_fdt.h>
31#include <linux/of_irq.h>
32#include <linux/of_platform.h>
33#include <linux/perf_event.h>
34#include <linux/platform_device.h>
35#include <linux/regmap.h>
36#include <linux/slab.h>
37
38#define CSW_CSWCR 0x0000
39#define CSW_CSWCR_DUALMCB_MASK BIT(0)
c0f7f7ac
HT		 40#define CSW_CSWCR_MCB0_ROUTING(x) (((x) & 0x0C) >> 2)
41#define CSW_CSWCR_MCB1_ROUTING(x) (((x) & 0x30) >> 4)
832c927d
TN		 42#define MCBADDRMR 0x0000
43#define MCBADDRMR_DUALMCU_MODE_MASK BIT(2)
44
45#define PCPPMU_INTSTATUS_REG 0x000
46#define PCPPMU_INTMASK_REG 0x004
47#define PCPPMU_INTMASK 0x0000000F
48#define PCPPMU_INTENMASK 0xFFFFFFFF
49#define PCPPMU_INTCLRMASK 0xFFFFFFF0
50#define PCPPMU_INT_MCU BIT(0)
51#define PCPPMU_INT_MCB BIT(1)
52#define PCPPMU_INT_L3C BIT(2)
53#define PCPPMU_INT_IOB BIT(3)
54
c0f7f7ac
HT		 55#define PCPPMU_V3_INTMASK 0x00FF33FF
56#define PCPPMU_V3_INTENMASK 0xFFFFFFFF
57#define PCPPMU_V3_INTCLRMASK 0xFF00CC00
58#define PCPPMU_V3_INT_MCU 0x000000FF
59#define PCPPMU_V3_INT_MCB 0x00000300
60#define PCPPMU_V3_INT_L3C 0x00FF0000
61#define PCPPMU_V3_INT_IOB 0x00003000
62
832c927d 63#define PMU_MAX_COUNTERS 4
c0f7f7ac
HT		 64#define PMU_CNT_MAX_PERIOD 0xFFFFFFFFULL
65#define PMU_V3_CNT_MAX_PERIOD 0xFFFFFFFFFFFFFFFFULL
832c927d
TN		 66#define PMU_OVERFLOW_MASK 0xF
67#define PMU_PMCR_E BIT(0)
68#define PMU_PMCR_P BIT(1)
69
70#define PMU_PMEVCNTR0 0x000
71#define PMU_PMEVCNTR1 0x004
72#define PMU_PMEVCNTR2 0x008
73#define PMU_PMEVCNTR3 0x00C
74#define PMU_PMEVTYPER0 0x400
75#define PMU_PMEVTYPER1 0x404
76#define PMU_PMEVTYPER2 0x408
77#define PMU_PMEVTYPER3 0x40C
78#define PMU_PMAMR0 0xA00
79#define PMU_PMAMR1 0xA04
80#define PMU_PMCNTENSET 0xC00
81#define PMU_PMCNTENCLR 0xC20
82#define PMU_PMINTENSET 0xC40
83#define PMU_PMINTENCLR 0xC60
84#define PMU_PMOVSR 0xC80
85#define PMU_PMCR 0xE04
86
c0f7f7ac
HT		 87/* PMU registers for V3 */
88#define PMU_PMOVSCLR 0xC80
89#define PMU_PMOVSSET 0xCC0
90
832c927d
TN		 91#define to_pmu_dev(p) container_of(p, struct xgene_pmu_dev, pmu)
92#define GET_CNTR(ev) (ev->hw.idx)
93#define GET_EVENTID(ev) (ev->hw.config & 0xFFULL)
94#define GET_AGENTID(ev) (ev->hw.config_base & 0xFFFFFFFFUL)
95#define GET_AGENT1ID(ev) ((ev->hw.config_base >> 32) & 0xFFFFFFFFUL)
96
97struct hw_pmu_info {
98 u32 type;
99 u32 enable_mask;
100 void __iomem *csr;
101};
102
103struct xgene_pmu_dev {
104 struct hw_pmu_info *inf;
105 struct xgene_pmu *parent;
106 struct pmu pmu;
107 u8 max_counters;
108 DECLARE_BITMAP(cntr_assign_mask, PMU_MAX_COUNTERS);
109 u64 max_period;
110 const struct attribute_group **attr_groups;
111 struct perf_event *pmu_counter_event[PMU_MAX_COUNTERS];
112};
113
e35e0a04
HT		 114struct xgene_pmu_ops {
115 void (*mask_int)(struct xgene_pmu *pmu);
116 void (*unmask_int)(struct xgene_pmu *pmu);
117 u64 (*read_counter)(struct xgene_pmu_dev *pmu, int idx);
118 void (*write_counter)(struct xgene_pmu_dev *pmu, int idx, u64 val);
119 void (*write_evttype)(struct xgene_pmu_dev *pmu_dev, int idx, u32 val);
120 void (*write_agentmsk)(struct xgene_pmu_dev *pmu_dev, u32 val);
121 void (*write_agent1msk)(struct xgene_pmu_dev *pmu_dev, u32 val);
122 void (*enable_counter)(struct xgene_pmu_dev *pmu_dev, int idx);
123 void (*disable_counter)(struct xgene_pmu_dev *pmu_dev, int idx);
124 void (*enable_counter_int)(struct xgene_pmu_dev *pmu_dev, int idx);
125 void (*disable_counter_int)(struct xgene_pmu_dev *pmu_dev, int idx);
126 void (*reset_counters)(struct xgene_pmu_dev *pmu_dev);
127 void (*start_counters)(struct xgene_pmu_dev *pmu_dev);
128 void (*stop_counters)(struct xgene_pmu_dev *pmu_dev);
129};
130
832c927d
TN		 131struct xgene_pmu {
132 struct device *dev;
133 int version;
134 void __iomem *pcppmu_csr;
135 u32 mcb_active_mask;
136 u32 mc_active_mask;
c0f7f7ac 137 u32 l3c_active_mask;
832c927d
TN		 138 cpumask_t cpu;
139 raw_spinlock_t lock;
e35e0a04 140 const struct xgene_pmu_ops *ops;
832c927d
TN		 141 struct list_head l3cpmus;
142 struct list_head iobpmus;
143 struct list_head mcbpmus;
144 struct list_head mcpmus;
145};
146
147struct xgene_pmu_dev_ctx {
148 char *name;
149 struct list_head next;
150 struct xgene_pmu_dev *pmu_dev;
151 struct hw_pmu_info inf;
152};
153
154struct xgene_pmu_data {
155 int id;
156 u32 data;
157};
158
159enum xgene_pmu_version {
160 PCP_PMU_V1 = 1,
161 PCP_PMU_V2,
c0f7f7ac 162 PCP_PMU_V3,
832c927d
TN		 163};
164
165enum xgene_pmu_dev_type {
166 PMU_TYPE_L3C = 0,
167 PMU_TYPE_IOB,
c0f7f7ac 168 PMU_TYPE_IOB_SLOW,
832c927d
TN		 169 PMU_TYPE_MCB,
170 PMU_TYPE_MC,
171};
172
173/*
174 * sysfs format attributes
175 */
176static ssize_t xgene_pmu_format_show(struct device *dev,
177 struct device_attribute *attr, char *buf)
178{
179 struct dev_ext_attribute *eattr;
180
181 eattr = container_of(attr, struct dev_ext_attribute, attr);
182 return sprintf(buf, "%s\n", (char *) eattr->var);
183}
184
185#define XGENE_PMU_FORMAT_ATTR(_name, _config) \
186 (&((struct dev_ext_attribute[]) { \
187 { .attr = __ATTR(_name, S_IRUGO, xgene_pmu_format_show, NULL), \
188 .var = (void *) _config, } \
189 })[0].attr.attr)
190
191static struct attribute *l3c_pmu_format_attrs[] = {
192 XGENE_PMU_FORMAT_ATTR(l3c_eventid, "config:0-7"),
193 XGENE_PMU_FORMAT_ATTR(l3c_agentid, "config1:0-9"),
194 NULL,
195};
196
197static struct attribute *iob_pmu_format_attrs[] = {
198 XGENE_PMU_FORMAT_ATTR(iob_eventid, "config:0-7"),
199 XGENE_PMU_FORMAT_ATTR(iob_agentid, "config1:0-63"),
200 NULL,
201};
202
203static struct attribute *mcb_pmu_format_attrs[] = {
204 XGENE_PMU_FORMAT_ATTR(mcb_eventid, "config:0-5"),
205 XGENE_PMU_FORMAT_ATTR(mcb_agentid, "config1:0-9"),
206 NULL,
207};
208
209static struct attribute *mc_pmu_format_attrs[] = {
210 XGENE_PMU_FORMAT_ATTR(mc_eventid, "config:0-28"),
211 NULL,
212};
213
214static const struct attribute_group l3c_pmu_format_attr_group = {
215 .name = "format",
216 .attrs = l3c_pmu_format_attrs,
217};
218
219static const struct attribute_group iob_pmu_format_attr_group = {
220 .name = "format",
221 .attrs = iob_pmu_format_attrs,
222};
223
224static const struct attribute_group mcb_pmu_format_attr_group = {
225 .name = "format",
226 .attrs = mcb_pmu_format_attrs,
227};
228
229static const struct attribute_group mc_pmu_format_attr_group = {
230 .name = "format",
231 .attrs = mc_pmu_format_attrs,
232};
233
c0f7f7ac
HT		 234static struct attribute *l3c_pmu_v3_format_attrs[] = {
235 XGENE_PMU_FORMAT_ATTR(l3c_eventid, "config:0-39"),
236 NULL,
237};
238
239static struct attribute *iob_pmu_v3_format_attrs[] = {
240 XGENE_PMU_FORMAT_ATTR(iob_eventid, "config:0-47"),
241 NULL,
242};
243
244static struct attribute *iob_slow_pmu_v3_format_attrs[] = {
245 XGENE_PMU_FORMAT_ATTR(iob_slow_eventid, "config:0-16"),
246 NULL,
247};
248
249static struct attribute *mcb_pmu_v3_format_attrs[] = {
250 XGENE_PMU_FORMAT_ATTR(mcb_eventid, "config:0-35"),
251 NULL,
252};
253
254static struct attribute *mc_pmu_v3_format_attrs[] = {
255 XGENE_PMU_FORMAT_ATTR(mc_eventid, "config:0-44"),
256 NULL,
257};
258
259static const struct attribute_group l3c_pmu_v3_format_attr_group = {
260 .name = "format",
261 .attrs = l3c_pmu_v3_format_attrs,
262};
263
264static const struct attribute_group iob_pmu_v3_format_attr_group = {
265 .name = "format",
266 .attrs = iob_pmu_v3_format_attrs,
267};
268
269static const struct attribute_group iob_slow_pmu_v3_format_attr_group = {
270 .name = "format",
271 .attrs = iob_slow_pmu_v3_format_attrs,
272};
273
274static const struct attribute_group mcb_pmu_v3_format_attr_group = {
275 .name = "format",
276 .attrs = mcb_pmu_v3_format_attrs,
277};
278
279static const struct attribute_group mc_pmu_v3_format_attr_group = {
280 .name = "format",
281 .attrs = mc_pmu_v3_format_attrs,
282};
283
832c927d
TN		 284/*
285 * sysfs event attributes
286 */
287static ssize_t xgene_pmu_event_show(struct device *dev,
288 struct device_attribute *attr, char *buf)
289{
290 struct dev_ext_attribute *eattr;
291
292 eattr = container_of(attr, struct dev_ext_attribute, attr);
293 return sprintf(buf, "config=0x%lx\n", (unsigned long) eattr->var);
294}
295
296#define XGENE_PMU_EVENT_ATTR(_name, _config) \
297 (&((struct dev_ext_attribute[]) { \
298 { .attr = __ATTR(_name, S_IRUGO, xgene_pmu_event_show, NULL), \
299 .var = (void *) _config, } \
300 })[0].attr.attr)
301
302static struct attribute *l3c_pmu_events_attrs[] = {
303 XGENE_PMU_EVENT_ATTR(cycle-count, 0x00),
304 XGENE_PMU_EVENT_ATTR(cycle-count-div-64, 0x01),
305 XGENE_PMU_EVENT_ATTR(read-hit, 0x02),
306 XGENE_PMU_EVENT_ATTR(read-miss, 0x03),
307 XGENE_PMU_EVENT_ATTR(write-need-replacement, 0x06),
308 XGENE_PMU_EVENT_ATTR(write-not-need-replacement, 0x07),
309 XGENE_PMU_EVENT_ATTR(tq-full, 0x08),
310 XGENE_PMU_EVENT_ATTR(ackq-full, 0x09),
311 XGENE_PMU_EVENT_ATTR(wdb-full, 0x0a),
312 XGENE_PMU_EVENT_ATTR(bank-fifo-full, 0x0b),
313 XGENE_PMU_EVENT_ATTR(odb-full, 0x0c),
314 XGENE_PMU_EVENT_ATTR(wbq-full, 0x0d),
315 XGENE_PMU_EVENT_ATTR(bank-conflict-fifo-issue, 0x0e),
316 XGENE_PMU_EVENT_ATTR(bank-fifo-issue, 0x0f),
317 NULL,
318};
319
320static struct attribute *iob_pmu_events_attrs[] = {
321 XGENE_PMU_EVENT_ATTR(cycle-count, 0x00),
322 XGENE_PMU_EVENT_ATTR(cycle-count-div-64, 0x01),
323 XGENE_PMU_EVENT_ATTR(axi0-read, 0x02),
324 XGENE_PMU_EVENT_ATTR(axi0-read-partial, 0x03),
325 XGENE_PMU_EVENT_ATTR(axi1-read, 0x04),
326 XGENE_PMU_EVENT_ATTR(axi1-read-partial, 0x05),
327 XGENE_PMU_EVENT_ATTR(csw-read-block, 0x06),
328 XGENE_PMU_EVENT_ATTR(csw-read-partial, 0x07),
329 XGENE_PMU_EVENT_ATTR(axi0-write, 0x10),
330 XGENE_PMU_EVENT_ATTR(axi0-write-partial, 0x11),
331 XGENE_PMU_EVENT_ATTR(axi1-write, 0x13),
332 XGENE_PMU_EVENT_ATTR(axi1-write-partial, 0x14),
333 XGENE_PMU_EVENT_ATTR(csw-inbound-dirty, 0x16),
334 NULL,
335};
336
337static struct attribute *mcb_pmu_events_attrs[] = {
338 XGENE_PMU_EVENT_ATTR(cycle-count, 0x00),
339 XGENE_PMU_EVENT_ATTR(cycle-count-div-64, 0x01),
340 XGENE_PMU_EVENT_ATTR(csw-read, 0x02),
341 XGENE_PMU_EVENT_ATTR(csw-write-request, 0x03),
342 XGENE_PMU_EVENT_ATTR(mcb-csw-stall, 0x04),
343 XGENE_PMU_EVENT_ATTR(cancel-read-gack, 0x05),
344 NULL,
345};
346
347static struct attribute *mc_pmu_events_attrs[] = {
348 XGENE_PMU_EVENT_ATTR(cycle-count, 0x00),
349 XGENE_PMU_EVENT_ATTR(cycle-count-div-64, 0x01),
350 XGENE_PMU_EVENT_ATTR(act-cmd-sent, 0x02),
351 XGENE_PMU_EVENT_ATTR(pre-cmd-sent, 0x03),
352 XGENE_PMU_EVENT_ATTR(rd-cmd-sent, 0x04),
353 XGENE_PMU_EVENT_ATTR(rda-cmd-sent, 0x05),
354 XGENE_PMU_EVENT_ATTR(wr-cmd-sent, 0x06),
355 XGENE_PMU_EVENT_ATTR(wra-cmd-sent, 0x07),
356 XGENE_PMU_EVENT_ATTR(pde-cmd-sent, 0x08),
357 XGENE_PMU_EVENT_ATTR(sre-cmd-sent, 0x09),
358 XGENE_PMU_EVENT_ATTR(prea-cmd-sent, 0x0a),
359 XGENE_PMU_EVENT_ATTR(ref-cmd-sent, 0x0b),
360 XGENE_PMU_EVENT_ATTR(rd-rda-cmd-sent, 0x0c),
361 XGENE_PMU_EVENT_ATTR(wr-wra-cmd-sent, 0x0d),
362 XGENE_PMU_EVENT_ATTR(in-rd-collision, 0x0e),
363 XGENE_PMU_EVENT_ATTR(in-wr-collision, 0x0f),
364 XGENE_PMU_EVENT_ATTR(collision-queue-not-empty, 0x10),
365 XGENE_PMU_EVENT_ATTR(collision-queue-full, 0x11),
366 XGENE_PMU_EVENT_ATTR(mcu-request, 0x12),
367 XGENE_PMU_EVENT_ATTR(mcu-rd-request, 0x13),
368 XGENE_PMU_EVENT_ATTR(mcu-hp-rd-request, 0x14),
369 XGENE_PMU_EVENT_ATTR(mcu-wr-request, 0x15),
370 XGENE_PMU_EVENT_ATTR(mcu-rd-proceed-all, 0x16),
371 XGENE_PMU_EVENT_ATTR(mcu-rd-proceed-cancel, 0x17),
372 XGENE_PMU_EVENT_ATTR(mcu-rd-response, 0x18),
373 XGENE_PMU_EVENT_ATTR(mcu-rd-proceed-speculative-all, 0x19),
374 XGENE_PMU_EVENT_ATTR(mcu-rd-proceed-speculative-cancel, 0x1a),
375 XGENE_PMU_EVENT_ATTR(mcu-wr-proceed-all, 0x1b),
376 XGENE_PMU_EVENT_ATTR(mcu-wr-proceed-cancel, 0x1c),
377 NULL,
378};
379
380static const struct attribute_group l3c_pmu_events_attr_group = {
381 .name = "events",
382 .attrs = l3c_pmu_events_attrs,
383};
384
385static const struct attribute_group iob_pmu_events_attr_group = {
386 .name = "events",
387 .attrs = iob_pmu_events_attrs,
388};
389
390static const struct attribute_group mcb_pmu_events_attr_group = {
391 .name = "events",
392 .attrs = mcb_pmu_events_attrs,
393};
394
395static const struct attribute_group mc_pmu_events_attr_group = {
396 .name = "events",
397 .attrs = mc_pmu_events_attrs,
398};
399
c0f7f7ac
HT		 400static struct attribute *l3c_pmu_v3_events_attrs[] = {
401 XGENE_PMU_EVENT_ATTR(cycle-count, 0x00),
402 XGENE_PMU_EVENT_ATTR(read-hit, 0x01),
403 XGENE_PMU_EVENT_ATTR(read-miss, 0x02),
404 XGENE_PMU_EVENT_ATTR(index-flush-eviction, 0x03),
405 XGENE_PMU_EVENT_ATTR(write-caused-replacement, 0x04),
406 XGENE_PMU_EVENT_ATTR(write-not-caused-replacement, 0x05),
407 XGENE_PMU_EVENT_ATTR(clean-eviction, 0x06),
408 XGENE_PMU_EVENT_ATTR(dirty-eviction, 0x07),
409 XGENE_PMU_EVENT_ATTR(read, 0x08),
410 XGENE_PMU_EVENT_ATTR(write, 0x09),
411 XGENE_PMU_EVENT_ATTR(request, 0x0a),
412 XGENE_PMU_EVENT_ATTR(tq-bank-conflict-issue-stall, 0x0b),
413 XGENE_PMU_EVENT_ATTR(tq-full, 0x0c),
414 XGENE_PMU_EVENT_ATTR(ackq-full, 0x0d),
415 XGENE_PMU_EVENT_ATTR(wdb-full, 0x0e),
416 XGENE_PMU_EVENT_ATTR(odb-full, 0x10),
417 XGENE_PMU_EVENT_ATTR(wbq-full, 0x11),
418 XGENE_PMU_EVENT_ATTR(input-req-async-fifo-stall, 0x12),
419 XGENE_PMU_EVENT_ATTR(output-req-async-fifo-stall, 0x13),
420 XGENE_PMU_EVENT_ATTR(output-data-async-fifo-stall, 0x14),
421 XGENE_PMU_EVENT_ATTR(total-insertion, 0x15),
422 XGENE_PMU_EVENT_ATTR(sip-insertions-r-set, 0x16),
423 XGENE_PMU_EVENT_ATTR(sip-insertions-r-clear, 0x17),
424 XGENE_PMU_EVENT_ATTR(dip-insertions-r-set, 0x18),
425 XGENE_PMU_EVENT_ATTR(dip-insertions-r-clear, 0x19),
426 XGENE_PMU_EVENT_ATTR(dip-insertions-force-r-set, 0x1a),
427 XGENE_PMU_EVENT_ATTR(egression, 0x1b),
428 XGENE_PMU_EVENT_ATTR(replacement, 0x1c),
429 XGENE_PMU_EVENT_ATTR(old-replacement, 0x1d),
430 XGENE_PMU_EVENT_ATTR(young-replacement, 0x1e),
431 XGENE_PMU_EVENT_ATTR(r-set-replacement, 0x1f),
432 XGENE_PMU_EVENT_ATTR(r-clear-replacement, 0x20),
433 XGENE_PMU_EVENT_ATTR(old-r-replacement, 0x21),
434 XGENE_PMU_EVENT_ATTR(old-nr-replacement, 0x22),
435 XGENE_PMU_EVENT_ATTR(young-r-replacement, 0x23),
436 XGENE_PMU_EVENT_ATTR(young-nr-replacement, 0x24),
437 XGENE_PMU_EVENT_ATTR(bloomfilter-clearing, 0x25),
438 XGENE_PMU_EVENT_ATTR(generation-flip, 0x26),
439 XGENE_PMU_EVENT_ATTR(vcc-droop-detected, 0x27),
440 NULL,
441};
442
443static struct attribute *iob_fast_pmu_v3_events_attrs[] = {
444 XGENE_PMU_EVENT_ATTR(cycle-count, 0x00),
445 XGENE_PMU_EVENT_ATTR(pa-req-buf-alloc-all, 0x01),
446 XGENE_PMU_EVENT_ATTR(pa-req-buf-alloc-rd, 0x02),
447 XGENE_PMU_EVENT_ATTR(pa-req-buf-alloc-wr, 0x03),
448 XGENE_PMU_EVENT_ATTR(pa-all-cp-req, 0x04),
449 XGENE_PMU_EVENT_ATTR(pa-cp-blk-req, 0x05),
450 XGENE_PMU_EVENT_ATTR(pa-cp-ptl-req, 0x06),
451 XGENE_PMU_EVENT_ATTR(pa-cp-rd-req, 0x07),
452 XGENE_PMU_EVENT_ATTR(pa-cp-wr-req, 0x08),
453 XGENE_PMU_EVENT_ATTR(ba-all-req, 0x09),
454 XGENE_PMU_EVENT_ATTR(ba-rd-req, 0x0a),
455 XGENE_PMU_EVENT_ATTR(ba-wr-req, 0x0b),
456 XGENE_PMU_EVENT_ATTR(pa-rd-shared-req-issued, 0x10),
457 XGENE_PMU_EVENT_ATTR(pa-rd-exclusive-req-issued, 0x11),
458 XGENE_PMU_EVENT_ATTR(pa-wr-invalidate-req-issued-stashable, 0x12),
459 XGENE_PMU_EVENT_ATTR(pa-wr-invalidate-req-issued-nonstashable, 0x13),
460 XGENE_PMU_EVENT_ATTR(pa-wr-back-req-issued-stashable, 0x14),
461 XGENE_PMU_EVENT_ATTR(pa-wr-back-req-issued-nonstashable, 0x15),
462 XGENE_PMU_EVENT_ATTR(pa-ptl-wr-req, 0x16),
463 XGENE_PMU_EVENT_ATTR(pa-ptl-rd-req, 0x17),
464 XGENE_PMU_EVENT_ATTR(pa-wr-back-clean-data, 0x18),
465 XGENE_PMU_EVENT_ATTR(pa-wr-back-cancelled-on-SS, 0x1b),
466 XGENE_PMU_EVENT_ATTR(pa-barrier-occurrence, 0x1c),
467 XGENE_PMU_EVENT_ATTR(pa-barrier-cycles, 0x1d),
468 XGENE_PMU_EVENT_ATTR(pa-total-cp-snoops, 0x20),
469 XGENE_PMU_EVENT_ATTR(pa-rd-shared-snoop, 0x21),
470 XGENE_PMU_EVENT_ATTR(pa-rd-shared-snoop-hit, 0x22),
471 XGENE_PMU_EVENT_ATTR(pa-rd-exclusive-snoop, 0x23),
472 XGENE_PMU_EVENT_ATTR(pa-rd-exclusive-snoop-hit, 0x24),
473 XGENE_PMU_EVENT_ATTR(pa-rd-wr-invalid-snoop, 0x25),
474 XGENE_PMU_EVENT_ATTR(pa-rd-wr-invalid-snoop-hit, 0x26),
475 XGENE_PMU_EVENT_ATTR(pa-req-buffer-full, 0x28),
476 XGENE_PMU_EVENT_ATTR(cswlf-outbound-req-fifo-full, 0x29),
477 XGENE_PMU_EVENT_ATTR(cswlf-inbound-snoop-fifo-backpressure, 0x2a),
478 XGENE_PMU_EVENT_ATTR(cswlf-outbound-lack-fifo-full, 0x2b),
479 XGENE_PMU_EVENT_ATTR(cswlf-inbound-gack-fifo-backpressure, 0x2c),
480 XGENE_PMU_EVENT_ATTR(cswlf-outbound-data-fifo-full, 0x2d),
481 XGENE_PMU_EVENT_ATTR(cswlf-inbound-data-fifo-backpressure, 0x2e),
482 XGENE_PMU_EVENT_ATTR(cswlf-inbound-req-backpressure, 0x2f),
483 NULL,
484};
485
486static struct attribute *iob_slow_pmu_v3_events_attrs[] = {
487 XGENE_PMU_EVENT_ATTR(cycle-count, 0x00),
488 XGENE_PMU_EVENT_ATTR(pa-axi0-rd-req, 0x01),
489 XGENE_PMU_EVENT_ATTR(pa-axi0-wr-req, 0x02),
490 XGENE_PMU_EVENT_ATTR(pa-axi1-rd-req, 0x03),
491 XGENE_PMU_EVENT_ATTR(pa-axi1-wr-req, 0x04),
492 XGENE_PMU_EVENT_ATTR(ba-all-axi-req, 0x07),
493 XGENE_PMU_EVENT_ATTR(ba-axi-rd-req, 0x08),
494 XGENE_PMU_EVENT_ATTR(ba-axi-wr-req, 0x09),
495 XGENE_PMU_EVENT_ATTR(ba-free-list-empty, 0x10),
496 NULL,
497};
498
499static struct attribute *mcb_pmu_v3_events_attrs[] = {
500 XGENE_PMU_EVENT_ATTR(cycle-count, 0x00),
501 XGENE_PMU_EVENT_ATTR(req-receive, 0x01),
502 XGENE_PMU_EVENT_ATTR(rd-req-recv, 0x02),
503 XGENE_PMU_EVENT_ATTR(rd-req-recv-2, 0x03),
504 XGENE_PMU_EVENT_ATTR(wr-req-recv, 0x04),
505 XGENE_PMU_EVENT_ATTR(wr-req-recv-2, 0x05),
506 XGENE_PMU_EVENT_ATTR(rd-req-sent-to-mcu, 0x06),
507 XGENE_PMU_EVENT_ATTR(rd-req-sent-to-mcu-2, 0x07),
508 XGENE_PMU_EVENT_ATTR(rd-req-sent-to-spec-mcu, 0x08),
509 XGENE_PMU_EVENT_ATTR(rd-req-sent-to-spec-mcu-2, 0x09),
510 XGENE_PMU_EVENT_ATTR(glbl-ack-recv-for-rd-sent-to-spec-mcu, 0x0a),
511 XGENE_PMU_EVENT_ATTR(glbl-ack-go-recv-for-rd-sent-to-spec-mcu, 0x0b),
512 XGENE_PMU_EVENT_ATTR(glbl-ack-nogo-recv-for-rd-sent-to-spec-mcu, 0x0c),
513 XGENE_PMU_EVENT_ATTR(glbl-ack-go-recv-any-rd-req, 0x0d),
514 XGENE_PMU_EVENT_ATTR(glbl-ack-go-recv-any-rd-req-2, 0x0e),
515 XGENE_PMU_EVENT_ATTR(wr-req-sent-to-mcu, 0x0f),
516 XGENE_PMU_EVENT_ATTR(gack-recv, 0x10),
517 XGENE_PMU_EVENT_ATTR(rd-gack-recv, 0x11),
518 XGENE_PMU_EVENT_ATTR(wr-gack-recv, 0x12),
519 XGENE_PMU_EVENT_ATTR(cancel-rd-gack, 0x13),
520 XGENE_PMU_EVENT_ATTR(cancel-wr-gack, 0x14),
521 XGENE_PMU_EVENT_ATTR(mcb-csw-req-stall, 0x15),
522 XGENE_PMU_EVENT_ATTR(mcu-req-intf-blocked, 0x16),
523 XGENE_PMU_EVENT_ATTR(mcb-mcu-rd-intf-stall, 0x17),
524 XGENE_PMU_EVENT_ATTR(csw-rd-intf-blocked, 0x18),
525 XGENE_PMU_EVENT_ATTR(csw-local-ack-intf-blocked, 0x19),
526 XGENE_PMU_EVENT_ATTR(mcu-req-table-full, 0x1a),
527 XGENE_PMU_EVENT_ATTR(mcu-stat-table-full, 0x1b),
528 XGENE_PMU_EVENT_ATTR(mcu-wr-table-full, 0x1c),
529 XGENE_PMU_EVENT_ATTR(mcu-rdreceipt-resp, 0x1d),
530 XGENE_PMU_EVENT_ATTR(mcu-wrcomplete-resp, 0x1e),
531 XGENE_PMU_EVENT_ATTR(mcu-retryack-resp, 0x1f),
532 XGENE_PMU_EVENT_ATTR(mcu-pcrdgrant-resp, 0x20),
533 XGENE_PMU_EVENT_ATTR(mcu-req-from-lastload, 0x21),
534 XGENE_PMU_EVENT_ATTR(mcu-req-from-bypass, 0x22),
535 XGENE_PMU_EVENT_ATTR(volt-droop-detect, 0x23),
536 NULL,
537};
538
539static struct attribute *mc_pmu_v3_events_attrs[] = {
540 XGENE_PMU_EVENT_ATTR(cycle-count, 0x00),
541 XGENE_PMU_EVENT_ATTR(act-sent, 0x01),
542 XGENE_PMU_EVENT_ATTR(pre-sent, 0x02),
543 XGENE_PMU_EVENT_ATTR(rd-sent, 0x03),
544 XGENE_PMU_EVENT_ATTR(rda-sent, 0x04),
545 XGENE_PMU_EVENT_ATTR(wr-sent, 0x05),
546 XGENE_PMU_EVENT_ATTR(wra-sent, 0x06),
547 XGENE_PMU_EVENT_ATTR(pd-entry-vld, 0x07),
548 XGENE_PMU_EVENT_ATTR(sref-entry-vld, 0x08),
549 XGENE_PMU_EVENT_ATTR(prea-sent, 0x09),
550 XGENE_PMU_EVENT_ATTR(ref-sent, 0x0a),
551 XGENE_PMU_EVENT_ATTR(rd-rda-sent, 0x0b),
552 XGENE_PMU_EVENT_ATTR(wr-wra-sent, 0x0c),
553 XGENE_PMU_EVENT_ATTR(raw-hazard, 0x0d),
554 XGENE_PMU_EVENT_ATTR(war-hazard, 0x0e),
555 XGENE_PMU_EVENT_ATTR(waw-hazard, 0x0f),
556 XGENE_PMU_EVENT_ATTR(rar-hazard, 0x10),
557 XGENE_PMU_EVENT_ATTR(raw-war-waw-hazard, 0x11),
558 XGENE_PMU_EVENT_ATTR(hprd-lprd-wr-req-vld, 0x12),
559 XGENE_PMU_EVENT_ATTR(lprd-req-vld, 0x13),
560 XGENE_PMU_EVENT_ATTR(hprd-req-vld, 0x14),
561 XGENE_PMU_EVENT_ATTR(hprd-lprd-req-vld, 0x15),
562 XGENE_PMU_EVENT_ATTR(wr-req-vld, 0x16),
563 XGENE_PMU_EVENT_ATTR(partial-wr-req-vld, 0x17),
564 XGENE_PMU_EVENT_ATTR(rd-retry, 0x18),
565 XGENE_PMU_EVENT_ATTR(wr-retry, 0x19),
566 XGENE_PMU_EVENT_ATTR(retry-gnt, 0x1a),
567 XGENE_PMU_EVENT_ATTR(rank-change, 0x1b),
568 XGENE_PMU_EVENT_ATTR(dir-change, 0x1c),
569 XGENE_PMU_EVENT_ATTR(rank-dir-change, 0x1d),
570 XGENE_PMU_EVENT_ATTR(rank-active, 0x1e),
571 XGENE_PMU_EVENT_ATTR(rank-idle, 0x1f),
572 XGENE_PMU_EVENT_ATTR(rank-pd, 0x20),
573 XGENE_PMU_EVENT_ATTR(rank-sref, 0x21),
574 XGENE_PMU_EVENT_ATTR(queue-fill-gt-thresh, 0x22),
575 XGENE_PMU_EVENT_ATTR(queue-rds-gt-thresh, 0x23),
576 XGENE_PMU_EVENT_ATTR(queue-wrs-gt-thresh, 0x24),
577 XGENE_PMU_EVENT_ATTR(phy-updt-complt, 0x25),
578 XGENE_PMU_EVENT_ATTR(tz-fail, 0x26),
579 XGENE_PMU_EVENT_ATTR(dram-errc, 0x27),
580 XGENE_PMU_EVENT_ATTR(dram-errd, 0x28),
581 XGENE_PMU_EVENT_ATTR(rd-enq, 0x29),
582 XGENE_PMU_EVENT_ATTR(wr-enq, 0x2a),
583 XGENE_PMU_EVENT_ATTR(tmac-limit-reached, 0x2b),
584 XGENE_PMU_EVENT_ATTR(tmaw-tracker-full, 0x2c),
585 NULL,
586};
587
588static const struct attribute_group l3c_pmu_v3_events_attr_group = {
589 .name = "events",
590 .attrs = l3c_pmu_v3_events_attrs,
591};
592
593static const struct attribute_group iob_fast_pmu_v3_events_attr_group = {
594 .name = "events",
595 .attrs = iob_fast_pmu_v3_events_attrs,
596};
597
598static const struct attribute_group iob_slow_pmu_v3_events_attr_group = {
599 .name = "events",
600 .attrs = iob_slow_pmu_v3_events_attrs,
601};
602
603static const struct attribute_group mcb_pmu_v3_events_attr_group = {
604 .name = "events",
605 .attrs = mcb_pmu_v3_events_attrs,
606};
607
608static const struct attribute_group mc_pmu_v3_events_attr_group = {
609 .name = "events",
610 .attrs = mc_pmu_v3_events_attrs,
611};
612
832c927d
TN		 613/*
614 * sysfs cpumask attributes
615 */
616static ssize_t xgene_pmu_cpumask_show(struct device *dev,
617 struct device_attribute *attr, char *buf)
618{
619 struct xgene_pmu_dev *pmu_dev = to_pmu_dev(dev_get_drvdata(dev));
620
621 return cpumap_print_to_pagebuf(true, buf, &pmu_dev->parent->cpu);
622}
623
624static DEVICE_ATTR(cpumask, S_IRUGO, xgene_pmu_cpumask_show, NULL);
625
626static struct attribute *xgene_pmu_cpumask_attrs[] = {
627 &dev_attr_cpumask.attr,
628 NULL,
629};
630
631static const struct attribute_group pmu_cpumask_attr_group = {
632 .attrs = xgene_pmu_cpumask_attrs,
633};
634
635/*
c0f7f7ac 636 * Per PMU device attribute groups of PMU v1 and v2
832c927d
TN		 637 */
638static const struct attribute_group *l3c_pmu_attr_groups[] = {
639 &l3c_pmu_format_attr_group,
640 &pmu_cpumask_attr_group,
641 &l3c_pmu_events_attr_group,
642 NULL
643};
644
645static const struct attribute_group *iob_pmu_attr_groups[] = {
646 &iob_pmu_format_attr_group,
647 &pmu_cpumask_attr_group,
648 &iob_pmu_events_attr_group,
649 NULL
650};
651
652static const struct attribute_group *mcb_pmu_attr_groups[] = {
653 &mcb_pmu_format_attr_group,
654 &pmu_cpumask_attr_group,
655 &mcb_pmu_events_attr_group,
656 NULL
657};
658
659static const struct attribute_group *mc_pmu_attr_groups[] = {
660 &mc_pmu_format_attr_group,
661 &pmu_cpumask_attr_group,
662 &mc_pmu_events_attr_group,
663 NULL
664};
665
c0f7f7ac
HT		 666/*
667 * Per PMU device attribute groups of PMU v3
668 */
669static const struct attribute_group *l3c_pmu_v3_attr_groups[] = {
670 &l3c_pmu_v3_format_attr_group,
671 &pmu_cpumask_attr_group,
672 &l3c_pmu_v3_events_attr_group,
673 NULL
674};
675
676static const struct attribute_group *iob_fast_pmu_v3_attr_groups[] = {
677 &iob_pmu_v3_format_attr_group,
678 &pmu_cpumask_attr_group,
679 &iob_fast_pmu_v3_events_attr_group,
680 NULL
681};
682
683static const struct attribute_group *iob_slow_pmu_v3_attr_groups[] = {
684 &iob_slow_pmu_v3_format_attr_group,
685 &pmu_cpumask_attr_group,
686 &iob_slow_pmu_v3_events_attr_group,
687 NULL
688};
689
690static const struct attribute_group *mcb_pmu_v3_attr_groups[] = {
691 &mcb_pmu_v3_format_attr_group,
692 &pmu_cpumask_attr_group,
693 &mcb_pmu_v3_events_attr_group,
694 NULL
695};
696
697static const struct attribute_group *mc_pmu_v3_attr_groups[] = {
698 &mc_pmu_v3_format_attr_group,
699 &pmu_cpumask_attr_group,
700 &mc_pmu_v3_events_attr_group,
701 NULL
702};
703
832c927d
TN		 704static int get_next_avail_cntr(struct xgene_pmu_dev *pmu_dev)
705{
706 int cntr;
707
708 cntr = find_first_zero_bit(pmu_dev->cntr_assign_mask,
709 pmu_dev->max_counters);
710 if (cntr == pmu_dev->max_counters)
711 return -ENOSPC;
712 set_bit(cntr, pmu_dev->cntr_assign_mask);
713
714 return cntr;
715}
716
717static void clear_avail_cntr(struct xgene_pmu_dev *pmu_dev, int cntr)
718{
719 clear_bit(cntr, pmu_dev->cntr_assign_mask);
720}
721
722static inline void xgene_pmu_mask_int(struct xgene_pmu *xgene_pmu)
723{
724 writel(PCPPMU_INTENMASK, xgene_pmu->pcppmu_csr + PCPPMU_INTMASK_REG);
725}
726
c0f7f7ac
HT		 727static inline void xgene_pmu_v3_mask_int(struct xgene_pmu *xgene_pmu)
728{
729 writel(PCPPMU_V3_INTENMASK, xgene_pmu->pcppmu_csr + PCPPMU_INTMASK_REG);
730}
731
832c927d
TN		 732static inline void xgene_pmu_unmask_int(struct xgene_pmu *xgene_pmu)
733{
734 writel(PCPPMU_INTCLRMASK, xgene_pmu->pcppmu_csr + PCPPMU_INTMASK_REG);
735}
736
c0f7f7ac
HT		 737static inline void xgene_pmu_v3_unmask_int(struct xgene_pmu *xgene_pmu)
738{
739 writel(PCPPMU_V3_INTCLRMASK,
740 xgene_pmu->pcppmu_csr + PCPPMU_INTMASK_REG);
741}
742
e35e0a04
HT		 743static inline u64 xgene_pmu_read_counter32(struct xgene_pmu_dev *pmu_dev,
744 int idx)
832c927d
TN		 745{
746 return readl(pmu_dev->inf->csr + PMU_PMEVCNTR0 + (4 * idx));
747}
748
c0f7f7ac
HT		 749static inline u64 xgene_pmu_read_counter64(struct xgene_pmu_dev *pmu_dev,
750 int idx)
751{
752 u32 lo, hi;
753
754 /*
755 * v3 has 64-bit counter registers composed by 2 32-bit registers
756 * This can be a problem if the counter increases and carries
757 * out of bit [31] between 2 reads. The extra reads would help
758 * to prevent this issue.
759 */
760 do {
761 hi = xgene_pmu_read_counter32(pmu_dev, 2 * idx + 1);
762 lo = xgene_pmu_read_counter32(pmu_dev, 2 * idx);
763 } while (hi != xgene_pmu_read_counter32(pmu_dev, 2 * idx + 1));
764
765 return (((u64)hi << 32) | lo);
766}
767
832c927d 768static inline void
e35e0a04 769xgene_pmu_write_counter32(struct xgene_pmu_dev *pmu_dev, int idx, u64 val)
832c927d
TN		 770{
771 writel(val, pmu_dev->inf->csr + PMU_PMEVCNTR0 + (4 * idx));
772}
773
c0f7f7ac
HT		 774static inline void
775xgene_pmu_write_counter64(struct xgene_pmu_dev *pmu_dev, int idx, u64 val)
776{
777 u32 cnt_lo, cnt_hi;
778
779 cnt_hi = upper_32_bits(val);
780 cnt_lo = lower_32_bits(val);
781
782 /* v3 has 64-bit counter registers composed by 2 32-bit registers */
783 xgene_pmu_write_counter32(pmu_dev, 2 * idx, cnt_lo);
784 xgene_pmu_write_counter32(pmu_dev, 2 * idx + 1, cnt_hi);
785}
786
832c927d
TN		 787static inline void
788xgene_pmu_write_evttype(struct xgene_pmu_dev *pmu_dev, int idx, u32 val)
789{
790 writel(val, pmu_dev->inf->csr + PMU_PMEVTYPER0 + (4 * idx));
791}
792
793static inline void
794xgene_pmu_write_agentmsk(struct xgene_pmu_dev *pmu_dev, u32 val)
795{
796 writel(val, pmu_dev->inf->csr + PMU_PMAMR0);
797}
798
c0f7f7ac
HT		 799static inline void
800xgene_pmu_v3_write_agentmsk(struct xgene_pmu_dev *pmu_dev, u32 val) { }
801
832c927d
TN		 802static inline void
803xgene_pmu_write_agent1msk(struct xgene_pmu_dev *pmu_dev, u32 val)
804{
805 writel(val, pmu_dev->inf->csr + PMU_PMAMR1);
806}
807
c0f7f7ac
HT		 808static inline void
809xgene_pmu_v3_write_agent1msk(struct xgene_pmu_dev *pmu_dev, u32 val) { }
810
832c927d
TN		 811static inline void
812xgene_pmu_enable_counter(struct xgene_pmu_dev *pmu_dev, int idx)
813{
814 u32 val;
815
816 val = readl(pmu_dev->inf->csr + PMU_PMCNTENSET);
817 val |= 1 << idx;
818 writel(val, pmu_dev->inf->csr + PMU_PMCNTENSET);
819}
820
821static inline void
822xgene_pmu_disable_counter(struct xgene_pmu_dev *pmu_dev, int idx)
823{
824 u32 val;
825
826 val = readl(pmu_dev->inf->csr + PMU_PMCNTENCLR);
827 val |= 1 << idx;
828 writel(val, pmu_dev->inf->csr + PMU_PMCNTENCLR);
829}
830
831static inline void
832xgene_pmu_enable_counter_int(struct xgene_pmu_dev *pmu_dev, int idx)
833{
834 u32 val;
835
836 val = readl(pmu_dev->inf->csr + PMU_PMINTENSET);
837 val |= 1 << idx;
838 writel(val, pmu_dev->inf->csr + PMU_PMINTENSET);
839}
840
841static inline void
842xgene_pmu_disable_counter_int(struct xgene_pmu_dev *pmu_dev, int idx)
843{
844 u32 val;
845
846 val = readl(pmu_dev->inf->csr + PMU_PMINTENCLR);
847 val |= 1 << idx;
848 writel(val, pmu_dev->inf->csr + PMU_PMINTENCLR);
849}
850
851static inline void xgene_pmu_reset_counters(struct xgene_pmu_dev *pmu_dev)
852{
853 u32 val;
854
855 val = readl(pmu_dev->inf->csr + PMU_PMCR);
856 val |= PMU_PMCR_P;
857 writel(val, pmu_dev->inf->csr + PMU_PMCR);
858}
859
860static inline void xgene_pmu_start_counters(struct xgene_pmu_dev *pmu_dev)
861{
862 u32 val;
863
864 val = readl(pmu_dev->inf->csr + PMU_PMCR);
865 val |= PMU_PMCR_E;
866 writel(val, pmu_dev->inf->csr + PMU_PMCR);
867}
868
869static inline void xgene_pmu_stop_counters(struct xgene_pmu_dev *pmu_dev)
870{
871 u32 val;
872
873 val = readl(pmu_dev->inf->csr + PMU_PMCR);
874 val &= ~PMU_PMCR_E;
875 writel(val, pmu_dev->inf->csr + PMU_PMCR);
876}
877
878static void xgene_perf_pmu_enable(struct pmu *pmu)
879{
880 struct xgene_pmu_dev *pmu_dev = to_pmu_dev(pmu);
e35e0a04 881 struct xgene_pmu *xgene_pmu = pmu_dev->parent;
832c927d
TN		 882 int enabled = bitmap_weight(pmu_dev->cntr_assign_mask,
883 pmu_dev->max_counters);
884
885 if (!enabled)
886 return;
887
e35e0a04 888 xgene_pmu->ops->start_counters(pmu_dev);
832c927d
TN		 889}
890
891static void xgene_perf_pmu_disable(struct pmu *pmu)
892{
893 struct xgene_pmu_dev *pmu_dev = to_pmu_dev(pmu);
e35e0a04 894 struct xgene_pmu *xgene_pmu = pmu_dev->parent;
832c927d 895
e35e0a04 896 xgene_pmu->ops->stop_counters(pmu_dev);
832c927d
TN		 897}
898
899static int xgene_perf_event_init(struct perf_event *event)
900{
901 struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu);
902 struct hw_perf_event *hw = &event->hw;
903 struct perf_event *sibling;
904
905 /* Test the event attr type check for PMU enumeration */
906 if (event->attr.type != event->pmu->type)
907 return -ENOENT;
908
909 /*
910 * SOC PMU counters are shared across all cores.
911 * Therefore, it does not support per-process mode.
912 * Also, it does not support event sampling mode.
913 */
914 if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK)
915 return -EINVAL;
916
917 /* SOC counters do not have usr/os/guest/host bits */
918 if (event->attr.exclude_user || event->attr.exclude_kernel ||
919 event->attr.exclude_host || event->attr.exclude_guest)
920 return -EINVAL;
921
922 if (event->cpu < 0)
923 return -EINVAL;
924 /*
925 * Many perf core operations (eg. events rotation) operate on a
926 * single CPU context. This is obvious for CPU PMUs, where one
927 * expects the same sets of events being observed on all CPUs,
928 * but can lead to issues for off-core PMUs, where each
929 * event could be theoretically assigned to a different CPU. To
930 * mitigate this, we enforce CPU assignment to one, selected
931 * processor (the one described in the "cpumask" attribute).
932 */
933 event->cpu = cpumask_first(&pmu_dev->parent->cpu);
934
935 hw->config = event->attr.config;
936 /*
937 * Each bit of the config1 field represents an agent from which the
938 * request of the event come. The event is counted only if it's caused
939 * by a request of an agent has the bit cleared.
940 * By default, the event is counted for all agents.
941 */
942 hw->config_base = event->attr.config1;
943
944 /*
945 * We must NOT create groups containing mixed PMUs, although software
946 * events are acceptable
947 */
948 if (event->group_leader->pmu != event->pmu &&
949 !is_software_event(event->group_leader))
950 return -EINVAL;
951
952 list_for_each_entry(sibling, &event->group_leader->sibling_list,
953 group_entry)
954 if (sibling->pmu != event->pmu &&
955 !is_software_event(sibling))
956 return -EINVAL;
957
958 return 0;
959}
960
961static void xgene_perf_enable_event(struct perf_event *event)
962{
963 struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu);
e35e0a04 964 struct xgene_pmu *xgene_pmu = pmu_dev->parent;
832c927d 965
e35e0a04
HT		 966 xgene_pmu->ops->write_evttype(pmu_dev, GET_CNTR(event),
967 GET_EVENTID(event));
968 xgene_pmu->ops->write_agentmsk(pmu_dev, ~((u32)GET_AGENTID(event)));
832c927d 969 if (pmu_dev->inf->type == PMU_TYPE_IOB)
e35e0a04
HT		 970 xgene_pmu->ops->write_agent1msk(pmu_dev,
971 ~((u32)GET_AGENT1ID(event)));
832c927d 972
e35e0a04
HT		 973 xgene_pmu->ops->enable_counter(pmu_dev, GET_CNTR(event));
974 xgene_pmu->ops->enable_counter_int(pmu_dev, GET_CNTR(event));
832c927d
TN		 975}
976
977static void xgene_perf_disable_event(struct perf_event *event)
978{
979 struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu);
e35e0a04 980 struct xgene_pmu *xgene_pmu = pmu_dev->parent;
832c927d 981
e35e0a04
HT		 982 xgene_pmu->ops->disable_counter(pmu_dev, GET_CNTR(event));
983 xgene_pmu->ops->disable_counter_int(pmu_dev, GET_CNTR(event));
832c927d
TN		 984}
985
986static void xgene_perf_event_set_period(struct perf_event *event)
987{
988 struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu);
e35e0a04 989 struct xgene_pmu *xgene_pmu = pmu_dev->parent;
832c927d
TN		 990 struct hw_perf_event *hw = &event->hw;
991 /*
c0f7f7ac
HT		 992 * For 32 bit counter, it has a period of 2^32. To account for the
993 * possibility of extreme interrupt latency we program for a period of
994 * half that. Hopefully, we can handle the interrupt before another 2^31
832c927d 995 * events occur and the counter overtakes its previous value.
c0f7f7ac 996 * For 64 bit counter, we don't expect it overflow.
832c927d
TN		 997 */
998 u64 val = 1ULL << 31;
999
1000 local64_set(&hw->prev_count, val);
e35e0a04 1001 xgene_pmu->ops->write_counter(pmu_dev, hw->idx, val);
832c927d
TN		 1002}
1003
1004static void xgene_perf_event_update(struct perf_event *event)
1005{
1006 struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu);
e35e0a04 1007 struct xgene_pmu *xgene_pmu = pmu_dev->parent;
832c927d
TN		 1008 struct hw_perf_event *hw = &event->hw;
1009 u64 delta, prev_raw_count, new_raw_count;
1010
1011again:
1012 prev_raw_count = local64_read(&hw->prev_count);
e35e0a04 1013 new_raw_count = xgene_pmu->ops->read_counter(pmu_dev, GET_CNTR(event));
832c927d
TN		 1014
1015 if (local64_cmpxchg(&hw->prev_count, prev_raw_count,
1016 new_raw_count) != prev_raw_count)
1017 goto again;
1018
1019 delta = (new_raw_count - prev_raw_count) & pmu_dev->max_period;
1020
1021 local64_add(delta, &event->count);
1022}
1023
1024static void xgene_perf_read(struct perf_event *event)
1025{
1026 xgene_perf_event_update(event);
1027}
1028
1029static void xgene_perf_start(struct perf_event *event, int flags)
1030{
1031 struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu);
e35e0a04 1032 struct xgene_pmu *xgene_pmu = pmu_dev->parent;
832c927d
TN		 1033 struct hw_perf_event *hw = &event->hw;
1034
1035 if (WARN_ON_ONCE(!(hw->state & PERF_HES_STOPPED)))
1036 return;
1037
1038 WARN_ON_ONCE(!(hw->state & PERF_HES_UPTODATE));
1039 hw->state = 0;
1040
1041 xgene_perf_event_set_period(event);
1042
1043 if (flags & PERF_EF_RELOAD) {
1044 u64 prev_raw_count = local64_read(&hw->prev_count);
1045
e35e0a04
HT		 1046 xgene_pmu->ops->write_counter(pmu_dev, GET_CNTR(event),
1047 prev_raw_count);
832c927d
TN		 1048 }
1049
1050 xgene_perf_enable_event(event);
1051 perf_event_update_userpage(event);
1052}
1053
1054static void xgene_perf_stop(struct perf_event *event, int flags)
1055{
1056 struct hw_perf_event *hw = &event->hw;
1057 u64 config;
1058
1059 if (hw->state & PERF_HES_UPTODATE)
1060 return;
1061
1062 xgene_perf_disable_event(event);
1063 WARN_ON_ONCE(hw->state & PERF_HES_STOPPED);
1064 hw->state |= PERF_HES_STOPPED;
1065
1066 if (hw->state & PERF_HES_UPTODATE)
1067 return;
1068
1069 config = hw->config;
1070 xgene_perf_read(event);
1071 hw->state |= PERF_HES_UPTODATE;
1072}
1073
1074static int xgene_perf_add(struct perf_event *event, int flags)
1075{
1076 struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu);
1077 struct hw_perf_event *hw = &event->hw;
1078
1079 hw->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
1080
1081 /* Allocate an event counter */
1082 hw->idx = get_next_avail_cntr(pmu_dev);
1083 if (hw->idx < 0)
1084 return -EAGAIN;
1085
1086 /* Update counter event pointer for Interrupt handler */
1087 pmu_dev->pmu_counter_event[hw->idx] = event;
1088
1089 if (flags & PERF_EF_START)
1090 xgene_perf_start(event, PERF_EF_RELOAD);
1091
1092 return 0;
1093}
1094
1095static void xgene_perf_del(struct perf_event *event, int flags)
1096{
1097 struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu);
1098 struct hw_perf_event *hw = &event->hw;
1099
1100 xgene_perf_stop(event, PERF_EF_UPDATE);
1101
1102 /* clear the assigned counter */
1103 clear_avail_cntr(pmu_dev, GET_CNTR(event));
1104
1105 perf_event_update_userpage(event);
1106 pmu_dev->pmu_counter_event[hw->idx] = NULL;
1107}
1108
1109static int xgene_init_perf(struct xgene_pmu_dev *pmu_dev, char *name)
1110{
1111 struct xgene_pmu *xgene_pmu;
1112
c0f7f7ac
HT		 1113 if (pmu_dev->parent->version == PCP_PMU_V3)
1114 pmu_dev->max_period = PMU_V3_CNT_MAX_PERIOD;
1115 else
1116 pmu_dev->max_period = PMU_CNT_MAX_PERIOD;
832c927d
TN		 1117 /* First version PMU supports only single event counter */
1118 xgene_pmu = pmu_dev->parent;
1119 if (xgene_pmu->version == PCP_PMU_V1)
1120 pmu_dev->max_counters = 1;
1121 else
1122 pmu_dev->max_counters = PMU_MAX_COUNTERS;
1123
1124 /* Perf driver registration */
1125 pmu_dev->pmu = (struct pmu) {
1126 .attr_groups = pmu_dev->attr_groups,
1127 .task_ctx_nr = perf_invalid_context,
1128 .pmu_enable = xgene_perf_pmu_enable,
1129 .pmu_disable = xgene_perf_pmu_disable,
1130 .event_init = xgene_perf_event_init,
1131 .add = xgene_perf_add,
1132 .del = xgene_perf_del,
1133 .start = xgene_perf_start,
1134 .stop = xgene_perf_stop,
1135 .read = xgene_perf_read,
1136 };
1137
1138 /* Hardware counter init */
e35e0a04
HT		 1139 xgene_pmu->ops->stop_counters(pmu_dev);
1140 xgene_pmu->ops->reset_counters(pmu_dev);
832c927d
TN		 1141
1142 return perf_pmu_register(&pmu_dev->pmu, name, -1);
1143}
1144
1145static int
1146xgene_pmu_dev_add(struct xgene_pmu *xgene_pmu, struct xgene_pmu_dev_ctx *ctx)
1147{
1148 struct device *dev = xgene_pmu->dev;
1149 struct xgene_pmu_dev *pmu;
1150 int rc;
1151
1152 pmu = devm_kzalloc(dev, sizeof(*pmu), GFP_KERNEL);
1153 if (!pmu)
1154 return -ENOMEM;
1155 pmu->parent = xgene_pmu;
1156 pmu->inf = &ctx->inf;
1157 ctx->pmu_dev = pmu;
1158
1159 switch (pmu->inf->type) {
1160 case PMU_TYPE_L3C:
c0f7f7ac
HT		 1161 if (!(xgene_pmu->l3c_active_mask & pmu->inf->enable_mask))
1162 goto dev_err;
1163 if (xgene_pmu->version == PCP_PMU_V3)
1164 pmu->attr_groups = l3c_pmu_v3_attr_groups;
1165 else
1166 pmu->attr_groups = l3c_pmu_attr_groups;
832c927d
TN		 1167 break;
1168 case PMU_TYPE_IOB:
c0f7f7ac
HT		 1169 if (xgene_pmu->version == PCP_PMU_V3)
1170 pmu->attr_groups = iob_fast_pmu_v3_attr_groups;
1171 else
1172 pmu->attr_groups = iob_pmu_attr_groups;
1173 break;
1174 case PMU_TYPE_IOB_SLOW:
1175 if (xgene_pmu->version == PCP_PMU_V3)
1176 pmu->attr_groups = iob_slow_pmu_v3_attr_groups;
832c927d
TN		 1177 break;
1178 case PMU_TYPE_MCB:
1179 if (!(xgene_pmu->mcb_active_mask & pmu->inf->enable_mask))
1180 goto dev_err;
c0f7f7ac
HT		 1181 if (xgene_pmu->version == PCP_PMU_V3)
1182 pmu->attr_groups = mcb_pmu_v3_attr_groups;
1183 else
1184 pmu->attr_groups = mcb_pmu_attr_groups;
832c927d
TN		 1185 break;
1186 case PMU_TYPE_MC:
1187 if (!(xgene_pmu->mc_active_mask & pmu->inf->enable_mask))
1188 goto dev_err;
c0f7f7ac
HT		 1189 if (xgene_pmu->version == PCP_PMU_V3)
1190 pmu->attr_groups = mc_pmu_v3_attr_groups;
1191 else
1192 pmu->attr_groups = mc_pmu_attr_groups;
832c927d
TN		 1193 break;
1194 default:
1195 return -EINVAL;
1196 }
1197
1198 rc = xgene_init_perf(pmu, ctx->name);
1199 if (rc) {
1200 dev_err(dev, "%s PMU: Failed to init perf driver\n", ctx->name);
1201 goto dev_err;
1202 }
1203
1204 dev_info(dev, "%s PMU registered\n", ctx->name);
1205
1206 return rc;
1207
1208dev_err:
1209 devm_kfree(dev, pmu);
1210 return -ENODEV;
1211}
1212
1213static void _xgene_pmu_isr(int irq, struct xgene_pmu_dev *pmu_dev)
1214{
1215 struct xgene_pmu *xgene_pmu = pmu_dev->parent;
c0f7f7ac 1216 void __iomem *csr = pmu_dev->inf->csr;
832c927d
TN		 1217 u32 pmovsr;
1218 int idx;
1219
c0f7f7ac
HT		 1220 xgene_pmu->ops->stop_counters(pmu_dev);
1221
1222 if (xgene_pmu->version == PCP_PMU_V3)
1223 pmovsr = readl(csr + PMU_PMOVSSET) & PMU_OVERFLOW_MASK;
1224 else
1225 pmovsr = readl(csr + PMU_PMOVSR) & PMU_OVERFLOW_MASK;
1226
832c927d 1227 if (!pmovsr)
c0f7f7ac 1228 goto out;
832c927d
TN		 1229
1230 /* Clear interrupt flag */
1231 if (xgene_pmu->version == PCP_PMU_V1)
c0f7f7ac
HT		 1232 writel(0x0, csr + PMU_PMOVSR);
1233 else if (xgene_pmu->version == PCP_PMU_V2)
1234 writel(pmovsr, csr + PMU_PMOVSR);
832c927d 1235 else
c0f7f7ac 1236 writel(pmovsr, csr + PMU_PMOVSCLR);
832c927d
TN		 1237
1238 for (idx = 0; idx < PMU_MAX_COUNTERS; idx++) {
1239 struct perf_event *event = pmu_dev->pmu_counter_event[idx];
1240 int overflowed = pmovsr & BIT(idx);
1241
1242 /* Ignore if we don't have an event. */
1243 if (!event || !overflowed)
1244 continue;
1245 xgene_perf_event_update(event);
1246 xgene_perf_event_set_period(event);
1247 }
c0f7f7ac
HT		 1248
1249out:
1250 xgene_pmu->ops->start_counters(pmu_dev);
832c927d
TN		 1251}
1252
1253static irqreturn_t xgene_pmu_isr(int irq, void *dev_id)
1254{
c0f7f7ac 1255 u32 intr_mcu, intr_mcb, intr_l3c, intr_iob;
832c927d
TN		 1256 struct xgene_pmu_dev_ctx *ctx;
1257 struct xgene_pmu *xgene_pmu = dev_id;
1258 unsigned long flags;
1259 u32 val;
1260
1261 raw_spin_lock_irqsave(&xgene_pmu->lock, flags);
1262
1263 /* Get Interrupt PMU source */
1264 val = readl(xgene_pmu->pcppmu_csr + PCPPMU_INTSTATUS_REG);
c0f7f7ac
HT		 1265 if (xgene_pmu->version == PCP_PMU_V3) {
1266 intr_mcu = PCPPMU_V3_INT_MCU;
1267 intr_mcb = PCPPMU_V3_INT_MCB;
1268 intr_l3c = PCPPMU_V3_INT_L3C;
1269 intr_iob = PCPPMU_V3_INT_IOB;
1270 } else {
1271 intr_mcu = PCPPMU_INT_MCU;
1272 intr_mcb = PCPPMU_INT_MCB;
1273 intr_l3c = PCPPMU_INT_L3C;
1274 intr_iob = PCPPMU_INT_IOB;
1275 }
1276 if (val & intr_mcu) {
832c927d
TN		 1277 list_for_each_entry(ctx, &xgene_pmu->mcpmus, next) {
1278 _xgene_pmu_isr(irq, ctx->pmu_dev);
1279 }
1280 }
c0f7f7ac 1281 if (val & intr_mcb) {
832c927d
TN		 1282 list_for_each_entry(ctx, &xgene_pmu->mcbpmus, next) {
1283 _xgene_pmu_isr(irq, ctx->pmu_dev);
1284 }
1285 }
c0f7f7ac 1286 if (val & intr_l3c) {
832c927d
TN		 1287 list_for_each_entry(ctx, &xgene_pmu->l3cpmus, next) {
1288 _xgene_pmu_isr(irq, ctx->pmu_dev);
1289 }
1290 }
c0f7f7ac 1291 if (val & intr_iob) {
832c927d
TN		 1292 list_for_each_entry(ctx, &xgene_pmu->iobpmus, next) {
1293 _xgene_pmu_isr(irq, ctx->pmu_dev);
1294 }
1295 }
1296
1297 raw_spin_unlock_irqrestore(&xgene_pmu->lock, flags);
1298
1299 return IRQ_HANDLED;
1300}
1301
c0f7f7ac
HT		 1302static int acpi_pmu_probe_active_mcb_mcu_l3c(struct xgene_pmu *xgene_pmu,
1303 struct platform_device *pdev)
832c927d
TN		 1304{
1305 void __iomem *csw_csr, *mcba_csr, *mcbb_csr;
1306 struct resource *res;
1307 unsigned int reg;
1308
1309 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1310 csw_csr = devm_ioremap_resource(&pdev->dev, res);
1311 if (IS_ERR(csw_csr)) {
1312 dev_err(&pdev->dev, "ioremap failed for CSW CSR resource\n");
1313 return PTR_ERR(csw_csr);
1314 }
1315
1316 res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
1317 mcba_csr = devm_ioremap_resource(&pdev->dev, res);
1318 if (IS_ERR(mcba_csr)) {
1319 dev_err(&pdev->dev, "ioremap failed for MCBA CSR resource\n");
1320 return PTR_ERR(mcba_csr);
1321 }
1322
1323 res = platform_get_resource(pdev, IORESOURCE_MEM, 3);
1324 mcbb_csr = devm_ioremap_resource(&pdev->dev, res);
1325 if (IS_ERR(mcbb_csr)) {
1326 dev_err(&pdev->dev, "ioremap failed for MCBB CSR resource\n");
1327 return PTR_ERR(mcbb_csr);
1328 }
1329
c0f7f7ac
HT		 1330 xgene_pmu->l3c_active_mask = 0x1;
1331
832c927d
TN		 1332 reg = readl(csw_csr + CSW_CSWCR);
1333 if (reg & CSW_CSWCR_DUALMCB_MASK) {
1334 /* Dual MCB active */
1335 xgene_pmu->mcb_active_mask = 0x3;
1336 /* Probe all active MC(s) */
1337 reg = readl(mcbb_csr + CSW_CSWCR);
1338 xgene_pmu->mc_active_mask =
1339 (reg & MCBADDRMR_DUALMCU_MODE_MASK) ? 0xF : 0x5;
1340 } else {
1341 /* Single MCB active */
1342 xgene_pmu->mcb_active_mask = 0x1;
1343 /* Probe all active MC(s) */
1344 reg = readl(mcba_csr + CSW_CSWCR);
1345 xgene_pmu->mc_active_mask =
1346 (reg & MCBADDRMR_DUALMCU_MODE_MASK) ? 0x3 : 0x1;
1347 }
1348
1349 return 0;
1350}
1351
c0f7f7ac
HT		 1352static int acpi_pmu_v3_probe_active_mcb_mcu_l3c(struct xgene_pmu *xgene_pmu,
1353 struct platform_device *pdev)
1354{
1355 void __iomem *csw_csr;
1356 struct resource *res;
1357 unsigned int reg;
1358 u32 mcb0routing;
1359 u32 mcb1routing;
1360
1361 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1362 csw_csr = devm_ioremap_resource(&pdev->dev, res);
1363 if (IS_ERR(csw_csr)) {
1364 dev_err(&pdev->dev, "ioremap failed for CSW CSR resource\n");
1365 return PTR_ERR(csw_csr);
1366 }
1367
1368 reg = readl(csw_csr + CSW_CSWCR);
1369 mcb0routing = CSW_CSWCR_MCB0_ROUTING(reg);
1370 mcb1routing = CSW_CSWCR_MCB1_ROUTING(reg);
1371 if (reg & CSW_CSWCR_DUALMCB_MASK) {
1372 /* Dual MCB active */
1373 xgene_pmu->mcb_active_mask = 0x3;
1374 /* Probe all active L3C(s), maximum is 8 */
1375 xgene_pmu->l3c_active_mask = 0xFF;
1376 /* Probe all active MC(s), maximum is 8 */
1377 if ((mcb0routing == 0x2) && (mcb1routing == 0x2))
1378 xgene_pmu->mc_active_mask = 0xFF;
1379 else if ((mcb0routing == 0x1) && (mcb1routing == 0x1))
1380 xgene_pmu->mc_active_mask = 0x33;
1381 else
1382 xgene_pmu->mc_active_mask = 0x11;
1383 } else {
1384 /* Single MCB active */
1385 xgene_pmu->mcb_active_mask = 0x1;
1386 /* Probe all active L3C(s), maximum is 4 */
1387 xgene_pmu->l3c_active_mask = 0x0F;
1388 /* Probe all active MC(s), maximum is 4 */
1389 if (mcb0routing == 0x2)
1390 xgene_pmu->mc_active_mask = 0x0F;
1391 else if (mcb0routing == 0x1)
1392 xgene_pmu->mc_active_mask = 0x03;
1393 else
1394 xgene_pmu->mc_active_mask = 0x01;
1395 }
1396
1397 return 0;
1398}
1399
1400static int fdt_pmu_probe_active_mcb_mcu_l3c(struct xgene_pmu *xgene_pmu,
1401 struct platform_device *pdev)
832c927d
TN		 1402{
1403 struct regmap *csw_map, *mcba_map, *mcbb_map;
1404 struct device_node *np = pdev->dev.of_node;
1405 unsigned int reg;
1406
1407 csw_map = syscon_regmap_lookup_by_phandle(np, "regmap-csw");
1408 if (IS_ERR(csw_map)) {
1409 dev_err(&pdev->dev, "unable to get syscon regmap csw\n");
1410 return PTR_ERR(csw_map);
1411 }
1412
1413 mcba_map = syscon_regmap_lookup_by_phandle(np, "regmap-mcba");
1414 if (IS_ERR(mcba_map)) {
1415 dev_err(&pdev->dev, "unable to get syscon regmap mcba\n");
1416 return PTR_ERR(mcba_map);
1417 }
1418
1419 mcbb_map = syscon_regmap_lookup_by_phandle(np, "regmap-mcbb");
1420 if (IS_ERR(mcbb_map)) {
1421 dev_err(&pdev->dev, "unable to get syscon regmap mcbb\n");
1422 return PTR_ERR(mcbb_map);
1423 }
1424
c0f7f7ac 1425 xgene_pmu->l3c_active_mask = 0x1;
832c927d
TN		 1426 if (regmap_read(csw_map, CSW_CSWCR, &reg))
1427 return -EINVAL;
1428
1429 if (reg & CSW_CSWCR_DUALMCB_MASK) {
1430 /* Dual MCB active */
1431 xgene_pmu->mcb_active_mask = 0x3;
1432 /* Probe all active MC(s) */
1433 if (regmap_read(mcbb_map, MCBADDRMR, &reg))
1434 return 0;
1435 xgene_pmu->mc_active_mask =
1436 (reg & MCBADDRMR_DUALMCU_MODE_MASK) ? 0xF : 0x5;
1437 } else {
1438 /* Single MCB active */
1439 xgene_pmu->mcb_active_mask = 0x1;
1440 /* Probe all active MC(s) */
1441 if (regmap_read(mcba_map, MCBADDRMR, &reg))
1442 return 0;
1443 xgene_pmu->mc_active_mask =
1444 (reg & MCBADDRMR_DUALMCU_MODE_MASK) ? 0x3 : 0x1;
1445 }
1446
1447 return 0;
1448}
1449
c0f7f7ac
HT		 1450static int xgene_pmu_probe_active_mcb_mcu_l3c(struct xgene_pmu *xgene_pmu,
1451 struct platform_device *pdev)
832c927d 1452{
c0f7f7ac
HT		 1453 if (has_acpi_companion(&pdev->dev)) {
1454 if (xgene_pmu->version == PCP_PMU_V3)
1455 return acpi_pmu_v3_probe_active_mcb_mcu_l3c(xgene_pmu,
1456 pdev);
1457 else
1458 return acpi_pmu_probe_active_mcb_mcu_l3c(xgene_pmu,
1459 pdev);
1460 }
1461 return fdt_pmu_probe_active_mcb_mcu_l3c(xgene_pmu, pdev);
832c927d
TN		 1462}
1463
1464static char *xgene_pmu_dev_name(struct device *dev, u32 type, int id)
1465{
1466 switch (type) {
1467 case PMU_TYPE_L3C:
1468 return devm_kasprintf(dev, GFP_KERNEL, "l3c%d", id);
1469 case PMU_TYPE_IOB:
1470 return devm_kasprintf(dev, GFP_KERNEL, "iob%d", id);
c0f7f7ac
HT		 1471 case PMU_TYPE_IOB_SLOW:
1472 return devm_kasprintf(dev, GFP_KERNEL, "iob-slow%d", id);
832c927d
TN		 1473 case PMU_TYPE_MCB:
1474 return devm_kasprintf(dev, GFP_KERNEL, "mcb%d", id);
1475 case PMU_TYPE_MC:
1476 return devm_kasprintf(dev, GFP_KERNEL, "mc%d", id);
1477 default:
1478 return devm_kasprintf(dev, GFP_KERNEL, "unknown");
1479 }
1480}
1481
1482#if defined(CONFIG_ACPI)
1483static int acpi_pmu_dev_add_resource(struct acpi_resource *ares, void *data)
1484{
1485 struct resource *res = data;
1486
1487 if (ares->type == ACPI_RESOURCE_TYPE_FIXED_MEMORY32)
1488 acpi_dev_resource_memory(ares, res);
1489
1490 /* Always tell the ACPI core to skip this resource */
1491 return 1;
1492}
1493
1494static struct
1495xgene_pmu_dev_ctx *acpi_get_pmu_hw_inf(struct xgene_pmu *xgene_pmu,
1496 struct acpi_device *adev, u32 type)
1497{
1498 struct device *dev = xgene_pmu->dev;
1499 struct list_head resource_list;
1500 struct xgene_pmu_dev_ctx *ctx;
1501 const union acpi_object *obj;
1502 struct hw_pmu_info *inf;
1503 void __iomem *dev_csr;
1504 struct resource res;
1505 int enable_bit;
1506 int rc;
1507
1508 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
1509 if (!ctx)
1510 return NULL;
1511
1512 INIT_LIST_HEAD(&resource_list);
1513 rc = acpi_dev_get_resources(adev, &resource_list,
1514 acpi_pmu_dev_add_resource, &res);
1515 acpi_dev_free_resource_list(&resource_list);
9a1a1f40 1516 if (rc < 0) {
832c927d
TN		 1517 dev_err(dev, "PMU type %d: No resource address found\n", type);
1518 goto err;
1519 }
1520
1521 dev_csr = devm_ioremap_resource(dev, &res);
1522 if (IS_ERR(dev_csr)) {
1523 dev_err(dev, "PMU type %d: Fail to map resource\n", type);
1524 goto err;
1525 }
1526
1527 /* A PMU device node without enable-bit-index is always enabled */
1528 rc = acpi_dev_get_property(adev, "enable-bit-index",
1529 ACPI_TYPE_INTEGER, &obj);
1530 if (rc < 0)
1531 enable_bit = 0;
1532 else
1533 enable_bit = (int) obj->integer.value;
1534
1535 ctx->name = xgene_pmu_dev_name(dev, type, enable_bit);
1536 if (!ctx->name) {
1537 dev_err(dev, "PMU type %d: Fail to get device name\n", type);
1538 goto err;
1539 }
1540 inf = &ctx->inf;
1541 inf->type = type;
1542 inf->csr = dev_csr;
1543 inf->enable_mask = 1 << enable_bit;
1544
1545 return ctx;
1546err:
1547 devm_kfree(dev, ctx);
1548 return NULL;
1549}
1550
838955e2
HT		 1551static const struct acpi_device_id xgene_pmu_acpi_type_match[] = {
1552 {"APMC0D5D", PMU_TYPE_L3C},
1553 {"APMC0D5E", PMU_TYPE_IOB},
1554 {"APMC0D5F", PMU_TYPE_MCB},
1555 {"APMC0D60", PMU_TYPE_MC},
c0f7f7ac
HT		 1556 {"APMC0D84", PMU_TYPE_L3C},
1557 {"APMC0D85", PMU_TYPE_IOB},
1558 {"APMC0D86", PMU_TYPE_IOB_SLOW},
1559 {"APMC0D87", PMU_TYPE_MCB},
1560 {"APMC0D88", PMU_TYPE_MC},
838955e2
HT		 1561 {},
1562};
1563
1564static const struct acpi_device_id *xgene_pmu_acpi_match_type(
1565 const struct acpi_device_id *ids,
1566 struct acpi_device *adev)
1567{
1568 const struct acpi_device_id *match_id = NULL;
1569 const struct acpi_device_id *id;
1570
1571 for (id = ids; id->id[0] || id->cls; id++) {
1572 if (!acpi_match_device_ids(adev, id))
1573 match_id = id;
1574 else if (match_id)
1575 break;
1576 }
1577
1578 return match_id;
1579}
1580
832c927d
TN		 1581static acpi_status acpi_pmu_dev_add(acpi_handle handle, u32 level,
1582 void *data, void **return_value)
1583{
838955e2 1584 const struct acpi_device_id *acpi_id;
832c927d
TN		 1585 struct xgene_pmu *xgene_pmu = data;
1586 struct xgene_pmu_dev_ctx *ctx;
1587 struct acpi_device *adev;
1588
1589 if (acpi_bus_get_device(handle, &adev))
1590 return AE_OK;
1591 if (acpi_bus_get_status(adev) || !adev->status.present)
1592 return AE_OK;
1593
838955e2
HT		 1594 acpi_id = xgene_pmu_acpi_match_type(xgene_pmu_acpi_type_match, adev);
1595 if (!acpi_id)
1596 return AE_OK;
832c927d 1597
838955e2 1598 ctx = acpi_get_pmu_hw_inf(xgene_pmu, adev, (u32)acpi_id->driver_data);
832c927d
TN		 1599 if (!ctx)
1600 return AE_OK;
1601
1602 if (xgene_pmu_dev_add(xgene_pmu, ctx)) {
1603 /* Can't add the PMU device, skip it */
1604 devm_kfree(xgene_pmu->dev, ctx);
1605 return AE_OK;
1606 }
1607
1608 switch (ctx->inf.type) {
1609 case PMU_TYPE_L3C:
1610 list_add(&ctx->next, &xgene_pmu->l3cpmus);
1611 break;
1612 case PMU_TYPE_IOB:
1613 list_add(&ctx->next, &xgene_pmu->iobpmus);
1614 break;
c0f7f7ac
HT		 1615 case PMU_TYPE_IOB_SLOW:
1616 list_add(&ctx->next, &xgene_pmu->iobpmus);
1617 break;
832c927d
TN		 1618 case PMU_TYPE_MCB:
1619 list_add(&ctx->next, &xgene_pmu->mcbpmus);
1620 break;
1621 case PMU_TYPE_MC:
1622 list_add(&ctx->next, &xgene_pmu->mcpmus);
1623 break;
1624 }
1625 return AE_OK;
1626}
1627
1628static int acpi_pmu_probe_pmu_dev(struct xgene_pmu *xgene_pmu,
1629 struct platform_device *pdev)
1630{
1631 struct device *dev = xgene_pmu->dev;
1632 acpi_handle handle;
1633 acpi_status status;
1634
1635 handle = ACPI_HANDLE(dev);
1636 if (!handle)
1637 return -EINVAL;
1638
1639 status = acpi_walk_namespace(ACPI_TYPE_DEVICE, handle, 1,
1640 acpi_pmu_dev_add, NULL, xgene_pmu, NULL);
1641 if (ACPI_FAILURE(status)) {
1642 dev_err(dev, "failed to probe PMU devices\n");
1643 return -ENODEV;
1644 }
1645
1646 return 0;
1647}
1648#else
1649static int acpi_pmu_probe_pmu_dev(struct xgene_pmu *xgene_pmu,
1650 struct platform_device *pdev)
1651{
1652 return 0;
1653}
1654#endif
1655
1656static struct
1657xgene_pmu_dev_ctx *fdt_get_pmu_hw_inf(struct xgene_pmu *xgene_pmu,
1658 struct device_node *np, u32 type)
1659{
1660 struct device *dev = xgene_pmu->dev;
1661 struct xgene_pmu_dev_ctx *ctx;
1662 struct hw_pmu_info *inf;
1663 void __iomem *dev_csr;
1664 struct resource res;
1665 int enable_bit;
1666 int rc;
1667
1668 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
1669 if (!ctx)
1670 return NULL;
1671 rc = of_address_to_resource(np, 0, &res);
1672 if (rc < 0) {
1673 dev_err(dev, "PMU type %d: No resource address found\n", type);
1674 goto err;
1675 }
1676 dev_csr = devm_ioremap_resource(dev, &res);
1677 if (IS_ERR(dev_csr)) {
1678 dev_err(dev, "PMU type %d: Fail to map resource\n", type);
1679 goto err;
1680 }
1681
1682 /* A PMU device node without enable-bit-index is always enabled */
1683 if (of_property_read_u32(np, "enable-bit-index", &enable_bit))
1684 enable_bit = 0;
1685
1686 ctx->name = xgene_pmu_dev_name(dev, type, enable_bit);
1687 if (!ctx->name) {
1688 dev_err(dev, "PMU type %d: Fail to get device name\n", type);
1689 goto err;
1690 }
1691 inf = &ctx->inf;
1692 inf->type = type;
1693 inf->csr = dev_csr;
1694 inf->enable_mask = 1 << enable_bit;
1695
1696 return ctx;
1697err:
1698 devm_kfree(dev, ctx);
1699 return NULL;
1700}
1701
1702static int fdt_pmu_probe_pmu_dev(struct xgene_pmu *xgene_pmu,
1703 struct platform_device *pdev)
1704{
1705 struct xgene_pmu_dev_ctx *ctx;
1706 struct device_node *np;
1707
1708 for_each_child_of_node(pdev->dev.of_node, np) {
1709 if (!of_device_is_available(np))
1710 continue;
1711
1712 if (of_device_is_compatible(np, "apm,xgene-pmu-l3c"))
1713 ctx = fdt_get_pmu_hw_inf(xgene_pmu, np, PMU_TYPE_L3C);
1714 else if (of_device_is_compatible(np, "apm,xgene-pmu-iob"))
1715 ctx = fdt_get_pmu_hw_inf(xgene_pmu, np, PMU_TYPE_IOB);
1716 else if (of_device_is_compatible(np, "apm,xgene-pmu-mcb"))
1717 ctx = fdt_get_pmu_hw_inf(xgene_pmu, np, PMU_TYPE_MCB);
1718 else if (of_device_is_compatible(np, "apm,xgene-pmu-mc"))
1719 ctx = fdt_get_pmu_hw_inf(xgene_pmu, np, PMU_TYPE_MC);
1720 else
1721 ctx = NULL;
1722
1723 if (!ctx)
1724 continue;
1725
1726 if (xgene_pmu_dev_add(xgene_pmu, ctx)) {
1727 /* Can't add the PMU device, skip it */
1728 devm_kfree(xgene_pmu->dev, ctx);
1729 continue;
1730 }
1731
1732 switch (ctx->inf.type) {
1733 case PMU_TYPE_L3C:
1734 list_add(&ctx->next, &xgene_pmu->l3cpmus);
1735 break;
1736 case PMU_TYPE_IOB:
1737 list_add(&ctx->next, &xgene_pmu->iobpmus);
1738 break;
c0f7f7ac
HT		 1739 case PMU_TYPE_IOB_SLOW:
1740 list_add(&ctx->next, &xgene_pmu->iobpmus);
1741 break;
832c927d
TN		 1742 case PMU_TYPE_MCB:
1743 list_add(&ctx->next, &xgene_pmu->mcbpmus);
1744 break;
1745 case PMU_TYPE_MC:
1746 list_add(&ctx->next, &xgene_pmu->mcpmus);
1747 break;
1748 }
1749 }
1750
1751 return 0;
1752}
1753
1754static int xgene_pmu_probe_pmu_dev(struct xgene_pmu *xgene_pmu,
1755 struct platform_device *pdev)
1756{
1757 if (has_acpi_companion(&pdev->dev))
1758 return acpi_pmu_probe_pmu_dev(xgene_pmu, pdev);
1759 return fdt_pmu_probe_pmu_dev(xgene_pmu, pdev);
1760}
1761
1762static const struct xgene_pmu_data xgene_pmu_data = {
1763 .id = PCP_PMU_V1,
1764};
1765
1766static const struct xgene_pmu_data xgene_pmu_v2_data = {
1767 .id = PCP_PMU_V2,
1768};
1769
e35e0a04
HT		 1770static const struct xgene_pmu_ops xgene_pmu_ops = {
1771 .mask_int = xgene_pmu_mask_int,
1772 .unmask_int = xgene_pmu_unmask_int,
1773 .read_counter = xgene_pmu_read_counter32,
1774 .write_counter = xgene_pmu_write_counter32,
1775 .write_evttype = xgene_pmu_write_evttype,
1776 .write_agentmsk = xgene_pmu_write_agentmsk,
1777 .write_agent1msk = xgene_pmu_write_agent1msk,
1778 .enable_counter = xgene_pmu_enable_counter,
1779 .disable_counter = xgene_pmu_disable_counter,
1780 .enable_counter_int = xgene_pmu_enable_counter_int,
1781 .disable_counter_int = xgene_pmu_disable_counter_int,
1782 .reset_counters = xgene_pmu_reset_counters,
1783 .start_counters = xgene_pmu_start_counters,
1784 .stop_counters = xgene_pmu_stop_counters,
1785};
1786
c0f7f7ac
HT		 1787static const struct xgene_pmu_ops xgene_pmu_v3_ops = {
1788 .mask_int = xgene_pmu_v3_mask_int,
1789 .unmask_int = xgene_pmu_v3_unmask_int,
1790 .read_counter = xgene_pmu_read_counter64,
1791 .write_counter = xgene_pmu_write_counter64,
1792 .write_evttype = xgene_pmu_write_evttype,
1793 .write_agentmsk = xgene_pmu_v3_write_agentmsk,
1794 .write_agent1msk = xgene_pmu_v3_write_agent1msk,
1795 .enable_counter = xgene_pmu_enable_counter,
1796 .disable_counter = xgene_pmu_disable_counter,
1797 .enable_counter_int = xgene_pmu_enable_counter_int,
1798 .disable_counter_int = xgene_pmu_disable_counter_int,
1799 .reset_counters = xgene_pmu_reset_counters,
1800 .start_counters = xgene_pmu_start_counters,
1801 .stop_counters = xgene_pmu_stop_counters,
1802};
1803
832c927d
TN		 1804static const struct of_device_id xgene_pmu_of_match[] = {
1805 { .compatible = "apm,xgene-pmu", .data = &xgene_pmu_data },
1806 { .compatible = "apm,xgene-pmu-v2", .data = &xgene_pmu_v2_data },
1807 {},
1808};
1809MODULE_DEVICE_TABLE(of, xgene_pmu_of_match);
1810#ifdef CONFIG_ACPI
1811static const struct acpi_device_id xgene_pmu_acpi_match[] = {
1812 {"APMC0D5B", PCP_PMU_V1},
1813 {"APMC0D5C", PCP_PMU_V2},
c0f7f7ac 1814 {"APMC0D83", PCP_PMU_V3},
832c927d
TN		 1815 {},
1816};
1817MODULE_DEVICE_TABLE(acpi, xgene_pmu_acpi_match);
1818#endif
1819
1820static int xgene_pmu_probe(struct platform_device *pdev)
1821{
1822 const struct xgene_pmu_data *dev_data;
1823 const struct of_device_id *of_id;
1824 struct xgene_pmu *xgene_pmu;
1825 struct resource *res;
1826 int irq, rc;
1827 int version;
1828
1829 xgene_pmu = devm_kzalloc(&pdev->dev, sizeof(*xgene_pmu), GFP_KERNEL);
1830 if (!xgene_pmu)
1831 return -ENOMEM;
1832 xgene_pmu->dev = &pdev->dev;
1833 platform_set_drvdata(pdev, xgene_pmu);
1834
1835 version = -EINVAL;
1836 of_id = of_match_device(xgene_pmu_of_match, &pdev->dev);
1837 if (of_id) {
1838 dev_data = (const struct xgene_pmu_data *) of_id->data;
1839 version = dev_data->id;
1840 }
1841
1842#ifdef CONFIG_ACPI
1843 if (ACPI_COMPANION(&pdev->dev)) {
1844 const struct acpi_device_id *acpi_id;
1845
1846 acpi_id = acpi_match_device(xgene_pmu_acpi_match, &pdev->dev);
1847 if (acpi_id)
1848 version = (int) acpi_id->driver_data;
1849 }
1850#endif
1851 if (version < 0)
1852 return -ENODEV;
1853
c0f7f7ac
HT		 1854 if (version == PCP_PMU_V3)
1855 xgene_pmu->ops = &xgene_pmu_v3_ops;
1856 else
1857 xgene_pmu->ops = &xgene_pmu_ops;
e35e0a04 1858
832c927d
TN		 1859 INIT_LIST_HEAD(&xgene_pmu->l3cpmus);
1860 INIT_LIST_HEAD(&xgene_pmu->iobpmus);
1861 INIT_LIST_HEAD(&xgene_pmu->mcbpmus);
1862 INIT_LIST_HEAD(&xgene_pmu->mcpmus);
1863
1864 xgene_pmu->version = version;
1865 dev_info(&pdev->dev, "X-Gene PMU version %d\n", xgene_pmu->version);
1866
1867 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1868 xgene_pmu->pcppmu_csr = devm_ioremap_resource(&pdev->dev, res);
1869 if (IS_ERR(xgene_pmu->pcppmu_csr)) {
1870 dev_err(&pdev->dev, "ioremap failed for PCP PMU resource\n");
1871 rc = PTR_ERR(xgene_pmu->pcppmu_csr);
1872 goto err;
1873 }
1874
1875 irq = platform_get_irq(pdev, 0);
1876 if (irq < 0) {
1877 dev_err(&pdev->dev, "No IRQ resource\n");
1878 rc = -EINVAL;
1879 goto err;
1880 }
1881 rc = devm_request_irq(&pdev->dev, irq, xgene_pmu_isr,
1882 IRQF_NOBALANCING | IRQF_NO_THREAD,
1883 dev_name(&pdev->dev), xgene_pmu);
1884 if (rc) {
1885 dev_err(&pdev->dev, "Could not request IRQ %d\n", irq);
1886 goto err;
1887 }
1888
1889 raw_spin_lock_init(&xgene_pmu->lock);
1890
1891 /* Check for active MCBs and MCUs */
c0f7f7ac 1892 rc = xgene_pmu_probe_active_mcb_mcu_l3c(xgene_pmu, pdev);
832c927d
TN		 1893 if (rc) {
1894 dev_warn(&pdev->dev, "Unknown MCB/MCU active status\n");
1895 xgene_pmu->mcb_active_mask = 0x1;
1896 xgene_pmu->mc_active_mask = 0x1;
1897 }
1898
1899 /* Pick one core to use for cpumask attributes */
1900 cpumask_set_cpu(smp_processor_id(), &xgene_pmu->cpu);
1901
1902 /* Make sure that the overflow interrupt is handled by this CPU */
1903 rc = irq_set_affinity(irq, &xgene_pmu->cpu);
1904 if (rc) {
1905 dev_err(&pdev->dev, "Failed to set interrupt affinity!\n");
1906 goto err;
1907 }
1908
1909 /* Walk through the tree for all PMU perf devices */
1910 rc = xgene_pmu_probe_pmu_dev(xgene_pmu, pdev);
1911 if (rc) {
1912 dev_err(&pdev->dev, "No PMU perf devices found!\n");
1913 goto err;
1914 }
1915
1916 /* Enable interrupt */
e35e0a04 1917 xgene_pmu->ops->unmask_int(xgene_pmu);
832c927d
TN		 1918
1919 return 0;
1920
1921err:
1922 if (xgene_pmu->pcppmu_csr)
1923 devm_iounmap(&pdev->dev, xgene_pmu->pcppmu_csr);
1924 devm_kfree(&pdev->dev, xgene_pmu);
1925
1926 return rc;
1927}
1928
1929static void
1930xgene_pmu_dev_cleanup(struct xgene_pmu *xgene_pmu, struct list_head *pmus)
1931{
1932 struct xgene_pmu_dev_ctx *ctx;
1933 struct device *dev = xgene_pmu->dev;
1934 struct xgene_pmu_dev *pmu_dev;
1935
1936 list_for_each_entry(ctx, pmus, next) {
1937 pmu_dev = ctx->pmu_dev;
1938 if (pmu_dev->inf->csr)
1939 devm_iounmap(dev, pmu_dev->inf->csr);
1940 devm_kfree(dev, ctx);
1941 devm_kfree(dev, pmu_dev);
1942 }
1943}
1944
1945static int xgene_pmu_remove(struct platform_device *pdev)
1946{
1947 struct xgene_pmu *xgene_pmu = dev_get_drvdata(&pdev->dev);
1948
1949 xgene_pmu_dev_cleanup(xgene_pmu, &xgene_pmu->l3cpmus);
1950 xgene_pmu_dev_cleanup(xgene_pmu, &xgene_pmu->iobpmus);
1951 xgene_pmu_dev_cleanup(xgene_pmu, &xgene_pmu->mcbpmus);
1952 xgene_pmu_dev_cleanup(xgene_pmu, &xgene_pmu->mcpmus);
1953
1954 if (xgene_pmu->pcppmu_csr)
1955 devm_iounmap(&pdev->dev, xgene_pmu->pcppmu_csr);
1956 devm_kfree(&pdev->dev, xgene_pmu);
1957
1958 return 0;
1959}
1960
1961static struct platform_driver xgene_pmu_driver = {
1962 .probe = xgene_pmu_probe,
1963 .remove = xgene_pmu_remove,
1964 .driver = {
1965 .name = "xgene-pmu",
1966 .of_match_table = xgene_pmu_of_match,
1967 .acpi_match_table = ACPI_PTR(xgene_pmu_acpi_match),
1968 },
1969};
1970
1971builtin_platform_driver(xgene_pmu_driver);
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