[mirror_ubuntu-artful-kernel.git] / drivers / phy / phy-exynos-mipi-video.c

/*
 * Samsung S5P/EXYNOS SoC series MIPI CSIS/DSIM DPHY driver
 *
 * Copyright (C) 2013,2016 Samsung Electronics Co., Ltd.
 * Author: Sylwester Nawrocki <s.nawrocki@samsung.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/err.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/phy/phy.h>
#include <linux/regmap.h>
#include <linux/spinlock.h>
#include <linux/soc/samsung/exynos-regs-pmu.h>
#include <linux/mfd/syscon.h>

enum exynos_mipi_phy_id {
	EXYNOS_MIPI_PHY_ID_NONE = -1,
	EXYNOS_MIPI_PHY_ID_CSIS0,
	EXYNOS_MIPI_PHY_ID_DSIM0,
	EXYNOS_MIPI_PHY_ID_CSIS1,
	EXYNOS_MIPI_PHY_ID_DSIM1,
	EXYNOS_MIPI_PHY_ID_CSIS2,
	EXYNOS_MIPI_PHYS_NUM
};

enum exynos_mipi_phy_regmap_id {
	EXYNOS_MIPI_REGMAP_PMU,
	EXYNOS_MIPI_REGMAP_DISP,
	EXYNOS_MIPI_REGMAP_CAM0,
	EXYNOS_MIPI_REGMAP_CAM1,
	EXYNOS_MIPI_REGMAPS_NUM
};

struct mipi_phy_device_desc {
	int num_phys;
	int num_regmaps;
	const char *regmap_names[EXYNOS_MIPI_REGMAPS_NUM];
	struct exynos_mipi_phy_desc {
		enum exynos_mipi_phy_id	coupled_phy_id;
		u32 enable_val;
		unsigned int enable_reg;
		enum exynos_mipi_phy_regmap_id enable_map;
		u32 resetn_val;
		unsigned int resetn_reg;
		enum exynos_mipi_phy_regmap_id resetn_map;
	} phys[EXYNOS_MIPI_PHYS_NUM];
};

static const struct mipi_phy_device_desc s5pv210_mipi_phy = {
	.num_regmaps = 1,
	.regmap_names = {"syscon"},
	.num_phys = 4,
	.phys = {
		{
			/* EXYNOS_MIPI_PHY_ID_CSIS0 */
			.coupled_phy_id = EXYNOS_MIPI_PHY_ID_DSIM0,
			.enable_val = EXYNOS4_PHY_ENABLE,
			.enable_reg = EXYNOS4_MIPI_PHY_CONTROL(0),
			.enable_map = EXYNOS_MIPI_REGMAP_PMU,
			.resetn_val = EXYNOS4_MIPI_PHY_SRESETN,
			.resetn_reg = EXYNOS4_MIPI_PHY_CONTROL(0),
			.resetn_map = EXYNOS_MIPI_REGMAP_PMU,
		}, {
			/* EXYNOS_MIPI_PHY_ID_DSIM0 */
			.coupled_phy_id = EXYNOS_MIPI_PHY_ID_CSIS0,
			.enable_val = EXYNOS4_PHY_ENABLE,
			.enable_reg = EXYNOS4_MIPI_PHY_CONTROL(0),
			.enable_map = EXYNOS_MIPI_REGMAP_PMU,
			.resetn_val = EXYNOS4_MIPI_PHY_MRESETN,
			.resetn_reg = EXYNOS4_MIPI_PHY_CONTROL(0),
			.resetn_map = EXYNOS_MIPI_REGMAP_PMU,
		}, {
			/* EXYNOS_MIPI_PHY_ID_CSIS1 */
			.coupled_phy_id = EXYNOS_MIPI_PHY_ID_DSIM1,
			.enable_val = EXYNOS4_PHY_ENABLE,
			.enable_reg = EXYNOS4_MIPI_PHY_CONTROL(1),
			.enable_map = EXYNOS_MIPI_REGMAP_PMU,
			.resetn_val = EXYNOS4_MIPI_PHY_SRESETN,
			.resetn_reg = EXYNOS4_MIPI_PHY_CONTROL(1),
			.resetn_map = EXYNOS_MIPI_REGMAP_PMU,
		}, {
			/* EXYNOS_MIPI_PHY_ID_DSIM1 */
			.coupled_phy_id = EXYNOS_MIPI_PHY_ID_CSIS1,
			.enable_val = EXYNOS4_PHY_ENABLE,
			.enable_reg = EXYNOS4_MIPI_PHY_CONTROL(1),
			.enable_map = EXYNOS_MIPI_REGMAP_PMU,
			.resetn_val = EXYNOS4_MIPI_PHY_MRESETN,
			.resetn_reg = EXYNOS4_MIPI_PHY_CONTROL(1),
			.resetn_map = EXYNOS_MIPI_REGMAP_PMU,
		},
	},
};

static const struct mipi_phy_device_desc exynos5420_mipi_phy = {
	.num_regmaps = 1,
	.regmap_names = {"syscon"},
	.num_phys = 5,
	.phys = {
		{
			/* EXYNOS_MIPI_PHY_ID_CSIS0 */
			.coupled_phy_id = EXYNOS_MIPI_PHY_ID_DSIM0,
			.enable_val = EXYNOS4_PHY_ENABLE,
			.enable_reg = EXYNOS5420_MIPI_PHY_CONTROL(0),
			.enable_map = EXYNOS_MIPI_REGMAP_PMU,
			.resetn_val = EXYNOS4_MIPI_PHY_SRESETN,
			.resetn_reg = EXYNOS5420_MIPI_PHY_CONTROL(0),
			.resetn_map = EXYNOS_MIPI_REGMAP_PMU,
		}, {
			/* EXYNOS_MIPI_PHY_ID_DSIM0 */
			.coupled_phy_id = EXYNOS_MIPI_PHY_ID_CSIS0,
			.enable_val = EXYNOS4_PHY_ENABLE,
			.enable_reg = EXYNOS5420_MIPI_PHY_CONTROL(0),
			.enable_map = EXYNOS_MIPI_REGMAP_PMU,
			.resetn_val = EXYNOS4_MIPI_PHY_MRESETN,
			.resetn_reg = EXYNOS5420_MIPI_PHY_CONTROL(0),
			.resetn_map = EXYNOS_MIPI_REGMAP_PMU,
		}, {
			/* EXYNOS_MIPI_PHY_ID_CSIS1 */
			.coupled_phy_id = EXYNOS_MIPI_PHY_ID_DSIM1,
			.enable_val = EXYNOS4_PHY_ENABLE,
			.enable_reg = EXYNOS5420_MIPI_PHY_CONTROL(1),
			.enable_map = EXYNOS_MIPI_REGMAP_PMU,
			.resetn_val = EXYNOS4_MIPI_PHY_SRESETN,
			.resetn_reg = EXYNOS5420_MIPI_PHY_CONTROL(1),
			.resetn_map = EXYNOS_MIPI_REGMAP_PMU,
		}, {
			/* EXYNOS_MIPI_PHY_ID_DSIM1 */
			.coupled_phy_id = EXYNOS_MIPI_PHY_ID_CSIS1,
			.enable_val = EXYNOS4_PHY_ENABLE,
			.enable_reg = EXYNOS5420_MIPI_PHY_CONTROL(1),
			.enable_map = EXYNOS_MIPI_REGMAP_PMU,
			.resetn_val = EXYNOS4_MIPI_PHY_MRESETN,
			.resetn_reg = EXYNOS5420_MIPI_PHY_CONTROL(1),
			.resetn_map = EXYNOS_MIPI_REGMAP_PMU,
		}, {
			/* EXYNOS_MIPI_PHY_ID_CSIS2 */
			.coupled_phy_id = EXYNOS_MIPI_PHY_ID_NONE,
			.enable_val = EXYNOS4_PHY_ENABLE,
			.enable_reg = EXYNOS5420_MIPI_PHY_CONTROL(2),
			.enable_map = EXYNOS_MIPI_REGMAP_PMU,
			.resetn_val = EXYNOS4_MIPI_PHY_SRESETN,
			.resetn_reg = EXYNOS5420_MIPI_PHY_CONTROL(2),
			.resetn_map = EXYNOS_MIPI_REGMAP_PMU,
		},
	},
};

#define EXYNOS5433_SYSREG_DISP_MIPI_PHY		0x100C
#define EXYNOS5433_SYSREG_CAM0_MIPI_DPHY_CON	0x1014
#define EXYNOS5433_SYSREG_CAM1_MIPI_DPHY_CON	0x1020

static const struct mipi_phy_device_desc exynos5433_mipi_phy = {
	.num_regmaps = 4,
	.regmap_names = {
		"samsung,pmu-syscon",
		"samsung,disp-sysreg",
		"samsung,cam0-sysreg",
		"samsung,cam1-sysreg"
	},
	.num_phys = 5,
	.phys = {
		{
			/* EXYNOS_MIPI_PHY_ID_CSIS0 */
			.coupled_phy_id = EXYNOS_MIPI_PHY_ID_DSIM0,
			.enable_val = EXYNOS4_PHY_ENABLE,
			.enable_reg = EXYNOS4_MIPI_PHY_CONTROL(0),
			.enable_map = EXYNOS_MIPI_REGMAP_PMU,
			.resetn_val = BIT(0),
			.resetn_reg = EXYNOS5433_SYSREG_CAM0_MIPI_DPHY_CON,
			.resetn_map = EXYNOS_MIPI_REGMAP_CAM0,
		}, {
			/* EXYNOS_MIPI_PHY_ID_DSIM0 */
			.coupled_phy_id = EXYNOS_MIPI_PHY_ID_CSIS0,
			.enable_val = EXYNOS4_PHY_ENABLE,
			.enable_reg = EXYNOS4_MIPI_PHY_CONTROL(0),
			.enable_map = EXYNOS_MIPI_REGMAP_PMU,
			.resetn_val = BIT(0),
			.resetn_reg = EXYNOS5433_SYSREG_DISP_MIPI_PHY,
			.resetn_map = EXYNOS_MIPI_REGMAP_DISP,
		}, {
			/* EXYNOS_MIPI_PHY_ID_CSIS1 */
			.coupled_phy_id = EXYNOS_MIPI_PHY_ID_NONE,
			.enable_val = EXYNOS4_PHY_ENABLE,
			.enable_reg = EXYNOS4_MIPI_PHY_CONTROL(1),
			.enable_map = EXYNOS_MIPI_REGMAP_PMU,
			.resetn_val = BIT(1),
			.resetn_reg = EXYNOS5433_SYSREG_CAM0_MIPI_DPHY_CON,
			.resetn_map = EXYNOS_MIPI_REGMAP_CAM0,
		}, {
			/* EXYNOS_MIPI_PHY_ID_DSIM1 */
			.coupled_phy_id = EXYNOS_MIPI_PHY_ID_NONE,
			.enable_val = EXYNOS4_PHY_ENABLE,
			.enable_reg = EXYNOS4_MIPI_PHY_CONTROL(1),
			.enable_map = EXYNOS_MIPI_REGMAP_PMU,
			.resetn_val = BIT(1),
			.resetn_reg = EXYNOS5433_SYSREG_DISP_MIPI_PHY,
			.resetn_map = EXYNOS_MIPI_REGMAP_DISP,
		}, {
			/* EXYNOS_MIPI_PHY_ID_CSIS2 */
			.coupled_phy_id = EXYNOS_MIPI_PHY_ID_NONE,
			.enable_val = EXYNOS4_PHY_ENABLE,
			.enable_reg = EXYNOS4_MIPI_PHY_CONTROL(2),
			.enable_map = EXYNOS_MIPI_REGMAP_PMU,
			.resetn_val = BIT(0),
			.resetn_reg = EXYNOS5433_SYSREG_CAM1_MIPI_DPHY_CON,
			.resetn_map = EXYNOS_MIPI_REGMAP_CAM1,
		},
	},
};

struct exynos_mipi_video_phy {
	struct regmap *regmaps[EXYNOS_MIPI_REGMAPS_NUM];
	int num_phys;
	struct video_phy_desc {
		struct phy *phy;
		unsigned int index;
		const struct exynos_mipi_phy_desc *data;
	} phys[EXYNOS_MIPI_PHYS_NUM];
	spinlock_t slock;
};

static int __set_phy_state(const struct exynos_mipi_phy_desc *data,
			   struct exynos_mipi_video_phy *state, unsigned int on)
{
	u32 val;

	spin_lock(&state->slock);

	/* disable in PMU sysreg */
	if (!on && data->coupled_phy_id >= 0 &&
	    state->phys[data->coupled_phy_id].phy->power_count == 0) {
		regmap_read(state->regmaps[data->enable_map], data->enable_reg,
			    &val);
		val &= ~data->enable_val;
		regmap_write(state->regmaps[data->enable_map], data->enable_reg,
			     val);
	}

	/* PHY reset */
	regmap_read(state->regmaps[data->resetn_map], data->resetn_reg, &val);
	val = on ? (val | data->resetn_val) : (val & ~data->resetn_val);
	regmap_write(state->regmaps[data->resetn_map], data->resetn_reg, val);

	/* enable in PMU sysreg */
	if (on) {
		regmap_read(state->regmaps[data->enable_map], data->enable_reg,
			    &val);
		val |= data->enable_val;
		regmap_write(state->regmaps[data->enable_map], data->enable_reg,
			     val);
	}

	spin_unlock(&state->slock);

	return 0;
}

#define to_mipi_video_phy(desc) \
	container_of((desc), struct exynos_mipi_video_phy, phys[(desc)->index])

static int exynos_mipi_video_phy_power_on(struct phy *phy)
{
	struct video_phy_desc *phy_desc = phy_get_drvdata(phy);
	struct exynos_mipi_video_phy *state = to_mipi_video_phy(phy_desc);

	return __set_phy_state(phy_desc->data, state, 1);
}

static int exynos_mipi_video_phy_power_off(struct phy *phy)
{
	struct video_phy_desc *phy_desc = phy_get_drvdata(phy);
	struct exynos_mipi_video_phy *state = to_mipi_video_phy(phy_desc);

	return __set_phy_state(phy_desc->data, state, 0);
}

static struct phy *exynos_mipi_video_phy_xlate(struct device *dev,
					struct of_phandle_args *args)
{
	struct exynos_mipi_video_phy *state = dev_get_drvdata(dev);

	if (WARN_ON(args->args[0] >= state->num_phys))
		return ERR_PTR(-ENODEV);

	return state->phys[args->args[0]].phy;
}

static const struct phy_ops exynos_mipi_video_phy_ops = {
	.power_on	= exynos_mipi_video_phy_power_on,
	.power_off	= exynos_mipi_video_phy_power_off,
	.owner		= THIS_MODULE,
};

static int exynos_mipi_video_phy_probe(struct platform_device *pdev)
{
	const struct mipi_phy_device_desc *phy_dev;
	struct exynos_mipi_video_phy *state;
	struct device *dev = &pdev->dev;
	struct device_node *np = dev->of_node;
	struct phy_provider *phy_provider;
	unsigned int i;

	phy_dev = of_device_get_match_data(dev);
	if (!phy_dev)
		return -ENODEV;

	state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL);
	if (!state)
		return -ENOMEM;

	for (i = 0; i < phy_dev->num_regmaps; i++) {
		state->regmaps[i] = syscon_regmap_lookup_by_phandle(np,
						phy_dev->regmap_names[i]);
		if (IS_ERR(state->regmaps[i]))
			return PTR_ERR(state->regmaps[i]);
	}
	state->num_phys = phy_dev->num_phys;
	spin_lock_init(&state->slock);

	dev_set_drvdata(dev, state);

	for (i = 0; i < state->num_phys; i++) {
		struct phy *phy = devm_phy_create(dev, NULL,
						  &exynos_mipi_video_phy_ops);
		if (IS_ERR(phy)) {
			dev_err(dev, "failed to create PHY %d\n", i);
			return PTR_ERR(phy);
		}

		state->phys[i].phy = phy;
		state->phys[i].index = i;
		state->phys[i].data = &phy_dev->phys[i];
		phy_set_drvdata(phy, &state->phys[i]);
	}

	phy_provider = devm_of_phy_provider_register(dev,
					exynos_mipi_video_phy_xlate);

	return PTR_ERR_OR_ZERO(phy_provider);
}

static const struct of_device_id exynos_mipi_video_phy_of_match[] = {
	{
		.compatible = "samsung,s5pv210-mipi-video-phy",
		.data = &s5pv210_mipi_phy,
	}, {
		.compatible = "samsung,exynos5420-mipi-video-phy",
		.data = &exynos5420_mipi_phy,
	}, {
		.compatible = "samsung,exynos5433-mipi-video-phy",
		.data = &exynos5433_mipi_phy,
	},
	{ /* sentinel */ },
};
MODULE_DEVICE_TABLE(of, exynos_mipi_video_phy_of_match);

static struct platform_driver exynos_mipi_video_phy_driver = {
	.probe	= exynos_mipi_video_phy_probe,
	.driver = {
		.of_match_table	= exynos_mipi_video_phy_of_match,
		.name  = "exynos-mipi-video-phy",
	}
};
module_platform_driver(exynos_mipi_video_phy_driver);

MODULE_DESCRIPTION("Samsung S5P/EXYNOS SoC MIPI CSI-2/DSI PHY driver");
MODULE_AUTHOR("Sylwester Nawrocki <s.nawrocki@samsung.com>");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
069d2e26 SN	1	/*
	2	* Samsung S5P/EXYNOS SoC series MIPI CSIS/DSIM DPHY driver
	3	*
71f5c63c	4	* Copyright (C) 2013,2016 Samsung Electronics Co., Ltd.
069d2e26 SN	5	* Author: Sylwester Nawrocki <s.nawrocki@samsung.com>
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11
22fda307	12	#include <linux/err.h>
069d2e26 SN	13	#include <linux/io.h>
	14	#include <linux/kernel.h>
	15	#include <linux/module.h>
	16	#include <linux/of.h>
	17	#include <linux/of_address.h>
97a3042f	18	#include <linux/of_device.h>
069d2e26	19	#include <linux/phy/phy.h>
e4b3d380	20	#include <linux/regmap.h>
069d2e26	21	#include <linux/spinlock.h>
5812f010	22	#include <linux/soc/samsung/exynos-regs-pmu.h>
e4b3d380	23	#include <linux/mfd/syscon.h>
069d2e26	24
069d2e26	25	enum exynos_mipi_phy_id {
97a3042f	26	EXYNOS_MIPI_PHY_ID_NONE = -1,
069d2e26 SN	27	EXYNOS_MIPI_PHY_ID_CSIS0,
	28	EXYNOS_MIPI_PHY_ID_DSIM0,
	29	EXYNOS_MIPI_PHY_ID_CSIS1,
	30	EXYNOS_MIPI_PHY_ID_DSIM1,
71f5c63c	31	EXYNOS_MIPI_PHY_ID_CSIS2,
069d2e26 SN	32	EXYNOS_MIPI_PHYS_NUM
	33	};
	34
97a3042f MS	35	enum exynos_mipi_phy_regmap_id {
97a3042f MS	36	EXYNOS_MIPI_REGMAP_PMU,
71f5c63c MS	37	EXYNOS_MIPI_REGMAP_DISP,
	38	EXYNOS_MIPI_REGMAP_CAM0,
	39	EXYNOS_MIPI_REGMAP_CAM1,
97a3042f MS	40	EXYNOS_MIPI_REGMAPS_NUM
	41	};
	42
	43	struct mipi_phy_device_desc {
	44	int num_phys;
	45	int num_regmaps;
	46	const char *regmap_names[EXYNOS_MIPI_REGMAPS_NUM];
	47	struct exynos_mipi_phy_desc {
	48	enum exynos_mipi_phy_id coupled_phy_id;
	49	u32 enable_val;
	50	unsigned int enable_reg;
	51	enum exynos_mipi_phy_regmap_id enable_map;
	52	u32 resetn_val;
	53	unsigned int resetn_reg;
	54	enum exynos_mipi_phy_regmap_id resetn_map;
	55	} phys[EXYNOS_MIPI_PHYS_NUM];
	56	};
	57
	58	static const struct mipi_phy_device_desc s5pv210_mipi_phy = {
	59	.num_regmaps = 1,
	60	.regmap_names = {"syscon"},
	61	.num_phys = 4,
	62	.phys = {
	63	{
	64	/* EXYNOS_MIPI_PHY_ID_CSIS0 */
	65	.coupled_phy_id = EXYNOS_MIPI_PHY_ID_DSIM0,
7a66647b	66	.enable_val = EXYNOS4_PHY_ENABLE,
97a3042f MS	67	.enable_reg = EXYNOS4_MIPI_PHY_CONTROL(0),
	68	.enable_map = EXYNOS_MIPI_REGMAP_PMU,
	69	.resetn_val = EXYNOS4_MIPI_PHY_SRESETN,
	70	.resetn_reg = EXYNOS4_MIPI_PHY_CONTROL(0),
	71	.resetn_map = EXYNOS_MIPI_REGMAP_PMU,
	72	}, {
	73	/* EXYNOS_MIPI_PHY_ID_DSIM0 */
	74	.coupled_phy_id = EXYNOS_MIPI_PHY_ID_CSIS0,
7a66647b	75	.enable_val = EXYNOS4_PHY_ENABLE,
97a3042f MS	76	.enable_reg = EXYNOS4_MIPI_PHY_CONTROL(0),
	77	.enable_map = EXYNOS_MIPI_REGMAP_PMU,
	78	.resetn_val = EXYNOS4_MIPI_PHY_MRESETN,
	79	.resetn_reg = EXYNOS4_MIPI_PHY_CONTROL(0),
	80	.resetn_map = EXYNOS_MIPI_REGMAP_PMU,
	81	}, {
	82	/* EXYNOS_MIPI_PHY_ID_CSIS1 */
	83	.coupled_phy_id = EXYNOS_MIPI_PHY_ID_DSIM1,
7a66647b	84	.enable_val = EXYNOS4_PHY_ENABLE,
97a3042f MS	85	.enable_reg = EXYNOS4_MIPI_PHY_CONTROL(1),
	86	.enable_map = EXYNOS_MIPI_REGMAP_PMU,
	87	.resetn_val = EXYNOS4_MIPI_PHY_SRESETN,
	88	.resetn_reg = EXYNOS4_MIPI_PHY_CONTROL(1),
	89	.resetn_map = EXYNOS_MIPI_REGMAP_PMU,
	90	}, {
	91	/* EXYNOS_MIPI_PHY_ID_DSIM1 */
	92	.coupled_phy_id = EXYNOS_MIPI_PHY_ID_CSIS1,
7a66647b	93	.enable_val = EXYNOS4_PHY_ENABLE,
97a3042f MS	94	.enable_reg = EXYNOS4_MIPI_PHY_CONTROL(1),
	95	.enable_map = EXYNOS_MIPI_REGMAP_PMU,
	96	.resetn_val = EXYNOS4_MIPI_PHY_MRESETN,
	97	.resetn_reg = EXYNOS4_MIPI_PHY_CONTROL(1),
	98	.resetn_map = EXYNOS_MIPI_REGMAP_PMU,
	99	},
	100	},
	101	};
	102
71f5c63c MS	103	static const struct mipi_phy_device_desc exynos5420_mipi_phy = {
	104	.num_regmaps = 1,
	105	.regmap_names = {"syscon"},
	106	.num_phys = 5,
	107	.phys = {
	108	{
	109	/* EXYNOS_MIPI_PHY_ID_CSIS0 */
	110	.coupled_phy_id = EXYNOS_MIPI_PHY_ID_DSIM0,
7a66647b	111	.enable_val = EXYNOS4_PHY_ENABLE,
cf09ee59	112	.enable_reg = EXYNOS5420_MIPI_PHY_CONTROL(0),
71f5c63c	113	.enable_map = EXYNOS_MIPI_REGMAP_PMU,
7a66647b	114	.resetn_val = EXYNOS4_MIPI_PHY_SRESETN,
cf09ee59	115	.resetn_reg = EXYNOS5420_MIPI_PHY_CONTROL(0),
71f5c63c MS	116	.resetn_map = EXYNOS_MIPI_REGMAP_PMU,
	117	}, {
	118	/* EXYNOS_MIPI_PHY_ID_DSIM0 */
	119	.coupled_phy_id = EXYNOS_MIPI_PHY_ID_CSIS0,
7a66647b	120	.enable_val = EXYNOS4_PHY_ENABLE,
cf09ee59	121	.enable_reg = EXYNOS5420_MIPI_PHY_CONTROL(0),
71f5c63c	122	.enable_map = EXYNOS_MIPI_REGMAP_PMU,
7a66647b	123	.resetn_val = EXYNOS4_MIPI_PHY_MRESETN,
cf09ee59	124	.resetn_reg = EXYNOS5420_MIPI_PHY_CONTROL(0),
71f5c63c MS	125	.resetn_map = EXYNOS_MIPI_REGMAP_PMU,
	126	}, {
	127	/* EXYNOS_MIPI_PHY_ID_CSIS1 */
	128	.coupled_phy_id = EXYNOS_MIPI_PHY_ID_DSIM1,
7a66647b	129	.enable_val = EXYNOS4_PHY_ENABLE,
cf09ee59	130	.enable_reg = EXYNOS5420_MIPI_PHY_CONTROL(1),
71f5c63c	131	.enable_map = EXYNOS_MIPI_REGMAP_PMU,
7a66647b	132	.resetn_val = EXYNOS4_MIPI_PHY_SRESETN,
cf09ee59	133	.resetn_reg = EXYNOS5420_MIPI_PHY_CONTROL(1),
71f5c63c MS	134	.resetn_map = EXYNOS_MIPI_REGMAP_PMU,
	135	}, {
	136	/* EXYNOS_MIPI_PHY_ID_DSIM1 */
	137	.coupled_phy_id = EXYNOS_MIPI_PHY_ID_CSIS1,
7a66647b	138	.enable_val = EXYNOS4_PHY_ENABLE,
cf09ee59	139	.enable_reg = EXYNOS5420_MIPI_PHY_CONTROL(1),
71f5c63c	140	.enable_map = EXYNOS_MIPI_REGMAP_PMU,
7a66647b	141	.resetn_val = EXYNOS4_MIPI_PHY_MRESETN,
cf09ee59	142	.resetn_reg = EXYNOS5420_MIPI_PHY_CONTROL(1),
71f5c63c MS	143	.resetn_map = EXYNOS_MIPI_REGMAP_PMU,
	144	}, {
	145	/* EXYNOS_MIPI_PHY_ID_CSIS2 */
	146	.coupled_phy_id = EXYNOS_MIPI_PHY_ID_NONE,
7a66647b	147	.enable_val = EXYNOS4_PHY_ENABLE,
cf09ee59	148	.enable_reg = EXYNOS5420_MIPI_PHY_CONTROL(2),
71f5c63c	149	.enable_map = EXYNOS_MIPI_REGMAP_PMU,
7a66647b	150	.resetn_val = EXYNOS4_MIPI_PHY_SRESETN,
cf09ee59	151	.resetn_reg = EXYNOS5420_MIPI_PHY_CONTROL(2),
71f5c63c MS	152	.resetn_map = EXYNOS_MIPI_REGMAP_PMU,
	153	},
	154	},
	155	};
	156
	157	#define EXYNOS5433_SYSREG_DISP_MIPI_PHY 0x100C
	158	#define EXYNOS5433_SYSREG_CAM0_MIPI_DPHY_CON 0x1014
	159	#define EXYNOS5433_SYSREG_CAM1_MIPI_DPHY_CON 0x1020
	160
	161	static const struct mipi_phy_device_desc exynos5433_mipi_phy = {
	162	.num_regmaps = 4,
	163	.regmap_names = {
	164	"samsung,pmu-syscon",
	165	"samsung,disp-sysreg",
	166	"samsung,cam0-sysreg",
	167	"samsung,cam1-sysreg"
	168	},
	169	.num_phys = 5,
	170	.phys = {
	171	{
	172	/* EXYNOS_MIPI_PHY_ID_CSIS0 */
	173	.coupled_phy_id = EXYNOS_MIPI_PHY_ID_DSIM0,
7a66647b	174	.enable_val = EXYNOS4_PHY_ENABLE,
5812f010	175	.enable_reg = EXYNOS4_MIPI_PHY_CONTROL(0),
71f5c63c MS	176	.enable_map = EXYNOS_MIPI_REGMAP_PMU,
	177	.resetn_val = BIT(0),
	178	.resetn_reg = EXYNOS5433_SYSREG_CAM0_MIPI_DPHY_CON,
	179	.resetn_map = EXYNOS_MIPI_REGMAP_CAM0,
	180	}, {
	181	/* EXYNOS_MIPI_PHY_ID_DSIM0 */
	182	.coupled_phy_id = EXYNOS_MIPI_PHY_ID_CSIS0,
7a66647b	183	.enable_val = EXYNOS4_PHY_ENABLE,
5812f010	184	.enable_reg = EXYNOS4_MIPI_PHY_CONTROL(0),
71f5c63c MS	185	.enable_map = EXYNOS_MIPI_REGMAP_PMU,
	186	.resetn_val = BIT(0),
	187	.resetn_reg = EXYNOS5433_SYSREG_DISP_MIPI_PHY,
	188	.resetn_map = EXYNOS_MIPI_REGMAP_DISP,
	189	}, {
	190	/* EXYNOS_MIPI_PHY_ID_CSIS1 */
	191	.coupled_phy_id = EXYNOS_MIPI_PHY_ID_NONE,
7a66647b	192	.enable_val = EXYNOS4_PHY_ENABLE,
5812f010	193	.enable_reg = EXYNOS4_MIPI_PHY_CONTROL(1),
71f5c63c MS	194	.enable_map = EXYNOS_MIPI_REGMAP_PMU,
	195	.resetn_val = BIT(1),
	196	.resetn_reg = EXYNOS5433_SYSREG_CAM0_MIPI_DPHY_CON,
	197	.resetn_map = EXYNOS_MIPI_REGMAP_CAM0,
	198	}, {
	199	/* EXYNOS_MIPI_PHY_ID_DSIM1 */
	200	.coupled_phy_id = EXYNOS_MIPI_PHY_ID_NONE,
7a66647b	201	.enable_val = EXYNOS4_PHY_ENABLE,
5812f010	202	.enable_reg = EXYNOS4_MIPI_PHY_CONTROL(1),
71f5c63c MS	203	.enable_map = EXYNOS_MIPI_REGMAP_PMU,
	204	.resetn_val = BIT(1),
	205	.resetn_reg = EXYNOS5433_SYSREG_DISP_MIPI_PHY,
	206	.resetn_map = EXYNOS_MIPI_REGMAP_DISP,
	207	}, {
	208	/* EXYNOS_MIPI_PHY_ID_CSIS2 */
	209	.coupled_phy_id = EXYNOS_MIPI_PHY_ID_NONE,
7a66647b	210	.enable_val = EXYNOS4_PHY_ENABLE,
5812f010	211	.enable_reg = EXYNOS4_MIPI_PHY_CONTROL(2),
71f5c63c MS	212	.enable_map = EXYNOS_MIPI_REGMAP_PMU,
	213	.resetn_val = BIT(0),
	214	.resetn_reg = EXYNOS5433_SYSREG_CAM1_MIPI_DPHY_CON,
	215	.resetn_map = EXYNOS_MIPI_REGMAP_CAM1,
	216	},
	217	},
	218	};
069d2e26 SN	219
069d2e26 SN	220	struct exynos_mipi_video_phy {
97a3042f MS	221	struct regmap *regmaps[EXYNOS_MIPI_REGMAPS_NUM];
97a3042f MS	222	int num_phys;
069d2e26 SN	223	struct video_phy_desc {
	224	struct phy *phy;
	225	unsigned int index;
97a3042f	226	const struct exynos_mipi_phy_desc *data;
069d2e26	227	} phys[EXYNOS_MIPI_PHYS_NUM];
e4b3d380	228	spinlock_t slock;
069d2e26 SN	229	};
069d2e26 SN	230
97a3042f MS	231	static int __set_phy_state(const struct exynos_mipi_phy_desc *data,
	232	struct exynos_mipi_video_phy *state, unsigned int on)
	233	{
	234	u32 val;
e4b3d380	235
af69decc AL	236	spin_lock(&state->slock);
af69decc AL	237
97a3042f MS	238	/* disable in PMU sysreg */
97a3042f MS	239	if (!on && data->coupled_phy_id >= 0 &&
b3e78cbc	240	state->phys[data->coupled_phy_id].phy->power_count == 0) {
97a3042f MS	241	regmap_read(state->regmaps[data->enable_map], data->enable_reg,
	242	&val);
	243	val &= ~data->enable_val;
	244	regmap_write(state->regmaps[data->enable_map], data->enable_reg,
	245	val);
	246	}
	247
	248	/* PHY reset */
	249	regmap_read(state->regmaps[data->resetn_map], data->resetn_reg, &val);
	250	val = on ? (val \| data->resetn_val) : (val & ~data->resetn_val);
	251	regmap_write(state->regmaps[data->resetn_map], data->resetn_reg, val);
	252
	253	/* enable in PMU sysreg */
	254	if (on) {
	255	regmap_read(state->regmaps[data->enable_map], data->enable_reg,
	256	&val);
	257	val \|= data->enable_val;
	258	regmap_write(state->regmaps[data->enable_map], data->enable_reg,
	259	val);
	260	}
069d2e26	261
af69decc	262	spin_unlock(&state->slock);
97a3042f	263
069d2e26 SN	264	return 0;
	265	}
	266
	267	#define to_mipi_video_phy(desc) \
97a3042f	268	container_of((desc), struct exynos_mipi_video_phy, phys[(desc)->index])
069d2e26 SN	269
	270	static int exynos_mipi_video_phy_power_on(struct phy *phy)
	271	{
	272	struct video_phy_desc *phy_desc = phy_get_drvdata(phy);
	273	struct exynos_mipi_video_phy *state = to_mipi_video_phy(phy_desc);
	274
97a3042f	275	return __set_phy_state(phy_desc->data, state, 1);
069d2e26 SN	276	}
	277
	278	static int exynos_mipi_video_phy_power_off(struct phy *phy)
	279	{
	280	struct video_phy_desc *phy_desc = phy_get_drvdata(phy);
	281	struct exynos_mipi_video_phy *state = to_mipi_video_phy(phy_desc);
	282
97a3042f	283	return __set_phy_state(phy_desc->data, state, 0);
069d2e26 SN	284	}
	285
	286	static struct phy exynos_mipi_video_phy_xlate(struct device dev,
	287	struct of_phandle_args *args)
	288	{
	289	struct exynos_mipi_video_phy *state = dev_get_drvdata(dev);
	290
97a3042f	291	if (WARN_ON(args->args[0] >= state->num_phys))
069d2e26 SN	292	return ERR_PTR(-ENODEV);
	293
	294	return state->phys[args->args[0]].phy;
	295	}
	296
4a9e5ca1	297	static const struct phy_ops exynos_mipi_video_phy_ops = {
069d2e26 SN	298	.power_on = exynos_mipi_video_phy_power_on,
	299	.power_off = exynos_mipi_video_phy_power_off,
	300	.owner = THIS_MODULE,
	301	};
	302
	303	static int exynos_mipi_video_phy_probe(struct platform_device *pdev)
	304	{
97a3042f	305	const struct mipi_phy_device_desc *phy_dev;
069d2e26 SN	306	struct exynos_mipi_video_phy *state;
069d2e26 SN	307	struct device *dev = &pdev->dev;
97a3042f	308	struct device_node *np = dev->of_node;
069d2e26 SN	309	struct phy_provider *phy_provider;
	310	unsigned int i;
	311
97a3042f MS	312	phy_dev = of_device_get_match_data(dev);
	313	if (!phy_dev)
	314	return -ENODEV;
	315
069d2e26 SN	316	state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL);
	317	if (!state)
	318	return -ENOMEM;
	319
97a3042f MS	320	for (i = 0; i < phy_dev->num_regmaps; i++) {
	321	state->regmaps[i] = syscon_regmap_lookup_by_phandle(np,
	322	phy_dev->regmap_names[i]);
	323	if (IS_ERR(state->regmaps[i]))
	324	return PTR_ERR(state->regmaps[i]);
	325	}
	326	state->num_phys = phy_dev->num_phys;
	327	spin_lock_init(&state->slock);
069d2e26 SN	328
069d2e26 SN	329	dev_set_drvdata(dev, state);
069d2e26	330
97a3042f	331	for (i = 0; i < state->num_phys; i++) {
f0ed8176	332	struct phy *phy = devm_phy_create(dev, NULL,
dbc98635	333	&exynos_mipi_video_phy_ops);
069d2e26 SN	334	if (IS_ERR(phy)) {
	335	dev_err(dev, "failed to create PHY %d\n", i);
	336	return PTR_ERR(phy);
	337	}
	338
	339	state->phys[i].phy = phy;
	340	state->phys[i].index = i;
97a3042f	341	state->phys[i].data = &phy_dev->phys[i];
069d2e26 SN	342	phy_set_drvdata(phy, &state->phys[i]);
	343	}
	344
64fe1891 KVA	345	phy_provider = devm_of_phy_provider_register(dev,
64fe1891 KVA	346	exynos_mipi_video_phy_xlate);
64fe1891	347
22fda307	348	return PTR_ERR_OR_ZERO(phy_provider);
069d2e26 SN	349	}
	350
	351	static const struct of_device_id exynos_mipi_video_phy_of_match[] = {
97a3042f MS	352	{
	353	.compatible = "samsung,s5pv210-mipi-video-phy",
	354	.data = &s5pv210_mipi_phy,
71f5c63c MS	355	}, {
	356	.compatible = "samsung,exynos5420-mipi-video-phy",
	357	.data = &exynos5420_mipi_phy,
	358	}, {
	359	.compatible = "samsung,exynos5433-mipi-video-phy",
	360	.data = &exynos5433_mipi_phy,
97a3042f MS	361	},
97a3042f MS	362	{ /* sentinel */ },
069d2e26 SN	363	};
	364	MODULE_DEVICE_TABLE(of, exynos_mipi_video_phy_of_match);
	365
	366	static struct platform_driver exynos_mipi_video_phy_driver = {
	367	.probe = exynos_mipi_video_phy_probe,
	368	.driver = {
	369	.of_match_table = exynos_mipi_video_phy_of_match,
	370	.name = "exynos-mipi-video-phy",
069d2e26 SN	371	}
	372	};
	373	module_platform_driver(exynos_mipi_video_phy_driver);
	374
	375	MODULE_DESCRIPTION("Samsung S5P/EXYNOS SoC MIPI CSI-2/DSI PHY driver");
	376	MODULE_AUTHOR("Sylwester Nawrocki <s.nawrocki@samsung.com>");
	377	MODULE_LICENSE("GPL v2");