[mirror_ubuntu-artful-kernel.git] / drivers / phy / phy-qcom-ufs-i.h

/*
 * Copyright (c) 2013-2015, Linux Foundation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * only version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */

#ifndef UFS_QCOM_PHY_I_H_
#define UFS_QCOM_PHY_I_H_

#include <linux/module.h>
#include <linux/clk.h>
#include <linux/regulator/consumer.h>
#include <linux/slab.h>
#include <linux/phy/phy-qcom-ufs.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/delay.h>

#define readl_poll_timeout(addr, val, cond, sleep_us, timeout_us) \
({ \
	ktime_t timeout = ktime_add_us(ktime_get(), timeout_us); \
	might_sleep_if(timeout_us); \
	for (;;) { \
		(val) = readl(addr); \
		if (cond) \
			break; \
		if (timeout_us && ktime_compare(ktime_get(), timeout) > 0) { \
			(val) = readl(addr); \
			break; \
		} \
		if (sleep_us) \
			usleep_range(DIV_ROUND_UP(sleep_us, 4), sleep_us); \
	} \
	(cond) ? 0 : -ETIMEDOUT; \
})

#define UFS_QCOM_PHY_CAL_ENTRY(reg, val)	\
	{				\
		.reg_offset = reg,	\
		.cfg_value = val,	\
	}

#define UFS_QCOM_PHY_NAME_LEN	30

enum {
	MASK_SERDES_START       = 0x1,
	MASK_PCS_READY          = 0x1,
};

enum {
	OFFSET_SERDES_START     = 0x0,
};

struct ufs_qcom_phy_stored_attributes {
	u32 att;
	u32 value;
};


struct ufs_qcom_phy_calibration {
	u32 reg_offset;
	u32 cfg_value;
};

struct ufs_qcom_phy_vreg {
	const char *name;
	struct regulator *reg;
	int max_uA;
	int min_uV;
	int max_uV;
	bool enabled;
};

struct ufs_qcom_phy {
	struct list_head list;
	struct device *dev;
	void __iomem *mmio;
	void __iomem *dev_ref_clk_ctrl_mmio;
	struct clk *tx_iface_clk;
	struct clk *rx_iface_clk;
	bool is_iface_clk_enabled;
	struct clk *ref_clk_src;
	struct clk *ref_clk_parent;
	struct clk *ref_clk;
	bool is_ref_clk_enabled;
	bool is_dev_ref_clk_enabled;
	struct ufs_qcom_phy_vreg vdda_pll;
	struct ufs_qcom_phy_vreg vdda_phy;
	struct ufs_qcom_phy_vreg vddp_ref_clk;
	unsigned int quirks;

	/*
	* If UFS link is put into Hibern8 and if UFS PHY analog hardware is
	* power collapsed (by clearing UFS_PHY_POWER_DOWN_CONTROL), Hibern8
	* exit might fail even after powering on UFS PHY analog hardware.
	* Enabling this quirk will help to solve above issue by doing
	* custom PHY settings just before PHY analog power collapse.
	*/
	#define UFS_QCOM_PHY_QUIRK_HIBERN8_EXIT_AFTER_PHY_PWR_COLLAPSE	BIT(0)

	u8 host_ctrl_rev_major;
	u16 host_ctrl_rev_minor;
	u16 host_ctrl_rev_step;

	char name[UFS_QCOM_PHY_NAME_LEN];
	struct ufs_qcom_phy_calibration *cached_regs;
	int cached_regs_table_size;
	bool is_powered_on;
	struct ufs_qcom_phy_specific_ops *phy_spec_ops;
};

/**
 * struct ufs_qcom_phy_specific_ops - set of pointers to functions which have a
 * specific implementation per phy. Each UFS phy, should implement
 * those functions according to its spec and requirements
 * @calibrate_phy: pointer to a function that calibrate the phy
 * @start_serdes: pointer to a function that starts the serdes
 * @is_physical_coding_sublayer_ready: pointer to a function that
 * checks pcs readiness. returns 0 for success and non-zero for error.
 * @set_tx_lane_enable: pointer to a function that enable tx lanes
 * @power_control: pointer to a function that controls analog rail of phy
 * and writes to QSERDES_RX_SIGDET_CNTRL attribute
 */
struct ufs_qcom_phy_specific_ops {
	int (*calibrate_phy)(struct ufs_qcom_phy *phy, bool is_rate_B);
	void (*start_serdes)(struct ufs_qcom_phy *phy);
	int (*is_physical_coding_sublayer_ready)(struct ufs_qcom_phy *phy);
	void (*set_tx_lane_enable)(struct ufs_qcom_phy *phy, u32 val);
	void (*power_control)(struct ufs_qcom_phy *phy, bool val);
};

struct ufs_qcom_phy *get_ufs_qcom_phy(struct phy *generic_phy);
int ufs_qcom_phy_power_on(struct phy *generic_phy);
int ufs_qcom_phy_power_off(struct phy *generic_phy);
int ufs_qcom_phy_init_clks(struct ufs_qcom_phy *phy_common);
int ufs_qcom_phy_init_vregulators(struct ufs_qcom_phy *phy_common);
int ufs_qcom_phy_remove(struct phy *generic_phy,
		       struct ufs_qcom_phy *ufs_qcom_phy);
struct phy *ufs_qcom_phy_generic_probe(struct platform_device *pdev,
			struct ufs_qcom_phy *common_cfg,
			const struct phy_ops *ufs_qcom_phy_gen_ops,
			struct ufs_qcom_phy_specific_ops *phy_spec_ops);
int ufs_qcom_phy_calibrate(struct ufs_qcom_phy *ufs_qcom_phy,
			struct ufs_qcom_phy_calibration *tbl_A, int tbl_size_A,
			struct ufs_qcom_phy_calibration *tbl_B, int tbl_size_B,
			bool is_rate_B);
#endif
Commit	Line	Data
adaafaa3 YG	1	/*
	2	* Copyright (c) 2013-2015, Linux Foundation. All rights reserved.
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 and
	6	* only version 2 as published by the Free Software Foundation.
	7	*
	8	* This program is distributed in the hope that it will be useful,
	9	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	10	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	11	* GNU General Public License for more details.
	12	*
	13	*/
	14
	15	#ifndef UFS_QCOM_PHY_I_H_
	16	#define UFS_QCOM_PHY_I_H_
	17
39e794bf	18	#include <linux/module.h>
adaafaa3	19	#include <linux/clk.h>
39e794bf	20	#include <linux/regulator/consumer.h>
adaafaa3	21	#include <linux/slab.h>
39e794bf	22	#include <linux/phy/phy-qcom-ufs.h>
adaafaa3 YG	23	#include <linux/platform_device.h>
	24	#include <linux/io.h>
	25	#include <linux/delay.h>
	26
39e794bf YG	27	#define readl_poll_timeout(addr, val, cond, sleep_us, timeout_us) \
	28	({ \
	29	ktime_t timeout = ktime_add_us(ktime_get(), timeout_us); \
	30	might_sleep_if(timeout_us); \
	31	for (;;) { \
	32	(val) = readl(addr); \
	33	if (cond) \
	34	break; \
	35	if (timeout_us && ktime_compare(ktime_get(), timeout) > 0) { \
	36	(val) = readl(addr); \
	37	break; \
	38	} \
	39	if (sleep_us) \
	40	usleep_range(DIV_ROUND_UP(sleep_us, 4), sleep_us); \
	41	} \
	42	(cond) ? 0 : -ETIMEDOUT; \
	43	})
	44
	45	#define UFS_QCOM_PHY_CAL_ENTRY(reg, val) \
	46	{ \
	47	.reg_offset = reg, \
	48	.cfg_value = val, \
	49	}
	50
adaafaa3 YG	51	#define UFS_QCOM_PHY_NAME_LEN 30
adaafaa3 YG	52
39e794bf YG	53	enum {
	54	MASK_SERDES_START = 0x1,
	55	MASK_PCS_READY = 0x1,
	56	};
	57
	58	enum {
	59	OFFSET_SERDES_START = 0x0,
	60	};
	61
	62	struct ufs_qcom_phy_stored_attributes {
	63	u32 att;
	64	u32 value;
	65	};
	66
	67
adaafaa3 YG	68	struct ufs_qcom_phy_calibration {
	69	u32 reg_offset;
	70	u32 cfg_value;
	71	};
	72
	73	struct ufs_qcom_phy_vreg {
	74	const char *name;
	75	struct regulator *reg;
	76	int max_uA;
	77	int min_uV;
	78	int max_uV;
	79	bool enabled;
adaafaa3 YG	80	};
	81
	82	struct ufs_qcom_phy {
	83	struct list_head list;
	84	struct device *dev;
	85	void __iomem *mmio;
	86	void __iomem *dev_ref_clk_ctrl_mmio;
	87	struct clk *tx_iface_clk;
	88	struct clk *rx_iface_clk;
	89	bool is_iface_clk_enabled;
	90	struct clk *ref_clk_src;
	91	struct clk *ref_clk_parent;
	92	struct clk *ref_clk;
	93	bool is_ref_clk_enabled;
	94	bool is_dev_ref_clk_enabled;
	95	struct ufs_qcom_phy_vreg vdda_pll;
	96	struct ufs_qcom_phy_vreg vdda_phy;
	97	struct ufs_qcom_phy_vreg vddp_ref_clk;
	98	unsigned int quirks;
	99
	100	/*
	101	* If UFS link is put into Hibern8 and if UFS PHY analog hardware is
	102	* power collapsed (by clearing UFS_PHY_POWER_DOWN_CONTROL), Hibern8
	103	* exit might fail even after powering on UFS PHY analog hardware.
	104	* Enabling this quirk will help to solve above issue by doing
	105	* custom PHY settings just before PHY analog power collapse.
	106	*/
	107	#define UFS_QCOM_PHY_QUIRK_HIBERN8_EXIT_AFTER_PHY_PWR_COLLAPSE BIT(0)
	108
	109	u8 host_ctrl_rev_major;
	110	u16 host_ctrl_rev_minor;
	111	u16 host_ctrl_rev_step;
	112
	113	char name[UFS_QCOM_PHY_NAME_LEN];
	114	struct ufs_qcom_phy_calibration *cached_regs;
	115	int cached_regs_table_size;
	116	bool is_powered_on;
	117	struct ufs_qcom_phy_specific_ops *phy_spec_ops;
	118	};
	119
	120	/**
	121	* struct ufs_qcom_phy_specific_ops - set of pointers to functions which have a
	122	* specific implementation per phy. Each UFS phy, should implement
	123	* those functions according to its spec and requirements
	124	* @calibrate_phy: pointer to a function that calibrate the phy
	125	* @start_serdes: pointer to a function that starts the serdes
	126	* @is_physical_coding_sublayer_ready: pointer to a function that
	127	* checks pcs readiness. returns 0 for success and non-zero for error.
	128	* @set_tx_lane_enable: pointer to a function that enable tx lanes
	129	* @power_control: pointer to a function that controls analog rail of phy
	130	* and writes to QSERDES_RX_SIGDET_CNTRL attribute
	131	*/
	132	struct ufs_qcom_phy_specific_ops {
	133	int (calibrate_phy)(struct ufs_qcom_phy phy, bool is_rate_B);
	134	void (start_serdes)(struct ufs_qcom_phy phy);
	135	int (is_physical_coding_sublayer_ready)(struct ufs_qcom_phy phy);
	136	void (set_tx_lane_enable)(struct ufs_qcom_phy phy, u32 val);
	137	void (power_control)(struct ufs_qcom_phy phy, bool val);
	138	};
	139
	140	struct ufs_qcom_phy get_ufs_qcom_phy(struct phy generic_phy);
	141	int ufs_qcom_phy_power_on(struct phy *generic_phy);
	142	int ufs_qcom_phy_power_off(struct phy *generic_phy);
89bd296b VG	143	int ufs_qcom_phy_init_clks(struct ufs_qcom_phy *phy_common);
89bd296b VG	144	int ufs_qcom_phy_init_vregulators(struct ufs_qcom_phy *phy_common);
adaafaa3 YG	145	int ufs_qcom_phy_remove(struct phy *generic_phy,
	146	struct ufs_qcom_phy *ufs_qcom_phy);
	147	struct phy ufs_qcom_phy_generic_probe(struct platform_device pdev,
	148	struct ufs_qcom_phy *common_cfg,
4a9e5ca1	149	const struct phy_ops *ufs_qcom_phy_gen_ops,
adaafaa3 YG	150	struct ufs_qcom_phy_specific_ops *phy_spec_ops);
	151	int ufs_qcom_phy_calibrate(struct ufs_qcom_phy *ufs_qcom_phy,
	152	struct ufs_qcom_phy_calibration *tbl_A, int tbl_size_A,
	153	struct ufs_qcom_phy_calibration *tbl_B, int tbl_size_B,
	154	bool is_rate_B);
	155	#endif