[mirror_ubuntu-zesty-kernel.git] / drivers / phy / phy-qcom-ufs-qmp-20nm.c

/*
 * Copyright (c) 2013-2015, Linux Foundation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * only version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */

#include "phy-qcom-ufs-qmp-20nm.h"

#define UFS_PHY_NAME "ufs_phy_qmp_20nm"

static
int ufs_qcom_phy_qmp_20nm_phy_calibrate(struct ufs_qcom_phy *ufs_qcom_phy,
					bool is_rate_B)
{
	struct ufs_qcom_phy_calibration *tbl_A, *tbl_B;
	int tbl_size_A, tbl_size_B;
	u8 major = ufs_qcom_phy->host_ctrl_rev_major;
	u16 minor = ufs_qcom_phy->host_ctrl_rev_minor;
	u16 step = ufs_qcom_phy->host_ctrl_rev_step;
	int err;

	if ((major == 0x1) && (minor == 0x002) && (step == 0x0000)) {
		tbl_size_A = ARRAY_SIZE(phy_cal_table_rate_A_1_2_0);
		tbl_A = phy_cal_table_rate_A_1_2_0;
	} else if ((major == 0x1) && (minor == 0x003) && (step == 0x0000)) {
		tbl_size_A = ARRAY_SIZE(phy_cal_table_rate_A_1_3_0);
		tbl_A = phy_cal_table_rate_A_1_3_0;
	} else {
		dev_err(ufs_qcom_phy->dev, "%s: Unknown UFS-PHY version, no calibration values\n",
			__func__);
		err = -ENODEV;
		goto out;
	}

	tbl_size_B = ARRAY_SIZE(phy_cal_table_rate_B);
	tbl_B = phy_cal_table_rate_B;

	err = ufs_qcom_phy_calibrate(ufs_qcom_phy, tbl_A, tbl_size_A,
						tbl_B, tbl_size_B, is_rate_B);

	if (err)
		dev_err(ufs_qcom_phy->dev, "%s: ufs_qcom_phy_calibrate() failed %d\n",
			__func__, err);

out:
	return err;
}

static
void ufs_qcom_phy_qmp_20nm_advertise_quirks(struct ufs_qcom_phy *phy_common)
{
	phy_common->quirks =
		UFS_QCOM_PHY_QUIRK_HIBERN8_EXIT_AFTER_PHY_PWR_COLLAPSE;
}

static int ufs_qcom_phy_qmp_20nm_init(struct phy *generic_phy)
{
	return 0;
}

static int ufs_qcom_phy_qmp_20nm_exit(struct phy *generic_phy)
{
	return 0;
}

static
void ufs_qcom_phy_qmp_20nm_power_control(struct ufs_qcom_phy *phy, bool val)
{
	bool hibern8_exit_after_pwr_collapse = phy->quirks &
		UFS_QCOM_PHY_QUIRK_HIBERN8_EXIT_AFTER_PHY_PWR_COLLAPSE;

	if (val) {
		writel_relaxed(0x1, phy->mmio + UFS_PHY_POWER_DOWN_CONTROL);
		/*
		 * Before any transactions involving PHY, ensure PHY knows
		 * that it's analog rail is powered ON.
		 */
		mb();

		if (hibern8_exit_after_pwr_collapse) {
			/*
			 * Give atleast 1us delay after restoring PHY analog
			 * power.
			 */
			usleep_range(1, 2);
			writel_relaxed(0x0A, phy->mmio +
				       QSERDES_COM_SYSCLK_EN_SEL_TXBAND);
			writel_relaxed(0x08, phy->mmio +
				       QSERDES_COM_SYSCLK_EN_SEL_TXBAND);
			/*
			 * Make sure workaround is deactivated before proceeding
			 * with normal PHY operations.
			 */
			mb();
		}
	} else {
		if (hibern8_exit_after_pwr_collapse) {
			writel_relaxed(0x0A, phy->mmio +
				       QSERDES_COM_SYSCLK_EN_SEL_TXBAND);
			writel_relaxed(0x02, phy->mmio +
				       QSERDES_COM_SYSCLK_EN_SEL_TXBAND);
			/*
			 * Make sure that above workaround is activated before
			 * PHY analog power collapse.
			 */
			mb();
		}

		writel_relaxed(0x0, phy->mmio + UFS_PHY_POWER_DOWN_CONTROL);
		/*
		 * ensure that PHY knows its PHY analog rail is going
		 * to be powered down
		 */
		mb();
	}
}

static
void ufs_qcom_phy_qmp_20nm_set_tx_lane_enable(struct ufs_qcom_phy *phy, u32 val)
{
	writel_relaxed(val & UFS_PHY_TX_LANE_ENABLE_MASK,
			phy->mmio + UFS_PHY_TX_LANE_ENABLE);
	mb();
}

static inline void ufs_qcom_phy_qmp_20nm_start_serdes(struct ufs_qcom_phy *phy)
{
	u32 tmp;

	tmp = readl_relaxed(phy->mmio + UFS_PHY_PHY_START);
	tmp &= ~MASK_SERDES_START;
	tmp |= (1 << OFFSET_SERDES_START);
	writel_relaxed(tmp, phy->mmio + UFS_PHY_PHY_START);
	mb();
}

static int ufs_qcom_phy_qmp_20nm_is_pcs_ready(struct ufs_qcom_phy *phy_common)
{
	int err = 0;
	u32 val;

	err = readl_poll_timeout(phy_common->mmio + UFS_PHY_PCS_READY_STATUS,
			val, (val & MASK_PCS_READY), 10, 1000000);
	if (err)
		dev_err(phy_common->dev, "%s: poll for pcs failed err = %d\n",
			__func__, err);
	return err;
}

static const struct phy_ops ufs_qcom_phy_qmp_20nm_phy_ops = {
	.init		= ufs_qcom_phy_qmp_20nm_init,
	.exit		= ufs_qcom_phy_qmp_20nm_exit,
	.power_on	= ufs_qcom_phy_power_on,
	.power_off	= ufs_qcom_phy_power_off,
	.owner		= THIS_MODULE,
};

static struct ufs_qcom_phy_specific_ops phy_20nm_ops = {
	.calibrate_phy		= ufs_qcom_phy_qmp_20nm_phy_calibrate,
	.start_serdes		= ufs_qcom_phy_qmp_20nm_start_serdes,
	.is_physical_coding_sublayer_ready = ufs_qcom_phy_qmp_20nm_is_pcs_ready,
	.set_tx_lane_enable	= ufs_qcom_phy_qmp_20nm_set_tx_lane_enable,
	.power_control		= ufs_qcom_phy_qmp_20nm_power_control,
};

static int ufs_qcom_phy_qmp_20nm_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct phy *generic_phy;
	struct ufs_qcom_phy_qmp_20nm *phy;
	struct ufs_qcom_phy *phy_common;
	int err = 0;

	phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
	if (!phy) {
		err = -ENOMEM;
		goto out;
	}
	phy_common = &phy->common_cfg;

	generic_phy = ufs_qcom_phy_generic_probe(pdev, phy_common,
				&ufs_qcom_phy_qmp_20nm_phy_ops, &phy_20nm_ops);

	if (!generic_phy) {
		dev_err(dev, "%s: ufs_qcom_phy_generic_probe() failed\n",
			__func__);
		err = -EIO;
		goto out;
	}

	err = ufs_qcom_phy_init_clks(phy_common);
	if (err) {
		dev_err(phy_common->dev, "%s: ufs_qcom_phy_init_clks() failed %d\n",
			__func__, err);
		goto out;
	}

	err = ufs_qcom_phy_init_vregulators(phy_common);
	if (err) {
		dev_err(phy_common->dev, "%s: ufs_qcom_phy_init_vregulators() failed %d\n",
			__func__, err);
		goto out;
	}

	ufs_qcom_phy_qmp_20nm_advertise_quirks(phy_common);

	phy_set_drvdata(generic_phy, phy);

	strlcpy(phy_common->name, UFS_PHY_NAME, sizeof(phy_common->name));

out:
	return err;
}

static const struct of_device_id ufs_qcom_phy_qmp_20nm_of_match[] = {
	{.compatible = "qcom,ufs-phy-qmp-20nm"},
	{},
};
MODULE_DEVICE_TABLE(of, ufs_qcom_phy_qmp_20nm_of_match);

static struct platform_driver ufs_qcom_phy_qmp_20nm_driver = {
	.probe = ufs_qcom_phy_qmp_20nm_probe,
	.driver = {
		.of_match_table = ufs_qcom_phy_qmp_20nm_of_match,
		.name = "ufs_qcom_phy_qmp_20nm",
	},
};

module_platform_driver(ufs_qcom_phy_qmp_20nm_driver);

MODULE_DESCRIPTION("Universal Flash Storage (UFS) QCOM PHY QMP 20nm");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
39e794bf YG	1	/*
	2	* Copyright (c) 2013-2015, Linux Foundation. All rights reserved.
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 and
	6	* only version 2 as published by the Free Software Foundation.
	7	*
	8	* This program is distributed in the hope that it will be useful,
	9	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	10	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	11	* GNU General Public License for more details.
	12	*
	13	*/
	14
	15	#include "phy-qcom-ufs-qmp-20nm.h"
	16
	17	#define UFS_PHY_NAME "ufs_phy_qmp_20nm"
	18
	19	static
	20	int ufs_qcom_phy_qmp_20nm_phy_calibrate(struct ufs_qcom_phy *ufs_qcom_phy,
	21	bool is_rate_B)
	22	{
	23	struct ufs_qcom_phy_calibration tbl_A, tbl_B;
	24	int tbl_size_A, tbl_size_B;
	25	u8 major = ufs_qcom_phy->host_ctrl_rev_major;
	26	u16 minor = ufs_qcom_phy->host_ctrl_rev_minor;
	27	u16 step = ufs_qcom_phy->host_ctrl_rev_step;
	28	int err;
	29
	30	if ((major == 0x1) && (minor == 0x002) && (step == 0x0000)) {
	31	tbl_size_A = ARRAY_SIZE(phy_cal_table_rate_A_1_2_0);
	32	tbl_A = phy_cal_table_rate_A_1_2_0;
	33	} else if ((major == 0x1) && (minor == 0x003) && (step == 0x0000)) {
	34	tbl_size_A = ARRAY_SIZE(phy_cal_table_rate_A_1_3_0);
	35	tbl_A = phy_cal_table_rate_A_1_3_0;
	36	} else {
	37	dev_err(ufs_qcom_phy->dev, "%s: Unknown UFS-PHY version, no calibration values\n",
	38	__func__);
	39	err = -ENODEV;
	40	goto out;
	41	}
	42
	43	tbl_size_B = ARRAY_SIZE(phy_cal_table_rate_B);
	44	tbl_B = phy_cal_table_rate_B;
	45
	46	err = ufs_qcom_phy_calibrate(ufs_qcom_phy, tbl_A, tbl_size_A,
	47	tbl_B, tbl_size_B, is_rate_B);
	48
	49	if (err)
	50	dev_err(ufs_qcom_phy->dev, "%s: ufs_qcom_phy_calibrate() failed %d\n",
	51	__func__, err);
	52
	53	out:
	54	return err;
	55	}
	56
	57	static
	58	void ufs_qcom_phy_qmp_20nm_advertise_quirks(struct ufs_qcom_phy *phy_common)
	59	{
	60	phy_common->quirks =
	61	UFS_QCOM_PHY_QUIRK_HIBERN8_EXIT_AFTER_PHY_PWR_COLLAPSE;
	62	}
	63
	64	static int ufs_qcom_phy_qmp_20nm_init(struct phy *generic_phy)
65	{
9c7ce698	66	return 0;
39e794bf YG	67	}
39e794bf YG	68
3d4640f1 VG	69	static int ufs_qcom_phy_qmp_20nm_exit(struct phy *generic_phy)
	70	{
	71	return 0;
	72	}
	73
39e794bf YG	74	static
	75	void ufs_qcom_phy_qmp_20nm_power_control(struct ufs_qcom_phy *phy, bool val)
	76	{
	77	bool hibern8_exit_after_pwr_collapse = phy->quirks &
	78	UFS_QCOM_PHY_QUIRK_HIBERN8_EXIT_AFTER_PHY_PWR_COLLAPSE;
	79
	80	if (val) {
	81	writel_relaxed(0x1, phy->mmio + UFS_PHY_POWER_DOWN_CONTROL);
	82	/*
	83	* Before any transactions involving PHY, ensure PHY knows
	84	* that it's analog rail is powered ON.
	85	*/
	86	mb();
	87
	88	if (hibern8_exit_after_pwr_collapse) {
	89	/*
	90	* Give atleast 1us delay after restoring PHY analog
	91	* power.
	92	*/
	93	usleep_range(1, 2);
	94	writel_relaxed(0x0A, phy->mmio +
	95	QSERDES_COM_SYSCLK_EN_SEL_TXBAND);
	96	writel_relaxed(0x08, phy->mmio +
	97	QSERDES_COM_SYSCLK_EN_SEL_TXBAND);
	98	/*
	99	* Make sure workaround is deactivated before proceeding
	100	* with normal PHY operations.
	101	*/
	102	mb();
	103	}
	104	} else {
	105	if (hibern8_exit_after_pwr_collapse) {
	106	writel_relaxed(0x0A, phy->mmio +
	107	QSERDES_COM_SYSCLK_EN_SEL_TXBAND);
	108	writel_relaxed(0x02, phy->mmio +
	109	QSERDES_COM_SYSCLK_EN_SEL_TXBAND);
	110	/*
	111	* Make sure that above workaround is activated before
	112	* PHY analog power collapse.
	113	*/
	114	mb();
	115	}
	116
	117	writel_relaxed(0x0, phy->mmio + UFS_PHY_POWER_DOWN_CONTROL);
	118	/*
	119	* ensure that PHY knows its PHY analog rail is going
	120	* to be powered down
	121	*/
	122	mb();
	123	}
	124	}
	125
	126	static
	127	void ufs_qcom_phy_qmp_20nm_set_tx_lane_enable(struct ufs_qcom_phy *phy, u32 val)
	128	{
	129	writel_relaxed(val & UFS_PHY_TX_LANE_ENABLE_MASK,
	130	phy->mmio + UFS_PHY_TX_LANE_ENABLE);
	131	mb();
	132	}
	133
	134	static inline void ufs_qcom_phy_qmp_20nm_start_serdes(struct ufs_qcom_phy *phy)
	135	{
	136	u32 tmp;
	137
138	tmp = readl_relaxed(phy->mmio + UFS_PHY_PHY_START);
139	tmp &= ~MASK_SERDES_START;
140	tmp \|= (1 << OFFSET_SERDES_START);
141	writel_relaxed(tmp, phy->mmio + UFS_PHY_PHY_START);
142	mb();
143	}
144
145	static int ufs_qcom_phy_qmp_20nm_is_pcs_ready(struct ufs_qcom_phy *phy_common)
146	{
147	int err = 0;
148	u32 val;
149
150	err = readl_poll_timeout(phy_common->mmio + UFS_PHY_PCS_READY_STATUS,
151	val, (val & MASK_PCS_READY), 10, 1000000);
152	if (err)
153	dev_err(phy_common->dev, "%s: poll for pcs failed err = %d\n",
154	__func__, err);
155	return err;
156	}
157
4a9e5ca1	158	static const struct phy_ops ufs_qcom_phy_qmp_20nm_phy_ops = {
39e794bf	159	.init = ufs_qcom_phy_qmp_20nm_init,
3d4640f1	160	.exit = ufs_qcom_phy_qmp_20nm_exit,
39e794bf YG	161	.power_on = ufs_qcom_phy_power_on,
	162	.power_off = ufs_qcom_phy_power_off,
	163	.owner = THIS_MODULE,
	164	};
	165
	166	static struct ufs_qcom_phy_specific_ops phy_20nm_ops = {
	167	.calibrate_phy = ufs_qcom_phy_qmp_20nm_phy_calibrate,
	168	.start_serdes = ufs_qcom_phy_qmp_20nm_start_serdes,
	169	.is_physical_coding_sublayer_ready = ufs_qcom_phy_qmp_20nm_is_pcs_ready,
	170	.set_tx_lane_enable = ufs_qcom_phy_qmp_20nm_set_tx_lane_enable,
	171	.power_control = ufs_qcom_phy_qmp_20nm_power_control,
	172	};
	173
	174	static int ufs_qcom_phy_qmp_20nm_probe(struct platform_device *pdev)
	175	{
	176	struct device *dev = &pdev->dev;
	177	struct phy *generic_phy;
	178	struct ufs_qcom_phy_qmp_20nm *phy;
9c7ce698	179	struct ufs_qcom_phy *phy_common;
39e794bf YG	180	int err = 0;
	181
	182	phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
	183	if (!phy) {
39e794bf YG	184	err = -ENOMEM;
	185	goto out;
	186	}
9c7ce698	187	phy_common = &phy->common_cfg;
39e794bf	188
9c7ce698	189	generic_phy = ufs_qcom_phy_generic_probe(pdev, phy_common,
39e794bf YG	190	&ufs_qcom_phy_qmp_20nm_phy_ops, &phy_20nm_ops);
	191
	192	if (!generic_phy) {
	193	dev_err(dev, "%s: ufs_qcom_phy_generic_probe() failed\n",
	194	__func__);
	195	err = -EIO;
	196	goto out;
	197	}
	198
9c7ce698 VG	199	err = ufs_qcom_phy_init_clks(phy_common);
	200	if (err) {
	201	dev_err(phy_common->dev, "%s: ufs_qcom_phy_init_clks() failed %d\n",
	202	__func__, err);
	203	goto out;
	204	}
	205
	206	err = ufs_qcom_phy_init_vregulators(phy_common);
	207	if (err) {
	208	dev_err(phy_common->dev, "%s: ufs_qcom_phy_init_vregulators() failed %d\n",
	209	__func__, err);
	210	goto out;
	211	}
	212
	213	ufs_qcom_phy_qmp_20nm_advertise_quirks(phy_common);
	214
39e794bf YG	215	phy_set_drvdata(generic_phy, phy);
39e794bf YG	216
9c7ce698	217	strlcpy(phy_common->name, UFS_PHY_NAME, sizeof(phy_common->name));
39e794bf YG	218
	219	out:
	220	return err;
	221	}
	222
39e794bf YG	223	static const struct of_device_id ufs_qcom_phy_qmp_20nm_of_match[] = {
	224	{.compatible = "qcom,ufs-phy-qmp-20nm"},
	225	{},
	226	};
	227	MODULE_DEVICE_TABLE(of, ufs_qcom_phy_qmp_20nm_of_match);
	228
	229	static struct platform_driver ufs_qcom_phy_qmp_20nm_driver = {
	230	.probe = ufs_qcom_phy_qmp_20nm_probe,
39e794bf YG	231	.driver = {
	232	.of_match_table = ufs_qcom_phy_qmp_20nm_of_match,
	233	.name = "ufs_qcom_phy_qmp_20nm",
39e794bf YG	234	},
	235	};
	236
	237	module_platform_driver(ufs_qcom_phy_qmp_20nm_driver);
	238
	239	MODULE_DESCRIPTION("Universal Flash Storage (UFS) QCOM PHY QMP 20nm");
	240	MODULE_LICENSE("GPL v2");