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c474a949 SL |
1 | /* |
2 | * Rockchip emmc PHY driver | |
3 | * | |
4 | * Copyright (C) 2016 Shawn Lin <shawn.lin@rock-chips.com> | |
5 | * Copyright (C) 2016 ROCKCHIP, Inc. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | */ | |
16 | ||
17 | #include <linux/delay.h> | |
18 | #include <linux/mfd/syscon.h> | |
19 | #include <linux/module.h> | |
20 | #include <linux/of.h> | |
21 | #include <linux/of_address.h> | |
22 | #include <linux/phy/phy.h> | |
23 | #include <linux/platform_device.h> | |
24 | #include <linux/regmap.h> | |
25 | ||
26 | /* | |
27 | * The higher 16-bit of this register is used for write protection | |
28 | * only if BIT(x + 16) set to 1 the BIT(x) can be written. | |
29 | */ | |
30 | #define HIWORD_UPDATE(val, mask, shift) \ | |
31 | ((val) << (shift) | (mask) << ((shift) + 16)) | |
32 | ||
33 | /* Register definition */ | |
34 | #define GRF_EMMCPHY_CON0 0x0 | |
35 | #define GRF_EMMCPHY_CON1 0x4 | |
36 | #define GRF_EMMCPHY_CON2 0x8 | |
37 | #define GRF_EMMCPHY_CON3 0xc | |
38 | #define GRF_EMMCPHY_CON4 0x10 | |
39 | #define GRF_EMMCPHY_CON5 0x14 | |
40 | #define GRF_EMMCPHY_CON6 0x18 | |
41 | #define GRF_EMMCPHY_STATUS 0x20 | |
42 | ||
43 | #define PHYCTRL_PDB_MASK 0x1 | |
44 | #define PHYCTRL_PDB_SHIFT 0x0 | |
45 | #define PHYCTRL_PDB_PWR_ON 0x1 | |
46 | #define PHYCTRL_PDB_PWR_OFF 0x0 | |
47 | #define PHYCTRL_ENDLL_MASK 0x1 | |
48 | #define PHYCTRL_ENDLL_SHIFT 0x1 | |
49 | #define PHYCTRL_ENDLL_ENABLE 0x1 | |
50 | #define PHYCTRL_ENDLL_DISABLE 0x0 | |
51 | #define PHYCTRL_CALDONE_MASK 0x1 | |
52 | #define PHYCTRL_CALDONE_SHIFT 0x6 | |
53 | #define PHYCTRL_CALDONE_DONE 0x1 | |
54 | #define PHYCTRL_CALDONE_GOING 0x0 | |
55 | #define PHYCTRL_DLLRDY_MASK 0x1 | |
56 | #define PHYCTRL_DLLRDY_SHIFT 0x5 | |
57 | #define PHYCTRL_DLLRDY_DONE 0x1 | |
58 | #define PHYCTRL_DLLRDY_GOING 0x0 | |
d7485772 SL |
59 | #define PHYCTRL_FREQSEL_200M 0x0 |
60 | #define PHYCTRL_FREQSEL_50M 0x1 | |
61 | #define PHYCTRL_FREQSEL_100M 0x2 | |
62 | #define PHYCTRL_FREQSEL_150M 0x3 | |
63 | #define PHYCTRL_FREQSEL_MASK 0x3 | |
64 | #define PHYCTRL_FREQSEL_SHIFT 0xc | |
65 | #define PHYCTRL_DR_MASK 0x7 | |
66 | #define PHYCTRL_DR_SHIFT 0x4 | |
67 | #define PHYCTRL_DR_50OHM 0x0 | |
68 | #define PHYCTRL_DR_33OHM 0x1 | |
69 | #define PHYCTRL_DR_66OHM 0x2 | |
70 | #define PHYCTRL_DR_100OHM 0x3 | |
71 | #define PHYCTRL_DR_40OHM 0x4 | |
36b5d460 BN |
72 | #define PHYCTRL_OTAPDLYENA 0x1 |
73 | #define PHYCTRL_OTAPDLYENA_MASK 0x1 | |
74 | #define PHYCTRL_OTAPDLYENA_SHIFT 0xb | |
75 | #define PHYCTRL_OTAPDLYSEL_MASK 0xf | |
76 | #define PHYCTRL_OTAPDLYSEL_SHIFT 0x7 | |
c474a949 SL |
77 | |
78 | struct rockchip_emmc_phy { | |
79 | unsigned int reg_offset; | |
80 | struct regmap *reg_base; | |
81 | }; | |
82 | ||
83 | static int rockchip_emmc_phy_power(struct rockchip_emmc_phy *rk_phy, | |
84 | bool on_off) | |
85 | { | |
86 | unsigned int caldone; | |
87 | unsigned int dllrdy; | |
88 | ||
89 | /* | |
90 | * Keep phyctrl_pdb and phyctrl_endll low to allow | |
91 | * initialization of CALIO state M/C DFFs | |
92 | */ | |
93 | regmap_write(rk_phy->reg_base, | |
94 | rk_phy->reg_offset + GRF_EMMCPHY_CON6, | |
95 | HIWORD_UPDATE(PHYCTRL_PDB_PWR_OFF, | |
96 | PHYCTRL_PDB_MASK, | |
97 | PHYCTRL_PDB_SHIFT)); | |
98 | regmap_write(rk_phy->reg_base, | |
99 | rk_phy->reg_offset + GRF_EMMCPHY_CON6, | |
100 | HIWORD_UPDATE(PHYCTRL_ENDLL_DISABLE, | |
101 | PHYCTRL_ENDLL_MASK, | |
102 | PHYCTRL_ENDLL_SHIFT)); | |
103 | ||
104 | /* Already finish power_off above */ | |
105 | if (on_off == PHYCTRL_PDB_PWR_OFF) | |
106 | return 0; | |
107 | ||
108 | /* | |
109 | * According to the user manual, calpad calibration | |
110 | * cycle takes more than 2us without the minimal recommended | |
111 | * value, so we may need a little margin here | |
112 | */ | |
113 | udelay(3); | |
114 | regmap_write(rk_phy->reg_base, | |
115 | rk_phy->reg_offset + GRF_EMMCPHY_CON6, | |
116 | HIWORD_UPDATE(PHYCTRL_PDB_PWR_ON, | |
117 | PHYCTRL_PDB_MASK, | |
118 | PHYCTRL_PDB_SHIFT)); | |
119 | ||
120 | /* | |
121 | * According to the user manual, it asks driver to | |
122 | * wait 5us for calpad busy trimming | |
123 | */ | |
124 | udelay(5); | |
125 | regmap_read(rk_phy->reg_base, | |
126 | rk_phy->reg_offset + GRF_EMMCPHY_STATUS, | |
127 | &caldone); | |
128 | caldone = (caldone >> PHYCTRL_CALDONE_SHIFT) & PHYCTRL_CALDONE_MASK; | |
129 | if (caldone != PHYCTRL_CALDONE_DONE) { | |
130 | pr_err("rockchip_emmc_phy_power: caldone timeout.\n"); | |
131 | return -ETIMEDOUT; | |
132 | } | |
133 | ||
134 | regmap_write(rk_phy->reg_base, | |
135 | rk_phy->reg_offset + GRF_EMMCPHY_CON6, | |
136 | HIWORD_UPDATE(PHYCTRL_ENDLL_ENABLE, | |
137 | PHYCTRL_ENDLL_MASK, | |
138 | PHYCTRL_ENDLL_SHIFT)); | |
139 | /* | |
4d54a25b SL |
140 | * After enable analog DLL circuits, we need an extra 10.2us |
141 | * for dll to be ready for work. But according to testing, we | |
142 | * find some chips need more than 25us. | |
c474a949 | 143 | */ |
4d54a25b | 144 | udelay(30); |
c474a949 SL |
145 | regmap_read(rk_phy->reg_base, |
146 | rk_phy->reg_offset + GRF_EMMCPHY_STATUS, | |
147 | &dllrdy); | |
148 | dllrdy = (dllrdy >> PHYCTRL_DLLRDY_SHIFT) & PHYCTRL_DLLRDY_MASK; | |
149 | if (dllrdy != PHYCTRL_DLLRDY_DONE) { | |
150 | pr_err("rockchip_emmc_phy_power: dllrdy timeout.\n"); | |
151 | return -ETIMEDOUT; | |
152 | } | |
153 | ||
154 | return 0; | |
155 | } | |
156 | ||
157 | static int rockchip_emmc_phy_power_off(struct phy *phy) | |
158 | { | |
159 | struct rockchip_emmc_phy *rk_phy = phy_get_drvdata(phy); | |
160 | int ret = 0; | |
161 | ||
162 | /* Power down emmc phy analog blocks */ | |
163 | ret = rockchip_emmc_phy_power(rk_phy, PHYCTRL_PDB_PWR_OFF); | |
164 | if (ret) | |
165 | return ret; | |
166 | ||
167 | return 0; | |
168 | } | |
169 | ||
170 | static int rockchip_emmc_phy_power_on(struct phy *phy) | |
171 | { | |
172 | struct rockchip_emmc_phy *rk_phy = phy_get_drvdata(phy); | |
173 | int ret = 0; | |
174 | ||
d7485772 SL |
175 | /* DLL operation: 200 MHz */ |
176 | regmap_write(rk_phy->reg_base, | |
177 | rk_phy->reg_offset + GRF_EMMCPHY_CON0, | |
178 | HIWORD_UPDATE(PHYCTRL_FREQSEL_200M, | |
179 | PHYCTRL_FREQSEL_MASK, | |
180 | PHYCTRL_FREQSEL_SHIFT)); | |
181 | ||
182 | /* Drive impedance: 50 Ohm */ | |
183 | regmap_write(rk_phy->reg_base, | |
184 | rk_phy->reg_offset + GRF_EMMCPHY_CON6, | |
185 | HIWORD_UPDATE(PHYCTRL_DR_50OHM, | |
186 | PHYCTRL_DR_MASK, | |
187 | PHYCTRL_DR_SHIFT)); | |
188 | ||
36b5d460 BN |
189 | /* Output tap delay: enable */ |
190 | regmap_write(rk_phy->reg_base, | |
191 | rk_phy->reg_offset + GRF_EMMCPHY_CON0, | |
192 | HIWORD_UPDATE(PHYCTRL_OTAPDLYENA, | |
193 | PHYCTRL_OTAPDLYENA_MASK, | |
194 | PHYCTRL_OTAPDLYENA_SHIFT)); | |
195 | ||
196 | /* Output tap delay */ | |
197 | regmap_write(rk_phy->reg_base, | |
198 | rk_phy->reg_offset + GRF_EMMCPHY_CON0, | |
199 | HIWORD_UPDATE(4, | |
200 | PHYCTRL_OTAPDLYSEL_MASK, | |
201 | PHYCTRL_OTAPDLYSEL_SHIFT)); | |
202 | ||
c474a949 SL |
203 | /* Power up emmc phy analog blocks */ |
204 | ret = rockchip_emmc_phy_power(rk_phy, PHYCTRL_PDB_PWR_ON); | |
205 | if (ret) | |
206 | return ret; | |
207 | ||
208 | return 0; | |
209 | } | |
210 | ||
211 | static const struct phy_ops ops = { | |
212 | .power_on = rockchip_emmc_phy_power_on, | |
213 | .power_off = rockchip_emmc_phy_power_off, | |
214 | .owner = THIS_MODULE, | |
215 | }; | |
216 | ||
217 | static int rockchip_emmc_phy_probe(struct platform_device *pdev) | |
218 | { | |
219 | struct device *dev = &pdev->dev; | |
220 | struct rockchip_emmc_phy *rk_phy; | |
221 | struct phy *generic_phy; | |
222 | struct phy_provider *phy_provider; | |
223 | struct regmap *grf; | |
224 | unsigned int reg_offset; | |
225 | ||
332184ad HS |
226 | if (!dev->parent || !dev->parent->of_node) |
227 | return -ENODEV; | |
228 | ||
229 | grf = syscon_node_to_regmap(dev->parent->of_node); | |
c474a949 SL |
230 | if (IS_ERR(grf)) { |
231 | dev_err(dev, "Missing rockchip,grf property\n"); | |
232 | return PTR_ERR(grf); | |
233 | } | |
234 | ||
235 | rk_phy = devm_kzalloc(dev, sizeof(*rk_phy), GFP_KERNEL); | |
236 | if (!rk_phy) | |
237 | return -ENOMEM; | |
238 | ||
239 | if (of_property_read_u32(dev->of_node, "reg", ®_offset)) { | |
240 | dev_err(dev, "missing reg property in node %s\n", | |
241 | dev->of_node->name); | |
242 | return -EINVAL; | |
243 | } | |
244 | ||
245 | rk_phy->reg_offset = reg_offset; | |
246 | rk_phy->reg_base = grf; | |
247 | ||
248 | generic_phy = devm_phy_create(dev, dev->of_node, &ops); | |
249 | if (IS_ERR(generic_phy)) { | |
250 | dev_err(dev, "failed to create PHY\n"); | |
251 | return PTR_ERR(generic_phy); | |
252 | } | |
253 | ||
254 | phy_set_drvdata(generic_phy, rk_phy); | |
255 | phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); | |
256 | ||
257 | return PTR_ERR_OR_ZERO(phy_provider); | |
258 | } | |
259 | ||
260 | static const struct of_device_id rockchip_emmc_phy_dt_ids[] = { | |
261 | { .compatible = "rockchip,rk3399-emmc-phy" }, | |
262 | {} | |
263 | }; | |
264 | ||
265 | MODULE_DEVICE_TABLE(of, rockchip_emmc_phy_dt_ids); | |
266 | ||
267 | static struct platform_driver rockchip_emmc_driver = { | |
268 | .probe = rockchip_emmc_phy_probe, | |
269 | .driver = { | |
270 | .name = "rockchip-emmc-phy", | |
271 | .of_match_table = rockchip_emmc_phy_dt_ids, | |
272 | }, | |
273 | }; | |
274 | ||
275 | module_platform_driver(rockchip_emmc_driver); | |
276 | ||
277 | MODULE_AUTHOR("Shawn Lin <shawn.lin@rock-chips.com>"); | |
278 | MODULE_DESCRIPTION("Rockchip EMMC PHY driver"); | |
279 | MODULE_LICENSE("GPL v2"); |