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c474a949 SL |
1 | /* |
2 | * Rockchip emmc PHY driver | |
3 | * | |
4 | * Copyright (C) 2016 Shawn Lin <shawn.lin@rock-chips.com> | |
5 | * Copyright (C) 2016 ROCKCHIP, Inc. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | */ | |
16 | ||
52c0624a | 17 | #include <linux/clk.h> |
c474a949 SL |
18 | #include <linux/delay.h> |
19 | #include <linux/mfd/syscon.h> | |
20 | #include <linux/module.h> | |
21 | #include <linux/of.h> | |
22 | #include <linux/of_address.h> | |
23 | #include <linux/phy/phy.h> | |
24 | #include <linux/platform_device.h> | |
25 | #include <linux/regmap.h> | |
26 | ||
27 | /* | |
28 | * The higher 16-bit of this register is used for write protection | |
29 | * only if BIT(x + 16) set to 1 the BIT(x) can be written. | |
30 | */ | |
31 | #define HIWORD_UPDATE(val, mask, shift) \ | |
32 | ((val) << (shift) | (mask) << ((shift) + 16)) | |
33 | ||
34 | /* Register definition */ | |
675f65c4 BN |
35 | #define GRF_EMMCPHY_CON0 0x0 |
36 | #define GRF_EMMCPHY_CON1 0x4 | |
37 | #define GRF_EMMCPHY_CON2 0x8 | |
38 | #define GRF_EMMCPHY_CON3 0xc | |
39 | #define GRF_EMMCPHY_CON4 0x10 | |
40 | #define GRF_EMMCPHY_CON5 0x14 | |
41 | #define GRF_EMMCPHY_CON6 0x18 | |
42 | #define GRF_EMMCPHY_STATUS 0x20 | |
c474a949 | 43 | |
675f65c4 BN |
44 | #define PHYCTRL_PDB_MASK 0x1 |
45 | #define PHYCTRL_PDB_SHIFT 0x0 | |
46 | #define PHYCTRL_PDB_PWR_ON 0x1 | |
47 | #define PHYCTRL_PDB_PWR_OFF 0x0 | |
48 | #define PHYCTRL_ENDLL_MASK 0x1 | |
49 | #define PHYCTRL_ENDLL_SHIFT 0x1 | |
50 | #define PHYCTRL_ENDLL_ENABLE 0x1 | |
51 | #define PHYCTRL_ENDLL_DISABLE 0x0 | |
52 | #define PHYCTRL_CALDONE_MASK 0x1 | |
53 | #define PHYCTRL_CALDONE_SHIFT 0x6 | |
54 | #define PHYCTRL_CALDONE_DONE 0x1 | |
55 | #define PHYCTRL_CALDONE_GOING 0x0 | |
56 | #define PHYCTRL_DLLRDY_MASK 0x1 | |
57 | #define PHYCTRL_DLLRDY_SHIFT 0x5 | |
58 | #define PHYCTRL_DLLRDY_DONE 0x1 | |
59 | #define PHYCTRL_DLLRDY_GOING 0x0 | |
60 | #define PHYCTRL_FREQSEL_200M 0x0 | |
61 | #define PHYCTRL_FREQSEL_50M 0x1 | |
62 | #define PHYCTRL_FREQSEL_100M 0x2 | |
63 | #define PHYCTRL_FREQSEL_150M 0x3 | |
64 | #define PHYCTRL_FREQSEL_MASK 0x3 | |
65 | #define PHYCTRL_FREQSEL_SHIFT 0xc | |
66 | #define PHYCTRL_DR_MASK 0x7 | |
67 | #define PHYCTRL_DR_SHIFT 0x4 | |
68 | #define PHYCTRL_DR_50OHM 0x0 | |
69 | #define PHYCTRL_DR_33OHM 0x1 | |
70 | #define PHYCTRL_DR_66OHM 0x2 | |
71 | #define PHYCTRL_DR_100OHM 0x3 | |
72 | #define PHYCTRL_DR_40OHM 0x4 | |
36b5d460 BN |
73 | #define PHYCTRL_OTAPDLYENA 0x1 |
74 | #define PHYCTRL_OTAPDLYENA_MASK 0x1 | |
75 | #define PHYCTRL_OTAPDLYENA_SHIFT 0xb | |
76 | #define PHYCTRL_OTAPDLYSEL_MASK 0xf | |
77 | #define PHYCTRL_OTAPDLYSEL_SHIFT 0x7 | |
c474a949 SL |
78 | |
79 | struct rockchip_emmc_phy { | |
80 | unsigned int reg_offset; | |
81 | struct regmap *reg_base; | |
52c0624a | 82 | struct clk *emmcclk; |
c474a949 SL |
83 | }; |
84 | ||
52c0624a | 85 | static int rockchip_emmc_phy_power(struct phy *phy, bool on_off) |
c474a949 | 86 | { |
52c0624a | 87 | struct rockchip_emmc_phy *rk_phy = phy_get_drvdata(phy); |
c474a949 SL |
88 | unsigned int caldone; |
89 | unsigned int dllrdy; | |
52c0624a | 90 | unsigned int freqsel = PHYCTRL_FREQSEL_200M; |
4e2ea670 | 91 | unsigned long rate; |
49f9ccd8 | 92 | unsigned long timeout; |
c474a949 | 93 | |
4e2ea670 DA |
94 | /* |
95 | * Keep phyctrl_pdb and phyctrl_endll low to allow | |
96 | * initialization of CALIO state M/C DFFs | |
97 | */ | |
98 | regmap_write(rk_phy->reg_base, | |
99 | rk_phy->reg_offset + GRF_EMMCPHY_CON6, | |
100 | HIWORD_UPDATE(PHYCTRL_PDB_PWR_OFF, | |
101 | PHYCTRL_PDB_MASK, | |
102 | PHYCTRL_PDB_SHIFT)); | |
103 | regmap_write(rk_phy->reg_base, | |
104 | rk_phy->reg_offset + GRF_EMMCPHY_CON6, | |
105 | HIWORD_UPDATE(PHYCTRL_ENDLL_DISABLE, | |
106 | PHYCTRL_ENDLL_MASK, | |
107 | PHYCTRL_ENDLL_SHIFT)); | |
108 | ||
109 | /* Already finish power_off above */ | |
110 | if (on_off == PHYCTRL_PDB_PWR_OFF) | |
111 | return 0; | |
112 | ||
113 | rate = clk_get_rate(rk_phy->emmcclk); | |
114 | ||
115 | if (rate != 0) { | |
52c0624a DA |
116 | unsigned long ideal_rate; |
117 | unsigned long diff; | |
118 | ||
119 | switch (rate) { | |
4e2ea670 | 120 | case 1 ... 74999999: |
52c0624a DA |
121 | ideal_rate = 50000000; |
122 | freqsel = PHYCTRL_FREQSEL_50M; | |
123 | break; | |
124 | case 75000000 ... 124999999: | |
125 | ideal_rate = 100000000; | |
126 | freqsel = PHYCTRL_FREQSEL_100M; | |
127 | break; | |
128 | case 125000000 ... 174999999: | |
129 | ideal_rate = 150000000; | |
130 | freqsel = PHYCTRL_FREQSEL_150M; | |
131 | break; | |
132 | default: | |
133 | ideal_rate = 200000000; | |
134 | break; | |
135 | }; | |
136 | ||
137 | diff = (rate > ideal_rate) ? | |
138 | rate - ideal_rate : ideal_rate - rate; | |
139 | ||
140 | /* | |
141 | * In order for tuning delays to be accurate we need to be | |
142 | * pretty spot on for the DLL range, so warn if we're too | |
143 | * far off. Also warn if we're above the 200 MHz max. Don't | |
144 | * warn for really slow rates since we won't be tuning then. | |
145 | */ | |
146 | if ((rate > 50000000 && diff > 15000000) || (rate > 200000000)) | |
147 | dev_warn(&phy->dev, "Unsupported rate: %lu\n", rate); | |
148 | } | |
149 | ||
c474a949 SL |
150 | /* |
151 | * According to the user manual, calpad calibration | |
152 | * cycle takes more than 2us without the minimal recommended | |
153 | * value, so we may need a little margin here | |
154 | */ | |
155 | udelay(3); | |
156 | regmap_write(rk_phy->reg_base, | |
157 | rk_phy->reg_offset + GRF_EMMCPHY_CON6, | |
158 | HIWORD_UPDATE(PHYCTRL_PDB_PWR_ON, | |
159 | PHYCTRL_PDB_MASK, | |
160 | PHYCTRL_PDB_SHIFT)); | |
161 | ||
162 | /* | |
163 | * According to the user manual, it asks driver to | |
164 | * wait 5us for calpad busy trimming | |
165 | */ | |
166 | udelay(5); | |
167 | regmap_read(rk_phy->reg_base, | |
168 | rk_phy->reg_offset + GRF_EMMCPHY_STATUS, | |
169 | &caldone); | |
170 | caldone = (caldone >> PHYCTRL_CALDONE_SHIFT) & PHYCTRL_CALDONE_MASK; | |
171 | if (caldone != PHYCTRL_CALDONE_DONE) { | |
172 | pr_err("rockchip_emmc_phy_power: caldone timeout.\n"); | |
173 | return -ETIMEDOUT; | |
174 | } | |
175 | ||
52c0624a DA |
176 | /* Set the frequency of the DLL operation */ |
177 | regmap_write(rk_phy->reg_base, | |
178 | rk_phy->reg_offset + GRF_EMMCPHY_CON0, | |
179 | HIWORD_UPDATE(freqsel, PHYCTRL_FREQSEL_MASK, | |
180 | PHYCTRL_FREQSEL_SHIFT)); | |
181 | ||
182 | /* Turn on the DLL */ | |
c474a949 SL |
183 | regmap_write(rk_phy->reg_base, |
184 | rk_phy->reg_offset + GRF_EMMCPHY_CON6, | |
185 | HIWORD_UPDATE(PHYCTRL_ENDLL_ENABLE, | |
186 | PHYCTRL_ENDLL_MASK, | |
187 | PHYCTRL_ENDLL_SHIFT)); | |
4e2ea670 DA |
188 | |
189 | /* | |
190 | * We turned on the DLL even though the rate was 0 because we the | |
191 | * clock might be turned on later. ...but we can't wait for the DLL | |
192 | * to lock when the rate is 0 because it will never lock with no | |
193 | * input clock. | |
194 | * | |
195 | * Technically we should be checking the lock later when the clock | |
196 | * is turned on, but for now we won't. | |
197 | */ | |
198 | if (rate == 0) | |
199 | return 0; | |
200 | ||
c474a949 | 201 | /* |
49f9ccd8 DA |
202 | * After enabling analog DLL circuits docs say that we need 10.2 us if |
203 | * our source clock is at 50 MHz and that lock time scales linearly | |
204 | * with clock speed. If we are powering on the PHY and the card clock | |
205 | * is super slow (like 100 kHZ) this could take as long as 5.1 ms as | |
206 | * per the math: 10.2 us * (50000000 Hz / 100000 Hz) => 5.1 ms | |
207 | * Hopefully we won't be running at 100 kHz, but we should still make | |
208 | * sure we wait long enough. | |
c474a949 | 209 | */ |
49f9ccd8 DA |
210 | timeout = jiffies + msecs_to_jiffies(10); |
211 | do { | |
212 | udelay(1); | |
213 | ||
214 | regmap_read(rk_phy->reg_base, | |
215 | rk_phy->reg_offset + GRF_EMMCPHY_STATUS, | |
216 | &dllrdy); | |
217 | dllrdy = (dllrdy >> PHYCTRL_DLLRDY_SHIFT) & PHYCTRL_DLLRDY_MASK; | |
218 | if (dllrdy == PHYCTRL_DLLRDY_DONE) | |
219 | break; | |
220 | } while (!time_after(jiffies, timeout)); | |
221 | ||
c474a949 SL |
222 | if (dllrdy != PHYCTRL_DLLRDY_DONE) { |
223 | pr_err("rockchip_emmc_phy_power: dllrdy timeout.\n"); | |
224 | return -ETIMEDOUT; | |
225 | } | |
226 | ||
227 | return 0; | |
228 | } | |
229 | ||
52c0624a DA |
230 | static int rockchip_emmc_phy_init(struct phy *phy) |
231 | { | |
232 | struct rockchip_emmc_phy *rk_phy = phy_get_drvdata(phy); | |
233 | int ret = 0; | |
234 | ||
235 | /* | |
236 | * We purposely get the clock here and not in probe to avoid the | |
237 | * circular dependency problem. We expect: | |
238 | * - PHY driver to probe | |
239 | * - SDHCI driver to start probe | |
240 | * - SDHCI driver to register it's clock | |
241 | * - SDHCI driver to get the PHY | |
242 | * - SDHCI driver to init the PHY | |
243 | * | |
244 | * The clock is optional, so upon any error we just set to NULL. | |
245 | * | |
246 | * NOTE: we don't do anything special for EPROBE_DEFER here. Given the | |
247 | * above expected use case, EPROBE_DEFER isn't sensible to expect, so | |
248 | * it's just like any other error. | |
249 | */ | |
250 | rk_phy->emmcclk = clk_get(&phy->dev, "emmcclk"); | |
251 | if (IS_ERR(rk_phy->emmcclk)) { | |
252 | dev_dbg(&phy->dev, "Error getting emmcclk: %d\n", ret); | |
253 | rk_phy->emmcclk = NULL; | |
254 | } | |
255 | ||
256 | return ret; | |
257 | } | |
258 | ||
259 | static int rockchip_emmc_phy_exit(struct phy *phy) | |
c474a949 SL |
260 | { |
261 | struct rockchip_emmc_phy *rk_phy = phy_get_drvdata(phy); | |
c474a949 | 262 | |
52c0624a DA |
263 | clk_put(rk_phy->emmcclk); |
264 | ||
265 | return 0; | |
266 | } | |
267 | ||
268 | static int rockchip_emmc_phy_power_off(struct phy *phy) | |
269 | { | |
c474a949 | 270 | /* Power down emmc phy analog blocks */ |
52c0624a | 271 | return rockchip_emmc_phy_power(phy, PHYCTRL_PDB_PWR_OFF); |
c474a949 SL |
272 | } |
273 | ||
274 | static int rockchip_emmc_phy_power_on(struct phy *phy) | |
275 | { | |
276 | struct rockchip_emmc_phy *rk_phy = phy_get_drvdata(phy); | |
c474a949 | 277 | |
d7485772 SL |
278 | /* Drive impedance: 50 Ohm */ |
279 | regmap_write(rk_phy->reg_base, | |
280 | rk_phy->reg_offset + GRF_EMMCPHY_CON6, | |
281 | HIWORD_UPDATE(PHYCTRL_DR_50OHM, | |
282 | PHYCTRL_DR_MASK, | |
283 | PHYCTRL_DR_SHIFT)); | |
284 | ||
36b5d460 BN |
285 | /* Output tap delay: enable */ |
286 | regmap_write(rk_phy->reg_base, | |
287 | rk_phy->reg_offset + GRF_EMMCPHY_CON0, | |
288 | HIWORD_UPDATE(PHYCTRL_OTAPDLYENA, | |
289 | PHYCTRL_OTAPDLYENA_MASK, | |
290 | PHYCTRL_OTAPDLYENA_SHIFT)); | |
291 | ||
292 | /* Output tap delay */ | |
293 | regmap_write(rk_phy->reg_base, | |
294 | rk_phy->reg_offset + GRF_EMMCPHY_CON0, | |
295 | HIWORD_UPDATE(4, | |
296 | PHYCTRL_OTAPDLYSEL_MASK, | |
297 | PHYCTRL_OTAPDLYSEL_SHIFT)); | |
298 | ||
c474a949 | 299 | /* Power up emmc phy analog blocks */ |
52c0624a | 300 | return rockchip_emmc_phy_power(phy, PHYCTRL_PDB_PWR_ON); |
c474a949 SL |
301 | } |
302 | ||
303 | static const struct phy_ops ops = { | |
52c0624a DA |
304 | .init = rockchip_emmc_phy_init, |
305 | .exit = rockchip_emmc_phy_exit, | |
c474a949 SL |
306 | .power_on = rockchip_emmc_phy_power_on, |
307 | .power_off = rockchip_emmc_phy_power_off, | |
308 | .owner = THIS_MODULE, | |
309 | }; | |
310 | ||
311 | static int rockchip_emmc_phy_probe(struct platform_device *pdev) | |
312 | { | |
313 | struct device *dev = &pdev->dev; | |
314 | struct rockchip_emmc_phy *rk_phy; | |
315 | struct phy *generic_phy; | |
316 | struct phy_provider *phy_provider; | |
317 | struct regmap *grf; | |
318 | unsigned int reg_offset; | |
319 | ||
332184ad HS |
320 | if (!dev->parent || !dev->parent->of_node) |
321 | return -ENODEV; | |
322 | ||
323 | grf = syscon_node_to_regmap(dev->parent->of_node); | |
c474a949 SL |
324 | if (IS_ERR(grf)) { |
325 | dev_err(dev, "Missing rockchip,grf property\n"); | |
326 | return PTR_ERR(grf); | |
327 | } | |
328 | ||
329 | rk_phy = devm_kzalloc(dev, sizeof(*rk_phy), GFP_KERNEL); | |
330 | if (!rk_phy) | |
331 | return -ENOMEM; | |
332 | ||
333 | if (of_property_read_u32(dev->of_node, "reg", ®_offset)) { | |
334 | dev_err(dev, "missing reg property in node %s\n", | |
335 | dev->of_node->name); | |
336 | return -EINVAL; | |
337 | } | |
338 | ||
339 | rk_phy->reg_offset = reg_offset; | |
340 | rk_phy->reg_base = grf; | |
341 | ||
342 | generic_phy = devm_phy_create(dev, dev->of_node, &ops); | |
343 | if (IS_ERR(generic_phy)) { | |
344 | dev_err(dev, "failed to create PHY\n"); | |
345 | return PTR_ERR(generic_phy); | |
346 | } | |
347 | ||
348 | phy_set_drvdata(generic_phy, rk_phy); | |
349 | phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); | |
350 | ||
351 | return PTR_ERR_OR_ZERO(phy_provider); | |
352 | } | |
353 | ||
354 | static const struct of_device_id rockchip_emmc_phy_dt_ids[] = { | |
355 | { .compatible = "rockchip,rk3399-emmc-phy" }, | |
356 | {} | |
357 | }; | |
358 | ||
359 | MODULE_DEVICE_TABLE(of, rockchip_emmc_phy_dt_ids); | |
360 | ||
361 | static struct platform_driver rockchip_emmc_driver = { | |
362 | .probe = rockchip_emmc_phy_probe, | |
363 | .driver = { | |
364 | .name = "rockchip-emmc-phy", | |
365 | .of_match_table = rockchip_emmc_phy_dt_ids, | |
366 | }, | |
367 | }; | |
368 | ||
369 | module_platform_driver(rockchip_emmc_driver); | |
370 | ||
371 | MODULE_AUTHOR("Shawn Lin <shawn.lin@rock-chips.com>"); | |
372 | MODULE_DESCRIPTION("Rockchip EMMC PHY driver"); | |
373 | MODULE_LICENSE("GPL v2"); |