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Commit | Line | Data |
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57f6ce07 | 1 | /* |
a70143bb | 2 | * phy-ti-pipe3 - PIPE3 PHY driver. |
57f6ce07 KVA |
3 | * |
4 | * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; either version 2 of the License, or | |
8 | * (at your option) any later version. | |
9 | * | |
10 | * Author: Kishon Vijay Abraham I <kishon@ti.com> | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | */ | |
18 | ||
19 | #include <linux/module.h> | |
20 | #include <linux/platform_device.h> | |
21 | #include <linux/slab.h> | |
a70143bb | 22 | #include <linux/phy/phy.h> |
57f6ce07 KVA |
23 | #include <linux/of.h> |
24 | #include <linux/clk.h> | |
25 | #include <linux/err.h> | |
a70143bb | 26 | #include <linux/io.h> |
57f6ce07 KVA |
27 | #include <linux/pm_runtime.h> |
28 | #include <linux/delay.h> | |
14da699b | 29 | #include <linux/phy/omap_control_phy.h> |
918ee0d2 | 30 | #include <linux/of_platform.h> |
6e738432 | 31 | #include <linux/spinlock.h> |
57f6ce07 | 32 | |
57f6ce07 KVA |
33 | #define PLL_STATUS 0x00000004 |
34 | #define PLL_GO 0x00000008 | |
35 | #define PLL_CONFIGURATION1 0x0000000C | |
36 | #define PLL_CONFIGURATION2 0x00000010 | |
37 | #define PLL_CONFIGURATION3 0x00000014 | |
38 | #define PLL_CONFIGURATION4 0x00000020 | |
39 | ||
40 | #define PLL_REGM_MASK 0x001FFE00 | |
41 | #define PLL_REGM_SHIFT 0x9 | |
42 | #define PLL_REGM_F_MASK 0x0003FFFF | |
43 | #define PLL_REGM_F_SHIFT 0x0 | |
44 | #define PLL_REGN_MASK 0x000001FE | |
45 | #define PLL_REGN_SHIFT 0x1 | |
46 | #define PLL_SELFREQDCO_MASK 0x0000000E | |
47 | #define PLL_SELFREQDCO_SHIFT 0x1 | |
48 | #define PLL_SD_MASK 0x0003FC00 | |
1562864f | 49 | #define PLL_SD_SHIFT 10 |
57f6ce07 | 50 | #define SET_PLL_GO 0x1 |
629138db RQ |
51 | #define PLL_LDOPWDN BIT(15) |
52 | #define PLL_TICOPWDN BIT(16) | |
57f6ce07 KVA |
53 | #define PLL_LOCK 0x2 |
54 | #define PLL_IDLE 0x1 | |
55 | ||
56 | /* | |
57 | * This is an Empirical value that works, need to confirm the actual | |
a70143bb KVA |
58 | * value required for the PIPE3PHY_PLL_CONFIGURATION2.PLL_IDLE status |
59 | * to be correctly reflected in the PIPE3PHY_PLL_STATUS register. | |
57f6ce07 | 60 | */ |
629138db RQ |
61 | #define PLL_IDLE_TIME 100 /* in milliseconds */ |
62 | #define PLL_LOCK_TIME 100 /* in milliseconds */ | |
57f6ce07 | 63 | |
a70143bb KVA |
64 | struct pipe3_dpll_params { |
65 | u16 m; | |
66 | u8 n; | |
67 | u8 freq:3; | |
68 | u8 sd; | |
69 | u32 mf; | |
70 | }; | |
71 | ||
61f54674 RQ |
72 | struct pipe3_dpll_map { |
73 | unsigned long rate; | |
74 | struct pipe3_dpll_params params; | |
75 | }; | |
76 | ||
a70143bb KVA |
77 | struct ti_pipe3 { |
78 | void __iomem *pll_ctrl_base; | |
79 | struct device *dev; | |
80 | struct device *control_dev; | |
81 | struct clk *wkupclk; | |
82 | struct clk *sys_clk; | |
1562864f | 83 | struct clk *refclk; |
99bbd48c | 84 | struct clk *div_clk; |
61f54674 | 85 | struct pipe3_dpll_map *dpll_map; |
6e738432 RQ |
86 | bool enabled; |
87 | spinlock_t lock; /* serialize clock enable/disable */ | |
7f33912d RQ |
88 | /* the below flag is needed specifically for SATA */ |
89 | bool refclk_enabled; | |
a70143bb KVA |
90 | }; |
91 | ||
61f54674 | 92 | static struct pipe3_dpll_map dpll_map_usb[] = { |
519c6013 RQ |
93 | {12000000, {1250, 5, 4, 20, 0} }, /* 12 MHz */ |
94 | {16800000, {3125, 20, 4, 20, 0} }, /* 16.8 MHz */ | |
95 | {19200000, {1172, 8, 4, 20, 65537} }, /* 19.2 MHz */ | |
96 | {20000000, {1000, 7, 4, 10, 0} }, /* 20 MHz */ | |
97 | {26000000, {1250, 12, 4, 20, 0} }, /* 26 MHz */ | |
98 | {38400000, {3125, 47, 4, 20, 92843} }, /* 38.4 MHz */ | |
61f54674 RQ |
99 | { }, /* Terminator */ |
100 | }; | |
101 | ||
102 | static struct pipe3_dpll_map dpll_map_sata[] = { | |
103 | {12000000, {1000, 7, 4, 6, 0} }, /* 12 MHz */ | |
104 | {16800000, {714, 7, 4, 6, 0} }, /* 16.8 MHz */ | |
105 | {19200000, {625, 7, 4, 6, 0} }, /* 19.2 MHz */ | |
106 | {20000000, {600, 7, 4, 6, 0} }, /* 20 MHz */ | |
107 | {26000000, {461, 7, 4, 6, 0} }, /* 26 MHz */ | |
108 | {38400000, {312, 7, 4, 6, 0} }, /* 38.4 MHz */ | |
109 | { }, /* Terminator */ | |
57f6ce07 KVA |
110 | }; |
111 | ||
a70143bb KVA |
112 | static inline u32 ti_pipe3_readl(void __iomem *addr, unsigned offset) |
113 | { | |
114 | return __raw_readl(addr + offset); | |
115 | } | |
116 | ||
117 | static inline void ti_pipe3_writel(void __iomem *addr, unsigned offset, | |
118 | u32 data) | |
119 | { | |
120 | __raw_writel(data, addr + offset); | |
121 | } | |
122 | ||
61f54674 | 123 | static struct pipe3_dpll_params *ti_pipe3_get_dpll_params(struct ti_pipe3 *phy) |
519c6013 | 124 | { |
61f54674 RQ |
125 | unsigned long rate; |
126 | struct pipe3_dpll_map *dpll_map = phy->dpll_map; | |
519c6013 | 127 | |
61f54674 RQ |
128 | rate = clk_get_rate(phy->sys_clk); |
129 | ||
130 | for (; dpll_map->rate; dpll_map++) { | |
131 | if (rate == dpll_map->rate) | |
132 | return &dpll_map->params; | |
519c6013 RQ |
133 | } |
134 | ||
61f54674 RQ |
135 | dev_err(phy->dev, "No DPLL configuration for %lu Hz SYS CLK\n", rate); |
136 | ||
1b97be8c | 137 | return NULL; |
519c6013 RQ |
138 | } |
139 | ||
a70143bb KVA |
140 | static int ti_pipe3_power_off(struct phy *x) |
141 | { | |
142 | struct ti_pipe3 *phy = phy_get_drvdata(x); | |
a70143bb | 143 | |
14da699b | 144 | omap_control_phy_power(phy->control_dev, 0); |
a70143bb KVA |
145 | |
146 | return 0; | |
147 | } | |
148 | ||
149 | static int ti_pipe3_power_on(struct phy *x) | |
57f6ce07 | 150 | { |
a70143bb | 151 | struct ti_pipe3 *phy = phy_get_drvdata(x); |
57f6ce07 | 152 | |
629138db | 153 | omap_control_phy_power(phy->control_dev, 1); |
57f6ce07 KVA |
154 | |
155 | return 0; | |
156 | } | |
157 | ||
629138db | 158 | static int ti_pipe3_dpll_wait_lock(struct ti_pipe3 *phy) |
57f6ce07 KVA |
159 | { |
160 | u32 val; | |
161 | unsigned long timeout; | |
162 | ||
629138db | 163 | timeout = jiffies + msecs_to_jiffies(PLL_LOCK_TIME); |
57f6ce07 | 164 | do { |
629138db | 165 | cpu_relax(); |
a70143bb | 166 | val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS); |
57f6ce07 KVA |
167 | if (val & PLL_LOCK) |
168 | break; | |
629138db RQ |
169 | } while (!time_after(jiffies, timeout)); |
170 | ||
171 | if (!(val & PLL_LOCK)) { | |
172 | dev_err(phy->dev, "DPLL failed to lock\n"); | |
173 | return -EBUSY; | |
174 | } | |
175 | ||
176 | return 0; | |
57f6ce07 KVA |
177 | } |
178 | ||
629138db | 179 | static int ti_pipe3_dpll_program(struct ti_pipe3 *phy) |
57f6ce07 KVA |
180 | { |
181 | u32 val; | |
a70143bb | 182 | struct pipe3_dpll_params *dpll_params; |
57f6ce07 | 183 | |
61f54674 RQ |
184 | dpll_params = ti_pipe3_get_dpll_params(phy); |
185 | if (!dpll_params) | |
57f6ce07 | 186 | return -EINVAL; |
57f6ce07 | 187 | |
a70143bb | 188 | val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1); |
57f6ce07 | 189 | val &= ~PLL_REGN_MASK; |
519c6013 | 190 | val |= dpll_params->n << PLL_REGN_SHIFT; |
a70143bb | 191 | ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val); |
57f6ce07 | 192 | |
a70143bb | 193 | val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2); |
57f6ce07 | 194 | val &= ~PLL_SELFREQDCO_MASK; |
519c6013 | 195 | val |= dpll_params->freq << PLL_SELFREQDCO_SHIFT; |
a70143bb | 196 | ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val); |
57f6ce07 | 197 | |
a70143bb | 198 | val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1); |
57f6ce07 | 199 | val &= ~PLL_REGM_MASK; |
519c6013 | 200 | val |= dpll_params->m << PLL_REGM_SHIFT; |
a70143bb | 201 | ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val); |
57f6ce07 | 202 | |
a70143bb | 203 | val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION4); |
57f6ce07 | 204 | val &= ~PLL_REGM_F_MASK; |
519c6013 | 205 | val |= dpll_params->mf << PLL_REGM_F_SHIFT; |
a70143bb | 206 | ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION4, val); |
57f6ce07 | 207 | |
a70143bb | 208 | val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION3); |
57f6ce07 | 209 | val &= ~PLL_SD_MASK; |
519c6013 | 210 | val |= dpll_params->sd << PLL_SD_SHIFT; |
a70143bb | 211 | ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION3, val); |
57f6ce07 | 212 | |
629138db | 213 | ti_pipe3_writel(phy->pll_ctrl_base, PLL_GO, SET_PLL_GO); |
57f6ce07 | 214 | |
629138db | 215 | return ti_pipe3_dpll_wait_lock(phy); |
57f6ce07 KVA |
216 | } |
217 | ||
a70143bb | 218 | static int ti_pipe3_init(struct phy *x) |
57f6ce07 | 219 | { |
a70143bb | 220 | struct ti_pipe3 *phy = phy_get_drvdata(x); |
629138db RQ |
221 | u32 val; |
222 | int ret = 0; | |
519c6013 | 223 | |
0bc09f9c V |
224 | /* |
225 | * Set pcie_pcs register to 0x96 for proper functioning of phy | |
226 | * as recommended in AM572x TRM SPRUHZ6, section 18.5.2.2, table | |
227 | * 18-1804. | |
228 | */ | |
f0e2cf7b | 229 | if (of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-pcie")) { |
0bc09f9c | 230 | omap_control_pcie_pcs(phy->control_dev, 0x96); |
99bbd48c | 231 | return 0; |
f0e2cf7b | 232 | } |
99bbd48c | 233 | |
629138db RQ |
234 | /* Bring it out of IDLE if it is IDLE */ |
235 | val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2); | |
236 | if (val & PLL_IDLE) { | |
237 | val &= ~PLL_IDLE; | |
238 | ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val); | |
239 | ret = ti_pipe3_dpll_wait_lock(phy); | |
240 | } | |
57f6ce07 | 241 | |
629138db RQ |
242 | /* Program the DPLL only if not locked */ |
243 | val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS); | |
244 | if (!(val & PLL_LOCK)) | |
245 | if (ti_pipe3_dpll_program(phy)) | |
246 | return -EINVAL; | |
57f6ce07 | 247 | |
629138db | 248 | return ret; |
57f6ce07 KVA |
249 | } |
250 | ||
629138db RQ |
251 | static int ti_pipe3_exit(struct phy *x) |
252 | { | |
253 | struct ti_pipe3 *phy = phy_get_drvdata(x); | |
254 | u32 val; | |
255 | unsigned long timeout; | |
256 | ||
99bbd48c KVA |
257 | /* SATA DPLL can't be powered down due to Errata i783 and PCIe |
258 | * does not have internal DPLL | |
259 | */ | |
260 | if (of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-sata") || | |
261 | of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-pcie")) | |
56042e4e RQ |
262 | return 0; |
263 | ||
629138db RQ |
264 | /* Put DPLL in IDLE mode */ |
265 | val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2); | |
266 | val |= PLL_IDLE; | |
267 | ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val); | |
268 | ||
269 | /* wait for LDO and Oscillator to power down */ | |
270 | timeout = jiffies + msecs_to_jiffies(PLL_IDLE_TIME); | |
271 | do { | |
272 | cpu_relax(); | |
273 | val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS); | |
274 | if ((val & PLL_TICOPWDN) && (val & PLL_LDOPWDN)) | |
275 | break; | |
276 | } while (!time_after(jiffies, timeout)); | |
277 | ||
278 | if (!(val & PLL_TICOPWDN) || !(val & PLL_LDOPWDN)) { | |
279 | dev_err(phy->dev, "Failed to power down: PLL_STATUS 0x%x\n", | |
280 | val); | |
281 | return -EBUSY; | |
282 | } | |
283 | ||
284 | return 0; | |
285 | } | |
a70143bb KVA |
286 | static struct phy_ops ops = { |
287 | .init = ti_pipe3_init, | |
629138db | 288 | .exit = ti_pipe3_exit, |
a70143bb KVA |
289 | .power_on = ti_pipe3_power_on, |
290 | .power_off = ti_pipe3_power_off, | |
291 | .owner = THIS_MODULE, | |
292 | }; | |
293 | ||
61f54674 | 294 | static const struct of_device_id ti_pipe3_id_table[]; |
61f54674 | 295 | |
a70143bb | 296 | static int ti_pipe3_probe(struct platform_device *pdev) |
57f6ce07 | 297 | { |
a70143bb KVA |
298 | struct ti_pipe3 *phy; |
299 | struct phy *generic_phy; | |
300 | struct phy_provider *phy_provider; | |
918ee0d2 RQ |
301 | struct resource *res; |
302 | struct device_node *node = pdev->dev.of_node; | |
303 | struct device_node *control_node; | |
304 | struct platform_device *control_pdev; | |
61f54674 | 305 | const struct of_device_id *match; |
99bbd48c | 306 | struct clk *clk; |
57f6ce07 KVA |
307 | |
308 | phy = devm_kzalloc(&pdev->dev, sizeof(*phy), GFP_KERNEL); | |
3a4cfcbb | 309 | if (!phy) |
57f6ce07 | 310 | return -ENOMEM; |
3a4cfcbb | 311 | |
99bbd48c | 312 | phy->dev = &pdev->dev; |
6e738432 | 313 | spin_lock_init(&phy->lock); |
57f6ce07 | 314 | |
99bbd48c | 315 | if (!of_device_is_compatible(node, "ti,phy-pipe3-pcie")) { |
298fe56e | 316 | match = of_match_device(ti_pipe3_id_table, &pdev->dev); |
99bbd48c KVA |
317 | if (!match) |
318 | return -EINVAL; | |
61f54674 | 319 | |
99bbd48c KVA |
320 | phy->dpll_map = (struct pipe3_dpll_map *)match->data; |
321 | if (!phy->dpll_map) { | |
322 | dev_err(&pdev->dev, "no DPLL data\n"); | |
323 | return -EINVAL; | |
324 | } | |
57f6ce07 | 325 | |
99bbd48c KVA |
326 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, |
327 | "pll_ctrl"); | |
328 | phy->pll_ctrl_base = devm_ioremap_resource(&pdev->dev, res); | |
329 | if (IS_ERR(phy->pll_ctrl_base)) | |
330 | return PTR_ERR(phy->pll_ctrl_base); | |
57f6ce07 | 331 | |
99bbd48c KVA |
332 | phy->sys_clk = devm_clk_get(phy->dev, "sysclk"); |
333 | if (IS_ERR(phy->sys_clk)) { | |
334 | dev_err(&pdev->dev, "unable to get sysclk\n"); | |
335 | return -EINVAL; | |
336 | } | |
337 | } | |
9c7f0443 | 338 | |
7f33912d RQ |
339 | phy->refclk = devm_clk_get(phy->dev, "refclk"); |
340 | if (IS_ERR(phy->refclk)) { | |
341 | dev_err(&pdev->dev, "unable to get refclk\n"); | |
342 | /* older DTBs have missing refclk in SATA PHY | |
343 | * so don't bail out in case of SATA PHY. | |
344 | */ | |
345 | if (!of_device_is_compatible(node, "ti,phy-pipe3-sata")) | |
346 | return PTR_ERR(phy->refclk); | |
347 | } | |
348 | ||
99bbd48c | 349 | if (!of_device_is_compatible(node, "ti,phy-pipe3-sata")) { |
9c7f0443 RQ |
350 | phy->wkupclk = devm_clk_get(phy->dev, "wkupclk"); |
351 | if (IS_ERR(phy->wkupclk)) { | |
352 | dev_err(&pdev->dev, "unable to get wkupclk\n"); | |
353 | return PTR_ERR(phy->wkupclk); | |
354 | } | |
9c7f0443 RQ |
355 | } else { |
356 | phy->wkupclk = ERR_PTR(-ENODEV); | |
57f6ce07 | 357 | } |
57f6ce07 | 358 | |
99bbd48c | 359 | if (of_device_is_compatible(node, "ti,phy-pipe3-pcie")) { |
99bbd48c KVA |
360 | |
361 | clk = devm_clk_get(phy->dev, "dpll_ref"); | |
362 | if (IS_ERR(clk)) { | |
363 | dev_err(&pdev->dev, "unable to get dpll ref clk\n"); | |
364 | return PTR_ERR(clk); | |
365 | } | |
366 | clk_set_rate(clk, 1500000000); | |
367 | ||
368 | clk = devm_clk_get(phy->dev, "dpll_ref_m2"); | |
369 | if (IS_ERR(clk)) { | |
370 | dev_err(&pdev->dev, "unable to get dpll ref m2 clk\n"); | |
371 | return PTR_ERR(clk); | |
372 | } | |
373 | clk_set_rate(clk, 100000000); | |
374 | ||
375 | clk = devm_clk_get(phy->dev, "phy-div"); | |
376 | if (IS_ERR(clk)) { | |
377 | dev_err(&pdev->dev, "unable to get phy-div clk\n"); | |
378 | return PTR_ERR(clk); | |
379 | } | |
380 | clk_set_rate(clk, 100000000); | |
381 | ||
382 | phy->div_clk = devm_clk_get(phy->dev, "div-clk"); | |
383 | if (IS_ERR(phy->div_clk)) { | |
384 | dev_err(&pdev->dev, "unable to get div-clk\n"); | |
385 | return PTR_ERR(phy->div_clk); | |
386 | } | |
387 | } else { | |
388 | phy->div_clk = ERR_PTR(-ENODEV); | |
57f6ce07 KVA |
389 | } |
390 | ||
918ee0d2 RQ |
391 | control_node = of_parse_phandle(node, "ctrl-module", 0); |
392 | if (!control_node) { | |
393 | dev_err(&pdev->dev, "Failed to get control device phandle\n"); | |
394 | return -EINVAL; | |
57f6ce07 | 395 | } |
a70143bb | 396 | |
918ee0d2 RQ |
397 | control_pdev = of_find_device_by_node(control_node); |
398 | if (!control_pdev) { | |
399 | dev_err(&pdev->dev, "Failed to get control device\n"); | |
400 | return -EINVAL; | |
401 | } | |
402 | ||
403 | phy->control_dev = &control_pdev->dev; | |
57f6ce07 | 404 | |
14da699b | 405 | omap_control_phy_power(phy->control_dev, 0); |
57f6ce07 KVA |
406 | |
407 | platform_set_drvdata(pdev, phy); | |
57f6ce07 | 408 | pm_runtime_enable(phy->dev); |
a70143bb | 409 | |
dbc98635 | 410 | generic_phy = devm_phy_create(phy->dev, NULL, &ops); |
a70143bb KVA |
411 | if (IS_ERR(generic_phy)) |
412 | return PTR_ERR(generic_phy); | |
413 | ||
414 | phy_set_drvdata(generic_phy, phy); | |
415 | phy_provider = devm_of_phy_provider_register(phy->dev, | |
416 | of_phy_simple_xlate); | |
417 | if (IS_ERR(phy_provider)) | |
418 | return PTR_ERR(phy_provider); | |
419 | ||
57f6ce07 KVA |
420 | pm_runtime_get(&pdev->dev); |
421 | ||
422 | return 0; | |
423 | } | |
424 | ||
a70143bb | 425 | static int ti_pipe3_remove(struct platform_device *pdev) |
57f6ce07 | 426 | { |
57f6ce07 KVA |
427 | if (!pm_runtime_suspended(&pdev->dev)) |
428 | pm_runtime_put(&pdev->dev); | |
429 | pm_runtime_disable(&pdev->dev); | |
430 | ||
431 | return 0; | |
432 | } | |
433 | ||
7ba37053 | 434 | #ifdef CONFIG_PM |
7f33912d RQ |
435 | static int ti_pipe3_enable_refclk(struct ti_pipe3 *phy) |
436 | { | |
437 | if (!IS_ERR(phy->refclk) && !phy->refclk_enabled) { | |
438 | int ret; | |
439 | ||
440 | ret = clk_prepare_enable(phy->refclk); | |
441 | if (ret) { | |
442 | dev_err(phy->dev, "Failed to enable refclk %d\n", ret); | |
443 | return ret; | |
444 | } | |
445 | phy->refclk_enabled = true; | |
446 | } | |
447 | ||
448 | return 0; | |
449 | } | |
450 | ||
451 | static void ti_pipe3_disable_refclk(struct ti_pipe3 *phy) | |
452 | { | |
453 | if (!IS_ERR(phy->refclk)) | |
454 | clk_disable_unprepare(phy->refclk); | |
455 | ||
456 | phy->refclk_enabled = false; | |
457 | } | |
57f6ce07 | 458 | |
6e738432 | 459 | static int ti_pipe3_enable_clocks(struct ti_pipe3 *phy) |
57f6ce07 | 460 | { |
6e738432 RQ |
461 | int ret = 0; |
462 | unsigned long flags; | |
57f6ce07 | 463 | |
6e738432 RQ |
464 | spin_lock_irqsave(&phy->lock, flags); |
465 | if (phy->enabled) | |
466 | goto err1; | |
57f6ce07 | 467 | |
7f33912d RQ |
468 | ret = ti_pipe3_enable_refclk(phy); |
469 | if (ret) | |
470 | goto err1; | |
57f6ce07 | 471 | |
1562864f RQ |
472 | if (!IS_ERR(phy->wkupclk)) { |
473 | ret = clk_prepare_enable(phy->wkupclk); | |
474 | if (ret) { | |
475 | dev_err(phy->dev, "Failed to enable wkupclk %d\n", ret); | |
476 | goto err2; | |
477 | } | |
57f6ce07 KVA |
478 | } |
479 | ||
99bbd48c KVA |
480 | if (!IS_ERR(phy->div_clk)) { |
481 | ret = clk_prepare_enable(phy->div_clk); | |
482 | if (ret) { | |
483 | dev_err(phy->dev, "Failed to enable div_clk %d\n", ret); | |
484 | goto err3; | |
485 | } | |
486 | } | |
6e738432 RQ |
487 | |
488 | phy->enabled = true; | |
489 | spin_unlock_irqrestore(&phy->lock, flags); | |
57f6ce07 KVA |
490 | return 0; |
491 | ||
99bbd48c KVA |
492 | err3: |
493 | if (!IS_ERR(phy->wkupclk)) | |
494 | clk_disable_unprepare(phy->wkupclk); | |
495 | ||
57f6ce07 | 496 | err2: |
1562864f RQ |
497 | if (!IS_ERR(phy->refclk)) |
498 | clk_disable_unprepare(phy->refclk); | |
57f6ce07 | 499 | |
7f33912d | 500 | ti_pipe3_disable_refclk(phy); |
57f6ce07 | 501 | err1: |
6e738432 RQ |
502 | spin_unlock_irqrestore(&phy->lock, flags); |
503 | return ret; | |
504 | } | |
505 | ||
506 | static void ti_pipe3_disable_clocks(struct ti_pipe3 *phy) | |
507 | { | |
508 | unsigned long flags; | |
509 | ||
510 | spin_lock_irqsave(&phy->lock, flags); | |
511 | if (!phy->enabled) { | |
512 | spin_unlock_irqrestore(&phy->lock, flags); | |
513 | return; | |
514 | } | |
515 | ||
516 | if (!IS_ERR(phy->wkupclk)) | |
517 | clk_disable_unprepare(phy->wkupclk); | |
7f33912d RQ |
518 | /* Don't disable refclk for SATA PHY due to Errata i783 */ |
519 | if (!of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-sata")) | |
520 | ti_pipe3_disable_refclk(phy); | |
6e738432 RQ |
521 | if (!IS_ERR(phy->div_clk)) |
522 | clk_disable_unprepare(phy->div_clk); | |
523 | phy->enabled = false; | |
524 | spin_unlock_irqrestore(&phy->lock, flags); | |
525 | } | |
526 | ||
527 | static int ti_pipe3_runtime_suspend(struct device *dev) | |
528 | { | |
529 | struct ti_pipe3 *phy = dev_get_drvdata(dev); | |
530 | ||
531 | ti_pipe3_disable_clocks(phy); | |
532 | return 0; | |
533 | } | |
534 | ||
535 | static int ti_pipe3_runtime_resume(struct device *dev) | |
536 | { | |
537 | struct ti_pipe3 *phy = dev_get_drvdata(dev); | |
538 | int ret = 0; | |
539 | ||
540 | ret = ti_pipe3_enable_clocks(phy); | |
57f6ce07 KVA |
541 | return ret; |
542 | } | |
543 | ||
6e738432 RQ |
544 | static int ti_pipe3_suspend(struct device *dev) |
545 | { | |
546 | struct ti_pipe3 *phy = dev_get_drvdata(dev); | |
547 | ||
548 | ti_pipe3_disable_clocks(phy); | |
549 | return 0; | |
550 | } | |
551 | ||
552 | static int ti_pipe3_resume(struct device *dev) | |
553 | { | |
554 | struct ti_pipe3 *phy = dev_get_drvdata(dev); | |
555 | int ret; | |
556 | ||
557 | ret = ti_pipe3_enable_clocks(phy); | |
558 | if (ret) | |
559 | return ret; | |
560 | ||
561 | pm_runtime_disable(dev); | |
562 | pm_runtime_set_active(dev); | |
563 | pm_runtime_enable(dev); | |
564 | return 0; | |
565 | } | |
566 | #endif | |
567 | ||
a70143bb KVA |
568 | static const struct dev_pm_ops ti_pipe3_pm_ops = { |
569 | SET_RUNTIME_PM_OPS(ti_pipe3_runtime_suspend, | |
570 | ti_pipe3_runtime_resume, NULL) | |
6e738432 | 571 | SET_SYSTEM_SLEEP_PM_OPS(ti_pipe3_suspend, ti_pipe3_resume) |
57f6ce07 KVA |
572 | }; |
573 | ||
a70143bb | 574 | static const struct of_device_id ti_pipe3_id_table[] = { |
61f54674 RQ |
575 | { |
576 | .compatible = "ti,phy-usb3", | |
577 | .data = dpll_map_usb, | |
578 | }, | |
579 | { | |
580 | .compatible = "ti,omap-usb3", | |
581 | .data = dpll_map_usb, | |
582 | }, | |
583 | { | |
584 | .compatible = "ti,phy-pipe3-sata", | |
585 | .data = dpll_map_sata, | |
586 | }, | |
99bbd48c KVA |
587 | { |
588 | .compatible = "ti,phy-pipe3-pcie", | |
589 | }, | |
57f6ce07 KVA |
590 | {} |
591 | }; | |
a70143bb | 592 | MODULE_DEVICE_TABLE(of, ti_pipe3_id_table); |
57f6ce07 | 593 | |
a70143bb KVA |
594 | static struct platform_driver ti_pipe3_driver = { |
595 | .probe = ti_pipe3_probe, | |
596 | .remove = ti_pipe3_remove, | |
57f6ce07 | 597 | .driver = { |
a70143bb | 598 | .name = "ti-pipe3", |
6e738432 | 599 | .pm = &ti_pipe3_pm_ops, |
298fe56e | 600 | .of_match_table = ti_pipe3_id_table, |
57f6ce07 KVA |
601 | }, |
602 | }; | |
603 | ||
a70143bb | 604 | module_platform_driver(ti_pipe3_driver); |
57f6ce07 | 605 | |
a70143bb | 606 | MODULE_ALIAS("platform: ti_pipe3"); |
57f6ce07 | 607 | MODULE_AUTHOR("Texas Instruments Inc."); |
a70143bb | 608 | MODULE_DESCRIPTION("TI PIPE3 phy driver"); |
57f6ce07 | 609 | MODULE_LICENSE("GPL v2"); |