[mirror_ubuntu-jammy-kernel.git] / drivers / phy / rockchip / phy-rockchip-pcie.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Rockchip PCIe PHY driver
 *
 * Copyright (C) 2016 Shawn Lin <shawn.lin@rock-chips.com>
 * Copyright (C) 2016 ROCKCHIP, Inc.
 */

#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/reset.h>

/*
 * The higher 16-bit of this register is used for write protection
 * only if BIT(x + 16) set to 1 the BIT(x) can be written.
 */
#define HIWORD_UPDATE(val, mask, shift) \
		((val) << (shift) | (mask) << ((shift) + 16))

#define PHY_MAX_LANE_NUM      4
#define PHY_CFG_DATA_SHIFT    7
#define PHY_CFG_ADDR_SHIFT    1
#define PHY_CFG_DATA_MASK     0xf
#define PHY_CFG_ADDR_MASK     0x3f
#define PHY_CFG_RD_MASK       0x3ff
#define PHY_CFG_WR_ENABLE     1
#define PHY_CFG_WR_DISABLE    1
#define PHY_CFG_WR_SHIFT      0
#define PHY_CFG_WR_MASK       1
#define PHY_CFG_PLL_LOCK      0x10
#define PHY_CFG_CLK_TEST      0x10
#define PHY_CFG_CLK_SCC       0x12
#define PHY_CFG_SEPE_RATE     BIT(3)
#define PHY_CFG_PLL_100M      BIT(3)
#define PHY_PLL_LOCKED        BIT(9)
#define PHY_PLL_OUTPUT        BIT(10)
#define PHY_LANE_A_STATUS     0x30
#define PHY_LANE_B_STATUS     0x31
#define PHY_LANE_C_STATUS     0x32
#define PHY_LANE_D_STATUS     0x33
#define PHY_LANE_RX_DET_SHIFT 11
#define PHY_LANE_RX_DET_TH    0x1
#define PHY_LANE_IDLE_OFF     0x1
#define PHY_LANE_IDLE_MASK    0x1
#define PHY_LANE_IDLE_A_SHIFT 3
#define PHY_LANE_IDLE_B_SHIFT 4
#define PHY_LANE_IDLE_C_SHIFT 5
#define PHY_LANE_IDLE_D_SHIFT 6

struct rockchip_pcie_data {
	unsigned int pcie_conf;
	unsigned int pcie_status;
	unsigned int pcie_laneoff;
};

struct rockchip_pcie_phy {
	struct rockchip_pcie_data *phy_data;
	struct regmap *reg_base;
	struct phy_pcie_instance {
		struct phy *phy;
		u32 index;
	} phys[PHY_MAX_LANE_NUM];
	struct mutex pcie_mutex;
	struct reset_control *phy_rst;
	struct clk *clk_pciephy_ref;
	int pwr_cnt;
	int init_cnt;
};

static struct rockchip_pcie_phy *to_pcie_phy(struct phy_pcie_instance *inst)
{
	return container_of(inst, struct rockchip_pcie_phy,
					phys[inst->index]);
}

static struct phy *rockchip_pcie_phy_of_xlate(struct device *dev,
					      struct of_phandle_args *args)
{
	struct rockchip_pcie_phy *rk_phy = dev_get_drvdata(dev);

	if (args->args_count == 0)
		return rk_phy->phys[0].phy;

	if (WARN_ON(args->args[0] >= PHY_MAX_LANE_NUM))
		return ERR_PTR(-ENODEV);

	return rk_phy->phys[args->args[0]].phy;
}


static inline void phy_wr_cfg(struct rockchip_pcie_phy *rk_phy,
			      u32 addr, u32 data)
{
	regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_conf,
		     HIWORD_UPDATE(data,
				   PHY_CFG_DATA_MASK,
				   PHY_CFG_DATA_SHIFT) |
		     HIWORD_UPDATE(addr,
				   PHY_CFG_ADDR_MASK,
				   PHY_CFG_ADDR_SHIFT));
	udelay(1);
	regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_conf,
		     HIWORD_UPDATE(PHY_CFG_WR_ENABLE,
				   PHY_CFG_WR_MASK,
				   PHY_CFG_WR_SHIFT));
	udelay(1);
	regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_conf,
		     HIWORD_UPDATE(PHY_CFG_WR_DISABLE,
				   PHY_CFG_WR_MASK,
				   PHY_CFG_WR_SHIFT));
}

static inline u32 phy_rd_cfg(struct rockchip_pcie_phy *rk_phy,
			     u32 addr)
{
	u32 val;

	regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_conf,
		     HIWORD_UPDATE(addr,
				   PHY_CFG_RD_MASK,
				   PHY_CFG_ADDR_SHIFT));
	regmap_read(rk_phy->reg_base,
		    rk_phy->phy_data->pcie_status,
		    &val);
	return val;
}

static int rockchip_pcie_phy_power_off(struct phy *phy)
{
	struct phy_pcie_instance *inst = phy_get_drvdata(phy);
	struct rockchip_pcie_phy *rk_phy = to_pcie_phy(inst);
	int err = 0;

	mutex_lock(&rk_phy->pcie_mutex);

	regmap_write(rk_phy->reg_base,
		     rk_phy->phy_data->pcie_laneoff,
		     HIWORD_UPDATE(PHY_LANE_IDLE_OFF,
				   PHY_LANE_IDLE_MASK,
				   PHY_LANE_IDLE_A_SHIFT + inst->index));

	if (--rk_phy->pwr_cnt)
		goto err_out;

	err = reset_control_assert(rk_phy->phy_rst);
	if (err) {
		dev_err(&phy->dev, "assert phy_rst err %d\n", err);
		goto err_restore;
	}

err_out:
	mutex_unlock(&rk_phy->pcie_mutex);
	return 0;

err_restore:
	rk_phy->pwr_cnt++;
	regmap_write(rk_phy->reg_base,
		     rk_phy->phy_data->pcie_laneoff,
		     HIWORD_UPDATE(!PHY_LANE_IDLE_OFF,
				   PHY_LANE_IDLE_MASK,
				   PHY_LANE_IDLE_A_SHIFT + inst->index));
	mutex_unlock(&rk_phy->pcie_mutex);
	return err;
}

static int rockchip_pcie_phy_power_on(struct phy *phy)
{
	struct phy_pcie_instance *inst = phy_get_drvdata(phy);
	struct rockchip_pcie_phy *rk_phy = to_pcie_phy(inst);
	int err = 0;
	u32 status;
	unsigned long timeout;

	mutex_lock(&rk_phy->pcie_mutex);

	if (rk_phy->pwr_cnt++)
		goto err_out;

	err = reset_control_deassert(rk_phy->phy_rst);
	if (err) {
		dev_err(&phy->dev, "deassert phy_rst err %d\n", err);
		goto err_pwr_cnt;
	}

	regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_conf,
		     HIWORD_UPDATE(PHY_CFG_PLL_LOCK,
				   PHY_CFG_ADDR_MASK,
				   PHY_CFG_ADDR_SHIFT));

	regmap_write(rk_phy->reg_base,
		     rk_phy->phy_data->pcie_laneoff,
		     HIWORD_UPDATE(!PHY_LANE_IDLE_OFF,
				   PHY_LANE_IDLE_MASK,
				   PHY_LANE_IDLE_A_SHIFT + inst->index));

	/*
	 * No documented timeout value for phy operation below,
	 * so we make it large enough here. And we use loop-break
	 * method which should not be harmful.
	 */
	timeout = jiffies + msecs_to_jiffies(1000);

	err = -EINVAL;
	while (time_before(jiffies, timeout)) {
		regmap_read(rk_phy->reg_base,
			    rk_phy->phy_data->pcie_status,
			    &status);
		if (status & PHY_PLL_LOCKED) {
			dev_dbg(&phy->dev, "pll locked!\n");
			err = 0;
			break;
		}
		msleep(20);
	}

	if (err) {
		dev_err(&phy->dev, "pll lock timeout!\n");
		goto err_pll_lock;
	}

	phy_wr_cfg(rk_phy, PHY_CFG_CLK_TEST, PHY_CFG_SEPE_RATE);
	phy_wr_cfg(rk_phy, PHY_CFG_CLK_SCC, PHY_CFG_PLL_100M);

	err = -ETIMEDOUT;
	while (time_before(jiffies, timeout)) {
		regmap_read(rk_phy->reg_base,
			    rk_phy->phy_data->pcie_status,
			    &status);
		if (!(status & PHY_PLL_OUTPUT)) {
			dev_dbg(&phy->dev, "pll output enable done!\n");
			err = 0;
			break;
		}
		msleep(20);
	}

	if (err) {
		dev_err(&phy->dev, "pll output enable timeout!\n");
		goto err_pll_lock;
	}

	regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_conf,
		     HIWORD_UPDATE(PHY_CFG_PLL_LOCK,
				   PHY_CFG_ADDR_MASK,
				   PHY_CFG_ADDR_SHIFT));
	err = -EINVAL;
	while (time_before(jiffies, timeout)) {
		regmap_read(rk_phy->reg_base,
			    rk_phy->phy_data->pcie_status,
			    &status);
		if (status & PHY_PLL_LOCKED) {
			dev_dbg(&phy->dev, "pll relocked!\n");
			err = 0;
			break;
		}
		msleep(20);
	}

	if (err) {
		dev_err(&phy->dev, "pll relock timeout!\n");
		goto err_pll_lock;
	}

err_out:
	mutex_unlock(&rk_phy->pcie_mutex);
	return 0;

err_pll_lock:
	reset_control_assert(rk_phy->phy_rst);
err_pwr_cnt:
	rk_phy->pwr_cnt--;
	mutex_unlock(&rk_phy->pcie_mutex);
	return err;
}

static int rockchip_pcie_phy_init(struct phy *phy)
{
	struct phy_pcie_instance *inst = phy_get_drvdata(phy);
	struct rockchip_pcie_phy *rk_phy = to_pcie_phy(inst);
	int err = 0;

	mutex_lock(&rk_phy->pcie_mutex);

	if (rk_phy->init_cnt++)
		goto err_out;

	err = clk_prepare_enable(rk_phy->clk_pciephy_ref);
	if (err) {
		dev_err(&phy->dev, "Fail to enable pcie ref clock.\n");
		goto err_refclk;
	}

	err = reset_control_assert(rk_phy->phy_rst);
	if (err) {
		dev_err(&phy->dev, "assert phy_rst err %d\n", err);
		goto err_reset;
	}

err_out:
	mutex_unlock(&rk_phy->pcie_mutex);
	return 0;

err_reset:

	clk_disable_unprepare(rk_phy->clk_pciephy_ref);
err_refclk:
	rk_phy->init_cnt--;
	mutex_unlock(&rk_phy->pcie_mutex);
	return err;
}

static int rockchip_pcie_phy_exit(struct phy *phy)
{
	struct phy_pcie_instance *inst = phy_get_drvdata(phy);
	struct rockchip_pcie_phy *rk_phy = to_pcie_phy(inst);

	mutex_lock(&rk_phy->pcie_mutex);

	if (--rk_phy->init_cnt)
		goto err_init_cnt;

	clk_disable_unprepare(rk_phy->clk_pciephy_ref);

err_init_cnt:
	mutex_unlock(&rk_phy->pcie_mutex);
	return 0;
}

static const struct phy_ops ops = {
	.init		= rockchip_pcie_phy_init,
	.exit		= rockchip_pcie_phy_exit,
	.power_on	= rockchip_pcie_phy_power_on,
	.power_off	= rockchip_pcie_phy_power_off,
	.owner		= THIS_MODULE,
};

static const struct rockchip_pcie_data rk3399_pcie_data = {
	.pcie_conf = 0xe220,
	.pcie_status = 0xe2a4,
	.pcie_laneoff = 0xe214,
};

static const struct of_device_id rockchip_pcie_phy_dt_ids[] = {
	{
		.compatible = "rockchip,rk3399-pcie-phy",
		.data = &rk3399_pcie_data,
	},
	{}
};

MODULE_DEVICE_TABLE(of, rockchip_pcie_phy_dt_ids);

static int rockchip_pcie_phy_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct rockchip_pcie_phy *rk_phy;
	struct phy_provider *phy_provider;
	struct regmap *grf;
	const struct of_device_id *of_id;
	int i;
	u32 phy_num;

	grf = syscon_node_to_regmap(dev->parent->of_node);
	if (IS_ERR(grf)) {
		dev_err(dev, "Cannot find GRF syscon\n");
		return PTR_ERR(grf);
	}

	rk_phy = devm_kzalloc(dev, sizeof(*rk_phy), GFP_KERNEL);
	if (!rk_phy)
		return -ENOMEM;

	of_id = of_match_device(rockchip_pcie_phy_dt_ids, &pdev->dev);
	if (!of_id)
		return -EINVAL;

	rk_phy->phy_data = (struct rockchip_pcie_data *)of_id->data;
	rk_phy->reg_base = grf;

	mutex_init(&rk_phy->pcie_mutex);

	rk_phy->phy_rst = devm_reset_control_get(dev, "phy");
	if (IS_ERR(rk_phy->phy_rst)) {
		if (PTR_ERR(rk_phy->phy_rst) != -EPROBE_DEFER)
			dev_err(dev,
				"missing phy property for reset controller\n");
		return PTR_ERR(rk_phy->phy_rst);
	}

	rk_phy->clk_pciephy_ref = devm_clk_get(dev, "refclk");
	if (IS_ERR(rk_phy->clk_pciephy_ref)) {
		dev_err(dev, "refclk not found.\n");
		return PTR_ERR(rk_phy->clk_pciephy_ref);
	}

	/* parse #phy-cells to see if it's legacy PHY model */
	if (of_property_read_u32(dev->of_node, "#phy-cells", &phy_num))
		return -ENOENT;

	phy_num = (phy_num == 0) ? 1 : PHY_MAX_LANE_NUM;
	dev_dbg(dev, "phy number is %d\n", phy_num);

	for (i = 0; i < phy_num; i++) {
		rk_phy->phys[i].phy = devm_phy_create(dev, dev->of_node, &ops);
		if (IS_ERR(rk_phy->phys[i].phy)) {
			dev_err(dev, "failed to create PHY%d\n", i);
			return PTR_ERR(rk_phy->phys[i].phy);
		}
		rk_phy->phys[i].index = i;
		phy_set_drvdata(rk_phy->phys[i].phy, &rk_phy->phys[i]);
	}

	platform_set_drvdata(pdev, rk_phy);
	phy_provider = devm_of_phy_provider_register(dev,
					rockchip_pcie_phy_of_xlate);

	return PTR_ERR_OR_ZERO(phy_provider);
}

static struct platform_driver rockchip_pcie_driver = {
	.probe		= rockchip_pcie_phy_probe,
	.driver		= {
		.name	= "rockchip-pcie-phy",
		.of_match_table = rockchip_pcie_phy_dt_ids,
	},
};

module_platform_driver(rockchip_pcie_driver);

MODULE_AUTHOR("Shawn Lin <shawn.lin@rock-chips.com>");
MODULE_DESCRIPTION("Rockchip PCIe PHY driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
2504ba9f	1	// SPDX-License-Identifier: GPL-2.0-only
fcffee3d SL	2	/*
	3	* Rockchip PCIe PHY driver
	4	*
	5	* Copyright (C) 2016 Shawn Lin <shawn.lin@rock-chips.com>
	6	* Copyright (C) 2016 ROCKCHIP, Inc.
fcffee3d SL	7	*/
	8
	9	#include <linux/clk.h>
	10	#include <linux/delay.h>
	11	#include <linux/io.h>
	12	#include <linux/mfd/syscon.h>
	13	#include <linux/module.h>
	14	#include <linux/of.h>
	15	#include <linux/of_address.h>
	16	#include <linux/of_platform.h>
	17	#include <linux/phy/phy.h>
	18	#include <linux/platform_device.h>
	19	#include <linux/regmap.h>
	20	#include <linux/reset.h>
	21
	22	/*
	23	* The higher 16-bit of this register is used for write protection
	24	* only if BIT(x + 16) set to 1 the BIT(x) can be written.
	25	*/
	26	#define HIWORD_UPDATE(val, mask, shift) \
	27	((val) << (shift) \| (mask) << ((shift) + 16))
	28
	29	#define PHY_MAX_LANE_NUM 4
	30	#define PHY_CFG_DATA_SHIFT 7
	31	#define PHY_CFG_ADDR_SHIFT 1
	32	#define PHY_CFG_DATA_MASK 0xf
	33	#define PHY_CFG_ADDR_MASK 0x3f
	34	#define PHY_CFG_RD_MASK 0x3ff
	35	#define PHY_CFG_WR_ENABLE 1
	36	#define PHY_CFG_WR_DISABLE 1
	37	#define PHY_CFG_WR_SHIFT 0
	38	#define PHY_CFG_WR_MASK 1
	39	#define PHY_CFG_PLL_LOCK 0x10
	40	#define PHY_CFG_CLK_TEST 0x10
	41	#define PHY_CFG_CLK_SCC 0x12
	42	#define PHY_CFG_SEPE_RATE BIT(3)
	43	#define PHY_CFG_PLL_100M BIT(3)
	44	#define PHY_PLL_LOCKED BIT(9)
	45	#define PHY_PLL_OUTPUT BIT(10)
	46	#define PHY_LANE_A_STATUS 0x30
	47	#define PHY_LANE_B_STATUS 0x31
	48	#define PHY_LANE_C_STATUS 0x32
	49	#define PHY_LANE_D_STATUS 0x33
	50	#define PHY_LANE_RX_DET_SHIFT 11
	51	#define PHY_LANE_RX_DET_TH 0x1
	52	#define PHY_LANE_IDLE_OFF 0x1
	53	#define PHY_LANE_IDLE_MASK 0x1
	54	#define PHY_LANE_IDLE_A_SHIFT 3
	55	#define PHY_LANE_IDLE_B_SHIFT 4
	56	#define PHY_LANE_IDLE_C_SHIFT 5
	57	#define PHY_LANE_IDLE_D_SHIFT 6
	58
	59	struct rockchip_pcie_data {
	60	unsigned int pcie_conf;
	61	unsigned int pcie_status;
	62	unsigned int pcie_laneoff;
	63	};
	64
	65	struct rockchip_pcie_phy {
	66	struct rockchip_pcie_data *phy_data;
	67	struct regmap *reg_base;
90a7612d SL	68	struct phy_pcie_instance {
	69	struct phy *phy;
	70	u32 index;
	71	} phys[PHY_MAX_LANE_NUM];
	72	struct mutex pcie_mutex;
fcffee3d SL	73	struct reset_control *phy_rst;
fcffee3d SL	74	struct clk *clk_pciephy_ref;
90a7612d SL	75	int pwr_cnt;
90a7612d SL	76	int init_cnt;
fcffee3d SL	77	};
fcffee3d SL	78
90a7612d SL	79	static struct rockchip_pcie_phy to_pcie_phy(struct phy_pcie_instance inst)
	80	{
	81	return container_of(inst, struct rockchip_pcie_phy,
	82	phys[inst->index]);
	83	}
	84
	85	static struct phy rockchip_pcie_phy_of_xlate(struct device dev,
	86	struct of_phandle_args *args)
	87	{
	88	struct rockchip_pcie_phy *rk_phy = dev_get_drvdata(dev);
	89
	90	if (args->args_count == 0)
	91	return rk_phy->phys[0].phy;
	92
	93	if (WARN_ON(args->args[0] >= PHY_MAX_LANE_NUM))
	94	return ERR_PTR(-ENODEV);
	95
	96	return rk_phy->phys[args->args[0]].phy;
	97	}
	98
	99
fcffee3d SL	100	static inline void phy_wr_cfg(struct rockchip_pcie_phy *rk_phy,
	101	u32 addr, u32 data)
	102	{
	103	regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_conf,
	104	HIWORD_UPDATE(data,
	105	PHY_CFG_DATA_MASK,
	106	PHY_CFG_DATA_SHIFT) \|
	107	HIWORD_UPDATE(addr,
	108	PHY_CFG_ADDR_MASK,
	109	PHY_CFG_ADDR_SHIFT));
	110	udelay(1);
	111	regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_conf,
	112	HIWORD_UPDATE(PHY_CFG_WR_ENABLE,
	113	PHY_CFG_WR_MASK,
	114	PHY_CFG_WR_SHIFT));
	115	udelay(1);
	116	regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_conf,
	117	HIWORD_UPDATE(PHY_CFG_WR_DISABLE,
	118	PHY_CFG_WR_MASK,
	119	PHY_CFG_WR_SHIFT));
	120	}
	121
	122	static inline u32 phy_rd_cfg(struct rockchip_pcie_phy *rk_phy,
	123	u32 addr)
	124	{
	125	u32 val;
	126
	127	regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_conf,
	128	HIWORD_UPDATE(addr,
	129	PHY_CFG_RD_MASK,
	130	PHY_CFG_ADDR_SHIFT));
	131	regmap_read(rk_phy->reg_base,
	132	rk_phy->phy_data->pcie_status,
	133	&val);
	134	return val;
	135	}
	136
	137	static int rockchip_pcie_phy_power_off(struct phy *phy)
	138	{
90a7612d SL	139	struct phy_pcie_instance *inst = phy_get_drvdata(phy);
90a7612d SL	140	struct rockchip_pcie_phy *rk_phy = to_pcie_phy(inst);
fcffee3d SL	141	int err = 0;
fcffee3d SL	142
90a7612d SL	143	mutex_lock(&rk_phy->pcie_mutex);
	144
	145	regmap_write(rk_phy->reg_base,
	146	rk_phy->phy_data->pcie_laneoff,
	147	HIWORD_UPDATE(PHY_LANE_IDLE_OFF,
	148	PHY_LANE_IDLE_MASK,
	149	PHY_LANE_IDLE_A_SHIFT + inst->index));
	150
	151	if (--rk_phy->pwr_cnt)
	152	goto err_out;
	153
fcffee3d SL	154	err = reset_control_assert(rk_phy->phy_rst);
	155	if (err) {
	156	dev_err(&phy->dev, "assert phy_rst err %d\n", err);
90a7612d	157	goto err_restore;
fcffee3d SL	158	}
fcffee3d SL	159
90a7612d SL	160	err_out:
90a7612d SL	161	mutex_unlock(&rk_phy->pcie_mutex);
fcffee3d	162	return 0;
90a7612d SL	163
	164	err_restore:
	165	rk_phy->pwr_cnt++;
	166	regmap_write(rk_phy->reg_base,
	167	rk_phy->phy_data->pcie_laneoff,
	168	HIWORD_UPDATE(!PHY_LANE_IDLE_OFF,
	169	PHY_LANE_IDLE_MASK,
	170	PHY_LANE_IDLE_A_SHIFT + inst->index));
	171	mutex_unlock(&rk_phy->pcie_mutex);
	172	return err;
fcffee3d SL	173	}
	174
	175	static int rockchip_pcie_phy_power_on(struct phy *phy)
	176	{
90a7612d SL	177	struct phy_pcie_instance *inst = phy_get_drvdata(phy);
90a7612d SL	178	struct rockchip_pcie_phy *rk_phy = to_pcie_phy(inst);
fcffee3d SL	179	int err = 0;
	180	u32 status;
	181	unsigned long timeout;
	182
90a7612d SL	183	mutex_lock(&rk_phy->pcie_mutex);
	184
	185	if (rk_phy->pwr_cnt++)
	186	goto err_out;
	187
fcffee3d SL	188	err = reset_control_deassert(rk_phy->phy_rst);
	189	if (err) {
	190	dev_err(&phy->dev, "deassert phy_rst err %d\n", err);
90a7612d	191	goto err_pwr_cnt;
fcffee3d SL	192	}
	193
	194	regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_conf,
	195	HIWORD_UPDATE(PHY_CFG_PLL_LOCK,
	196	PHY_CFG_ADDR_MASK,
	197	PHY_CFG_ADDR_SHIFT));
	198
90a7612d SL	199	regmap_write(rk_phy->reg_base,
	200	rk_phy->phy_data->pcie_laneoff,
	201	HIWORD_UPDATE(!PHY_LANE_IDLE_OFF,
	202	PHY_LANE_IDLE_MASK,
	203	PHY_LANE_IDLE_A_SHIFT + inst->index));
	204
fcffee3d SL	205	/*
	206	* No documented timeout value for phy operation below,
	207	* so we make it large enough here. And we use loop-break
	208	* method which should not be harmful.
	209	*/
	210	timeout = jiffies + msecs_to_jiffies(1000);
	211
	212	err = -EINVAL;
	213	while (time_before(jiffies, timeout)) {
	214	regmap_read(rk_phy->reg_base,
	215	rk_phy->phy_data->pcie_status,
	216	&status);
	217	if (status & PHY_PLL_LOCKED) {
	218	dev_dbg(&phy->dev, "pll locked!\n");
	219	err = 0;
	220	break;
	221	}
	222	msleep(20);
	223	}
	224
	225	if (err) {
	226	dev_err(&phy->dev, "pll lock timeout!\n");
	227	goto err_pll_lock;
	228	}
	229
	230	phy_wr_cfg(rk_phy, PHY_CFG_CLK_TEST, PHY_CFG_SEPE_RATE);
	231	phy_wr_cfg(rk_phy, PHY_CFG_CLK_SCC, PHY_CFG_PLL_100M);
	232
	233	err = -ETIMEDOUT;
	234	while (time_before(jiffies, timeout)) {
	235	regmap_read(rk_phy->reg_base,
	236	rk_phy->phy_data->pcie_status,
	237	&status);
	238	if (!(status & PHY_PLL_OUTPUT)) {
	239	dev_dbg(&phy->dev, "pll output enable done!\n");
	240	err = 0;
	241	break;
	242	}
	243	msleep(20);
	244	}
	245
	246	if (err) {
	247	dev_err(&phy->dev, "pll output enable timeout!\n");
	248	goto err_pll_lock;
	249	}
	250
	251	regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_conf,
	252	HIWORD_UPDATE(PHY_CFG_PLL_LOCK,
	253	PHY_CFG_ADDR_MASK,
	254	PHY_CFG_ADDR_SHIFT));
	255	err = -EINVAL;
	256	while (time_before(jiffies, timeout)) {
	257	regmap_read(rk_phy->reg_base,
	258	rk_phy->phy_data->pcie_status,
	259	&status);
	260	if (status & PHY_PLL_LOCKED) {
	261	dev_dbg(&phy->dev, "pll relocked!\n");
	262	err = 0;
	263	break;
	264	}
	265	msleep(20);
	266	}
	267
	268	if (err) {
269	dev_err(&phy->dev, "pll relock timeout!\n");
270	goto err_pll_lock;
271	}
272
90a7612d SL	273	err_out:
90a7612d SL	274	mutex_unlock(&rk_phy->pcie_mutex);
fcffee3d SL	275	return 0;
	276
	277	err_pll_lock:
	278	reset_control_assert(rk_phy->phy_rst);
90a7612d SL	279	err_pwr_cnt:
	280	rk_phy->pwr_cnt--;
	281	mutex_unlock(&rk_phy->pcie_mutex);
fcffee3d SL	282	return err;
	283	}
	284
	285	static int rockchip_pcie_phy_init(struct phy *phy)
	286	{
90a7612d SL	287	struct phy_pcie_instance *inst = phy_get_drvdata(phy);
90a7612d SL	288	struct rockchip_pcie_phy *rk_phy = to_pcie_phy(inst);
fcffee3d SL	289	int err = 0;
fcffee3d SL	290
90a7612d SL	291	mutex_lock(&rk_phy->pcie_mutex);
	292
	293	if (rk_phy->init_cnt++)
	294	goto err_out;
	295
fcffee3d SL	296	err = clk_prepare_enable(rk_phy->clk_pciephy_ref);
	297	if (err) {
	298	dev_err(&phy->dev, "Fail to enable pcie ref clock.\n");
	299	goto err_refclk;
	300	}
	301
	302	err = reset_control_assert(rk_phy->phy_rst);
	303	if (err) {
	304	dev_err(&phy->dev, "assert phy_rst err %d\n", err);
	305	goto err_reset;
	306	}
	307
90a7612d SL	308	err_out:
	309	mutex_unlock(&rk_phy->pcie_mutex);
	310	return 0;
fcffee3d SL	311
fcffee3d SL	312	err_reset:
90a7612d	313
fcffee3d SL	314	clk_disable_unprepare(rk_phy->clk_pciephy_ref);
fcffee3d SL	315	err_refclk:
90a7612d SL	316	rk_phy->init_cnt--;
90a7612d SL	317	mutex_unlock(&rk_phy->pcie_mutex);
fcffee3d SL	318	return err;
	319	}
	320
	321	static int rockchip_pcie_phy_exit(struct phy *phy)
	322	{
90a7612d SL	323	struct phy_pcie_instance *inst = phy_get_drvdata(phy);
	324	struct rockchip_pcie_phy *rk_phy = to_pcie_phy(inst);
	325
	326	mutex_lock(&rk_phy->pcie_mutex);
	327
	328	if (--rk_phy->init_cnt)
	329	goto err_init_cnt;
fcffee3d SL	330
	331	clk_disable_unprepare(rk_phy->clk_pciephy_ref);
	332
90a7612d SL	333	err_init_cnt:
90a7612d SL	334	mutex_unlock(&rk_phy->pcie_mutex);
232c2609	335	return 0;
fcffee3d SL	336	}
	337
	338	static const struct phy_ops ops = {
	339	.init = rockchip_pcie_phy_init,
	340	.exit = rockchip_pcie_phy_exit,
	341	.power_on = rockchip_pcie_phy_power_on,
	342	.power_off = rockchip_pcie_phy_power_off,
	343	.owner = THIS_MODULE,
	344	};
	345
	346	static const struct rockchip_pcie_data rk3399_pcie_data = {
	347	.pcie_conf = 0xe220,
	348	.pcie_status = 0xe2a4,
	349	.pcie_laneoff = 0xe214,
	350	};
	351
	352	static const struct of_device_id rockchip_pcie_phy_dt_ids[] = {
	353	{
	354	.compatible = "rockchip,rk3399-pcie-phy",
	355	.data = &rk3399_pcie_data,
	356	},
	357	{}
	358	};
	359
	360	MODULE_DEVICE_TABLE(of, rockchip_pcie_phy_dt_ids);
	361
	362	static int rockchip_pcie_phy_probe(struct platform_device *pdev)
	363	{
	364	struct device *dev = &pdev->dev;
	365	struct rockchip_pcie_phy *rk_phy;
fcffee3d SL	366	struct phy_provider *phy_provider;
	367	struct regmap *grf;
	368	const struct of_device_id *of_id;
90a7612d SL	369	int i;
90a7612d SL	370	u32 phy_num;
fcffee3d SL	371
	372	grf = syscon_node_to_regmap(dev->parent->of_node);
	373	if (IS_ERR(grf)) {
	374	dev_err(dev, "Cannot find GRF syscon\n");
	375	return PTR_ERR(grf);
	376	}
	377
	378	rk_phy = devm_kzalloc(dev, sizeof(*rk_phy), GFP_KERNEL);
	379	if (!rk_phy)
	380	return -ENOMEM;
	381
	382	of_id = of_match_device(rockchip_pcie_phy_dt_ids, &pdev->dev);
	383	if (!of_id)
	384	return -EINVAL;
	385
	386	rk_phy->phy_data = (struct rockchip_pcie_data *)of_id->data;
	387	rk_phy->reg_base = grf;
	388
90a7612d SL	389	mutex_init(&rk_phy->pcie_mutex);
90a7612d SL	390
fcffee3d SL	391	rk_phy->phy_rst = devm_reset_control_get(dev, "phy");
	392	if (IS_ERR(rk_phy->phy_rst)) {
	393	if (PTR_ERR(rk_phy->phy_rst) != -EPROBE_DEFER)
	394	dev_err(dev,
	395	"missing phy property for reset controller\n");
	396	return PTR_ERR(rk_phy->phy_rst);
	397	}
	398
	399	rk_phy->clk_pciephy_ref = devm_clk_get(dev, "refclk");
	400	if (IS_ERR(rk_phy->clk_pciephy_ref)) {
	401	dev_err(dev, "refclk not found.\n");
	402	return PTR_ERR(rk_phy->clk_pciephy_ref);
	403	}
	404
90a7612d SL	405	/* parse #phy-cells to see if it's legacy PHY model */
	406	if (of_property_read_u32(dev->of_node, "#phy-cells", &phy_num))
	407	return -ENOENT;
	408
	409	phy_num = (phy_num == 0) ? 1 : PHY_MAX_LANE_NUM;
	410	dev_dbg(dev, "phy number is %d\n", phy_num);
	411
	412	for (i = 0; i < phy_num; i++) {
	413	rk_phy->phys[i].phy = devm_phy_create(dev, dev->of_node, &ops);
	414	if (IS_ERR(rk_phy->phys[i].phy)) {
	415	dev_err(dev, "failed to create PHY%d\n", i);
	416	return PTR_ERR(rk_phy->phys[i].phy);
	417	}
	418	rk_phy->phys[i].index = i;
	419	phy_set_drvdata(rk_phy->phys[i].phy, &rk_phy->phys[i]);
fcffee3d SL	420	}
fcffee3d SL	421
90a7612d SL	422	platform_set_drvdata(pdev, rk_phy);
	423	phy_provider = devm_of_phy_provider_register(dev,
	424	rockchip_pcie_phy_of_xlate);
fcffee3d SL	425
	426	return PTR_ERR_OR_ZERO(phy_provider);
	427	}
	428
	429	static struct platform_driver rockchip_pcie_driver = {
	430	.probe = rockchip_pcie_phy_probe,
	431	.driver = {
	432	.name = "rockchip-pcie-phy",
	433	.of_match_table = rockchip_pcie_phy_dt_ids,
	434	},
	435	};
	436
	437	module_platform_driver(rockchip_pcie_driver);
	438
	439	MODULE_AUTHOR("Shawn Lin <shawn.lin@rock-chips.com>");
	440	MODULE_DESCRIPTION("Rockchip PCIe PHY driver");
	441	MODULE_LICENSE("GPL v2");