[mirror_ubuntu-jammy-kernel.git] / drivers / phy / rockchip / phy-rockchip-usb.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Rockchip usb PHY driver
 *
 * Copyright (C) 2014 Yunzhi Li <lyz@rock-chips.com>
 * Copyright (C) 2014 ROCKCHIP, Inc.
 */

#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/regulator/consumer.h>
#include <linux/reset.h>
#include <linux/regmap.h>
#include <linux/mfd/syscon.h>
#include <linux/delay.h>

static int enable_usb_uart;

#define HIWORD_UPDATE(val, mask) \
		((val) | (mask) << 16)

#define UOC_CON0					0x00
#define UOC_CON0_SIDDQ					BIT(13)
#define UOC_CON0_DISABLE				BIT(4)
#define UOC_CON0_COMMON_ON_N				BIT(0)

#define UOC_CON2					0x08
#define UOC_CON2_SOFT_CON_SEL				BIT(2)

#define UOC_CON3					0x0c
/* bits present on rk3188 and rk3288 phys */
#define UOC_CON3_UTMI_TERMSEL_FULLSPEED			BIT(5)
#define UOC_CON3_UTMI_XCVRSEELCT_FSTRANSC		(1 << 3)
#define UOC_CON3_UTMI_XCVRSEELCT_MASK			(3 << 3)
#define UOC_CON3_UTMI_OPMODE_NODRIVING			(1 << 1)
#define UOC_CON3_UTMI_OPMODE_MASK			(3 << 1)
#define UOC_CON3_UTMI_SUSPENDN				BIT(0)

struct rockchip_usb_phys {
	int reg;
	const char *pll_name;
};

struct rockchip_usb_phy_base;
struct rockchip_usb_phy_pdata {
	struct rockchip_usb_phys *phys;
	int (*init_usb_uart)(struct regmap *grf,
			     const struct rockchip_usb_phy_pdata *pdata);
	int usb_uart_phy;
};

struct rockchip_usb_phy_base {
	struct device *dev;
	struct regmap *reg_base;
	const struct rockchip_usb_phy_pdata *pdata;
};

struct rockchip_usb_phy {
	struct rockchip_usb_phy_base *base;
	struct device_node *np;
	unsigned int	reg_offset;
	struct clk	*clk;
	struct clk      *clk480m;
	struct clk_hw	clk480m_hw;
	struct phy	*phy;
	bool		uart_enabled;
	struct reset_control *reset;
	struct regulator *vbus;
};

static int rockchip_usb_phy_power(struct rockchip_usb_phy *phy,
					   bool siddq)
{
	u32 val = HIWORD_UPDATE(siddq ? UOC_CON0_SIDDQ : 0, UOC_CON0_SIDDQ);

	return regmap_write(phy->base->reg_base, phy->reg_offset, val);
}

static unsigned long rockchip_usb_phy480m_recalc_rate(struct clk_hw *hw,
						unsigned long parent_rate)
{
	return 480000000;
}

static void rockchip_usb_phy480m_disable(struct clk_hw *hw)
{
	struct rockchip_usb_phy *phy = container_of(hw,
						    struct rockchip_usb_phy,
						    clk480m_hw);

	if (phy->vbus)
		regulator_disable(phy->vbus);

	/* Power down usb phy analog blocks by set siddq 1 */
	rockchip_usb_phy_power(phy, 1);
}

static int rockchip_usb_phy480m_enable(struct clk_hw *hw)
{
	struct rockchip_usb_phy *phy = container_of(hw,
						    struct rockchip_usb_phy,
						    clk480m_hw);

	/* Power up usb phy analog blocks by set siddq 0 */
	return rockchip_usb_phy_power(phy, 0);
}

static int rockchip_usb_phy480m_is_enabled(struct clk_hw *hw)
{
	struct rockchip_usb_phy *phy = container_of(hw,
						    struct rockchip_usb_phy,
						    clk480m_hw);
	int ret;
	u32 val;

	ret = regmap_read(phy->base->reg_base, phy->reg_offset, &val);
	if (ret < 0)
		return ret;

	return (val & UOC_CON0_SIDDQ) ? 0 : 1;
}

static const struct clk_ops rockchip_usb_phy480m_ops = {
	.enable = rockchip_usb_phy480m_enable,
	.disable = rockchip_usb_phy480m_disable,
	.is_enabled = rockchip_usb_phy480m_is_enabled,
	.recalc_rate = rockchip_usb_phy480m_recalc_rate,
};

static int rockchip_usb_phy_power_off(struct phy *_phy)
{
	struct rockchip_usb_phy *phy = phy_get_drvdata(_phy);

	if (phy->uart_enabled)
		return -EBUSY;

	clk_disable_unprepare(phy->clk480m);

	return 0;
}

static int rockchip_usb_phy_power_on(struct phy *_phy)
{
	struct rockchip_usb_phy *phy = phy_get_drvdata(_phy);

	if (phy->uart_enabled)
		return -EBUSY;

	if (phy->vbus) {
		int ret;

		ret = regulator_enable(phy->vbus);
		if (ret)
			return ret;
	}

	return clk_prepare_enable(phy->clk480m);
}

static int rockchip_usb_phy_reset(struct phy *_phy)
{
	struct rockchip_usb_phy *phy = phy_get_drvdata(_phy);

	if (phy->reset) {
		reset_control_assert(phy->reset);
		udelay(10);
		reset_control_deassert(phy->reset);
	}

	return 0;
}

static const struct phy_ops ops = {
	.power_on	= rockchip_usb_phy_power_on,
	.power_off	= rockchip_usb_phy_power_off,
	.reset		= rockchip_usb_phy_reset,
	.owner		= THIS_MODULE,
};

static void rockchip_usb_phy_action(void *data)
{
	struct rockchip_usb_phy *rk_phy = data;

	if (!rk_phy->uart_enabled) {
		of_clk_del_provider(rk_phy->np);
		clk_unregister(rk_phy->clk480m);
	}

	if (rk_phy->clk)
		clk_put(rk_phy->clk);
}

static int rockchip_usb_phy_init(struct rockchip_usb_phy_base *base,
				 struct device_node *child)
{
	struct rockchip_usb_phy *rk_phy;
	unsigned int reg_offset;
	const char *clk_name;
	struct clk_init_data init;
	int err, i;

	rk_phy = devm_kzalloc(base->dev, sizeof(*rk_phy), GFP_KERNEL);
	if (!rk_phy)
		return -ENOMEM;

	rk_phy->base = base;
	rk_phy->np = child;

	if (of_property_read_u32(child, "reg", &reg_offset)) {
		dev_err(base->dev, "missing reg property in node %pOFn\n",
			child);
		return -EINVAL;
	}

	rk_phy->reset = of_reset_control_get(child, "phy-reset");
	if (IS_ERR(rk_phy->reset))
		rk_phy->reset = NULL;

	rk_phy->reg_offset = reg_offset;

	rk_phy->clk = of_clk_get_by_name(child, "phyclk");
	if (IS_ERR(rk_phy->clk))
		rk_phy->clk = NULL;

	i = 0;
	init.name = NULL;
	while (base->pdata->phys[i].reg) {
		if (base->pdata->phys[i].reg == reg_offset) {
			init.name = base->pdata->phys[i].pll_name;
			break;
		}
		i++;
	}

	if (!init.name) {
		dev_err(base->dev, "phy data not found\n");
		return -EINVAL;
	}

	if (enable_usb_uart && base->pdata->usb_uart_phy == i) {
		dev_dbg(base->dev, "phy%d used as uart output\n", i);
		rk_phy->uart_enabled = true;
	} else {
		if (rk_phy->clk) {
			clk_name = __clk_get_name(rk_phy->clk);
			init.flags = 0;
			init.parent_names = &clk_name;
			init.num_parents = 1;
		} else {
			init.flags = 0;
			init.parent_names = NULL;
			init.num_parents = 0;
		}

		init.ops = &rockchip_usb_phy480m_ops;
		rk_phy->clk480m_hw.init = &init;

		rk_phy->clk480m = clk_register(base->dev, &rk_phy->clk480m_hw);
		if (IS_ERR(rk_phy->clk480m)) {
			err = PTR_ERR(rk_phy->clk480m);
			goto err_clk;
		}

		err = of_clk_add_provider(child, of_clk_src_simple_get,
					rk_phy->clk480m);
		if (err < 0)
			goto err_clk_prov;
	}

	err = devm_add_action_or_reset(base->dev, rockchip_usb_phy_action,
				       rk_phy);
	if (err)
		return err;

	rk_phy->phy = devm_phy_create(base->dev, child, &ops);
	if (IS_ERR(rk_phy->phy)) {
		dev_err(base->dev, "failed to create PHY\n");
		return PTR_ERR(rk_phy->phy);
	}
	phy_set_drvdata(rk_phy->phy, rk_phy);

	rk_phy->vbus = devm_regulator_get_optional(&rk_phy->phy->dev, "vbus");
	if (IS_ERR(rk_phy->vbus)) {
		if (PTR_ERR(rk_phy->vbus) == -EPROBE_DEFER)
			return PTR_ERR(rk_phy->vbus);
		rk_phy->vbus = NULL;
	}

	/*
	 * When acting as uart-pipe, just keep clock on otherwise
	 * only power up usb phy when it use, so disable it when init
	 */
	if (rk_phy->uart_enabled)
		return clk_prepare_enable(rk_phy->clk);
	else
		return rockchip_usb_phy_power(rk_phy, 1);

err_clk_prov:
	if (!rk_phy->uart_enabled)
		clk_unregister(rk_phy->clk480m);
err_clk:
	if (rk_phy->clk)
		clk_put(rk_phy->clk);
	return err;
}

static const struct rockchip_usb_phy_pdata rk3066a_pdata = {
	.phys = (struct rockchip_usb_phys[]){
		{ .reg = 0x17c, .pll_name = "sclk_otgphy0_480m" },
		{ .reg = 0x188, .pll_name = "sclk_otgphy1_480m" },
		{ /* sentinel */ }
	},
};

static int __init rockchip_init_usb_uart_common(struct regmap *grf,
				const struct rockchip_usb_phy_pdata *pdata)
{
	int regoffs = pdata->phys[pdata->usb_uart_phy].reg;
	int ret;
	u32 val;

	/*
	 * COMMON_ON and DISABLE settings are described in the TRM,
	 * but were not present in the original code.
	 * Also disable the analog phy components to save power.
	 */
	val = HIWORD_UPDATE(UOC_CON0_COMMON_ON_N
				| UOC_CON0_DISABLE
				| UOC_CON0_SIDDQ,
			    UOC_CON0_COMMON_ON_N
				| UOC_CON0_DISABLE
				| UOC_CON0_SIDDQ);
	ret = regmap_write(grf, regoffs + UOC_CON0, val);
	if (ret)
		return ret;

	val = HIWORD_UPDATE(UOC_CON2_SOFT_CON_SEL,
			    UOC_CON2_SOFT_CON_SEL);
	ret = regmap_write(grf, regoffs + UOC_CON2, val);
	if (ret)
		return ret;

	val = HIWORD_UPDATE(UOC_CON3_UTMI_OPMODE_NODRIVING
				| UOC_CON3_UTMI_XCVRSEELCT_FSTRANSC
				| UOC_CON3_UTMI_TERMSEL_FULLSPEED,
			    UOC_CON3_UTMI_SUSPENDN
				| UOC_CON3_UTMI_OPMODE_MASK
				| UOC_CON3_UTMI_XCVRSEELCT_MASK
				| UOC_CON3_UTMI_TERMSEL_FULLSPEED);
	ret = regmap_write(grf, UOC_CON3, val);
	if (ret)
		return ret;

	return 0;
}

#define RK3188_UOC0_CON0				0x10c
#define RK3188_UOC0_CON0_BYPASSSEL			BIT(9)
#define RK3188_UOC0_CON0_BYPASSDMEN			BIT(8)

/*
 * Enable the bypass of uart2 data through the otg usb phy.
 * See description of rk3288-variant for details.
 */
static int __init rk3188_init_usb_uart(struct regmap *grf,
				const struct rockchip_usb_phy_pdata *pdata)
{
	u32 val;
	int ret;

	ret = rockchip_init_usb_uart_common(grf, pdata);
	if (ret)
		return ret;

	val = HIWORD_UPDATE(RK3188_UOC0_CON0_BYPASSSEL
				| RK3188_UOC0_CON0_BYPASSDMEN,
			    RK3188_UOC0_CON0_BYPASSSEL
				| RK3188_UOC0_CON0_BYPASSDMEN);
	ret = regmap_write(grf, RK3188_UOC0_CON0, val);
	if (ret)
		return ret;

	return 0;
}

static const struct rockchip_usb_phy_pdata rk3188_pdata = {
	.phys = (struct rockchip_usb_phys[]){
		{ .reg = 0x10c, .pll_name = "sclk_otgphy0_480m" },
		{ .reg = 0x11c, .pll_name = "sclk_otgphy1_480m" },
		{ /* sentinel */ }
	},
	.init_usb_uart = rk3188_init_usb_uart,
	.usb_uart_phy = 0,
};

#define RK3288_UOC0_CON3				0x32c
#define RK3288_UOC0_CON3_BYPASSDMEN			BIT(6)
#define RK3288_UOC0_CON3_BYPASSSEL			BIT(7)

/*
 * Enable the bypass of uart2 data through the otg usb phy.
 * Original description in the TRM.
 * 1. Disable the OTG block by setting OTGDISABLE0 to 1’b1.
 * 2. Disable the pull-up resistance on the D+ line by setting
 *    OPMODE0[1:0] to 2’b01.
 * 3. To ensure that the XO, Bias, and PLL blocks are powered down in Suspend
 *    mode, set COMMONONN to 1’b1.
 * 4. Place the USB PHY in Suspend mode by setting SUSPENDM0 to 1’b0.
 * 5. Set BYPASSSEL0 to 1’b1.
 * 6. To transmit data, controls BYPASSDMEN0, and BYPASSDMDATA0.
 * To receive data, monitor FSVPLUS0.
 *
 * The actual code in the vendor kernel does some things differently.
 */
static int __init rk3288_init_usb_uart(struct regmap *grf,
				const struct rockchip_usb_phy_pdata *pdata)
{
	u32 val;
	int ret;

	ret = rockchip_init_usb_uart_common(grf, pdata);
	if (ret)
		return ret;

	val = HIWORD_UPDATE(RK3288_UOC0_CON3_BYPASSSEL
				| RK3288_UOC0_CON3_BYPASSDMEN,
			    RK3288_UOC0_CON3_BYPASSSEL
				| RK3288_UOC0_CON3_BYPASSDMEN);
	ret = regmap_write(grf, RK3288_UOC0_CON3, val);
	if (ret)
		return ret;

	return 0;
}

static const struct rockchip_usb_phy_pdata rk3288_pdata = {
	.phys = (struct rockchip_usb_phys[]){
		{ .reg = 0x320, .pll_name = "sclk_otgphy0_480m" },
		{ .reg = 0x334, .pll_name = "sclk_otgphy1_480m" },
		{ .reg = 0x348, .pll_name = "sclk_otgphy2_480m" },
		{ /* sentinel */ }
	},
	.init_usb_uart = rk3288_init_usb_uart,
	.usb_uart_phy = 0,
};

static int rockchip_usb_phy_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct rockchip_usb_phy_base *phy_base;
	struct phy_provider *phy_provider;
	const struct of_device_id *match;
	struct device_node *child;
	int err;

	phy_base = devm_kzalloc(dev, sizeof(*phy_base), GFP_KERNEL);
	if (!phy_base)
		return -ENOMEM;

	match = of_match_device(dev->driver->of_match_table, dev);
	if (!match || !match->data) {
		dev_err(dev, "missing phy data\n");
		return -EINVAL;
	}

	phy_base->pdata = match->data;

	phy_base->dev = dev;
	phy_base->reg_base = ERR_PTR(-ENODEV);
	if (dev->parent && dev->parent->of_node)
		phy_base->reg_base = syscon_node_to_regmap(
						dev->parent->of_node);
	if (IS_ERR(phy_base->reg_base))
		phy_base->reg_base = syscon_regmap_lookup_by_phandle(
						dev->of_node, "rockchip,grf");
	if (IS_ERR(phy_base->reg_base)) {
		dev_err(&pdev->dev, "Missing rockchip,grf property\n");
		return PTR_ERR(phy_base->reg_base);
	}

	for_each_available_child_of_node(dev->of_node, child) {
		err = rockchip_usb_phy_init(phy_base, child);
		if (err) {
			of_node_put(child);
			return err;
		}
	}

	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
	return PTR_ERR_OR_ZERO(phy_provider);
}

static const struct of_device_id rockchip_usb_phy_dt_ids[] = {
	{ .compatible = "rockchip,rk3066a-usb-phy", .data = &rk3066a_pdata },
	{ .compatible = "rockchip,rk3188-usb-phy", .data = &rk3188_pdata },
	{ .compatible = "rockchip,rk3288-usb-phy", .data = &rk3288_pdata },
	{}
};

MODULE_DEVICE_TABLE(of, rockchip_usb_phy_dt_ids);

static struct platform_driver rockchip_usb_driver = {
	.probe		= rockchip_usb_phy_probe,
	.driver		= {
		.name	= "rockchip-usb-phy",
		.of_match_table = rockchip_usb_phy_dt_ids,
	},
};

module_platform_driver(rockchip_usb_driver);

#ifndef MODULE
static int __init rockchip_init_usb_uart(void)
{
	const struct of_device_id *match;
	const struct rockchip_usb_phy_pdata *data;
	struct device_node *np;
	struct regmap *grf;
	int ret;

	if (!enable_usb_uart)
		return 0;

	np = of_find_matching_node_and_match(NULL, rockchip_usb_phy_dt_ids,
					     &match);
	if (!np) {
		pr_err("%s: failed to find usbphy node\n", __func__);
		return -ENOTSUPP;
	}

	pr_debug("%s: using settings for %s\n", __func__, match->compatible);
	data = match->data;

	if (!data->init_usb_uart) {
		pr_err("%s: usb-uart not available on %s\n",
		       __func__, match->compatible);
		return -ENOTSUPP;
	}

	grf = ERR_PTR(-ENODEV);
	if (np->parent)
		grf = syscon_node_to_regmap(np->parent);
	if (IS_ERR(grf))
		grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
	if (IS_ERR(grf)) {
		pr_err("%s: Missing rockchip,grf property, %lu\n",
		       __func__, PTR_ERR(grf));
		return PTR_ERR(grf);
	}

	ret = data->init_usb_uart(grf, data);
	if (ret) {
		pr_err("%s: could not init usb_uart, %d\n", __func__, ret);
		enable_usb_uart = 0;
		return ret;
	}

	return 0;
}
early_initcall(rockchip_init_usb_uart);

static int __init rockchip_usb_uart(char *buf)
{
	enable_usb_uart = true;
	return 0;
}
early_param("rockchip.usb_uart", rockchip_usb_uart);
#endif

MODULE_AUTHOR("Yunzhi Li <lyz@rock-chips.com>");
MODULE_DESCRIPTION("Rockchip USB 2.0 PHY driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
2504ba9f	1	// SPDX-License-Identifier: GPL-2.0-only
64d11406 YL	2	/*
	3	* Rockchip usb PHY driver
	4	*
	5	* Copyright (C) 2014 Yunzhi Li <lyz@rock-chips.com>
	6	* Copyright (C) 2014 ROCKCHIP, Inc.
64d11406 YL	7	*/
	8
	9	#include <linux/clk.h>
b74fe7c7	10	#include <linux/clk-provider.h>
64d11406 YL	11	#include <linux/io.h>
	12	#include <linux/kernel.h>
	13	#include <linux/module.h>
	14	#include <linux/mutex.h>
	15	#include <linux/of.h>
	16	#include <linux/of_address.h>
b74fe7c7	17	#include <linux/of_platform.h>
64d11406 YL	18	#include <linux/phy/phy.h>
	19	#include <linux/platform_device.h>
	20	#include <linux/regulator/consumer.h>
	21	#include <linux/reset.h>
	22	#include <linux/regmap.h>
	23	#include <linux/mfd/syscon.h>
0f74ab59	24	#include <linux/delay.h>
64d11406	25
605df8af HS	26	static int enable_usb_uart;
	27
	28	#define HIWORD_UPDATE(val, mask) \
	29	((val) \| (mask) << 16)
	30
63bd0f19 HS	31	#define UOC_CON0 0x00
	32	#define UOC_CON0_SIDDQ BIT(13)
	33	#define UOC_CON0_DISABLE BIT(4)
	34	#define UOC_CON0_COMMON_ON_N BIT(0)
	35
	36	#define UOC_CON2 0x08
	37	#define UOC_CON2_SOFT_CON_SEL BIT(2)
	38
	39	#define UOC_CON3 0x0c
	40	/* bits present on rk3188 and rk3288 phys */
	41	#define UOC_CON3_UTMI_TERMSEL_FULLSPEED BIT(5)
	42	#define UOC_CON3_UTMI_XCVRSEELCT_FSTRANSC (1 << 3)
	43	#define UOC_CON3_UTMI_XCVRSEELCT_MASK (3 << 3)
	44	#define UOC_CON3_UTMI_OPMODE_NODRIVING (1 << 1)
	45	#define UOC_CON3_UTMI_OPMODE_MASK (3 << 1)
	46	#define UOC_CON3_UTMI_SUSPENDN BIT(0)
64d11406	47
b74fe7c7 HS	48	struct rockchip_usb_phys {
	49	int reg;
	50	const char *pll_name;
	51	};
	52
605df8af	53	struct rockchip_usb_phy_base;
b74fe7c7 HS	54	struct rockchip_usb_phy_pdata {
b74fe7c7 HS	55	struct rockchip_usb_phys *phys;
63bd0f19 HS	56	int (init_usb_uart)(struct regmap grf,
63bd0f19 HS	57	const struct rockchip_usb_phy_pdata *pdata);
605df8af	58	int usb_uart_phy;
b74fe7c7 HS	59	};
b74fe7c7 HS	60
5fdbb97d HS	61	struct rockchip_usb_phy_base {
	62	struct device *dev;
	63	struct regmap *reg_base;
b74fe7c7	64	const struct rockchip_usb_phy_pdata *pdata;
5fdbb97d HS	65	};
5fdbb97d HS	66
64d11406	67	struct rockchip_usb_phy {
5fdbb97d	68	struct rockchip_usb_phy_base *base;
b74fe7c7	69	struct device_node *np;
64d11406	70	unsigned int reg_offset;
64d11406	71	struct clk *clk;
b74fe7c7 HS	72	struct clk *clk480m;
b74fe7c7 HS	73	struct clk_hw clk480m_hw;
64d11406	74	struct phy *phy;
605df8af	75	bool uart_enabled;
0f74ab59	76	struct reset_control *reset;
9d685ed7	77	struct regulator *vbus;
64d11406 YL	78	};
	79
	80	static int rockchip_usb_phy_power(struct rockchip_usb_phy *phy,
	81	bool siddq)
	82	{
605df8af HS	83	u32 val = HIWORD_UPDATE(siddq ? UOC_CON0_SIDDQ : 0, UOC_CON0_SIDDQ);
	84
	85	return regmap_write(phy->base->reg_base, phy->reg_offset, val);
64d11406 YL	86	}
64d11406 YL	87
b74fe7c7 HS	88	static unsigned long rockchip_usb_phy480m_recalc_rate(struct clk_hw *hw,
b74fe7c7 HS	89	unsigned long parent_rate)
64d11406	90	{
b74fe7c7 HS	91	return 480000000;
	92	}
	93
	94	static void rockchip_usb_phy480m_disable(struct clk_hw *hw)
	95	{
	96	struct rockchip_usb_phy *phy = container_of(hw,
	97	struct rockchip_usb_phy,
	98	clk480m_hw);
64d11406	99
9d685ed7 SS	100	if (phy->vbus)
	101	regulator_disable(phy->vbus);
	102
64d11406	103	/* Power down usb phy analog blocks by set siddq 1 */
b74fe7c7 HS	104	rockchip_usb_phy_power(phy, 1);
	105	}
	106
	107	static int rockchip_usb_phy480m_enable(struct clk_hw *hw)
	108	{
	109	struct rockchip_usb_phy *phy = container_of(hw,
	110	struct rockchip_usb_phy,
	111	clk480m_hw);
	112
	113	/* Power up usb phy analog blocks by set siddq 0 */
	114	return rockchip_usb_phy_power(phy, 0);
	115	}
	116
	117	static int rockchip_usb_phy480m_is_enabled(struct clk_hw *hw)
	118	{
	119	struct rockchip_usb_phy *phy = container_of(hw,
	120	struct rockchip_usb_phy,
	121	clk480m_hw);
	122	int ret;
	123	u32 val;
	124
	125	ret = regmap_read(phy->base->reg_base, phy->reg_offset, &val);
	126	if (ret < 0)
64d11406 YL	127	return ret;
64d11406 YL	128
605df8af	129	return (val & UOC_CON0_SIDDQ) ? 0 : 1;
b74fe7c7 HS	130	}
	131
	132	static const struct clk_ops rockchip_usb_phy480m_ops = {
	133	.enable = rockchip_usb_phy480m_enable,
	134	.disable = rockchip_usb_phy480m_disable,
	135	.is_enabled = rockchip_usb_phy480m_is_enabled,
	136	.recalc_rate = rockchip_usb_phy480m_recalc_rate,
	137	};
	138
	139	static int rockchip_usb_phy_power_off(struct phy *_phy)
	140	{
	141	struct rockchip_usb_phy *phy = phy_get_drvdata(_phy);
	142
605df8af HS	143	if (phy->uart_enabled)
	144	return -EBUSY;
	145
b74fe7c7	146	clk_disable_unprepare(phy->clk480m);
64d11406 YL	147
	148	return 0;
	149	}
	150
	151	static int rockchip_usb_phy_power_on(struct phy *_phy)
	152	{
	153	struct rockchip_usb_phy *phy = phy_get_drvdata(_phy);
64d11406	154
605df8af HS	155	if (phy->uart_enabled)
	156	return -EBUSY;
	157
9d685ed7 SS	158	if (phy->vbus) {
	159	int ret;
	160
	161	ret = regulator_enable(phy->vbus);
	162	if (ret)
	163	return ret;
	164	}
	165
b74fe7c7	166	return clk_prepare_enable(phy->clk480m);
64d11406 YL	167	}
64d11406 YL	168
0f74ab59 RL	169	static int rockchip_usb_phy_reset(struct phy *_phy)
	170	{
	171	struct rockchip_usb_phy *phy = phy_get_drvdata(_phy);
	172
	173	if (phy->reset) {
	174	reset_control_assert(phy->reset);
	175	udelay(10);
	176	reset_control_deassert(phy->reset);
	177	}
	178
	179	return 0;
	180	}
	181
4a9e5ca1	182	static const struct phy_ops ops = {
64d11406 YL	183	.power_on = rockchip_usb_phy_power_on,
64d11406 YL	184	.power_off = rockchip_usb_phy_power_off,
0f74ab59	185	.reset = rockchip_usb_phy_reset,
64d11406 YL	186	.owner = THIS_MODULE,
	187	};
	188
75d390fe HS	189	static void rockchip_usb_phy_action(void *data)
	190	{
	191	struct rockchip_usb_phy *rk_phy = data;
	192
605df8af HS	193	if (!rk_phy->uart_enabled) {
	194	of_clk_del_provider(rk_phy->np);
	195	clk_unregister(rk_phy->clk480m);
	196	}
b74fe7c7	197
75d390fe HS	198	if (rk_phy->clk)
	199	clk_put(rk_phy->clk);
	200	}
	201
97dd9101 HS	202	static int rockchip_usb_phy_init(struct rockchip_usb_phy_base *base,
	203	struct device_node *child)
	204	{
	205	struct rockchip_usb_phy *rk_phy;
	206	unsigned int reg_offset;
b74fe7c7 HS	207	const char *clk_name;
	208	struct clk_init_data init;
	209	int err, i;
97dd9101 HS	210
	211	rk_phy = devm_kzalloc(base->dev, sizeof(*rk_phy), GFP_KERNEL);
	212	if (!rk_phy)
	213	return -ENOMEM;
	214
	215	rk_phy->base = base;
b74fe7c7	216	rk_phy->np = child;
97dd9101 HS	217
97dd9101 HS	218	if (of_property_read_u32(child, "reg", &reg_offset)) {
ac9ba7dc RH	219	dev_err(base->dev, "missing reg property in node %pOFn\n",
ac9ba7dc RH	220	child);
97dd9101 HS	221	return -EINVAL;
	222	}
	223
0f74ab59 RL	224	rk_phy->reset = of_reset_control_get(child, "phy-reset");
	225	if (IS_ERR(rk_phy->reset))
	226	rk_phy->reset = NULL;
	227
97dd9101 HS	228	rk_phy->reg_offset = reg_offset;
97dd9101 HS	229
97dd9101 HS	230	rk_phy->clk = of_clk_get_by_name(child, "phyclk");
	231	if (IS_ERR(rk_phy->clk))
	232	rk_phy->clk = NULL;
	233
b74fe7c7 HS	234	i = 0;
	235	init.name = NULL;
	236	while (base->pdata->phys[i].reg) {
	237	if (base->pdata->phys[i].reg == reg_offset) {
	238	init.name = base->pdata->phys[i].pll_name;
	239	break;
	240	}
	241	i++;
	242	}
	243
	244	if (!init.name) {
	245	dev_err(base->dev, "phy data not found\n");
	246	return -EINVAL;
	247	}
	248
605df8af HS	249	if (enable_usb_uart && base->pdata->usb_uart_phy == i) {
	250	dev_dbg(base->dev, "phy%d used as uart output\n", i);
	251	rk_phy->uart_enabled = true;
b74fe7c7	252	} else {
605df8af HS	253	if (rk_phy->clk) {
	254	clk_name = __clk_get_name(rk_phy->clk);
	255	init.flags = 0;
	256	init.parent_names = &clk_name;
	257	init.num_parents = 1;
	258	} else {
444525d4	259	init.flags = 0;
605df8af HS	260	init.parent_names = NULL;
	261	init.num_parents = 0;
	262	}
b74fe7c7	263
605df8af HS	264	init.ops = &rockchip_usb_phy480m_ops;
605df8af HS	265	rk_phy->clk480m_hw.init = &init;
b74fe7c7	266
605df8af HS	267	rk_phy->clk480m = clk_register(base->dev, &rk_phy->clk480m_hw);
	268	if (IS_ERR(rk_phy->clk480m)) {
	269	err = PTR_ERR(rk_phy->clk480m);
	270	goto err_clk;
	271	}
b74fe7c7	272
605df8af HS	273	err = of_clk_add_provider(child, of_clk_src_simple_get,
	274	rk_phy->clk480m);
	275	if (err < 0)
	276	goto err_clk_prov;
	277	}
b74fe7c7	278
d33fb008 SM	279	err = devm_add_action_or_reset(base->dev, rockchip_usb_phy_action,
d33fb008 SM	280	rk_phy);
b74fe7c7	281	if (err)
d33fb008	282	return err;
b74fe7c7	283
97dd9101 HS	284	rk_phy->phy = devm_phy_create(base->dev, child, &ops);
	285	if (IS_ERR(rk_phy->phy)) {
	286	dev_err(base->dev, "failed to create PHY\n");
	287	return PTR_ERR(rk_phy->phy);
	288	}
	289	phy_set_drvdata(rk_phy->phy, rk_phy);
	290
9d685ed7 SS	291	rk_phy->vbus = devm_regulator_get_optional(&rk_phy->phy->dev, "vbus");
	292	if (IS_ERR(rk_phy->vbus)) {
	293	if (PTR_ERR(rk_phy->vbus) == -EPROBE_DEFER)
	294	return PTR_ERR(rk_phy->vbus);
	295	rk_phy->vbus = NULL;
	296	}
	297
605df8af HS	298	/*
	299	* When acting as uart-pipe, just keep clock on otherwise
	300	* only power up usb phy when it use, so disable it when init
	301	*/
	302	if (rk_phy->uart_enabled)
	303	return clk_prepare_enable(rk_phy->clk);
	304	else
	305	return rockchip_usb_phy_power(rk_phy, 1);
b74fe7c7	306
b74fe7c7	307	err_clk_prov:
605df8af HS	308	if (!rk_phy->uart_enabled)
605df8af HS	309	clk_unregister(rk_phy->clk480m);
b74fe7c7 HS	310	err_clk:
	311	if (rk_phy->clk)
	312	clk_put(rk_phy->clk);
	313	return err;
97dd9101 HS	314	}
97dd9101 HS	315
b74fe7c7 HS	316	static const struct rockchip_usb_phy_pdata rk3066a_pdata = {
	317	.phys = (struct rockchip_usb_phys[]){
	318	{ .reg = 0x17c, .pll_name = "sclk_otgphy0_480m" },
	319	{ .reg = 0x188, .pll_name = "sclk_otgphy1_480m" },
	320	{ /* sentinel */ }
	321	},
	322	};
	323
63bd0f19 HS	324	static int __init rockchip_init_usb_uart_common(struct regmap *grf,
	325	const struct rockchip_usb_phy_pdata *pdata)
	326	{
	327	int regoffs = pdata->phys[pdata->usb_uart_phy].reg;
	328	int ret;
	329	u32 val;
	330
	331	/*
	332	* COMMON_ON and DISABLE settings are described in the TRM,
	333	* but were not present in the original code.
	334	* Also disable the analog phy components to save power.
	335	*/
	336	val = HIWORD_UPDATE(UOC_CON0_COMMON_ON_N
	337	\| UOC_CON0_DISABLE
	338	\| UOC_CON0_SIDDQ,
	339	UOC_CON0_COMMON_ON_N
	340	\| UOC_CON0_DISABLE
	341	\| UOC_CON0_SIDDQ);
	342	ret = regmap_write(grf, regoffs + UOC_CON0, val);
	343	if (ret)
	344	return ret;
	345
	346	val = HIWORD_UPDATE(UOC_CON2_SOFT_CON_SEL,
	347	UOC_CON2_SOFT_CON_SEL);
	348	ret = regmap_write(grf, regoffs + UOC_CON2, val);
	349	if (ret)
	350	return ret;
	351
	352	val = HIWORD_UPDATE(UOC_CON3_UTMI_OPMODE_NODRIVING
	353	\| UOC_CON3_UTMI_XCVRSEELCT_FSTRANSC
	354	\| UOC_CON3_UTMI_TERMSEL_FULLSPEED,
	355	UOC_CON3_UTMI_SUSPENDN
	356	\| UOC_CON3_UTMI_OPMODE_MASK
	357	\| UOC_CON3_UTMI_XCVRSEELCT_MASK
	358	\| UOC_CON3_UTMI_TERMSEL_FULLSPEED);
	359	ret = regmap_write(grf, UOC_CON3, val);
	360	if (ret)
	361	return ret;
	362
	363	return 0;
	364	}
	365
	366	#define RK3188_UOC0_CON0 0x10c
	367	#define RK3188_UOC0_CON0_BYPASSSEL BIT(9)
	368	#define RK3188_UOC0_CON0_BYPASSDMEN BIT(8)
	369
	370	/*
	371	* Enable the bypass of uart2 data through the otg usb phy.
	372	* See description of rk3288-variant for details.
	373	*/
	374	static int __init rk3188_init_usb_uart(struct regmap *grf,
	375	const struct rockchip_usb_phy_pdata *pdata)
	376	{
	377	u32 val;
	378	int ret;
	379
	380	ret = rockchip_init_usb_uart_common(grf, pdata);
	381	if (ret)
	382	return ret;
	383
	384	val = HIWORD_UPDATE(RK3188_UOC0_CON0_BYPASSSEL
	385	\| RK3188_UOC0_CON0_BYPASSDMEN,
	386	RK3188_UOC0_CON0_BYPASSSEL
	387	\| RK3188_UOC0_CON0_BYPASSDMEN);
388	ret = regmap_write(grf, RK3188_UOC0_CON0, val);
389	if (ret)
390	return ret;
391
392	return 0;
393	}
394
b74fe7c7 HS	395	static const struct rockchip_usb_phy_pdata rk3188_pdata = {
	396	.phys = (struct rockchip_usb_phys[]){
	397	{ .reg = 0x10c, .pll_name = "sclk_otgphy0_480m" },
	398	{ .reg = 0x11c, .pll_name = "sclk_otgphy1_480m" },
	399	{ /* sentinel */ }
	400	},
63bd0f19 HS	401	.init_usb_uart = rk3188_init_usb_uart,
63bd0f19 HS	402	.usb_uart_phy = 0,
b74fe7c7 HS	403	};
b74fe7c7 HS	404
605df8af	405	#define RK3288_UOC0_CON3 0x32c
605df8af HS	406	#define RK3288_UOC0_CON3_BYPASSDMEN BIT(6)
	407	#define RK3288_UOC0_CON3_BYPASSSEL BIT(7)
	408
	409	/*
	410	* Enable the bypass of uart2 data through the otg usb phy.
	411	* Original description in the TRM.
	412	* 1. Disable the OTG block by setting OTGDISABLE0 to 1’b1.
	413	* 2. Disable the pull-up resistance on the D+ line by setting
	414	* OPMODE0[1:0] to 2’b01.
	415	* 3. To ensure that the XO, Bias, and PLL blocks are powered down in Suspend
	416	* mode, set COMMONONN to 1’b1.
	417	* 4. Place the USB PHY in Suspend mode by setting SUSPENDM0 to 1’b0.
	418	* 5. Set BYPASSSEL0 to 1’b1.
	419	* 6. To transmit data, controls BYPASSDMEN0, and BYPASSDMDATA0.
	420	* To receive data, monitor FSVPLUS0.
	421	*
	422	* The actual code in the vendor kernel does some things differently.
	423	*/
63bd0f19 HS	424	static int __init rk3288_init_usb_uart(struct regmap *grf,
63bd0f19 HS	425	const struct rockchip_usb_phy_pdata *pdata)
605df8af HS	426	{
	427	u32 val;
	428	int ret;
	429
63bd0f19	430	ret = rockchip_init_usb_uart_common(grf, pdata);
605df8af HS	431	if (ret)
	432	return ret;
	433
	434	val = HIWORD_UPDATE(RK3288_UOC0_CON3_BYPASSSEL
	435	\| RK3288_UOC0_CON3_BYPASSDMEN,
	436	RK3288_UOC0_CON3_BYPASSSEL
	437	\| RK3288_UOC0_CON3_BYPASSDMEN);
	438	ret = regmap_write(grf, RK3288_UOC0_CON3, val);
	439	if (ret)
	440	return ret;
	441
	442	return 0;
	443	}
	444
b74fe7c7 HS	445	static const struct rockchip_usb_phy_pdata rk3288_pdata = {
	446	.phys = (struct rockchip_usb_phys[]){
	447	{ .reg = 0x320, .pll_name = "sclk_otgphy0_480m" },
	448	{ .reg = 0x334, .pll_name = "sclk_otgphy1_480m" },
	449	{ .reg = 0x348, .pll_name = "sclk_otgphy2_480m" },
	450	{ /* sentinel */ }
	451	},
605df8af HS	452	.init_usb_uart = rk3288_init_usb_uart,
605df8af HS	453	.usb_uart_phy = 0,
b74fe7c7 HS	454	};
b74fe7c7 HS	455
64d11406 YL	456	static int rockchip_usb_phy_probe(struct platform_device *pdev)
	457	{
	458	struct device *dev = &pdev->dev;
5fdbb97d	459	struct rockchip_usb_phy_base *phy_base;
64d11406	460	struct phy_provider *phy_provider;
b74fe7c7	461	const struct of_device_id *match;
64d11406	462	struct device_node *child;
08db7e5c	463	int err;
64d11406	464
5fdbb97d HS	465	phy_base = devm_kzalloc(dev, sizeof(*phy_base), GFP_KERNEL);
	466	if (!phy_base)
	467	return -ENOMEM;
	468
b74fe7c7 HS	469	match = of_match_device(dev->driver->of_match_table, dev);
	470	if (!match \|\| !match->data) {
	471	dev_err(dev, "missing phy data\n");
	472	return -EINVAL;
	473	}
	474
	475	phy_base->pdata = match->data;
	476
5fdbb97d	477	phy_base->dev = dev;
a0da445a HS	478	phy_base->reg_base = ERR_PTR(-ENODEV);
	479	if (dev->parent && dev->parent->of_node)
	480	phy_base->reg_base = syscon_node_to_regmap(
	481	dev->parent->of_node);
	482	if (IS_ERR(phy_base->reg_base))
	483	phy_base->reg_base = syscon_regmap_lookup_by_phandle(
	484	dev->of_node, "rockchip,grf");
5fdbb97d	485	if (IS_ERR(phy_base->reg_base)) {
64d11406	486	dev_err(&pdev->dev, "Missing rockchip,grf property\n");
5fdbb97d	487	return PTR_ERR(phy_base->reg_base);
64d11406 YL	488	}
	489
	490	for_each_available_child_of_node(dev->of_node, child) {
97dd9101 HS	491	err = rockchip_usb_phy_init(phy_base, child);
	492	if (err) {
	493	of_node_put(child);
75d390fe	494	return err;
64d11406	495	}
64d11406 YL	496	}
	497
	498	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
	499	return PTR_ERR_OR_ZERO(phy_provider);
	500	}
	501
	502	static const struct of_device_id rockchip_usb_phy_dt_ids[] = {
b74fe7c7 HS	503	{ .compatible = "rockchip,rk3066a-usb-phy", .data = &rk3066a_pdata },
	504	{ .compatible = "rockchip,rk3188-usb-phy", .data = &rk3188_pdata },
	505	{ .compatible = "rockchip,rk3288-usb-phy", .data = &rk3288_pdata },
64d11406 YL	506	{}
	507	};
	508
	509	MODULE_DEVICE_TABLE(of, rockchip_usb_phy_dt_ids);
	510
	511	static struct platform_driver rockchip_usb_driver = {
	512	.probe = rockchip_usb_phy_probe,
	513	.driver = {
	514	.name = "rockchip-usb-phy",
64d11406 YL	515	.of_match_table = rockchip_usb_phy_dt_ids,
	516	},
	517	};
	518
	519	module_platform_driver(rockchip_usb_driver);
	520
605df8af HS	521	#ifndef MODULE
	522	static int __init rockchip_init_usb_uart(void)
	523	{
	524	const struct of_device_id *match;
	525	const struct rockchip_usb_phy_pdata *data;
	526	struct device_node *np;
	527	struct regmap *grf;
	528	int ret;
	529
	530	if (!enable_usb_uart)
	531	return 0;
	532
	533	np = of_find_matching_node_and_match(NULL, rockchip_usb_phy_dt_ids,
	534	&match);
	535	if (!np) {
	536	pr_err("%s: failed to find usbphy node\n", __func__);
	537	return -ENOTSUPP;
	538	}
	539
	540	pr_debug("%s: using settings for %s\n", __func__, match->compatible);
	541	data = match->data;
	542
	543	if (!data->init_usb_uart) {
	544	pr_err("%s: usb-uart not available on %s\n",
	545	__func__, match->compatible);
	546	return -ENOTSUPP;
	547	}
	548
a0da445a HS	549	grf = ERR_PTR(-ENODEV);
	550	if (np->parent)
	551	grf = syscon_node_to_regmap(np->parent);
	552	if (IS_ERR(grf))
	553	grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
605df8af HS	554	if (IS_ERR(grf)) {
	555	pr_err("%s: Missing rockchip,grf property, %lu\n",
	556	__func__, PTR_ERR(grf));
	557	return PTR_ERR(grf);
	558	}
	559
63bd0f19	560	ret = data->init_usb_uart(grf, data);
605df8af HS	561	if (ret) {
	562	pr_err("%s: could not init usb_uart, %d\n", __func__, ret);
	563	enable_usb_uart = 0;
	564	return ret;
	565	}
	566
	567	return 0;
	568	}
	569	early_initcall(rockchip_init_usb_uart);
	570
	571	static int __init rockchip_usb_uart(char *buf)
	572	{
	573	enable_usb_uart = true;
	574	return 0;
	575	}
	576	early_param("rockchip.usb_uart", rockchip_usb_uart);
	577	#endif
	578
64d11406 YL	579	MODULE_AUTHOR("Yunzhi Li <lyz@rock-chips.com>");
	580	MODULE_DESCRIPTION("Rockchip USB 2.0 PHY driver");
	581	MODULE_LICENSE("GPL v2");