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Commit | Line | Data |
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57f6ce07 | 1 | /* |
a70143bb | 2 | * phy-ti-pipe3 - PIPE3 PHY driver. |
57f6ce07 KVA |
3 | * |
4 | * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; either version 2 of the License, or | |
8 | * (at your option) any later version. | |
9 | * | |
10 | * Author: Kishon Vijay Abraham I <kishon@ti.com> | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | */ | |
18 | ||
19 | #include <linux/module.h> | |
20 | #include <linux/platform_device.h> | |
21 | #include <linux/slab.h> | |
a70143bb | 22 | #include <linux/phy/phy.h> |
57f6ce07 KVA |
23 | #include <linux/of.h> |
24 | #include <linux/clk.h> | |
25 | #include <linux/err.h> | |
a70143bb | 26 | #include <linux/io.h> |
57f6ce07 KVA |
27 | #include <linux/pm_runtime.h> |
28 | #include <linux/delay.h> | |
14da699b | 29 | #include <linux/phy/omap_control_phy.h> |
918ee0d2 | 30 | #include <linux/of_platform.h> |
c934b361 RQ |
31 | #include <linux/mfd/syscon.h> |
32 | #include <linux/regmap.h> | |
57f6ce07 | 33 | |
57f6ce07 KVA |
34 | #define PLL_STATUS 0x00000004 |
35 | #define PLL_GO 0x00000008 | |
36 | #define PLL_CONFIGURATION1 0x0000000C | |
37 | #define PLL_CONFIGURATION2 0x00000010 | |
38 | #define PLL_CONFIGURATION3 0x00000014 | |
39 | #define PLL_CONFIGURATION4 0x00000020 | |
40 | ||
41 | #define PLL_REGM_MASK 0x001FFE00 | |
42 | #define PLL_REGM_SHIFT 0x9 | |
43 | #define PLL_REGM_F_MASK 0x0003FFFF | |
44 | #define PLL_REGM_F_SHIFT 0x0 | |
45 | #define PLL_REGN_MASK 0x000001FE | |
46 | #define PLL_REGN_SHIFT 0x1 | |
47 | #define PLL_SELFREQDCO_MASK 0x0000000E | |
48 | #define PLL_SELFREQDCO_SHIFT 0x1 | |
49 | #define PLL_SD_MASK 0x0003FC00 | |
1562864f | 50 | #define PLL_SD_SHIFT 10 |
57f6ce07 | 51 | #define SET_PLL_GO 0x1 |
629138db RQ |
52 | #define PLL_LDOPWDN BIT(15) |
53 | #define PLL_TICOPWDN BIT(16) | |
57f6ce07 KVA |
54 | #define PLL_LOCK 0x2 |
55 | #define PLL_IDLE 0x1 | |
56 | ||
c934b361 RQ |
57 | #define SATA_PLL_SOFT_RESET BIT(18) |
58 | ||
c396a1c7 KVA |
59 | #define PIPE3_PHY_PWRCTL_CLK_CMD_MASK 0x003FC000 |
60 | #define PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT 14 | |
61 | ||
62 | #define PIPE3_PHY_PWRCTL_CLK_FREQ_MASK 0xFFC00000 | |
63 | #define PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT 22 | |
64 | ||
65 | #define PIPE3_PHY_TX_RX_POWERON 0x3 | |
66 | #define PIPE3_PHY_TX_RX_POWEROFF 0x0 | |
67 | ||
3f2362c5 KVA |
68 | #define PCIE_PCS_MASK 0xFF0000 |
69 | #define PCIE_PCS_DELAY_COUNT_SHIFT 0x10 | |
70 | ||
2796ceb0 KVA |
71 | #define PCIEPHYRX_ANA_PROGRAMMABILITY 0x0000000C |
72 | #define INTERFACE_MASK GENMASK(31, 27) | |
73 | #define INTERFACE_SHIFT 27 | |
74 | #define LOSD_MASK GENMASK(17, 14) | |
75 | #define LOSD_SHIFT 14 | |
76 | #define MEM_PLLDIV GENMASK(6, 5) | |
77 | ||
78 | #define PCIEPHYRX_TRIM 0x0000001C | |
79 | #define MEM_DLL_TRIM_SEL GENMASK(31, 30) | |
80 | #define MEM_DLL_TRIM_SHIFT 30 | |
81 | ||
82 | #define PCIEPHYRX_DLL 0x00000024 | |
83 | #define MEM_DLL_PHINT_RATE GENMASK(31, 30) | |
84 | ||
85 | #define PCIEPHYRX_DIGITAL_MODES 0x00000028 | |
86 | #define MEM_CDR_FASTLOCK BIT(23) | |
87 | #define MEM_CDR_LBW GENMASK(22, 21) | |
88 | #define MEM_CDR_STEPCNT GENMASK(20, 19) | |
89 | #define MEM_CDR_STL_MASK GENMASK(18, 16) | |
90 | #define MEM_CDR_STL_SHIFT 16 | |
91 | #define MEM_CDR_THR_MASK GENMASK(15, 13) | |
92 | #define MEM_CDR_THR_SHIFT 13 | |
93 | #define MEM_CDR_THR_MODE BIT(12) | |
94 | #define MEM_CDR_CDR_2NDO_SDM_MODE BIT(11) | |
95 | #define MEM_OVRD_HS_RATE BIT(26) | |
96 | ||
97 | #define PCIEPHYRX_EQUALIZER 0x00000038 | |
98 | #define MEM_EQLEV GENMASK(31, 16) | |
99 | #define MEM_EQFTC GENMASK(15, 11) | |
100 | #define MEM_EQCTL GENMASK(10, 7) | |
101 | #define MEM_EQCTL_SHIFT 7 | |
102 | #define MEM_OVRD_EQLEV BIT(2) | |
103 | #define MEM_OVRD_EQFTC BIT(1) | |
104 | ||
57f6ce07 KVA |
105 | /* |
106 | * This is an Empirical value that works, need to confirm the actual | |
a70143bb KVA |
107 | * value required for the PIPE3PHY_PLL_CONFIGURATION2.PLL_IDLE status |
108 | * to be correctly reflected in the PIPE3PHY_PLL_STATUS register. | |
57f6ce07 | 109 | */ |
629138db RQ |
110 | #define PLL_IDLE_TIME 100 /* in milliseconds */ |
111 | #define PLL_LOCK_TIME 100 /* in milliseconds */ | |
57f6ce07 | 112 | |
22940823 RQ |
113 | enum pipe3_mode { PIPE3_MODE_PCIE = 1, |
114 | PIPE3_MODE_SATA, | |
115 | PIPE3_MODE_USBSS }; | |
116 | ||
a70143bb KVA |
117 | struct pipe3_dpll_params { |
118 | u16 m; | |
119 | u8 n; | |
120 | u8 freq:3; | |
121 | u8 sd; | |
122 | u32 mf; | |
123 | }; | |
124 | ||
61f54674 RQ |
125 | struct pipe3_dpll_map { |
126 | unsigned long rate; | |
127 | struct pipe3_dpll_params params; | |
128 | }; | |
129 | ||
a70143bb KVA |
130 | struct ti_pipe3 { |
131 | void __iomem *pll_ctrl_base; | |
2796ceb0 KVA |
132 | void __iomem *phy_rx; |
133 | void __iomem *phy_tx; | |
a70143bb KVA |
134 | struct device *dev; |
135 | struct device *control_dev; | |
136 | struct clk *wkupclk; | |
137 | struct clk *sys_clk; | |
1562864f | 138 | struct clk *refclk; |
99bbd48c | 139 | struct clk *div_clk; |
61f54674 | 140 | struct pipe3_dpll_map *dpll_map; |
c396a1c7 | 141 | struct regmap *phy_power_syscon; /* ctrl. reg. acces */ |
3f2362c5 | 142 | struct regmap *pcs_syscon; /* ctrl. reg. acces */ |
c934b361 RQ |
143 | struct regmap *dpll_reset_syscon; /* ctrl. reg. acces */ |
144 | unsigned int dpll_reset_reg; /* reg. index within syscon */ | |
c396a1c7 | 145 | unsigned int power_reg; /* power reg. index within syscon */ |
3f2362c5 | 146 | unsigned int pcie_pcs_reg; /* pcs reg. index in syscon */ |
c934b361 | 147 | bool sata_refclk_enabled; |
22940823 | 148 | enum pipe3_mode mode; |
a70143bb KVA |
149 | }; |
150 | ||
61f54674 | 151 | static struct pipe3_dpll_map dpll_map_usb[] = { |
519c6013 RQ |
152 | {12000000, {1250, 5, 4, 20, 0} }, /* 12 MHz */ |
153 | {16800000, {3125, 20, 4, 20, 0} }, /* 16.8 MHz */ | |
154 | {19200000, {1172, 8, 4, 20, 65537} }, /* 19.2 MHz */ | |
155 | {20000000, {1000, 7, 4, 10, 0} }, /* 20 MHz */ | |
156 | {26000000, {1250, 12, 4, 20, 0} }, /* 26 MHz */ | |
157 | {38400000, {3125, 47, 4, 20, 92843} }, /* 38.4 MHz */ | |
61f54674 RQ |
158 | { }, /* Terminator */ |
159 | }; | |
160 | ||
161 | static struct pipe3_dpll_map dpll_map_sata[] = { | |
325ce0fe RQ |
162 | {12000000, {625, 4, 4, 6, 0} }, /* 12 MHz */ |
163 | {16800000, {625, 6, 4, 7, 0} }, /* 16.8 MHz */ | |
61f54674 | 164 | {19200000, {625, 7, 4, 6, 0} }, /* 19.2 MHz */ |
325ce0fe RQ |
165 | {20000000, {750, 9, 4, 6, 0} }, /* 20 MHz */ |
166 | {26000000, {750, 12, 4, 6, 0} }, /* 26 MHz */ | |
167 | {38400000, {625, 15, 4, 6, 0} }, /* 38.4 MHz */ | |
61f54674 | 168 | { }, /* Terminator */ |
57f6ce07 KVA |
169 | }; |
170 | ||
22940823 RQ |
171 | struct pipe3_data { |
172 | enum pipe3_mode mode; | |
173 | struct pipe3_dpll_map *dpll_map; | |
174 | }; | |
175 | ||
176 | static struct pipe3_data data_usb = { | |
177 | .mode = PIPE3_MODE_USBSS, | |
178 | .dpll_map = dpll_map_usb, | |
179 | }; | |
180 | ||
181 | static struct pipe3_data data_sata = { | |
182 | .mode = PIPE3_MODE_SATA, | |
183 | .dpll_map = dpll_map_sata, | |
184 | }; | |
185 | ||
186 | static struct pipe3_data data_pcie = { | |
187 | .mode = PIPE3_MODE_PCIE, | |
188 | }; | |
189 | ||
a70143bb KVA |
190 | static inline u32 ti_pipe3_readl(void __iomem *addr, unsigned offset) |
191 | { | |
192 | return __raw_readl(addr + offset); | |
193 | } | |
194 | ||
195 | static inline void ti_pipe3_writel(void __iomem *addr, unsigned offset, | |
196 | u32 data) | |
197 | { | |
198 | __raw_writel(data, addr + offset); | |
199 | } | |
200 | ||
61f54674 | 201 | static struct pipe3_dpll_params *ti_pipe3_get_dpll_params(struct ti_pipe3 *phy) |
519c6013 | 202 | { |
61f54674 RQ |
203 | unsigned long rate; |
204 | struct pipe3_dpll_map *dpll_map = phy->dpll_map; | |
519c6013 | 205 | |
61f54674 RQ |
206 | rate = clk_get_rate(phy->sys_clk); |
207 | ||
208 | for (; dpll_map->rate; dpll_map++) { | |
209 | if (rate == dpll_map->rate) | |
210 | return &dpll_map->params; | |
519c6013 RQ |
211 | } |
212 | ||
61f54674 RQ |
213 | dev_err(phy->dev, "No DPLL configuration for %lu Hz SYS CLK\n", rate); |
214 | ||
1b97be8c | 215 | return NULL; |
519c6013 RQ |
216 | } |
217 | ||
0a0830fe RQ |
218 | static int ti_pipe3_enable_clocks(struct ti_pipe3 *phy); |
219 | static void ti_pipe3_disable_clocks(struct ti_pipe3 *phy); | |
220 | ||
a70143bb KVA |
221 | static int ti_pipe3_power_off(struct phy *x) |
222 | { | |
c396a1c7 KVA |
223 | u32 val; |
224 | int ret; | |
a70143bb | 225 | struct ti_pipe3 *phy = phy_get_drvdata(x); |
a70143bb | 226 | |
c396a1c7 KVA |
227 | if (!phy->phy_power_syscon) { |
228 | omap_control_phy_power(phy->control_dev, 0); | |
229 | return 0; | |
230 | } | |
a70143bb | 231 | |
c396a1c7 KVA |
232 | val = PIPE3_PHY_TX_RX_POWEROFF << PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT; |
233 | ||
234 | ret = regmap_update_bits(phy->phy_power_syscon, phy->power_reg, | |
235 | PIPE3_PHY_PWRCTL_CLK_CMD_MASK, val); | |
236 | return ret; | |
a70143bb KVA |
237 | } |
238 | ||
239 | static int ti_pipe3_power_on(struct phy *x) | |
57f6ce07 | 240 | { |
c396a1c7 KVA |
241 | u32 val; |
242 | u32 mask; | |
243 | int ret; | |
244 | unsigned long rate; | |
a70143bb | 245 | struct ti_pipe3 *phy = phy_get_drvdata(x); |
57f6ce07 | 246 | |
c396a1c7 KVA |
247 | if (!phy->phy_power_syscon) { |
248 | omap_control_phy_power(phy->control_dev, 1); | |
249 | return 0; | |
250 | } | |
57f6ce07 | 251 | |
c396a1c7 KVA |
252 | rate = clk_get_rate(phy->sys_clk); |
253 | if (!rate) { | |
254 | dev_err(phy->dev, "Invalid clock rate\n"); | |
255 | return -EINVAL; | |
256 | } | |
257 | rate = rate / 1000000; | |
258 | mask = OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK | | |
259 | OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK; | |
260 | val = PIPE3_PHY_TX_RX_POWERON << PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT; | |
261 | val |= rate << OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT; | |
262 | ||
263 | ret = regmap_update_bits(phy->phy_power_syscon, phy->power_reg, | |
264 | mask, val); | |
265 | return ret; | |
57f6ce07 KVA |
266 | } |
267 | ||
629138db | 268 | static int ti_pipe3_dpll_wait_lock(struct ti_pipe3 *phy) |
57f6ce07 KVA |
269 | { |
270 | u32 val; | |
271 | unsigned long timeout; | |
272 | ||
629138db | 273 | timeout = jiffies + msecs_to_jiffies(PLL_LOCK_TIME); |
57f6ce07 | 274 | do { |
629138db | 275 | cpu_relax(); |
a70143bb | 276 | val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS); |
57f6ce07 | 277 | if (val & PLL_LOCK) |
a5e5d3c0 | 278 | return 0; |
629138db RQ |
279 | } while (!time_after(jiffies, timeout)); |
280 | ||
a5e5d3c0 AL |
281 | dev_err(phy->dev, "DPLL failed to lock\n"); |
282 | return -EBUSY; | |
57f6ce07 KVA |
283 | } |
284 | ||
629138db | 285 | static int ti_pipe3_dpll_program(struct ti_pipe3 *phy) |
57f6ce07 KVA |
286 | { |
287 | u32 val; | |
a70143bb | 288 | struct pipe3_dpll_params *dpll_params; |
57f6ce07 | 289 | |
61f54674 RQ |
290 | dpll_params = ti_pipe3_get_dpll_params(phy); |
291 | if (!dpll_params) | |
57f6ce07 | 292 | return -EINVAL; |
57f6ce07 | 293 | |
a70143bb | 294 | val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1); |
57f6ce07 | 295 | val &= ~PLL_REGN_MASK; |
519c6013 | 296 | val |= dpll_params->n << PLL_REGN_SHIFT; |
a70143bb | 297 | ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val); |
57f6ce07 | 298 | |
a70143bb | 299 | val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2); |
57f6ce07 | 300 | val &= ~PLL_SELFREQDCO_MASK; |
519c6013 | 301 | val |= dpll_params->freq << PLL_SELFREQDCO_SHIFT; |
a70143bb | 302 | ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val); |
57f6ce07 | 303 | |
a70143bb | 304 | val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1); |
57f6ce07 | 305 | val &= ~PLL_REGM_MASK; |
519c6013 | 306 | val |= dpll_params->m << PLL_REGM_SHIFT; |
a70143bb | 307 | ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val); |
57f6ce07 | 308 | |
a70143bb | 309 | val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION4); |
57f6ce07 | 310 | val &= ~PLL_REGM_F_MASK; |
519c6013 | 311 | val |= dpll_params->mf << PLL_REGM_F_SHIFT; |
a70143bb | 312 | ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION4, val); |
57f6ce07 | 313 | |
a70143bb | 314 | val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION3); |
57f6ce07 | 315 | val &= ~PLL_SD_MASK; |
519c6013 | 316 | val |= dpll_params->sd << PLL_SD_SHIFT; |
a70143bb | 317 | ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION3, val); |
57f6ce07 | 318 | |
629138db | 319 | ti_pipe3_writel(phy->pll_ctrl_base, PLL_GO, SET_PLL_GO); |
57f6ce07 | 320 | |
629138db | 321 | return ti_pipe3_dpll_wait_lock(phy); |
57f6ce07 KVA |
322 | } |
323 | ||
2796ceb0 KVA |
324 | static void ti_pipe3_calibrate(struct ti_pipe3 *phy) |
325 | { | |
326 | u32 val; | |
327 | ||
328 | val = ti_pipe3_readl(phy->phy_rx, PCIEPHYRX_ANA_PROGRAMMABILITY); | |
329 | val &= ~(INTERFACE_MASK | LOSD_MASK | MEM_PLLDIV); | |
e6577cb5 | 330 | val |= (0x1 << INTERFACE_SHIFT | 0xA << LOSD_SHIFT); |
2796ceb0 KVA |
331 | ti_pipe3_writel(phy->phy_rx, PCIEPHYRX_ANA_PROGRAMMABILITY, val); |
332 | ||
333 | val = ti_pipe3_readl(phy->phy_rx, PCIEPHYRX_DIGITAL_MODES); | |
334 | val &= ~(MEM_CDR_STEPCNT | MEM_CDR_STL_MASK | MEM_CDR_THR_MASK | | |
335 | MEM_CDR_CDR_2NDO_SDM_MODE | MEM_OVRD_HS_RATE); | |
336 | val |= (MEM_CDR_FASTLOCK | MEM_CDR_LBW | 0x3 << MEM_CDR_STL_SHIFT | | |
337 | 0x1 << MEM_CDR_THR_SHIFT | MEM_CDR_THR_MODE); | |
338 | ti_pipe3_writel(phy->phy_rx, PCIEPHYRX_DIGITAL_MODES, val); | |
339 | ||
340 | val = ti_pipe3_readl(phy->phy_rx, PCIEPHYRX_TRIM); | |
341 | val &= ~MEM_DLL_TRIM_SEL; | |
342 | val |= 0x2 << MEM_DLL_TRIM_SHIFT; | |
343 | ti_pipe3_writel(phy->phy_rx, PCIEPHYRX_TRIM, val); | |
344 | ||
345 | val = ti_pipe3_readl(phy->phy_rx, PCIEPHYRX_DLL); | |
346 | val |= MEM_DLL_PHINT_RATE; | |
347 | ti_pipe3_writel(phy->phy_rx, PCIEPHYRX_DLL, val); | |
348 | ||
349 | val = ti_pipe3_readl(phy->phy_rx, PCIEPHYRX_EQUALIZER); | |
350 | val &= ~(MEM_EQLEV | MEM_EQCTL | MEM_OVRD_EQLEV | MEM_OVRD_EQFTC); | |
351 | val |= MEM_EQFTC | 0x1 << MEM_EQCTL_SHIFT; | |
352 | ti_pipe3_writel(phy->phy_rx, PCIEPHYRX_EQUALIZER, val); | |
353 | } | |
354 | ||
a70143bb | 355 | static int ti_pipe3_init(struct phy *x) |
57f6ce07 | 356 | { |
a70143bb | 357 | struct ti_pipe3 *phy = phy_get_drvdata(x); |
629138db RQ |
358 | u32 val; |
359 | int ret = 0; | |
519c6013 | 360 | |
0a0830fe | 361 | ti_pipe3_enable_clocks(phy); |
0bc09f9c V |
362 | /* |
363 | * Set pcie_pcs register to 0x96 for proper functioning of phy | |
364 | * as recommended in AM572x TRM SPRUHZ6, section 18.5.2.2, table | |
365 | * 18-1804. | |
366 | */ | |
22940823 | 367 | if (phy->mode == PIPE3_MODE_PCIE) { |
3f2362c5 KVA |
368 | if (!phy->pcs_syscon) { |
369 | omap_control_pcie_pcs(phy->control_dev, 0x96); | |
370 | return 0; | |
371 | } | |
372 | ||
373 | val = 0x96 << OMAP_CTRL_PCIE_PCS_DELAY_COUNT_SHIFT; | |
374 | ret = regmap_update_bits(phy->pcs_syscon, phy->pcie_pcs_reg, | |
375 | PCIE_PCS_MASK, val); | |
2796ceb0 KVA |
376 | if (ret) |
377 | return ret; | |
378 | ||
379 | ti_pipe3_calibrate(phy); | |
380 | ||
381 | return 0; | |
f0e2cf7b | 382 | } |
99bbd48c | 383 | |
629138db RQ |
384 | /* Bring it out of IDLE if it is IDLE */ |
385 | val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2); | |
386 | if (val & PLL_IDLE) { | |
387 | val &= ~PLL_IDLE; | |
388 | ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val); | |
389 | ret = ti_pipe3_dpll_wait_lock(phy); | |
390 | } | |
57f6ce07 | 391 | |
31b2a32f | 392 | /* SATA has issues if re-programmed when locked */ |
629138db | 393 | val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS); |
22940823 | 394 | if ((val & PLL_LOCK) && phy->mode == PIPE3_MODE_SATA) |
31b2a32f RQ |
395 | return ret; |
396 | ||
397 | /* Program the DPLL */ | |
398 | ret = ti_pipe3_dpll_program(phy); | |
399 | if (ret) { | |
400 | ti_pipe3_disable_clocks(phy); | |
401 | return -EINVAL; | |
402 | } | |
57f6ce07 | 403 | |
629138db | 404 | return ret; |
57f6ce07 KVA |
405 | } |
406 | ||
629138db RQ |
407 | static int ti_pipe3_exit(struct phy *x) |
408 | { | |
409 | struct ti_pipe3 *phy = phy_get_drvdata(x); | |
410 | u32 val; | |
411 | unsigned long timeout; | |
412 | ||
c934b361 RQ |
413 | /* If dpll_reset_syscon is not present we wont power down SATA DPLL |
414 | * due to Errata i783 | |
415 | */ | |
22940823 | 416 | if (phy->mode == PIPE3_MODE_SATA && !phy->dpll_reset_syscon) |
56042e4e RQ |
417 | return 0; |
418 | ||
0a0830fe | 419 | /* PCIe doesn't have internal DPLL */ |
22940823 | 420 | if (phy->mode != PIPE3_MODE_PCIE) { |
0a0830fe RQ |
421 | /* Put DPLL in IDLE mode */ |
422 | val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2); | |
423 | val |= PLL_IDLE; | |
424 | ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val); | |
629138db | 425 | |
0a0830fe RQ |
426 | /* wait for LDO and Oscillator to power down */ |
427 | timeout = jiffies + msecs_to_jiffies(PLL_IDLE_TIME); | |
428 | do { | |
429 | cpu_relax(); | |
430 | val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS); | |
431 | if ((val & PLL_TICOPWDN) && (val & PLL_LDOPWDN)) | |
432 | break; | |
433 | } while (!time_after(jiffies, timeout)); | |
434 | ||
435 | if (!(val & PLL_TICOPWDN) || !(val & PLL_LDOPWDN)) { | |
436 | dev_err(phy->dev, "Failed to power down: PLL_STATUS 0x%x\n", | |
437 | val); | |
438 | return -EBUSY; | |
439 | } | |
629138db RQ |
440 | } |
441 | ||
c934b361 | 442 | /* i783: SATA needs control bit toggle after PLL unlock */ |
22940823 | 443 | if (phy->mode == PIPE3_MODE_SATA) { |
c934b361 RQ |
444 | regmap_update_bits(phy->dpll_reset_syscon, phy->dpll_reset_reg, |
445 | SATA_PLL_SOFT_RESET, SATA_PLL_SOFT_RESET); | |
446 | regmap_update_bits(phy->dpll_reset_syscon, phy->dpll_reset_reg, | |
447 | SATA_PLL_SOFT_RESET, 0); | |
448 | } | |
449 | ||
0a0830fe RQ |
450 | ti_pipe3_disable_clocks(phy); |
451 | ||
629138db RQ |
452 | return 0; |
453 | } | |
4a9e5ca1 | 454 | static const struct phy_ops ops = { |
a70143bb | 455 | .init = ti_pipe3_init, |
629138db | 456 | .exit = ti_pipe3_exit, |
a70143bb KVA |
457 | .power_on = ti_pipe3_power_on, |
458 | .power_off = ti_pipe3_power_off, | |
459 | .owner = THIS_MODULE, | |
460 | }; | |
461 | ||
61f54674 | 462 | static const struct of_device_id ti_pipe3_id_table[]; |
61f54674 | 463 | |
234738ea | 464 | static int ti_pipe3_get_clk(struct ti_pipe3 *phy) |
57f6ce07 | 465 | { |
99bbd48c | 466 | struct clk *clk; |
234738ea | 467 | struct device *dev = phy->dev; |
9c7f0443 | 468 | |
d65ff52e | 469 | phy->refclk = devm_clk_get(dev, "refclk"); |
7f33912d | 470 | if (IS_ERR(phy->refclk)) { |
d65ff52e | 471 | dev_err(dev, "unable to get refclk\n"); |
7f33912d RQ |
472 | /* older DTBs have missing refclk in SATA PHY |
473 | * so don't bail out in case of SATA PHY. | |
474 | */ | |
22940823 | 475 | if (phy->mode != PIPE3_MODE_SATA) |
7f33912d RQ |
476 | return PTR_ERR(phy->refclk); |
477 | } | |
478 | ||
22940823 | 479 | if (phy->mode != PIPE3_MODE_SATA) { |
d65ff52e | 480 | phy->wkupclk = devm_clk_get(dev, "wkupclk"); |
9c7f0443 | 481 | if (IS_ERR(phy->wkupclk)) { |
d65ff52e | 482 | dev_err(dev, "unable to get wkupclk\n"); |
9c7f0443 RQ |
483 | return PTR_ERR(phy->wkupclk); |
484 | } | |
9c7f0443 RQ |
485 | } else { |
486 | phy->wkupclk = ERR_PTR(-ENODEV); | |
234738ea KVA |
487 | } |
488 | ||
22940823 | 489 | if (phy->mode != PIPE3_MODE_PCIE || phy->phy_power_syscon) { |
234738ea KVA |
490 | phy->sys_clk = devm_clk_get(dev, "sysclk"); |
491 | if (IS_ERR(phy->sys_clk)) { | |
492 | dev_err(dev, "unable to get sysclk\n"); | |
493 | return -EINVAL; | |
c934b361 | 494 | } |
57f6ce07 | 495 | } |
57f6ce07 | 496 | |
22940823 | 497 | if (phy->mode == PIPE3_MODE_PCIE) { |
d65ff52e | 498 | clk = devm_clk_get(dev, "dpll_ref"); |
99bbd48c | 499 | if (IS_ERR(clk)) { |
d65ff52e | 500 | dev_err(dev, "unable to get dpll ref clk\n"); |
99bbd48c KVA |
501 | return PTR_ERR(clk); |
502 | } | |
503 | clk_set_rate(clk, 1500000000); | |
504 | ||
d65ff52e | 505 | clk = devm_clk_get(dev, "dpll_ref_m2"); |
99bbd48c | 506 | if (IS_ERR(clk)) { |
d65ff52e | 507 | dev_err(dev, "unable to get dpll ref m2 clk\n"); |
99bbd48c KVA |
508 | return PTR_ERR(clk); |
509 | } | |
510 | clk_set_rate(clk, 100000000); | |
511 | ||
d65ff52e | 512 | clk = devm_clk_get(dev, "phy-div"); |
99bbd48c | 513 | if (IS_ERR(clk)) { |
d65ff52e | 514 | dev_err(dev, "unable to get phy-div clk\n"); |
99bbd48c KVA |
515 | return PTR_ERR(clk); |
516 | } | |
517 | clk_set_rate(clk, 100000000); | |
518 | ||
d65ff52e | 519 | phy->div_clk = devm_clk_get(dev, "div-clk"); |
99bbd48c | 520 | if (IS_ERR(phy->div_clk)) { |
d65ff52e | 521 | dev_err(dev, "unable to get div-clk\n"); |
99bbd48c KVA |
522 | return PTR_ERR(phy->div_clk); |
523 | } | |
524 | } else { | |
525 | phy->div_clk = ERR_PTR(-ENODEV); | |
57f6ce07 KVA |
526 | } |
527 | ||
234738ea KVA |
528 | return 0; |
529 | } | |
530 | ||
73bbc78e KVA |
531 | static int ti_pipe3_get_sysctrl(struct ti_pipe3 *phy) |
532 | { | |
533 | struct device *dev = phy->dev; | |
534 | struct device_node *node = dev->of_node; | |
535 | struct device_node *control_node; | |
536 | struct platform_device *control_pdev; | |
537 | ||
c396a1c7 KVA |
538 | phy->phy_power_syscon = syscon_regmap_lookup_by_phandle(node, |
539 | "syscon-phy-power"); | |
540 | if (IS_ERR(phy->phy_power_syscon)) { | |
541 | dev_dbg(dev, | |
542 | "can't get syscon-phy-power, using control device\n"); | |
543 | phy->phy_power_syscon = NULL; | |
544 | } else { | |
545 | if (of_property_read_u32_index(node, | |
546 | "syscon-phy-power", 1, | |
547 | &phy->power_reg)) { | |
548 | dev_err(dev, "couldn't get power reg. offset\n"); | |
549 | return -EINVAL; | |
550 | } | |
73bbc78e KVA |
551 | } |
552 | ||
c396a1c7 KVA |
553 | if (!phy->phy_power_syscon) { |
554 | control_node = of_parse_phandle(node, "ctrl-module", 0); | |
555 | if (!control_node) { | |
556 | dev_err(dev, "Failed to get control device phandle\n"); | |
557 | return -EINVAL; | |
558 | } | |
73bbc78e | 559 | |
c396a1c7 KVA |
560 | control_pdev = of_find_device_by_node(control_node); |
561 | if (!control_pdev) { | |
562 | dev_err(dev, "Failed to get control device\n"); | |
563 | return -EINVAL; | |
564 | } | |
565 | ||
566 | phy->control_dev = &control_pdev->dev; | |
567 | } | |
73bbc78e | 568 | |
22940823 | 569 | if (phy->mode == PIPE3_MODE_PCIE) { |
3f2362c5 KVA |
570 | phy->pcs_syscon = syscon_regmap_lookup_by_phandle(node, |
571 | "syscon-pcs"); | |
572 | if (IS_ERR(phy->pcs_syscon)) { | |
573 | dev_dbg(dev, | |
574 | "can't get syscon-pcs, using omap control\n"); | |
575 | phy->pcs_syscon = NULL; | |
576 | } else { | |
577 | if (of_property_read_u32_index(node, | |
578 | "syscon-pcs", 1, | |
579 | &phy->pcie_pcs_reg)) { | |
580 | dev_err(dev, | |
581 | "couldn't get pcie pcs reg. offset\n"); | |
582 | return -EINVAL; | |
583 | } | |
584 | } | |
585 | } | |
586 | ||
22940823 | 587 | if (phy->mode == PIPE3_MODE_SATA) { |
73bbc78e KVA |
588 | phy->dpll_reset_syscon = syscon_regmap_lookup_by_phandle(node, |
589 | "syscon-pllreset"); | |
590 | if (IS_ERR(phy->dpll_reset_syscon)) { | |
591 | dev_info(dev, | |
592 | "can't get syscon-pllreset, sata dpll won't idle\n"); | |
593 | phy->dpll_reset_syscon = NULL; | |
594 | } else { | |
595 | if (of_property_read_u32_index(node, | |
596 | "syscon-pllreset", 1, | |
597 | &phy->dpll_reset_reg)) { | |
598 | dev_err(dev, | |
599 | "couldn't get pllreset reg. offset\n"); | |
600 | return -EINVAL; | |
601 | } | |
602 | } | |
603 | } | |
604 | ||
605 | return 0; | |
606 | } | |
607 | ||
2796ceb0 KVA |
608 | static int ti_pipe3_get_tx_rx_base(struct ti_pipe3 *phy) |
609 | { | |
610 | struct resource *res; | |
611 | struct device *dev = phy->dev; | |
2796ceb0 KVA |
612 | struct platform_device *pdev = to_platform_device(dev); |
613 | ||
22940823 | 614 | if (phy->mode != PIPE3_MODE_PCIE) |
2796ceb0 KVA |
615 | return 0; |
616 | ||
617 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, | |
618 | "phy_rx"); | |
619 | phy->phy_rx = devm_ioremap_resource(dev, res); | |
620 | if (IS_ERR(phy->phy_rx)) | |
621 | return PTR_ERR(phy->phy_rx); | |
622 | ||
623 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, | |
624 | "phy_tx"); | |
625 | phy->phy_tx = devm_ioremap_resource(dev, res); | |
626 | ||
627 | return PTR_ERR_OR_ZERO(phy->phy_tx); | |
628 | } | |
629 | ||
1fe52122 KVA |
630 | static int ti_pipe3_get_pll_base(struct ti_pipe3 *phy) |
631 | { | |
632 | struct resource *res; | |
1fe52122 | 633 | struct device *dev = phy->dev; |
1fe52122 KVA |
634 | struct platform_device *pdev = to_platform_device(dev); |
635 | ||
22940823 | 636 | if (phy->mode == PIPE3_MODE_PCIE) |
1fe52122 KVA |
637 | return 0; |
638 | ||
1fe52122 KVA |
639 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, |
640 | "pll_ctrl"); | |
641 | phy->pll_ctrl_base = devm_ioremap_resource(dev, res); | |
045ef311 | 642 | return PTR_ERR_OR_ZERO(phy->pll_ctrl_base); |
1fe52122 KVA |
643 | } |
644 | ||
234738ea KVA |
645 | static int ti_pipe3_probe(struct platform_device *pdev) |
646 | { | |
647 | struct ti_pipe3 *phy; | |
648 | struct phy *generic_phy; | |
649 | struct phy_provider *phy_provider; | |
234738ea KVA |
650 | struct device *dev = &pdev->dev; |
651 | int ret; | |
22940823 RQ |
652 | const struct of_device_id *match; |
653 | struct pipe3_data *data; | |
234738ea KVA |
654 | |
655 | phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL); | |
656 | if (!phy) | |
657 | return -ENOMEM; | |
658 | ||
22940823 RQ |
659 | match = of_match_device(ti_pipe3_id_table, dev); |
660 | if (!match) | |
661 | return -EINVAL; | |
662 | ||
663 | data = (struct pipe3_data *)match->data; | |
664 | if (!data) { | |
665 | dev_err(dev, "no driver data\n"); | |
666 | return -EINVAL; | |
667 | } | |
668 | ||
669 | phy->dev = dev; | |
670 | phy->mode = data->mode; | |
671 | phy->dpll_map = data->dpll_map; | |
234738ea | 672 | |
1fe52122 KVA |
673 | ret = ti_pipe3_get_pll_base(phy); |
674 | if (ret) | |
675 | return ret; | |
234738ea | 676 | |
2796ceb0 KVA |
677 | ret = ti_pipe3_get_tx_rx_base(phy); |
678 | if (ret) | |
679 | return ret; | |
680 | ||
73bbc78e KVA |
681 | ret = ti_pipe3_get_sysctrl(phy); |
682 | if (ret) | |
683 | return ret; | |
234738ea KVA |
684 | |
685 | ret = ti_pipe3_get_clk(phy); | |
686 | if (ret) | |
687 | return ret; | |
688 | ||
57f6ce07 | 689 | platform_set_drvdata(pdev, phy); |
d65ff52e | 690 | pm_runtime_enable(dev); |
c934b361 RQ |
691 | |
692 | /* | |
693 | * Prevent auto-disable of refclk for SATA PHY due to Errata i783 | |
694 | */ | |
22940823 | 695 | if (phy->mode == PIPE3_MODE_SATA) { |
c934b361 | 696 | if (!IS_ERR(phy->refclk)) { |
0a0830fe | 697 | clk_prepare_enable(phy->refclk); |
c934b361 RQ |
698 | phy->sata_refclk_enabled = true; |
699 | } | |
700 | } | |
a70143bb | 701 | |
d65ff52e | 702 | generic_phy = devm_phy_create(dev, NULL, &ops); |
a70143bb KVA |
703 | if (IS_ERR(generic_phy)) |
704 | return PTR_ERR(generic_phy); | |
705 | ||
706 | phy_set_drvdata(generic_phy, phy); | |
cc34ace7 KVA |
707 | |
708 | ti_pipe3_power_off(generic_phy); | |
709 | ||
d65ff52e | 710 | phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); |
045ef311 | 711 | return PTR_ERR_OR_ZERO(phy_provider); |
57f6ce07 KVA |
712 | } |
713 | ||
a70143bb | 714 | static int ti_pipe3_remove(struct platform_device *pdev) |
57f6ce07 | 715 | { |
57f6ce07 KVA |
716 | pm_runtime_disable(&pdev->dev); |
717 | ||
718 | return 0; | |
719 | } | |
720 | ||
0a0830fe | 721 | static int ti_pipe3_enable_clocks(struct ti_pipe3 *phy) |
7f33912d | 722 | { |
0a0830fe | 723 | int ret = 0; |
7f33912d | 724 | |
0a0830fe | 725 | if (!IS_ERR(phy->refclk)) { |
7f33912d RQ |
726 | ret = clk_prepare_enable(phy->refclk); |
727 | if (ret) { | |
728 | dev_err(phy->dev, "Failed to enable refclk %d\n", ret); | |
729 | return ret; | |
730 | } | |
7f33912d RQ |
731 | } |
732 | ||
1562864f RQ |
733 | if (!IS_ERR(phy->wkupclk)) { |
734 | ret = clk_prepare_enable(phy->wkupclk); | |
735 | if (ret) { | |
736 | dev_err(phy->dev, "Failed to enable wkupclk %d\n", ret); | |
0a0830fe | 737 | goto disable_refclk; |
1562864f | 738 | } |
57f6ce07 KVA |
739 | } |
740 | ||
99bbd48c KVA |
741 | if (!IS_ERR(phy->div_clk)) { |
742 | ret = clk_prepare_enable(phy->div_clk); | |
743 | if (ret) { | |
744 | dev_err(phy->dev, "Failed to enable div_clk %d\n", ret); | |
0a0830fe | 745 | goto disable_wkupclk; |
99bbd48c KVA |
746 | } |
747 | } | |
6e738432 | 748 | |
57f6ce07 KVA |
749 | return 0; |
750 | ||
0a0830fe | 751 | disable_wkupclk: |
99bbd48c KVA |
752 | if (!IS_ERR(phy->wkupclk)) |
753 | clk_disable_unprepare(phy->wkupclk); | |
754 | ||
0a0830fe | 755 | disable_refclk: |
1562864f RQ |
756 | if (!IS_ERR(phy->refclk)) |
757 | clk_disable_unprepare(phy->refclk); | |
57f6ce07 | 758 | |
6e738432 RQ |
759 | return ret; |
760 | } | |
761 | ||
762 | static void ti_pipe3_disable_clocks(struct ti_pipe3 *phy) | |
763 | { | |
6e738432 RQ |
764 | if (!IS_ERR(phy->wkupclk)) |
765 | clk_disable_unprepare(phy->wkupclk); | |
c934b361 | 766 | if (!IS_ERR(phy->refclk)) { |
0a0830fe | 767 | clk_disable_unprepare(phy->refclk); |
c934b361 RQ |
768 | /* |
769 | * SATA refclk needs an additional disable as we left it | |
770 | * on in probe to avoid Errata i783 | |
771 | */ | |
772 | if (phy->sata_refclk_enabled) { | |
773 | clk_disable_unprepare(phy->refclk); | |
774 | phy->sata_refclk_enabled = false; | |
775 | } | |
776 | } | |
777 | ||
6e738432 RQ |
778 | if (!IS_ERR(phy->div_clk)) |
779 | clk_disable_unprepare(phy->div_clk); | |
6e738432 RQ |
780 | } |
781 | ||
a70143bb | 782 | static const struct of_device_id ti_pipe3_id_table[] = { |
61f54674 RQ |
783 | { |
784 | .compatible = "ti,phy-usb3", | |
22940823 | 785 | .data = &data_usb, |
61f54674 RQ |
786 | }, |
787 | { | |
788 | .compatible = "ti,omap-usb3", | |
22940823 | 789 | .data = &data_usb, |
61f54674 RQ |
790 | }, |
791 | { | |
792 | .compatible = "ti,phy-pipe3-sata", | |
22940823 | 793 | .data = &data_sata, |
61f54674 | 794 | }, |
99bbd48c KVA |
795 | { |
796 | .compatible = "ti,phy-pipe3-pcie", | |
22940823 | 797 | .data = &data_pcie, |
99bbd48c | 798 | }, |
57f6ce07 KVA |
799 | {} |
800 | }; | |
a70143bb | 801 | MODULE_DEVICE_TABLE(of, ti_pipe3_id_table); |
57f6ce07 | 802 | |
a70143bb KVA |
803 | static struct platform_driver ti_pipe3_driver = { |
804 | .probe = ti_pipe3_probe, | |
805 | .remove = ti_pipe3_remove, | |
57f6ce07 | 806 | .driver = { |
a70143bb | 807 | .name = "ti-pipe3", |
298fe56e | 808 | .of_match_table = ti_pipe3_id_table, |
57f6ce07 KVA |
809 | }, |
810 | }; | |
811 | ||
a70143bb | 812 | module_platform_driver(ti_pipe3_driver); |
57f6ce07 | 813 | |
dd64ad38 | 814 | MODULE_ALIAS("platform:ti_pipe3"); |
57f6ce07 | 815 | MODULE_AUTHOR("Texas Instruments Inc."); |
a70143bb | 816 | MODULE_DESCRIPTION("TI PIPE3 phy driver"); |
57f6ce07 | 817 | MODULE_LICENSE("GPL v2"); |