]>
Commit | Line | Data |
---|---|---|
2874c5fd | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
56e57cb6 AJ |
2 | /* |
3 | * Copyright (C) 2016 IBM Corp. | |
56e57cb6 AJ |
4 | */ |
5 | #include <linux/bitops.h> | |
6 | #include <linux/init.h> | |
7 | #include <linux/io.h> | |
8 | #include <linux/kernel.h> | |
7d29ed88 | 9 | #include <linux/mfd/syscon.h> |
56e57cb6 AJ |
10 | #include <linux/mutex.h> |
11 | #include <linux/of.h> | |
12 | #include <linux/platform_device.h> | |
13 | #include <linux/pinctrl/pinctrl.h> | |
14 | #include <linux/pinctrl/pinmux.h> | |
15 | #include <linux/pinctrl/pinconf.h> | |
16 | #include <linux/pinctrl/pinconf-generic.h> | |
17 | #include <linux/string.h> | |
18 | #include <linux/types.h> | |
19 | ||
20 | #include "../core.h" | |
21 | #include "../pinctrl-utils.h" | |
22 | #include "pinctrl-aspeed.h" | |
23 | ||
9ffac449 | 24 | #define ASPEED_G5_NR_PINS 236 |
56e57cb6 | 25 | |
7d29ed88 AJ |
26 | #define COND1 { ASPEED_IP_SCU, SCU90, BIT(6), 0, 0 } |
27 | #define COND2 { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 0, 0 } | |
56e57cb6 | 28 | |
f1337856 AJ |
29 | /* LHCR0 is offset from the end of the H8S/2168-compatible registers */ |
30 | #define LHCR0 0x20 | |
31 | #define GFX064 0x64 | |
32 | ||
56e57cb6 AJ |
33 | #define B14 0 |
34 | SSSF_PIN_DECL(B14, GPIOA0, MAC1LINK, SIG_DESC_SET(SCU80, 0)); | |
35 | ||
f1337856 AJ |
36 | #define D14 1 |
37 | SSSF_PIN_DECL(D14, GPIOA1, MAC2LINK, SIG_DESC_SET(SCU80, 1)); | |
38 | ||
39 | #define D13 2 | |
40 | SIG_EXPR_LIST_DECL_SINGLE(SPI1CS1, SPI1CS1, SIG_DESC_SET(SCU80, 15)); | |
41 | SIG_EXPR_LIST_DECL_SINGLE(TIMER3, TIMER3, SIG_DESC_SET(SCU80, 2)); | |
42 | MS_PIN_DECL(D13, GPIOA2, SPI1CS1, TIMER3); | |
43 | FUNC_GROUP_DECL(SPI1CS1, D13); | |
44 | FUNC_GROUP_DECL(TIMER3, D13); | |
45 | ||
56e57cb6 AJ |
46 | #define E13 3 |
47 | SSSF_PIN_DECL(E13, GPIOA3, TIMER4, SIG_DESC_SET(SCU80, 3)); | |
48 | ||
49 | #define I2C9_DESC SIG_DESC_SET(SCU90, 22) | |
50 | ||
51 | #define C14 4 | |
52 | SIG_EXPR_LIST_DECL_SINGLE(SCL9, I2C9, I2C9_DESC, COND1); | |
53 | SIG_EXPR_LIST_DECL_SINGLE(TIMER5, TIMER5, SIG_DESC_SET(SCU80, 4), COND1); | |
54 | MS_PIN_DECL(C14, GPIOA4, SCL9, TIMER5); | |
55 | ||
56 | FUNC_GROUP_DECL(TIMER5, C14); | |
57 | ||
58 | #define A13 5 | |
59 | SIG_EXPR_LIST_DECL_SINGLE(SDA9, I2C9, I2C9_DESC, COND1); | |
60 | SIG_EXPR_LIST_DECL_SINGLE(TIMER6, TIMER6, SIG_DESC_SET(SCU80, 5), COND1); | |
61 | MS_PIN_DECL(A13, GPIOA5, SDA9, TIMER6); | |
62 | ||
63 | FUNC_GROUP_DECL(TIMER6, A13); | |
64 | ||
65 | FUNC_GROUP_DECL(I2C9, C14, A13); | |
66 | ||
67 | #define MDIO2_DESC SIG_DESC_SET(SCU90, 2) | |
68 | ||
69 | #define C13 6 | |
70 | SIG_EXPR_LIST_DECL_SINGLE(MDC2, MDIO2, MDIO2_DESC, COND1); | |
71 | SIG_EXPR_LIST_DECL_SINGLE(TIMER7, TIMER7, SIG_DESC_SET(SCU80, 6), COND1); | |
72 | MS_PIN_DECL(C13, GPIOA6, MDC2, TIMER7); | |
73 | ||
74 | FUNC_GROUP_DECL(TIMER7, C13); | |
75 | ||
76 | #define B13 7 | |
77 | SIG_EXPR_LIST_DECL_SINGLE(MDIO2, MDIO2, MDIO2_DESC, COND1); | |
78 | SIG_EXPR_LIST_DECL_SINGLE(TIMER8, TIMER8, SIG_DESC_SET(SCU80, 7), COND1); | |
79 | MS_PIN_DECL(B13, GPIOA7, MDIO2, TIMER8); | |
80 | ||
81 | FUNC_GROUP_DECL(TIMER8, B13); | |
82 | ||
83 | FUNC_GROUP_DECL(MDIO2, C13, B13); | |
84 | ||
f1337856 AJ |
85 | #define K19 8 |
86 | GPIO_PIN_DECL(K19, GPIOB0); | |
87 | ||
88 | #define L19 9 | |
89 | GPIO_PIN_DECL(L19, GPIOB1); | |
90 | ||
91 | #define L18 10 | |
92 | GPIO_PIN_DECL(L18, GPIOB2); | |
93 | ||
94 | #define K18 11 | |
95 | GPIO_PIN_DECL(K18, GPIOB3); | |
96 | ||
97 | #define J20 12 | |
98 | SSSF_PIN_DECL(J20, GPIOB4, USBCKI, SIG_DESC_SET(HW_STRAP1, 23)); | |
99 | ||
100 | #define H21 13 | |
101 | #define H21_DESC SIG_DESC_SET(SCU80, 13) | |
102 | SIG_EXPR_LIST_DECL_SINGLE(LPCPD, LPCPD, H21_DESC); | |
103 | SIG_EXPR_LIST_DECL_SINGLE(LPCSMI, LPCSMI, H21_DESC); | |
104 | MS_PIN_DECL(H21, GPIOB5, LPCPD, LPCSMI); | |
105 | FUNC_GROUP_DECL(LPCPD, H21); | |
106 | FUNC_GROUP_DECL(LPCSMI, H21); | |
107 | ||
108 | #define H22 14 | |
109 | SSSF_PIN_DECL(H22, GPIOB6, LPCPME, SIG_DESC_SET(SCU80, 14)); | |
110 | ||
56e57cb6 AJ |
111 | #define H20 15 |
112 | GPIO_PIN_DECL(H20, GPIOB7); | |
113 | ||
114 | #define SD1_DESC SIG_DESC_SET(SCU90, 0) | |
115 | ||
116 | #define C12 16 | |
117 | #define I2C10_DESC SIG_DESC_SET(SCU90, 23) | |
118 | SIG_EXPR_LIST_DECL_SINGLE(SD1CLK, SD1, SD1_DESC); | |
119 | SIG_EXPR_LIST_DECL_SINGLE(SCL10, I2C10, I2C10_DESC); | |
120 | MS_PIN_DECL(C12, GPIOC0, SD1CLK, SCL10); | |
121 | ||
122 | #define A12 17 | |
123 | SIG_EXPR_LIST_DECL_SINGLE(SD1CMD, SD1, SD1_DESC); | |
124 | SIG_EXPR_LIST_DECL_SINGLE(SDA10, I2C10, I2C10_DESC); | |
125 | MS_PIN_DECL(A12, GPIOC1, SD1CMD, SDA10); | |
126 | ||
127 | FUNC_GROUP_DECL(I2C10, C12, A12); | |
128 | ||
129 | #define B12 18 | |
130 | #define I2C11_DESC SIG_DESC_SET(SCU90, 24) | |
131 | SIG_EXPR_LIST_DECL_SINGLE(SD1DAT0, SD1, SD1_DESC); | |
132 | SIG_EXPR_LIST_DECL_SINGLE(SCL11, I2C11, I2C11_DESC); | |
133 | MS_PIN_DECL(B12, GPIOC2, SD1DAT0, SCL11); | |
134 | ||
135 | #define D9 19 | |
136 | SIG_EXPR_LIST_DECL_SINGLE(SD1DAT1, SD1, SD1_DESC); | |
137 | SIG_EXPR_LIST_DECL_SINGLE(SDA11, I2C11, I2C11_DESC); | |
138 | MS_PIN_DECL(D9, GPIOC3, SD1DAT1, SDA11); | |
139 | ||
140 | FUNC_GROUP_DECL(I2C11, B12, D9); | |
141 | ||
142 | #define D10 20 | |
143 | #define I2C12_DESC SIG_DESC_SET(SCU90, 25) | |
144 | SIG_EXPR_LIST_DECL_SINGLE(SD1DAT2, SD1, SD1_DESC); | |
145 | SIG_EXPR_LIST_DECL_SINGLE(SCL12, I2C12, I2C12_DESC); | |
146 | MS_PIN_DECL(D10, GPIOC4, SD1DAT2, SCL12); | |
147 | ||
148 | #define E12 21 | |
149 | SIG_EXPR_LIST_DECL_SINGLE(SD1DAT3, SD1, SD1_DESC); | |
150 | SIG_EXPR_LIST_DECL_SINGLE(SDA12, I2C12, I2C12_DESC); | |
151 | MS_PIN_DECL(E12, GPIOC5, SD1DAT3, SDA12); | |
152 | ||
153 | FUNC_GROUP_DECL(I2C12, D10, E12); | |
154 | ||
155 | #define C11 22 | |
156 | #define I2C13_DESC SIG_DESC_SET(SCU90, 26) | |
157 | SIG_EXPR_LIST_DECL_SINGLE(SD1CD, SD1, SD1_DESC); | |
158 | SIG_EXPR_LIST_DECL_SINGLE(SCL13, I2C13, I2C13_DESC); | |
159 | MS_PIN_DECL(C11, GPIOC6, SD1CD, SCL13); | |
160 | ||
161 | #define B11 23 | |
162 | SIG_EXPR_LIST_DECL_SINGLE(SD1WP, SD1, SD1_DESC); | |
163 | SIG_EXPR_LIST_DECL_SINGLE(SDA13, I2C13, I2C13_DESC); | |
164 | MS_PIN_DECL(B11, GPIOC7, SD1WP, SDA13); | |
165 | ||
166 | FUNC_GROUP_DECL(I2C13, C11, B11); | |
167 | FUNC_GROUP_DECL(SD1, C12, A12, B12, D9, D10, E12, C11, B11); | |
168 | ||
169 | #define SD2_DESC SIG_DESC_SET(SCU90, 1) | |
170 | #define GPID0_DESC SIG_DESC_SET(SCU8C, 8) | |
171 | #define GPID_DESC SIG_DESC_SET(HW_STRAP1, 21) | |
172 | ||
173 | #define F19 24 | |
174 | SIG_EXPR_LIST_DECL_SINGLE(SD2CLK, SD2, SD2_DESC); | |
175 | SIG_EXPR_DECL(GPID0IN, GPID0, GPID0_DESC); | |
176 | SIG_EXPR_DECL(GPID0IN, GPID, GPID_DESC); | |
177 | SIG_EXPR_LIST_DECL_DUAL(GPID0IN, GPID0, GPID); | |
178 | MS_PIN_DECL(F19, GPIOD0, SD2CLK, GPID0IN); | |
179 | ||
180 | #define E21 25 | |
181 | SIG_EXPR_LIST_DECL_SINGLE(SD2CMD, SD2, SD2_DESC); | |
182 | SIG_EXPR_DECL(GPID0OUT, GPID0, GPID0_DESC); | |
183 | SIG_EXPR_DECL(GPID0OUT, GPID, GPID_DESC); | |
184 | SIG_EXPR_LIST_DECL_DUAL(GPID0OUT, GPID0, GPID); | |
185 | MS_PIN_DECL(E21, GPIOD1, SD2CMD, GPID0OUT); | |
186 | ||
187 | FUNC_GROUP_DECL(GPID0, F19, E21); | |
188 | ||
189 | #define GPID2_DESC SIG_DESC_SET(SCU8C, 9) | |
190 | ||
97e8c3f5 | 191 | #define F20 26 |
56e57cb6 AJ |
192 | SIG_EXPR_LIST_DECL_SINGLE(SD2DAT0, SD2, SD2_DESC); |
193 | SIG_EXPR_DECL(GPID2IN, GPID2, GPID2_DESC); | |
194 | SIG_EXPR_DECL(GPID2IN, GPID, GPID_DESC); | |
195 | SIG_EXPR_LIST_DECL_DUAL(GPID2IN, GPID2, GPID); | |
97e8c3f5 | 196 | MS_PIN_DECL(F20, GPIOD2, SD2DAT0, GPID2IN); |
56e57cb6 | 197 | |
97e8c3f5 | 198 | #define D20 27 |
56e57cb6 AJ |
199 | SIG_EXPR_LIST_DECL_SINGLE(SD2DAT1, SD2, SD2_DESC); |
200 | SIG_EXPR_DECL(GPID2OUT, GPID2, GPID2_DESC); | |
201 | SIG_EXPR_DECL(GPID2OUT, GPID, GPID_DESC); | |
202 | SIG_EXPR_LIST_DECL_DUAL(GPID2OUT, GPID2, GPID); | |
97e8c3f5 | 203 | MS_PIN_DECL(D20, GPIOD3, SD2DAT1, GPID2OUT); |
56e57cb6 | 204 | |
97e8c3f5 | 205 | FUNC_GROUP_DECL(GPID2, F20, D20); |
56e57cb6 | 206 | |
f1337856 AJ |
207 | #define GPID4_DESC SIG_DESC_SET(SCU8C, 10) |
208 | ||
209 | #define D21 28 | |
210 | SIG_EXPR_LIST_DECL_SINGLE(SD2DAT2, SD2, SD2_DESC); | |
211 | SIG_EXPR_DECL(GPID4IN, GPID4, GPID4_DESC); | |
212 | SIG_EXPR_DECL(GPID4IN, GPID, GPID_DESC); | |
213 | SIG_EXPR_LIST_DECL_DUAL(GPID4IN, GPID4, GPID); | |
214 | MS_PIN_DECL(D21, GPIOD4, SD2DAT2, GPID4IN); | |
215 | ||
216 | #define E20 29 | |
217 | SIG_EXPR_LIST_DECL_SINGLE(SD2DAT3, SD2, SD2_DESC); | |
218 | SIG_EXPR_DECL(GPID4OUT, GPID4, GPID4_DESC); | |
219 | SIG_EXPR_DECL(GPID4OUT, GPID, GPID_DESC); | |
220 | SIG_EXPR_LIST_DECL_DUAL(GPID4OUT, GPID4, GPID); | |
221 | MS_PIN_DECL(E20, GPIOD5, SD2DAT3, GPID4OUT); | |
222 | ||
223 | FUNC_GROUP_DECL(GPID4, D21, E20); | |
224 | ||
225 | #define GPID6_DESC SIG_DESC_SET(SCU8C, 11) | |
226 | ||
227 | #define G18 30 | |
228 | SIG_EXPR_LIST_DECL_SINGLE(SD2CD, SD2, SD2_DESC); | |
229 | SIG_EXPR_DECL(GPID6IN, GPID6, GPID6_DESC); | |
230 | SIG_EXPR_DECL(GPID6IN, GPID, GPID_DESC); | |
231 | SIG_EXPR_LIST_DECL_DUAL(GPID6IN, GPID6, GPID); | |
232 | MS_PIN_DECL(G18, GPIOD6, SD2CD, GPID6IN); | |
233 | ||
234 | #define C21 31 | |
235 | SIG_EXPR_LIST_DECL_SINGLE(SD2WP, SD2, SD2_DESC); | |
236 | SIG_EXPR_DECL(GPID6OUT, GPID6, GPID6_DESC); | |
237 | SIG_EXPR_DECL(GPID6OUT, GPID, GPID_DESC); | |
238 | SIG_EXPR_LIST_DECL_DUAL(GPID6OUT, GPID6, GPID); | |
239 | MS_PIN_DECL(C21, GPIOD7, SD2WP, GPID6OUT); | |
240 | ||
241 | FUNC_GROUP_DECL(GPID6, G18, C21); | |
242 | FUNC_GROUP_DECL(SD2, F19, E21, F20, D20, D21, E20, G18, C21); | |
243 | ||
244 | #define GPIE_DESC SIG_DESC_SET(HW_STRAP1, 22) | |
56e57cb6 AJ |
245 | #define GPIE0_DESC SIG_DESC_SET(SCU8C, 12) |
246 | ||
247 | #define B20 32 | |
248 | SIG_EXPR_LIST_DECL_SINGLE(NCTS3, NCTS3, SIG_DESC_SET(SCU80, 16)); | |
249 | SIG_EXPR_DECL(GPIE0IN, GPIE0, GPIE0_DESC); | |
250 | SIG_EXPR_DECL(GPIE0IN, GPIE, GPIE_DESC); | |
251 | SIG_EXPR_LIST_DECL_DUAL(GPIE0IN, GPIE0, GPIE); | |
252 | MS_PIN_DECL(B20, GPIOE0, NCTS3, GPIE0IN); | |
f1337856 | 253 | FUNC_GROUP_DECL(NCTS3, B20); |
56e57cb6 AJ |
254 | |
255 | #define C20 33 | |
256 | SIG_EXPR_LIST_DECL_SINGLE(NDCD3, NDCD3, SIG_DESC_SET(SCU80, 17)); | |
257 | SIG_EXPR_DECL(GPIE0OUT, GPIE0, GPIE0_DESC); | |
258 | SIG_EXPR_DECL(GPIE0OUT, GPIE, GPIE_DESC); | |
259 | SIG_EXPR_LIST_DECL_DUAL(GPIE0OUT, GPIE0, GPIE); | |
d3dbabe9 | 260 | MS_PIN_DECL(C20, GPIOE1, NDCD3, GPIE0OUT); |
f1337856 | 261 | FUNC_GROUP_DECL(NDCD3, C20); |
56e57cb6 AJ |
262 | |
263 | FUNC_GROUP_DECL(GPIE0, B20, C20); | |
264 | ||
f1337856 AJ |
265 | #define GPIE2_DESC SIG_DESC_SET(SCU8C, 13) |
266 | ||
267 | #define F18 34 | |
268 | SIG_EXPR_LIST_DECL_SINGLE(NDSR3, NDSR3, SIG_DESC_SET(SCU80, 18)); | |
269 | SIG_EXPR_DECL(GPIE2IN, GPIE2, GPIE2_DESC); | |
270 | SIG_EXPR_DECL(GPIE2IN, GPIE, GPIE_DESC); | |
271 | SIG_EXPR_LIST_DECL_DUAL(GPIE2IN, GPIE2, GPIE); | |
272 | MS_PIN_DECL(F18, GPIOE2, NDSR3, GPIE2IN); | |
273 | FUNC_GROUP_DECL(NDSR3, F18); | |
274 | ||
275 | ||
276 | #define F17 35 | |
277 | SIG_EXPR_LIST_DECL_SINGLE(NRI3, NRI3, SIG_DESC_SET(SCU80, 19)); | |
278 | SIG_EXPR_DECL(GPIE2OUT, GPIE2, GPIE2_DESC); | |
279 | SIG_EXPR_DECL(GPIE2OUT, GPIE, GPIE_DESC); | |
280 | SIG_EXPR_LIST_DECL_DUAL(GPIE2OUT, GPIE2, GPIE); | |
281 | MS_PIN_DECL(F17, GPIOE3, NRI3, GPIE2OUT); | |
282 | FUNC_GROUP_DECL(NRI3, F17); | |
283 | ||
284 | FUNC_GROUP_DECL(GPIE2, F18, F17); | |
285 | ||
286 | #define GPIE4_DESC SIG_DESC_SET(SCU8C, 14) | |
287 | ||
288 | #define E18 36 | |
289 | SIG_EXPR_LIST_DECL_SINGLE(NDTR3, NDTR3, SIG_DESC_SET(SCU80, 20)); | |
290 | SIG_EXPR_DECL(GPIE4IN, GPIE4, GPIE4_DESC); | |
291 | SIG_EXPR_DECL(GPIE4IN, GPIE, GPIE_DESC); | |
292 | SIG_EXPR_LIST_DECL_DUAL(GPIE4IN, GPIE4, GPIE); | |
293 | MS_PIN_DECL(E18, GPIOE4, NDTR3, GPIE4IN); | |
294 | FUNC_GROUP_DECL(NDTR3, E18); | |
295 | ||
296 | #define D19 37 | |
297 | SIG_EXPR_LIST_DECL_SINGLE(NRTS3, NRTS3, SIG_DESC_SET(SCU80, 21)); | |
298 | SIG_EXPR_DECL(GPIE4OUT, GPIE4, GPIE4_DESC); | |
299 | SIG_EXPR_DECL(GPIE4OUT, GPIE, GPIE_DESC); | |
300 | SIG_EXPR_LIST_DECL_DUAL(GPIE4OUT, GPIE4, GPIE); | |
301 | MS_PIN_DECL(D19, GPIOE5, NRTS3, GPIE4OUT); | |
302 | FUNC_GROUP_DECL(NRTS3, D19); | |
303 | ||
304 | FUNC_GROUP_DECL(GPIE4, E18, D19); | |
305 | ||
306 | #define GPIE6_DESC SIG_DESC_SET(SCU8C, 15) | |
307 | ||
308 | #define A20 38 | |
309 | SIG_EXPR_LIST_DECL_SINGLE(TXD3, TXD3, SIG_DESC_SET(SCU80, 22)); | |
310 | SIG_EXPR_DECL(GPIE6IN, GPIE6, GPIE6_DESC); | |
311 | SIG_EXPR_DECL(GPIE6IN, GPIE, GPIE_DESC); | |
312 | SIG_EXPR_LIST_DECL_DUAL(GPIE6IN, GPIE6, GPIE); | |
313 | MS_PIN_DECL(A20, GPIOE6, TXD3, GPIE6IN); | |
314 | FUNC_GROUP_DECL(TXD3, A20); | |
315 | ||
316 | #define B19 39 | |
317 | SIG_EXPR_LIST_DECL_SINGLE(RXD3, RXD3, SIG_DESC_SET(SCU80, 23)); | |
318 | SIG_EXPR_DECL(GPIE6OUT, GPIE6, GPIE6_DESC); | |
319 | SIG_EXPR_DECL(GPIE6OUT, GPIE, GPIE_DESC); | |
320 | SIG_EXPR_LIST_DECL_DUAL(GPIE6OUT, GPIE6, GPIE); | |
321 | MS_PIN_DECL(B19, GPIOE7, RXD3, GPIE6OUT); | |
322 | FUNC_GROUP_DECL(RXD3, B19); | |
323 | ||
324 | FUNC_GROUP_DECL(GPIE6, A20, B19); | |
325 | ||
326 | #define LPCHC_DESC SIG_DESC_IP_SET(ASPEED_IP_LPC, LHCR0, 0) | |
327 | #define LPCPLUS_DESC SIG_DESC_SET(SCU90, 30) | |
328 | ||
329 | #define J19 40 | |
330 | SIG_EXPR_DECL(LHAD0, LPCHC, LPCHC_DESC); | |
331 | SIG_EXPR_DECL(LHAD0, LPCPLUS, LPCPLUS_DESC); | |
332 | SIG_EXPR_LIST_DECL_DUAL(LHAD0, LPCHC, LPCPLUS); | |
333 | SIG_EXPR_LIST_DECL_SINGLE(NCTS4, NCTS4, SIG_DESC_SET(SCU80, 24)); | |
334 | MS_PIN_DECL(J19, GPIOF0, LHAD0, NCTS4); | |
335 | FUNC_GROUP_DECL(NCTS4, J19); | |
336 | ||
337 | #define J18 41 | |
338 | SIG_EXPR_DECL(LHAD1, LPCHC, LPCHC_DESC); | |
339 | SIG_EXPR_DECL(LHAD1, LPCPLUS, LPCPLUS_DESC); | |
340 | SIG_EXPR_LIST_DECL_DUAL(LHAD1, LPCHC, LPCPLUS); | |
341 | SIG_EXPR_LIST_DECL_SINGLE(NDCD4, NDCD4, SIG_DESC_SET(SCU80, 25)); | |
342 | MS_PIN_DECL(J18, GPIOF1, LHAD1, NDCD4); | |
343 | FUNC_GROUP_DECL(NDCD4, J18); | |
344 | ||
345 | #define B22 42 | |
346 | SIG_EXPR_DECL(LHAD2, LPCHC, LPCHC_DESC); | |
347 | SIG_EXPR_DECL(LHAD2, LPCPLUS, LPCPLUS_DESC); | |
348 | SIG_EXPR_LIST_DECL_DUAL(LHAD2, LPCHC, LPCPLUS); | |
349 | SIG_EXPR_LIST_DECL_SINGLE(NDSR4, NDSR4, SIG_DESC_SET(SCU80, 26)); | |
350 | MS_PIN_DECL(B22, GPIOF2, LHAD2, NDSR4); | |
351 | FUNC_GROUP_DECL(NDSR4, B22); | |
352 | ||
353 | #define B21 43 | |
354 | SIG_EXPR_DECL(LHAD3, LPCHC, LPCHC_DESC); | |
355 | SIG_EXPR_DECL(LHAD3, LPCPLUS, LPCPLUS_DESC); | |
356 | SIG_EXPR_LIST_DECL_DUAL(LHAD3, LPCHC, LPCPLUS); | |
357 | SIG_EXPR_LIST_DECL_SINGLE(NRI4, NRI4, SIG_DESC_SET(SCU80, 27)); | |
358 | MS_PIN_DECL(B21, GPIOF3, LHAD3, NRI4); | |
359 | FUNC_GROUP_DECL(NRI4, B21); | |
360 | ||
361 | #define A21 44 | |
362 | SIG_EXPR_DECL(LHCLK, LPCHC, LPCHC_DESC); | |
363 | SIG_EXPR_DECL(LHCLK, LPCPLUS, LPCPLUS_DESC); | |
364 | SIG_EXPR_LIST_DECL_DUAL(LHCLK, LPCHC, LPCPLUS); | |
365 | SIG_EXPR_LIST_DECL_SINGLE(NDTR4, NDTR4, SIG_DESC_SET(SCU80, 28)); | |
366 | MS_PIN_DECL(A21, GPIOF4, LHCLK, NDTR4); | |
367 | FUNC_GROUP_DECL(NDTR4, A21); | |
368 | ||
369 | #define H19 45 | |
370 | SIG_EXPR_DECL(LHFRAME, LPCHC, LPCHC_DESC); | |
371 | SIG_EXPR_DECL(LHFRAME, LPCPLUS, LPCPLUS_DESC); | |
372 | SIG_EXPR_LIST_DECL_DUAL(LHFRAME, LPCHC, LPCPLUS); | |
373 | SIG_EXPR_LIST_DECL_SINGLE(NRTS4, NRTS4, SIG_DESC_SET(SCU80, 29)); | |
374 | MS_PIN_DECL(H19, GPIOF5, LHFRAME, NRTS4); | |
375 | FUNC_GROUP_DECL(NRTS4, H19); | |
376 | ||
377 | #define G17 46 | |
378 | SIG_EXPR_LIST_DECL_SINGLE(LHSIRQ, LPCHC, LPCHC_DESC); | |
379 | SIG_EXPR_LIST_DECL_SINGLE(TXD4, TXD4, SIG_DESC_SET(SCU80, 30)); | |
380 | MS_PIN_DECL(G17, GPIOF6, LHSIRQ, TXD4); | |
381 | FUNC_GROUP_DECL(TXD4, G17); | |
382 | ||
383 | #define H18 47 | |
384 | SIG_EXPR_DECL(LHRST, LPCHC, LPCHC_DESC); | |
385 | SIG_EXPR_DECL(LHRST, LPCPLUS, LPCPLUS_DESC); | |
386 | SIG_EXPR_LIST_DECL_DUAL(LHRST, LPCHC, LPCPLUS); | |
387 | SIG_EXPR_LIST_DECL_SINGLE(RXD4, RXD4, SIG_DESC_SET(SCU80, 31)); | |
388 | MS_PIN_DECL(H18, GPIOF7, LHRST, RXD4); | |
389 | FUNC_GROUP_DECL(RXD4, H18); | |
390 | ||
391 | FUNC_GROUP_DECL(LPCHC, J19, J18, B22, B21, A21, H19, G17, H18); | |
392 | FUNC_GROUP_DECL(LPCPLUS, J19, J18, B22, B21, A21, H19, H18); | |
393 | ||
394 | #define A19 48 | |
395 | SIG_EXPR_LIST_DECL_SINGLE(SGPS1CK, SGPS1, COND1, SIG_DESC_SET(SCU84, 0)); | |
396 | SS_PIN_DECL(A19, GPIOG0, SGPS1CK); | |
397 | ||
398 | #define E19 49 | |
399 | SIG_EXPR_LIST_DECL_SINGLE(SGPS1LD, SGPS1, COND1, SIG_DESC_SET(SCU84, 1)); | |
400 | SS_PIN_DECL(E19, GPIOG1, SGPS1LD); | |
401 | ||
402 | #define C19 50 | |
403 | SIG_EXPR_LIST_DECL_SINGLE(SGPS1I0, SGPS1, COND1, SIG_DESC_SET(SCU84, 2)); | |
404 | SS_PIN_DECL(C19, GPIOG2, SGPS1I0); | |
405 | ||
406 | #define E16 51 | |
407 | SIG_EXPR_LIST_DECL_SINGLE(SGPS1I1, SGPS1, COND1, SIG_DESC_SET(SCU84, 3)); | |
408 | SS_PIN_DECL(E16, GPIOG3, SGPS1I1); | |
409 | ||
410 | FUNC_GROUP_DECL(SGPS1, A19, E19, C19, E16); | |
411 | ||
412 | #define SGPS2_DESC SIG_DESC_SET(SCU94, 12) | |
413 | ||
414 | #define E17 52 | |
415 | SIG_EXPR_LIST_DECL_SINGLE(SGPS2CK, SGPS2, COND1, SGPS2_DESC); | |
416 | SIG_EXPR_LIST_DECL_SINGLE(SALT1, SALT1, COND1, SIG_DESC_SET(SCU84, 4)); | |
417 | MS_PIN_DECL(E17, GPIOG4, SGPS2CK, SALT1); | |
418 | FUNC_GROUP_DECL(SALT1, E17); | |
419 | ||
420 | #define D16 53 | |
421 | SIG_EXPR_LIST_DECL_SINGLE(SGPS2LD, SGPS2, COND1, SGPS2_DESC); | |
422 | SIG_EXPR_LIST_DECL_SINGLE(SALT2, SALT2, COND1, SIG_DESC_SET(SCU84, 5)); | |
423 | MS_PIN_DECL(D16, GPIOG5, SGPS2LD, SALT2); | |
424 | FUNC_GROUP_DECL(SALT2, D16); | |
425 | ||
426 | #define D15 54 | |
427 | SIG_EXPR_LIST_DECL_SINGLE(SGPS2I0, SGPS2, COND1, SGPS2_DESC); | |
428 | SIG_EXPR_LIST_DECL_SINGLE(SALT3, SALT3, COND1, SIG_DESC_SET(SCU84, 6)); | |
429 | MS_PIN_DECL(D15, GPIOG6, SGPS2I0, SALT3); | |
430 | FUNC_GROUP_DECL(SALT3, D15); | |
431 | ||
432 | #define E14 55 | |
433 | SIG_EXPR_LIST_DECL_SINGLE(SGPS2I1, SGPS2, COND1, SGPS2_DESC); | |
434 | SIG_EXPR_LIST_DECL_SINGLE(SALT4, SALT4, COND1, SIG_DESC_SET(SCU84, 7)); | |
435 | MS_PIN_DECL(E14, GPIOG7, SGPS2I1, SALT4); | |
436 | FUNC_GROUP_DECL(SALT4, E14); | |
437 | ||
438 | FUNC_GROUP_DECL(SGPS2, E17, D16, D15, E14); | |
439 | ||
440 | #define UART6_DESC SIG_DESC_SET(SCU90, 7) | |
441 | ||
442 | #define A18 56 | |
443 | SIG_EXPR_LIST_DECL_SINGLE(DASHA18, DASHA18, COND1, SIG_DESC_SET(SCU94, 5)); | |
444 | SIG_EXPR_LIST_DECL_SINGLE(NCTS6, UART6, COND1, UART6_DESC); | |
445 | MS_PIN_DECL(A18, GPIOH0, DASHA18, NCTS6); | |
446 | ||
447 | #define B18 57 | |
448 | SIG_EXPR_LIST_DECL_SINGLE(DASHB18, DASHB18, COND1, SIG_DESC_SET(SCU94, 5)); | |
449 | SIG_EXPR_LIST_DECL_SINGLE(NDCD6, UART6, COND1, UART6_DESC); | |
450 | MS_PIN_DECL(B18, GPIOH1, DASHB18, NDCD6); | |
451 | ||
452 | #define D17 58 | |
453 | SIG_EXPR_LIST_DECL_SINGLE(DASHD17, DASHD17, COND1, SIG_DESC_SET(SCU94, 6)); | |
454 | SIG_EXPR_LIST_DECL_SINGLE(NDSR6, UART6, COND1, UART6_DESC); | |
455 | MS_PIN_DECL(D17, GPIOH2, DASHD17, NDSR6); | |
456 | ||
457 | #define C17 59 | |
458 | SIG_EXPR_LIST_DECL_SINGLE(DASHC17, DASHC17, COND1, SIG_DESC_SET(SCU94, 6)); | |
459 | SIG_EXPR_LIST_DECL_SINGLE(NRI6, UART6, COND1, UART6_DESC); | |
460 | MS_PIN_DECL(C17, GPIOH3, DASHC17, NRI6); | |
461 | ||
462 | #define A17 60 | |
463 | SIG_EXPR_LIST_DECL_SINGLE(DASHA17, DASHA17, COND1, SIG_DESC_SET(SCU94, 7)); | |
464 | SIG_EXPR_LIST_DECL_SINGLE(NDTR6, UART6, COND1, UART6_DESC); | |
465 | MS_PIN_DECL(A17, GPIOH4, DASHA17, NDTR6); | |
466 | ||
467 | #define B17 61 | |
468 | SIG_EXPR_LIST_DECL_SINGLE(DASHB17, DASHB17, COND1, SIG_DESC_SET(SCU94, 7)); | |
469 | SIG_EXPR_LIST_DECL_SINGLE(NRTS6, UART6, COND1, UART6_DESC); | |
470 | MS_PIN_DECL(B17, GPIOH5, DASHB17, NRTS6); | |
471 | ||
472 | #define A16 62 | |
473 | SIG_EXPR_LIST_DECL_SINGLE(TXD6, UART6, COND1, UART6_DESC); | |
474 | SS_PIN_DECL(A16, GPIOH6, TXD6); | |
475 | ||
476 | #define D18 63 | |
477 | SIG_EXPR_LIST_DECL_SINGLE(RXD6, UART6, COND1, UART6_DESC); | |
478 | SS_PIN_DECL(D18, GPIOH7, RXD6); | |
479 | ||
480 | FUNC_GROUP_DECL(UART6, A18, B18, D17, C17, A17, B17, A16, D18); | |
481 | ||
7d29ed88 AJ |
482 | #define SPI1_DESC \ |
483 | { ASPEED_IP_SCU, HW_STRAP1, GENMASK(13, 12), 1, 0 } | |
484 | #define SPI1DEBUG_DESC \ | |
485 | { ASPEED_IP_SCU, HW_STRAP1, GENMASK(13, 12), 2, 0 } | |
486 | #define SPI1PASSTHRU_DESC \ | |
487 | { ASPEED_IP_SCU, HW_STRAP1, GENMASK(13, 12), 3, 0 } | |
8eb37aff | 488 | |
56e57cb6 | 489 | #define C18 64 |
8eb37aff AJ |
490 | SIG_EXPR_DECL(SYSCS, SPI1DEBUG, COND1, SPI1DEBUG_DESC); |
491 | SIG_EXPR_DECL(SYSCS, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC); | |
492 | SIG_EXPR_LIST_DECL_DUAL(SYSCS, SPI1DEBUG, SPI1PASSTHRU); | |
56e57cb6 AJ |
493 | SS_PIN_DECL(C18, GPIOI0, SYSCS); |
494 | ||
495 | #define E15 65 | |
8eb37aff AJ |
496 | SIG_EXPR_DECL(SYSCK, SPI1DEBUG, COND1, SPI1DEBUG_DESC); |
497 | SIG_EXPR_DECL(SYSCK, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC); | |
498 | SIG_EXPR_LIST_DECL_DUAL(SYSCK, SPI1DEBUG, SPI1PASSTHRU); | |
56e57cb6 AJ |
499 | SS_PIN_DECL(E15, GPIOI1, SYSCK); |
500 | ||
8eb37aff AJ |
501 | #define B16 66 |
502 | SIG_EXPR_DECL(SYSMOSI, SPI1DEBUG, COND1, SPI1DEBUG_DESC); | |
503 | SIG_EXPR_DECL(SYSMOSI, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC); | |
504 | SIG_EXPR_LIST_DECL_DUAL(SYSMOSI, SPI1DEBUG, SPI1PASSTHRU); | |
505 | SS_PIN_DECL(B16, GPIOI2, SYSMOSI); | |
56e57cb6 AJ |
506 | |
507 | #define C16 67 | |
8eb37aff AJ |
508 | SIG_EXPR_DECL(SYSMISO, SPI1DEBUG, COND1, SPI1DEBUG_DESC); |
509 | SIG_EXPR_DECL(SYSMISO, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC); | |
510 | SIG_EXPR_LIST_DECL_DUAL(SYSMISO, SPI1DEBUG, SPI1PASSTHRU); | |
56e57cb6 AJ |
511 | SS_PIN_DECL(C16, GPIOI3, SYSMISO); |
512 | ||
8eb37aff AJ |
513 | #define VB_DESC SIG_DESC_SET(HW_STRAP1, 5) |
514 | ||
515 | #define B15 68 | |
516 | SIG_EXPR_DECL(SPI1CS0, SPI1, COND1, SPI1_DESC); | |
517 | SIG_EXPR_DECL(SPI1CS0, SPI1DEBUG, COND1, SPI1DEBUG_DESC); | |
518 | SIG_EXPR_DECL(SPI1CS0, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC); | |
519 | SIG_EXPR_LIST_DECL(SPI1CS0, SIG_EXPR_PTR(SPI1CS0, SPI1), | |
520 | SIG_EXPR_PTR(SPI1CS0, SPI1DEBUG), | |
521 | SIG_EXPR_PTR(SPI1CS0, SPI1PASSTHRU)); | |
522 | SIG_EXPR_LIST_DECL_SINGLE(VBCS, VGABIOSROM, COND1, VB_DESC); | |
523 | MS_PIN_DECL(B15, GPIOI4, SPI1CS0, VBCS); | |
524 | ||
525 | #define C15 69 | |
526 | SIG_EXPR_DECL(SPI1CK, SPI1, COND1, SPI1_DESC); | |
527 | SIG_EXPR_DECL(SPI1CK, SPI1DEBUG, COND1, SPI1DEBUG_DESC); | |
528 | SIG_EXPR_DECL(SPI1CK, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC); | |
529 | SIG_EXPR_LIST_DECL(SPI1CK, SIG_EXPR_PTR(SPI1CK, SPI1), | |
530 | SIG_EXPR_PTR(SPI1CK, SPI1DEBUG), | |
531 | SIG_EXPR_PTR(SPI1CK, SPI1PASSTHRU)); | |
532 | SIG_EXPR_LIST_DECL_SINGLE(VBCK, VGABIOSROM, COND1, VB_DESC); | |
533 | MS_PIN_DECL(C15, GPIOI5, SPI1CK, VBCK); | |
534 | ||
535 | #define A14 70 | |
536 | SIG_EXPR_DECL(SPI1MOSI, SPI1, COND1, SPI1_DESC); | |
537 | SIG_EXPR_DECL(SPI1MOSI, SPI1DEBUG, COND1, SPI1DEBUG_DESC); | |
538 | SIG_EXPR_DECL(SPI1MOSI, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC); | |
539 | SIG_EXPR_LIST_DECL(SPI1MOSI, SIG_EXPR_PTR(SPI1MOSI, SPI1), | |
540 | SIG_EXPR_PTR(SPI1MOSI, SPI1DEBUG), | |
541 | SIG_EXPR_PTR(SPI1MOSI, SPI1PASSTHRU)); | |
542 | SIG_EXPR_LIST_DECL_SINGLE(VBMOSI, VGABIOSROM, COND1, VB_DESC); | |
543 | MS_PIN_DECL(A14, GPIOI6, SPI1MOSI, VBMOSI); | |
544 | ||
545 | #define A15 71 | |
546 | SIG_EXPR_DECL(SPI1MISO, SPI1, COND1, SPI1_DESC); | |
547 | SIG_EXPR_DECL(SPI1MISO, SPI1DEBUG, COND1, SPI1DEBUG_DESC); | |
548 | SIG_EXPR_DECL(SPI1MISO, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC); | |
549 | SIG_EXPR_LIST_DECL(SPI1MISO, SIG_EXPR_PTR(SPI1MISO, SPI1), | |
550 | SIG_EXPR_PTR(SPI1MISO, SPI1DEBUG), | |
551 | SIG_EXPR_PTR(SPI1MISO, SPI1PASSTHRU)); | |
552 | SIG_EXPR_LIST_DECL_SINGLE(VBMISO, VGABIOSROM, COND1, VB_DESC); | |
553 | MS_PIN_DECL(A15, GPIOI7, SPI1MISO, VBMISO); | |
554 | ||
555 | FUNC_GROUP_DECL(SPI1, B15, C15, A14, A15); | |
556 | FUNC_GROUP_DECL(SPI1DEBUG, C18, E15, B16, C16, B15, C15, A14, A15); | |
557 | FUNC_GROUP_DECL(SPI1PASSTHRU, C18, E15, B16, C16, B15, C15, A14, A15); | |
558 | FUNC_GROUP_DECL(VGABIOSROM, B15, C15, A14, A15); | |
559 | ||
560 | #define R2 72 | |
561 | SIG_EXPR_LIST_DECL_SINGLE(SGPMCK, SGPM, SIG_DESC_SET(SCU84, 8)); | |
562 | SS_PIN_DECL(R2, GPIOJ0, SGPMCK); | |
56e57cb6 AJ |
563 | |
564 | #define L2 73 | |
565 | SIG_EXPR_LIST_DECL_SINGLE(SGPMLD, SGPM, SIG_DESC_SET(SCU84, 9)); | |
566 | SS_PIN_DECL(L2, GPIOJ1, SGPMLD); | |
567 | ||
568 | #define N3 74 | |
569 | SIG_EXPR_LIST_DECL_SINGLE(SGPMO, SGPM, SIG_DESC_SET(SCU84, 10)); | |
570 | SS_PIN_DECL(N3, GPIOJ2, SGPMO); | |
571 | ||
572 | #define N4 75 | |
573 | SIG_EXPR_LIST_DECL_SINGLE(SGPMI, SGPM, SIG_DESC_SET(SCU84, 11)); | |
574 | SS_PIN_DECL(N4, GPIOJ3, SGPMI); | |
575 | ||
f1337856 AJ |
576 | #define N5 76 |
577 | SIG_EXPR_LIST_DECL_SINGLE(VGAHS, VGAHS, SIG_DESC_SET(SCU84, 12)); | |
578 | SIG_EXPR_LIST_DECL_SINGLE(DASHN5, DASHN5, SIG_DESC_SET(SCU94, 8)); | |
579 | MS_PIN_DECL(N5, GPIOJ4, VGAHS, DASHN5); | |
580 | FUNC_GROUP_DECL(VGAHS, N5); | |
581 | ||
582 | #define R4 77 | |
583 | SIG_EXPR_LIST_DECL_SINGLE(VGAVS, VGAVS, SIG_DESC_SET(SCU84, 13)); | |
584 | SIG_EXPR_LIST_DECL_SINGLE(DASHR4, DASHR4, SIG_DESC_SET(SCU94, 8)); | |
585 | MS_PIN_DECL(R4, GPIOJ5, VGAVS, DASHR4); | |
586 | FUNC_GROUP_DECL(VGAVS, R4); | |
587 | ||
588 | #define R3 78 | |
589 | SIG_EXPR_LIST_DECL_SINGLE(DDCCLK, DDCCLK, SIG_DESC_SET(SCU84, 14)); | |
590 | SIG_EXPR_LIST_DECL_SINGLE(DASHR3, DASHR3, SIG_DESC_SET(SCU94, 9)); | |
591 | MS_PIN_DECL(R3, GPIOJ6, DDCCLK, DASHR3); | |
592 | FUNC_GROUP_DECL(DDCCLK, R3); | |
593 | ||
594 | #define T3 79 | |
595 | SIG_EXPR_LIST_DECL_SINGLE(DDCDAT, DDCDAT, SIG_DESC_SET(SCU84, 15)); | |
596 | SIG_EXPR_LIST_DECL_SINGLE(DASHT3, DASHT3, SIG_DESC_SET(SCU94, 9)); | |
597 | MS_PIN_DECL(T3, GPIOJ7, DDCDAT, DASHT3); | |
598 | FUNC_GROUP_DECL(DDCDAT, T3); | |
599 | ||
56e57cb6 AJ |
600 | #define I2C5_DESC SIG_DESC_SET(SCU90, 18) |
601 | ||
602 | #define L3 80 | |
603 | SIG_EXPR_LIST_DECL_SINGLE(SCL5, I2C5, I2C5_DESC); | |
604 | SS_PIN_DECL(L3, GPIOK0, SCL5); | |
605 | ||
606 | #define L4 81 | |
607 | SIG_EXPR_LIST_DECL_SINGLE(SDA5, I2C5, I2C5_DESC); | |
608 | SS_PIN_DECL(L4, GPIOK1, SDA5); | |
609 | ||
610 | FUNC_GROUP_DECL(I2C5, L3, L4); | |
611 | ||
612 | #define I2C6_DESC SIG_DESC_SET(SCU90, 19) | |
613 | ||
614 | #define L1 82 | |
615 | SIG_EXPR_LIST_DECL_SINGLE(SCL6, I2C6, I2C6_DESC); | |
616 | SS_PIN_DECL(L1, GPIOK2, SCL6); | |
617 | ||
618 | #define N2 83 | |
619 | SIG_EXPR_LIST_DECL_SINGLE(SDA6, I2C6, I2C6_DESC); | |
620 | SS_PIN_DECL(N2, GPIOK3, SDA6); | |
621 | ||
622 | FUNC_GROUP_DECL(I2C6, L1, N2); | |
623 | ||
624 | #define I2C7_DESC SIG_DESC_SET(SCU90, 20) | |
625 | ||
626 | #define N1 84 | |
627 | SIG_EXPR_LIST_DECL_SINGLE(SCL7, I2C7, I2C7_DESC); | |
628 | SS_PIN_DECL(N1, GPIOK4, SCL7); | |
629 | ||
630 | #define P1 85 | |
631 | SIG_EXPR_LIST_DECL_SINGLE(SDA7, I2C7, I2C7_DESC); | |
632 | SS_PIN_DECL(P1, GPIOK5, SDA7); | |
633 | ||
634 | FUNC_GROUP_DECL(I2C7, N1, P1); | |
635 | ||
636 | #define I2C8_DESC SIG_DESC_SET(SCU90, 21) | |
637 | ||
638 | #define P2 86 | |
639 | SIG_EXPR_LIST_DECL_SINGLE(SCL8, I2C8, I2C8_DESC); | |
640 | SS_PIN_DECL(P2, GPIOK6, SCL8); | |
641 | ||
642 | #define R1 87 | |
643 | SIG_EXPR_LIST_DECL_SINGLE(SDA8, I2C8, I2C8_DESC); | |
644 | SS_PIN_DECL(R1, GPIOK7, SDA8); | |
645 | ||
646 | FUNC_GROUP_DECL(I2C8, P2, R1); | |
647 | ||
f1337856 AJ |
648 | #define T2 88 |
649 | SSSF_PIN_DECL(T2, GPIOL0, NCTS1, SIG_DESC_SET(SCU84, 16)); | |
650 | ||
7d29ed88 AJ |
651 | #define VPIOFF0_DESC { ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 0, 0 } |
652 | #define VPIOFF1_DESC { ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 1, 0 } | |
653 | #define VPI24_DESC { ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 2, 0 } | |
654 | #define VPIRSVD_DESC { ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 3, 0 } | |
f1337856 AJ |
655 | #define VPI_24_RSVD_DESC SIG_DESC_SET(SCU90, 5) |
656 | ||
657 | #define T1 89 | |
658 | #define T1_DESC SIG_DESC_SET(SCU84, 17) | |
659 | SIG_EXPR_LIST_DECL_SINGLE(VPIDE, VPI24, VPI_24_RSVD_DESC, T1_DESC, COND2); | |
660 | SIG_EXPR_LIST_DECL_SINGLE(NDCD1, NDCD1, T1_DESC, COND2); | |
661 | MS_PIN_DECL(T1, GPIOL1, VPIDE, NDCD1); | |
662 | FUNC_GROUP_DECL(NDCD1, T1); | |
663 | ||
664 | #define U1 90 | |
665 | #define U1_DESC SIG_DESC_SET(SCU84, 18) | |
666 | SIG_EXPR_LIST_DECL_SINGLE(DASHU1, VPI24, VPI_24_RSVD_DESC, U1_DESC); | |
667 | SIG_EXPR_LIST_DECL_SINGLE(NDSR1, NDSR1, U1_DESC); | |
668 | MS_PIN_DECL(U1, GPIOL2, DASHU1, NDSR1); | |
669 | FUNC_GROUP_DECL(NDSR1, U1); | |
670 | ||
671 | #define U2 91 | |
672 | #define U2_DESC SIG_DESC_SET(SCU84, 19) | |
673 | SIG_EXPR_LIST_DECL_SINGLE(VPIHS, VPI24, VPI_24_RSVD_DESC, U2_DESC, COND2); | |
674 | SIG_EXPR_LIST_DECL_SINGLE(NRI1, NRI1, U2_DESC, COND2); | |
675 | MS_PIN_DECL(U2, GPIOL3, VPIHS, NRI1); | |
676 | FUNC_GROUP_DECL(NRI1, U2); | |
677 | ||
678 | #define P4 92 | |
679 | #define P4_DESC SIG_DESC_SET(SCU84, 20) | |
680 | SIG_EXPR_LIST_DECL_SINGLE(VPIVS, VPI24, VPI_24_RSVD_DESC, P4_DESC, COND2); | |
681 | SIG_EXPR_LIST_DECL_SINGLE(NDTR1, NDTR1, P4_DESC, COND2); | |
682 | MS_PIN_DECL(P4, GPIOL4, VPIVS, NDTR1); | |
683 | FUNC_GROUP_DECL(NDTR1, P4); | |
684 | ||
685 | #define P3 93 | |
686 | #define P3_DESC SIG_DESC_SET(SCU84, 21) | |
687 | SIG_EXPR_LIST_DECL_SINGLE(VPICLK, VPI24, VPI_24_RSVD_DESC, P3_DESC, COND2); | |
688 | SIG_EXPR_LIST_DECL_SINGLE(NRTS1, NRTS1, P3_DESC, COND2); | |
689 | MS_PIN_DECL(P3, GPIOL5, VPICLK, NRTS1); | |
690 | FUNC_GROUP_DECL(NRTS1, P3); | |
691 | ||
692 | #define V1 94 | |
693 | #define V1_DESC SIG_DESC_SET(SCU84, 22) | |
694 | SIG_EXPR_LIST_DECL_SINGLE(DASHV1, DASHV1, VPIRSVD_DESC, V1_DESC); | |
695 | SIG_EXPR_LIST_DECL_SINGLE(TXD1, TXD1, V1_DESC, COND2); | |
696 | MS_PIN_DECL(V1, GPIOL6, DASHV1, TXD1); | |
697 | FUNC_GROUP_DECL(TXD1, V1); | |
698 | ||
699 | #define W1 95 | |
700 | #define W1_DESC SIG_DESC_SET(SCU84, 23) | |
701 | SIG_EXPR_LIST_DECL_SINGLE(DASHW1, DASHW1, VPIRSVD_DESC, W1_DESC); | |
702 | SIG_EXPR_LIST_DECL_SINGLE(RXD1, RXD1, W1_DESC, COND2); | |
703 | MS_PIN_DECL(W1, GPIOL7, DASHW1, RXD1); | |
704 | FUNC_GROUP_DECL(RXD1, W1); | |
705 | ||
706 | #define Y1 96 | |
707 | #define Y1_DESC SIG_DESC_SET(SCU84, 24) | |
708 | SIG_EXPR_LIST_DECL_SINGLE(VPIB2, VPI24, VPI_24_RSVD_DESC, Y1_DESC, COND2); | |
709 | SIG_EXPR_LIST_DECL_SINGLE(NCTS2, NCTS2, Y1_DESC, COND2); | |
710 | MS_PIN_DECL(Y1, GPIOM0, VPIB2, NCTS2); | |
711 | FUNC_GROUP_DECL(NCTS2, Y1); | |
712 | ||
713 | #define AB2 97 | |
714 | #define AB2_DESC SIG_DESC_SET(SCU84, 25) | |
715 | SIG_EXPR_LIST_DECL_SINGLE(VPIB3, VPI24, VPI_24_RSVD_DESC, AB2_DESC, COND2); | |
716 | SIG_EXPR_LIST_DECL_SINGLE(NDCD2, NDCD2, AB2_DESC, COND2); | |
717 | MS_PIN_DECL(AB2, GPIOM1, VPIB3, NDCD2); | |
718 | FUNC_GROUP_DECL(NDCD2, AB2); | |
719 | ||
720 | #define AA1 98 | |
721 | #define AA1_DESC SIG_DESC_SET(SCU84, 26) | |
722 | SIG_EXPR_LIST_DECL_SINGLE(VPIB4, VPI24, VPI_24_RSVD_DESC, AA1_DESC, COND2); | |
723 | SIG_EXPR_LIST_DECL_SINGLE(NDSR2, NDSR2, AA1_DESC, COND2); | |
724 | MS_PIN_DECL(AA1, GPIOM2, VPIB4, NDSR2); | |
725 | FUNC_GROUP_DECL(NDSR2, AA1); | |
726 | ||
727 | #define Y2 99 | |
728 | #define Y2_DESC SIG_DESC_SET(SCU84, 27) | |
729 | SIG_EXPR_LIST_DECL_SINGLE(VPIB5, VPI24, VPI_24_RSVD_DESC, Y2_DESC, COND2); | |
730 | SIG_EXPR_LIST_DECL_SINGLE(NRI2, NRI2, Y2_DESC, COND2); | |
731 | MS_PIN_DECL(Y2, GPIOM3, VPIB5, NRI2); | |
732 | FUNC_GROUP_DECL(NRI2, Y2); | |
733 | ||
734 | #define AA2 100 | |
735 | #define AA2_DESC SIG_DESC_SET(SCU84, 28) | |
736 | SIG_EXPR_LIST_DECL_SINGLE(VPIB6, VPI24, VPI_24_RSVD_DESC, AA2_DESC, COND2); | |
737 | SIG_EXPR_LIST_DECL_SINGLE(NDTR2, NDTR2, AA2_DESC, COND2); | |
738 | MS_PIN_DECL(AA2, GPIOM4, VPIB6, NDTR2); | |
739 | FUNC_GROUP_DECL(NDTR2, AA2); | |
740 | ||
741 | #define P5 101 | |
742 | #define P5_DESC SIG_DESC_SET(SCU84, 29) | |
743 | SIG_EXPR_LIST_DECL_SINGLE(VPIB7, VPI24, VPI_24_RSVD_DESC, P5_DESC, COND2); | |
744 | SIG_EXPR_LIST_DECL_SINGLE(NRTS2, NRTS2, P5_DESC, COND2); | |
745 | MS_PIN_DECL(P5, GPIOM5, VPIB7, NRTS2); | |
746 | FUNC_GROUP_DECL(NRTS2, P5); | |
747 | ||
748 | #define R5 102 | |
749 | #define R5_DESC SIG_DESC_SET(SCU84, 30) | |
750 | SIG_EXPR_LIST_DECL_SINGLE(VPIB8, VPI24, VPI_24_RSVD_DESC, R5_DESC, COND2); | |
751 | SIG_EXPR_LIST_DECL_SINGLE(TXD2, TXD2, R5_DESC, COND2); | |
752 | MS_PIN_DECL(R5, GPIOM6, VPIB8, TXD2); | |
753 | FUNC_GROUP_DECL(TXD2, R5); | |
754 | ||
755 | #define T5 103 | |
756 | #define T5_DESC SIG_DESC_SET(SCU84, 31) | |
757 | SIG_EXPR_LIST_DECL_SINGLE(VPIB9, VPI24, VPI_24_RSVD_DESC, T5_DESC, COND2); | |
758 | SIG_EXPR_LIST_DECL_SINGLE(RXD2, RXD2, T5_DESC, COND2); | |
759 | MS_PIN_DECL(T5, GPIOM7, VPIB9, RXD2); | |
760 | FUNC_GROUP_DECL(RXD2, T5); | |
56e57cb6 AJ |
761 | |
762 | #define V2 104 | |
763 | #define V2_DESC SIG_DESC_SET(SCU88, 0) | |
764 | SIG_EXPR_LIST_DECL_SINGLE(DASHN0, DASHN0, VPIRSVD_DESC, V2_DESC); | |
765 | SIG_EXPR_LIST_DECL_SINGLE(PWM0, PWM0, V2_DESC, COND2); | |
766 | MS_PIN_DECL(V2, GPION0, DASHN0, PWM0); | |
767 | FUNC_GROUP_DECL(PWM0, V2); | |
768 | ||
769 | #define W2 105 | |
770 | #define W2_DESC SIG_DESC_SET(SCU88, 1) | |
771 | SIG_EXPR_LIST_DECL_SINGLE(DASHN1, DASHN1, VPIRSVD_DESC, W2_DESC); | |
772 | SIG_EXPR_LIST_DECL_SINGLE(PWM1, PWM1, W2_DESC, COND2); | |
773 | MS_PIN_DECL(W2, GPION1, DASHN1, PWM1); | |
774 | FUNC_GROUP_DECL(PWM1, W2); | |
775 | ||
776 | #define V3 106 | |
777 | #define V3_DESC SIG_DESC_SET(SCU88, 2) | |
778 | SIG_EXPR_DECL(VPIG2, VPI24, VPI24_DESC, V3_DESC, COND2); | |
779 | SIG_EXPR_DECL(VPIG2, VPIRSVD, VPIRSVD_DESC, V3_DESC, COND2); | |
780 | SIG_EXPR_LIST_DECL_DUAL(VPIG2, VPI24, VPIRSVD); | |
781 | SIG_EXPR_LIST_DECL_SINGLE(PWM2, PWM2, V3_DESC, COND2); | |
782 | MS_PIN_DECL(V3, GPION2, VPIG2, PWM2); | |
783 | FUNC_GROUP_DECL(PWM2, V3); | |
784 | ||
785 | #define U3 107 | |
786 | #define U3_DESC SIG_DESC_SET(SCU88, 3) | |
787 | SIG_EXPR_DECL(VPIG3, VPI24, VPI24_DESC, U3_DESC, COND2); | |
788 | SIG_EXPR_DECL(VPIG3, VPIRSVD, VPIRSVD_DESC, U3_DESC, COND2); | |
789 | SIG_EXPR_LIST_DECL_DUAL(VPIG3, VPI24, VPIRSVD); | |
790 | SIG_EXPR_LIST_DECL_SINGLE(PWM3, PWM3, U3_DESC, COND2); | |
791 | MS_PIN_DECL(U3, GPION3, VPIG3, PWM3); | |
792 | FUNC_GROUP_DECL(PWM3, U3); | |
793 | ||
794 | #define W3 108 | |
795 | #define W3_DESC SIG_DESC_SET(SCU88, 4) | |
796 | SIG_EXPR_DECL(VPIG4, VPI24, VPI24_DESC, W3_DESC, COND2); | |
797 | SIG_EXPR_DECL(VPIG4, VPIRSVD, VPIRSVD_DESC, W3_DESC, COND2); | |
798 | SIG_EXPR_LIST_DECL_DUAL(VPIG4, VPI24, VPIRSVD); | |
799 | SIG_EXPR_LIST_DECL_SINGLE(PWM4, PWM4, W3_DESC, COND2); | |
800 | MS_PIN_DECL(W3, GPION4, VPIG4, PWM4); | |
801 | FUNC_GROUP_DECL(PWM4, W3); | |
802 | ||
803 | #define AA3 109 | |
804 | #define AA3_DESC SIG_DESC_SET(SCU88, 5) | |
805 | SIG_EXPR_DECL(VPIG5, VPI24, VPI24_DESC, AA3_DESC, COND2); | |
806 | SIG_EXPR_DECL(VPIG5, VPIRSVD, VPIRSVD_DESC, AA3_DESC, COND2); | |
807 | SIG_EXPR_LIST_DECL_DUAL(VPIG5, VPI24, VPIRSVD); | |
808 | SIG_EXPR_LIST_DECL_SINGLE(PWM5, PWM5, AA3_DESC, COND2); | |
809 | MS_PIN_DECL(AA3, GPION5, VPIG5, PWM5); | |
810 | FUNC_GROUP_DECL(PWM5, AA3); | |
811 | ||
812 | #define Y3 110 | |
813 | #define Y3_DESC SIG_DESC_SET(SCU88, 6) | |
814 | SIG_EXPR_LIST_DECL_SINGLE(VPIG6, VPI24, VPI24_DESC, Y3_DESC); | |
815 | SIG_EXPR_LIST_DECL_SINGLE(PWM6, PWM6, Y3_DESC, COND2); | |
816 | MS_PIN_DECL(Y3, GPION6, VPIG6, PWM6); | |
817 | FUNC_GROUP_DECL(PWM6, Y3); | |
818 | ||
819 | #define T4 111 | |
820 | #define T4_DESC SIG_DESC_SET(SCU88, 7) | |
821 | SIG_EXPR_LIST_DECL_SINGLE(VPIG7, VPI24, VPI24_DESC, T4_DESC); | |
822 | SIG_EXPR_LIST_DECL_SINGLE(PWM7, PWM7, T4_DESC, COND2); | |
823 | MS_PIN_DECL(T4, GPION7, VPIG7, PWM7); | |
824 | FUNC_GROUP_DECL(PWM7, T4); | |
825 | ||
f1337856 AJ |
826 | #define U5 112 |
827 | SIG_EXPR_LIST_DECL_SINGLE(VPIG8, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 8), | |
828 | COND2); | |
829 | SS_PIN_DECL(U5, GPIOO0, VPIG8); | |
830 | ||
831 | #define U4 113 | |
832 | SIG_EXPR_LIST_DECL_SINGLE(VPIG9, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 9), | |
833 | COND2); | |
834 | SS_PIN_DECL(U4, GPIOO1, VPIG9); | |
835 | ||
836 | #define V5 114 | |
837 | SIG_EXPR_LIST_DECL_SINGLE(DASHV5, DASHV5, VPI_24_RSVD_DESC, | |
838 | SIG_DESC_SET(SCU88, 10)); | |
839 | SS_PIN_DECL(V5, GPIOO2, DASHV5); | |
840 | ||
841 | #define AB4 115 | |
842 | SIG_EXPR_LIST_DECL_SINGLE(DASHAB4, DASHAB4, VPI_24_RSVD_DESC, | |
843 | SIG_DESC_SET(SCU88, 11)); | |
844 | SS_PIN_DECL(AB4, GPIOO3, DASHAB4); | |
845 | ||
846 | #define AB3 116 | |
847 | SIG_EXPR_LIST_DECL_SINGLE(VPIR2, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 12), | |
848 | COND2); | |
849 | SS_PIN_DECL(AB3, GPIOO4, VPIR2); | |
850 | ||
851 | #define Y4 117 | |
852 | SIG_EXPR_LIST_DECL_SINGLE(VPIR3, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 13), | |
853 | COND2); | |
854 | SS_PIN_DECL(Y4, GPIOO5, VPIR3); | |
855 | ||
856 | #define AA4 118 | |
857 | SIG_EXPR_LIST_DECL_SINGLE(VPIR4, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 14), | |
858 | COND2); | |
859 | SS_PIN_DECL(AA4, GPIOO6, VPIR4); | |
860 | ||
861 | #define W4 119 | |
862 | SIG_EXPR_LIST_DECL_SINGLE(VPIR5, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 15), | |
863 | COND2); | |
864 | SS_PIN_DECL(W4, GPIOO7, VPIR5); | |
865 | ||
866 | #define V4 120 | |
867 | SIG_EXPR_LIST_DECL_SINGLE(VPIR6, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 16), | |
868 | COND2); | |
869 | SS_PIN_DECL(V4, GPIOP0, VPIR6); | |
870 | ||
871 | #define W5 121 | |
872 | SIG_EXPR_LIST_DECL_SINGLE(VPIR7, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 17), | |
873 | COND2); | |
874 | SS_PIN_DECL(W5, GPIOP1, VPIR7); | |
875 | ||
876 | #define AA5 122 | |
877 | SIG_EXPR_LIST_DECL_SINGLE(VPIR8, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 18), | |
878 | COND2); | |
879 | SS_PIN_DECL(AA5, GPIOP2, VPIR8); | |
880 | ||
881 | #define AB5 123 | |
882 | SIG_EXPR_LIST_DECL_SINGLE(VPIR9, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 19), | |
883 | COND2); | |
884 | SS_PIN_DECL(AB5, GPIOP3, VPIR9); | |
885 | ||
886 | FUNC_GROUP_DECL(VPI24, T1, U2, P4, P3, Y1, AB2, AA1, Y2, AA2, P5, R5, T5, V3, | |
887 | U3, W3, AA3, Y3, T4, U5, U4, AB3, Y4, AA4, W4, V4, W5, AA5, | |
888 | AB5); | |
889 | ||
890 | #define Y6 124 | |
891 | SIG_EXPR_LIST_DECL_SINGLE(DASHY6, DASHY6, SIG_DESC_SET(SCU90, 28), | |
892 | SIG_DESC_SET(SCU88, 20)); | |
893 | SS_PIN_DECL(Y6, GPIOP4, DASHY6); | |
894 | ||
895 | #define Y5 125 | |
896 | SIG_EXPR_LIST_DECL_SINGLE(DASHY5, DASHY5, SIG_DESC_SET(SCU90, 28), | |
897 | SIG_DESC_SET(SCU88, 21)); | |
898 | SS_PIN_DECL(Y5, GPIOP5, DASHY5); | |
899 | ||
900 | #define W6 126 | |
901 | SIG_EXPR_LIST_DECL_SINGLE(DASHW6, DASHW6, SIG_DESC_SET(SCU90, 28), | |
902 | SIG_DESC_SET(SCU88, 22)); | |
903 | SS_PIN_DECL(W6, GPIOP6, DASHW6); | |
904 | ||
56e57cb6 AJ |
905 | #define V6 127 |
906 | SIG_EXPR_LIST_DECL_SINGLE(DASHV6, DASHV6, SIG_DESC_SET(SCU90, 28), | |
f1337856 | 907 | SIG_DESC_SET(SCU88, 23)); |
56e57cb6 AJ |
908 | SS_PIN_DECL(V6, GPIOP7, DASHV6); |
909 | ||
910 | #define I2C3_DESC SIG_DESC_SET(SCU90, 16) | |
911 | ||
912 | #define A11 128 | |
913 | SIG_EXPR_LIST_DECL_SINGLE(SCL3, I2C3, I2C3_DESC); | |
914 | SS_PIN_DECL(A11, GPIOQ0, SCL3); | |
915 | ||
916 | #define A10 129 | |
917 | SIG_EXPR_LIST_DECL_SINGLE(SDA3, I2C3, I2C3_DESC); | |
918 | SS_PIN_DECL(A10, GPIOQ1, SDA3); | |
919 | ||
920 | FUNC_GROUP_DECL(I2C3, A11, A10); | |
921 | ||
922 | #define I2C4_DESC SIG_DESC_SET(SCU90, 17) | |
923 | ||
924 | #define A9 130 | |
925 | SIG_EXPR_LIST_DECL_SINGLE(SCL4, I2C4, I2C4_DESC); | |
926 | SS_PIN_DECL(A9, GPIOQ2, SCL4); | |
927 | ||
928 | #define B9 131 | |
929 | SIG_EXPR_LIST_DECL_SINGLE(SDA4, I2C4, I2C4_DESC); | |
930 | SS_PIN_DECL(B9, GPIOQ3, SDA4); | |
931 | ||
932 | FUNC_GROUP_DECL(I2C4, A9, B9); | |
933 | ||
934 | #define I2C14_DESC SIG_DESC_SET(SCU90, 27) | |
935 | ||
936 | #define N21 132 | |
937 | SIG_EXPR_LIST_DECL_SINGLE(SCL14, I2C14, I2C14_DESC); | |
938 | SS_PIN_DECL(N21, GPIOQ4, SCL14); | |
939 | ||
940 | #define N22 133 | |
941 | SIG_EXPR_LIST_DECL_SINGLE(SDA14, I2C14, I2C14_DESC); | |
942 | SS_PIN_DECL(N22, GPIOQ5, SDA14); | |
943 | ||
944 | FUNC_GROUP_DECL(I2C14, N21, N22); | |
945 | ||
946 | #define B10 134 | |
947 | SSSF_PIN_DECL(B10, GPIOQ6, OSCCLK, SIG_DESC_SET(SCU2C, 1)); | |
948 | ||
949 | #define N20 135 | |
950 | SSSF_PIN_DECL(N20, GPIOQ7, PEWAKE, SIG_DESC_SET(SCU2C, 29)); | |
951 | ||
f1337856 AJ |
952 | #define AA19 136 |
953 | SSSF_PIN_DECL(AA19, GPIOR0, FWSPICS1, SIG_DESC_SET(SCU88, 24), COND2); | |
954 | ||
955 | #define T19 137 | |
956 | SSSF_PIN_DECL(T19, GPIOR1, FWSPICS2, SIG_DESC_SET(SCU88, 25), COND2); | |
957 | ||
958 | #define T17 138 | |
959 | SSSF_PIN_DECL(T17, GPIOR2, SPI2CS0, SIG_DESC_SET(SCU88, 26), COND2); | |
960 | ||
961 | #define Y19 139 | |
962 | SSSF_PIN_DECL(Y19, GPIOR3, SPI2CK, SIG_DESC_SET(SCU88, 27), COND2); | |
963 | ||
964 | #define W19 140 | |
965 | SSSF_PIN_DECL(W19, GPIOR4, SPI2MOSI, SIG_DESC_SET(SCU88, 28), COND2); | |
966 | ||
967 | #define V19 141 | |
968 | SSSF_PIN_DECL(V19, GPIOR5, SPI2MISO, SIG_DESC_SET(SCU88, 29), COND2); | |
969 | ||
56e57cb6 AJ |
970 | #define D8 142 |
971 | SIG_EXPR_LIST_DECL_SINGLE(MDC1, MDIO1, SIG_DESC_SET(SCU88, 30)); | |
972 | SS_PIN_DECL(D8, GPIOR6, MDC1); | |
973 | ||
974 | #define E10 143 | |
975 | SIG_EXPR_LIST_DECL_SINGLE(MDIO1, MDIO1, SIG_DESC_SET(SCU88, 31)); | |
976 | SS_PIN_DECL(E10, GPIOR7, MDIO1); | |
977 | ||
978 | FUNC_GROUP_DECL(MDIO1, D8, E10); | |
979 | ||
f1337856 AJ |
980 | #define VPOOFF0_DESC { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 0, 0 } |
981 | #define VPO_DESC { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 1, 0 } | |
982 | #define VPOOFF1_DESC { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 2, 0 } | |
983 | #define VPOOFF2_DESC { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 3, 0 } | |
984 | ||
985 | #define CRT_DVO_EN_DESC SIG_DESC_IP_SET(ASPEED_IP_GFX, GFX064, 7) | |
986 | ||
987 | #define V20 144 | |
988 | #define V20_DESC SIG_DESC_SET(SCU8C, 0) | |
989 | SIG_EXPR_DECL(VPOB2, VPO, V20_DESC, VPO_DESC, CRT_DVO_EN_DESC); | |
990 | SIG_EXPR_DECL(VPOB2, VPOOFF1, V20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); | |
991 | SIG_EXPR_DECL(VPOB2, VPOOFF2, V20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); | |
992 | SIG_EXPR_LIST_DECL(VPOB2, SIG_EXPR_PTR(VPOB2, VPO), | |
993 | SIG_EXPR_PTR(VPOB2, VPOOFF1), SIG_EXPR_PTR(VPOB2, VPOOFF2)); | |
994 | SIG_EXPR_LIST_DECL_SINGLE(SPI2CS1, SPI2CS1, V20_DESC); | |
995 | MS_PIN_DECL(V20, GPIOS0, VPOB2, SPI2CS1); | |
996 | FUNC_GROUP_DECL(SPI2CS1, V20); | |
997 | ||
998 | #define U19 145 | |
999 | #define U19_DESC SIG_DESC_SET(SCU8C, 1) | |
1000 | SIG_EXPR_DECL(VPOB3, VPO, U19_DESC, VPO_DESC, CRT_DVO_EN_DESC); | |
1001 | SIG_EXPR_DECL(VPOB3, VPOOFF1, U19_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); | |
1002 | SIG_EXPR_DECL(VPOB3, VPOOFF2, U19_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); | |
1003 | SIG_EXPR_LIST_DECL(VPOB3, SIG_EXPR_PTR(VPOB3, VPO), | |
1004 | SIG_EXPR_PTR(VPOB3, VPOOFF1), SIG_EXPR_PTR(VPOB3, VPOOFF2)); | |
1005 | SIG_EXPR_LIST_DECL_SINGLE(BMCINT, BMCINT, U19_DESC); | |
1006 | MS_PIN_DECL(U19, GPIOS1, VPOB3, BMCINT); | |
1007 | FUNC_GROUP_DECL(BMCINT, U19); | |
1008 | ||
1009 | #define R18 146 | |
1010 | #define R18_DESC SIG_DESC_SET(SCU8C, 2) | |
1011 | SIG_EXPR_DECL(VPOB4, VPO, R18_DESC, VPO_DESC, CRT_DVO_EN_DESC); | |
1012 | SIG_EXPR_DECL(VPOB4, VPOOFF1, R18_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); | |
1013 | SIG_EXPR_DECL(VPOB4, VPOOFF2, R18_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); | |
1014 | SIG_EXPR_LIST_DECL(VPOB4, SIG_EXPR_PTR(VPOB4, VPO), | |
1015 | SIG_EXPR_PTR(VPOB4, VPOOFF1), SIG_EXPR_PTR(VPOB4, VPOOFF2)); | |
1016 | SIG_EXPR_LIST_DECL_SINGLE(SALT5, SALT5, R18_DESC); | |
1017 | MS_PIN_DECL(R18, GPIOS2, VPOB4, SALT5); | |
1018 | FUNC_GROUP_DECL(SALT5, R18); | |
1019 | ||
1020 | #define P18 147 | |
1021 | #define P18_DESC SIG_DESC_SET(SCU8C, 3) | |
1022 | SIG_EXPR_DECL(VPOB5, VPO, P18_DESC, VPO_DESC, CRT_DVO_EN_DESC); | |
1023 | SIG_EXPR_DECL(VPOB5, VPOOFF1, P18_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); | |
1024 | SIG_EXPR_DECL(VPOB5, VPOOFF2, P18_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); | |
1025 | SIG_EXPR_LIST_DECL(VPOB5, SIG_EXPR_PTR(VPOB5, VPO), | |
1026 | SIG_EXPR_PTR(VPOB5, VPOOFF1), SIG_EXPR_PTR(VPOB5, VPOOFF2)); | |
1027 | SIG_EXPR_LIST_DECL_SINGLE(SALT6, SALT6, P18_DESC); | |
1028 | MS_PIN_DECL(P18, GPIOS3, VPOB5, SALT6); | |
1029 | FUNC_GROUP_DECL(SALT6, P18); | |
1030 | ||
1031 | #define R19 148 | |
1032 | #define R19_DESC SIG_DESC_SET(SCU8C, 4) | |
1033 | SIG_EXPR_DECL(VPOB6, VPO, R19_DESC, VPO_DESC, CRT_DVO_EN_DESC); | |
1034 | SIG_EXPR_DECL(VPOB6, VPOOFF1, R19_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); | |
1035 | SIG_EXPR_DECL(VPOB6, VPOOFF2, R19_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); | |
1036 | SIG_EXPR_LIST_DECL(VPOB6, SIG_EXPR_PTR(VPOB6, VPO), | |
1037 | SIG_EXPR_PTR(VPOB6, VPOOFF1), SIG_EXPR_PTR(VPOB6, VPOOFF2)); | |
1038 | SS_PIN_DECL(R19, GPIOS4, VPOB6); | |
1039 | ||
1040 | #define W20 149 | |
1041 | #define W20_DESC SIG_DESC_SET(SCU8C, 5) | |
1042 | SIG_EXPR_DECL(VPOB7, VPO, W20_DESC, VPO_DESC, CRT_DVO_EN_DESC); | |
1043 | SIG_EXPR_DECL(VPOB7, VPOOFF1, W20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); | |
1044 | SIG_EXPR_DECL(VPOB7, VPOOFF2, W20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); | |
1045 | SIG_EXPR_LIST_DECL(VPOB7, SIG_EXPR_PTR(VPOB7, VPO), | |
1046 | SIG_EXPR_PTR(VPOB7, VPOOFF1), SIG_EXPR_PTR(VPOB7, VPOOFF2)); | |
1047 | SS_PIN_DECL(W20, GPIOS5, VPOB7); | |
1048 | ||
1049 | #define U20 150 | |
1050 | #define U20_DESC SIG_DESC_SET(SCU8C, 6) | |
1051 | SIG_EXPR_DECL(VPOB8, VPO, U20_DESC, VPO_DESC, CRT_DVO_EN_DESC); | |
1052 | SIG_EXPR_DECL(VPOB8, VPOOFF1, U20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); | |
1053 | SIG_EXPR_DECL(VPOB8, VPOOFF2, U20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); | |
1054 | SIG_EXPR_LIST_DECL(VPOB8, SIG_EXPR_PTR(VPOB8, VPO), | |
1055 | SIG_EXPR_PTR(VPOB8, VPOOFF1), SIG_EXPR_PTR(VPOB8, VPOOFF2)); | |
1056 | SS_PIN_DECL(U20, GPIOS6, VPOB8); | |
1057 | ||
1058 | #define AA20 151 | |
1059 | #define AA20_DESC SIG_DESC_SET(SCU8C, 7) | |
1060 | SIG_EXPR_DECL(VPOB9, VPO, AA20_DESC, VPO_DESC, CRT_DVO_EN_DESC); | |
1061 | SIG_EXPR_DECL(VPOB9, VPOOFF1, AA20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); | |
1062 | SIG_EXPR_DECL(VPOB9, VPOOFF2, AA20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); | |
1063 | SIG_EXPR_LIST_DECL(VPOB9, SIG_EXPR_PTR(VPOB9, VPO), | |
1064 | SIG_EXPR_PTR(VPOB9, VPOOFF1), SIG_EXPR_PTR(VPOB9, VPOOFF2)); | |
1065 | SS_PIN_DECL(AA20, GPIOS7, VPOB9); | |
1066 | ||
56e57cb6 AJ |
1067 | /* RGMII1/RMII1 */ |
1068 | ||
1069 | #define RMII1_DESC SIG_DESC_BIT(HW_STRAP1, 6, 0) | |
1070 | #define RMII2_DESC SIG_DESC_BIT(HW_STRAP1, 7, 0) | |
1071 | ||
1072 | #define B5 152 | |
1073 | SIG_EXPR_LIST_DECL_SINGLE(GPIOT0, GPIOT0, SIG_DESC_SET(SCUA0, 0)); | |
1074 | SIG_EXPR_LIST_DECL_SINGLE(RMII1RCLKO, RMII1, RMII1_DESC, | |
1075 | SIG_DESC_SET(SCU48, 29)); | |
1076 | SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXCK, RGMII1); | |
1077 | MS_PIN_DECL_(B5, SIG_EXPR_LIST_PTR(GPIOT0), SIG_EXPR_LIST_PTR(RMII1RCLKO), | |
1078 | SIG_EXPR_LIST_PTR(RGMII1TXCK)); | |
1079 | ||
1080 | #define E9 153 | |
1081 | SIG_EXPR_LIST_DECL_SINGLE(GPIOT1, GPIOT1, SIG_DESC_SET(SCUA0, 1)); | |
1082 | SIG_EXPR_LIST_DECL_SINGLE(RMII1TXEN, RMII1, RMII1_DESC); | |
1083 | SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXCTL, RGMII1); | |
1084 | MS_PIN_DECL_(E9, SIG_EXPR_LIST_PTR(GPIOT1), SIG_EXPR_LIST_PTR(RMII1TXEN), | |
1085 | SIG_EXPR_LIST_PTR(RGMII1TXCTL)); | |
1086 | ||
1087 | #define F9 154 | |
1088 | SIG_EXPR_LIST_DECL_SINGLE(GPIOT2, GPIOT2, SIG_DESC_SET(SCUA0, 2)); | |
1089 | SIG_EXPR_LIST_DECL_SINGLE(RMII1TXD0, RMII1, RMII1_DESC); | |
1090 | SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXD0, RGMII1); | |
1091 | MS_PIN_DECL_(F9, SIG_EXPR_LIST_PTR(GPIOT2), SIG_EXPR_LIST_PTR(RMII1TXD0), | |
1092 | SIG_EXPR_LIST_PTR(RGMII1TXD0)); | |
1093 | ||
1094 | #define A5 155 | |
1095 | SIG_EXPR_LIST_DECL_SINGLE(GPIOT3, GPIOT3, SIG_DESC_SET(SCUA0, 3)); | |
1096 | SIG_EXPR_LIST_DECL_SINGLE(RMII1TXD1, RMII1, RMII1_DESC); | |
1097 | SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXD1, RGMII1); | |
1098 | MS_PIN_DECL_(A5, SIG_EXPR_LIST_PTR(GPIOT3), SIG_EXPR_LIST_PTR(RMII1TXD1), | |
1099 | SIG_EXPR_LIST_PTR(RGMII1TXD1)); | |
1100 | ||
1101 | #define E7 156 | |
1102 | SIG_EXPR_LIST_DECL_SINGLE(GPIOT4, GPIOT4, SIG_DESC_SET(SCUA0, 4)); | |
1103 | SIG_EXPR_LIST_DECL_SINGLE(RMII1DASH0, RMII1, RMII1_DESC); | |
1104 | SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXD2, RGMII1); | |
1105 | MS_PIN_DECL_(E7, SIG_EXPR_LIST_PTR(GPIOT4), SIG_EXPR_LIST_PTR(RMII1DASH0), | |
1106 | SIG_EXPR_LIST_PTR(RGMII1TXD2)); | |
1107 | ||
1108 | #define D7 157 | |
1109 | SIG_EXPR_LIST_DECL_SINGLE(GPIOT5, GPIOT5, SIG_DESC_SET(SCUA0, 5)); | |
1110 | SIG_EXPR_LIST_DECL_SINGLE(RMII1DASH1, RMII1, RMII1_DESC); | |
1111 | SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXD3, RGMII1); | |
1112 | MS_PIN_DECL_(D7, SIG_EXPR_LIST_PTR(GPIOT5), SIG_EXPR_LIST_PTR(RMII1DASH1), | |
1113 | SIG_EXPR_LIST_PTR(RGMII1TXD3)); | |
1114 | ||
1115 | #define B2 158 | |
1116 | SIG_EXPR_LIST_DECL_SINGLE(GPIOT6, GPIOT6, SIG_DESC_SET(SCUA0, 6)); | |
1117 | SIG_EXPR_LIST_DECL_SINGLE(RMII2RCLKO, RMII2, RMII2_DESC, | |
1118 | SIG_DESC_SET(SCU48, 30)); | |
1119 | SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXCK, RGMII2); | |
1120 | MS_PIN_DECL_(B2, SIG_EXPR_LIST_PTR(GPIOT6), SIG_EXPR_LIST_PTR(RMII2RCLKO), | |
1121 | SIG_EXPR_LIST_PTR(RGMII2TXCK)); | |
1122 | ||
1123 | #define B1 159 | |
1124 | SIG_EXPR_LIST_DECL_SINGLE(GPIOT7, GPIOT7, SIG_DESC_SET(SCUA0, 7)); | |
1125 | SIG_EXPR_LIST_DECL_SINGLE(RMII2TXEN, RMII2, RMII2_DESC); | |
1126 | SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXCTL, RGMII2); | |
1127 | MS_PIN_DECL_(B1, SIG_EXPR_LIST_PTR(GPIOT7), SIG_EXPR_LIST_PTR(RMII2TXEN), | |
1128 | SIG_EXPR_LIST_PTR(RGMII2TXCTL)); | |
1129 | ||
1130 | #define A2 160 | |
1131 | SIG_EXPR_LIST_DECL_SINGLE(GPIOU0, GPIOU0, SIG_DESC_SET(SCUA0, 8)); | |
1132 | SIG_EXPR_LIST_DECL_SINGLE(RMII2TXD0, RMII2, RMII2_DESC); | |
1133 | SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXD0, RGMII2); | |
1134 | MS_PIN_DECL_(A2, SIG_EXPR_LIST_PTR(GPIOU0), SIG_EXPR_LIST_PTR(RMII2TXD0), | |
1135 | SIG_EXPR_LIST_PTR(RGMII2TXD0)); | |
1136 | ||
1137 | #define B3 161 | |
1138 | SIG_EXPR_LIST_DECL_SINGLE(GPIOU1, GPIOU1, SIG_DESC_SET(SCUA0, 9)); | |
1139 | SIG_EXPR_LIST_DECL_SINGLE(RMII2TXD1, RMII2, RMII2_DESC); | |
1140 | SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXD1, RGMII2); | |
1141 | MS_PIN_DECL_(B3, SIG_EXPR_LIST_PTR(GPIOU1), SIG_EXPR_LIST_PTR(RMII2TXD1), | |
1142 | SIG_EXPR_LIST_PTR(RGMII2TXD1)); | |
1143 | ||
1144 | #define D5 162 | |
1145 | SIG_EXPR_LIST_DECL_SINGLE(GPIOU2, GPIOU2, SIG_DESC_SET(SCUA0, 10)); | |
1146 | SIG_EXPR_LIST_DECL_SINGLE(RMII2DASH0, RMII2, RMII2_DESC); | |
1147 | SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXD2, RGMII2); | |
1148 | MS_PIN_DECL_(D5, SIG_EXPR_LIST_PTR(GPIOU2), SIG_EXPR_LIST_PTR(RMII2DASH0), | |
1149 | SIG_EXPR_LIST_PTR(RGMII2TXD2)); | |
1150 | ||
1151 | #define D4 163 | |
1152 | SIG_EXPR_LIST_DECL_SINGLE(GPIOU3, GPIOU3, SIG_DESC_SET(SCUA0, 11)); | |
1153 | SIG_EXPR_LIST_DECL_SINGLE(RMII2DASH1, RMII2, RMII2_DESC); | |
1154 | SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXD3, RGMII2); | |
1155 | MS_PIN_DECL_(D4, SIG_EXPR_LIST_PTR(GPIOU3), SIG_EXPR_LIST_PTR(RMII2DASH1), | |
1156 | SIG_EXPR_LIST_PTR(RGMII2TXD3)); | |
1157 | ||
1158 | #define B4 164 | |
1159 | SIG_EXPR_LIST_DECL_SINGLE(GPIOU4, GPIOU4, SIG_DESC_SET(SCUA0, 12)); | |
1160 | SIG_EXPR_LIST_DECL_SINGLE(RMII1RCLKI, RMII1, RMII1_DESC); | |
1161 | SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXCK, RGMII1); | |
1162 | MS_PIN_DECL_(B4, SIG_EXPR_LIST_PTR(GPIOU4), SIG_EXPR_LIST_PTR(RMII1RCLKI), | |
1163 | SIG_EXPR_LIST_PTR(RGMII1RXCK)); | |
1164 | ||
1165 | #define A4 165 | |
1166 | SIG_EXPR_LIST_DECL_SINGLE(GPIOU5, GPIOU5, SIG_DESC_SET(SCUA0, 13)); | |
1167 | SIG_EXPR_LIST_DECL_SINGLE(RMII1DASH2, RMII1, RMII1_DESC); | |
1168 | SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXCTL, RGMII1); | |
1169 | MS_PIN_DECL_(A4, SIG_EXPR_LIST_PTR(GPIOU5), SIG_EXPR_LIST_PTR(RMII1DASH2), | |
1170 | SIG_EXPR_LIST_PTR(RGMII1RXCTL)); | |
1171 | ||
1172 | #define A3 166 | |
1173 | SIG_EXPR_LIST_DECL_SINGLE(GPIOU6, GPIOU6, SIG_DESC_SET(SCUA0, 14)); | |
1174 | SIG_EXPR_LIST_DECL_SINGLE(RMII1RXD0, RMII1, RMII1_DESC); | |
1175 | SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXD0, RGMII1); | |
1176 | MS_PIN_DECL_(A3, SIG_EXPR_LIST_PTR(GPIOU6), SIG_EXPR_LIST_PTR(RMII1RXD0), | |
1177 | SIG_EXPR_LIST_PTR(RGMII1RXD0)); | |
1178 | ||
1179 | #define D6 167 | |
1180 | SIG_EXPR_LIST_DECL_SINGLE(GPIOU7, GPIOU7, SIG_DESC_SET(SCUA0, 15)); | |
1181 | SIG_EXPR_LIST_DECL_SINGLE(RMII1RXD1, RMII1, RMII1_DESC); | |
1182 | SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXD1, RGMII1); | |
1183 | MS_PIN_DECL_(D6, SIG_EXPR_LIST_PTR(GPIOU7), SIG_EXPR_LIST_PTR(RMII1RXD1), | |
1184 | SIG_EXPR_LIST_PTR(RGMII1RXD1)); | |
1185 | ||
1186 | #define C5 168 | |
1187 | SIG_EXPR_LIST_DECL_SINGLE(GPIOV0, GPIOV0, SIG_DESC_SET(SCUA0, 16)); | |
1188 | SIG_EXPR_LIST_DECL_SINGLE(RMII1CRSDV, RMII1, RMII1_DESC); | |
1189 | SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXD2, RGMII1); | |
1190 | MS_PIN_DECL_(C5, SIG_EXPR_LIST_PTR(GPIOV0), SIG_EXPR_LIST_PTR(RMII1CRSDV), | |
1191 | SIG_EXPR_LIST_PTR(RGMII1RXD2)); | |
1192 | ||
1193 | #define C4 169 | |
1194 | SIG_EXPR_LIST_DECL_SINGLE(GPIOV1, GPIOV1, SIG_DESC_SET(SCUA0, 17)); | |
1195 | SIG_EXPR_LIST_DECL_SINGLE(RMII1RXER, RMII1, RMII1_DESC); | |
1196 | SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXD3, RGMII1); | |
1197 | MS_PIN_DECL_(C4, SIG_EXPR_LIST_PTR(GPIOV1), SIG_EXPR_LIST_PTR(RMII1RXER), | |
1198 | SIG_EXPR_LIST_PTR(RGMII1RXD3)); | |
1199 | ||
1200 | FUNC_GROUP_DECL(RGMII1, B4, A4, A3, D6, C5, C4, B5, E9, F9, A5, E7, D7); | |
1201 | FUNC_GROUP_DECL(RMII1, B4, A3, D6, C5, C4, B5, E9, F9, A5); | |
1202 | ||
1203 | #define C2 170 | |
1204 | SIG_EXPR_LIST_DECL_SINGLE(GPIOV2, GPIOV2, SIG_DESC_SET(SCUA0, 18)); | |
1205 | SIG_EXPR_LIST_DECL_SINGLE(RMII2RCLKI, RMII2, RMII2_DESC); | |
1206 | SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXCK, RGMII2); | |
1207 | MS_PIN_DECL_(C2, SIG_EXPR_LIST_PTR(GPIOV2), SIG_EXPR_LIST_PTR(RMII2RCLKI), | |
1208 | SIG_EXPR_LIST_PTR(RGMII2RXCK)); | |
1209 | ||
1210 | #define C1 171 | |
1211 | SIG_EXPR_LIST_DECL_SINGLE(GPIOV3, GPIOV3, SIG_DESC_SET(SCUA0, 19)); | |
1212 | SIG_EXPR_LIST_DECL_SINGLE(RMII2DASH2, RMII2, RMII2_DESC); | |
1213 | SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXCTL, RGMII2); | |
1214 | MS_PIN_DECL_(C1, SIG_EXPR_LIST_PTR(GPIOV3), SIG_EXPR_LIST_PTR(RMII2DASH2), | |
1215 | SIG_EXPR_LIST_PTR(RGMII2RXCTL)); | |
1216 | ||
1217 | #define C3 172 | |
1218 | SIG_EXPR_LIST_DECL_SINGLE(GPIOV4, GPIOV4, SIG_DESC_SET(SCUA0, 20)); | |
1219 | SIG_EXPR_LIST_DECL_SINGLE(RMII2RXD0, RMII2, RMII2_DESC); | |
1220 | SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXD0, RGMII2); | |
1221 | MS_PIN_DECL_(C3, SIG_EXPR_LIST_PTR(GPIOV4), SIG_EXPR_LIST_PTR(RMII2RXD0), | |
1222 | SIG_EXPR_LIST_PTR(RGMII2RXD0)); | |
1223 | ||
1224 | #define D1 173 | |
1225 | SIG_EXPR_LIST_DECL_SINGLE(GPIOV5, GPIOV5, SIG_DESC_SET(SCUA0, 21)); | |
1226 | SIG_EXPR_LIST_DECL_SINGLE(RMII2RXD1, RMII2, RMII2_DESC); | |
1227 | SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXD1, RGMII2); | |
1228 | MS_PIN_DECL_(D1, SIG_EXPR_LIST_PTR(GPIOV5), SIG_EXPR_LIST_PTR(RMII2RXD1), | |
1229 | SIG_EXPR_LIST_PTR(RGMII2RXD1)); | |
1230 | ||
1231 | #define D2 174 | |
1232 | SIG_EXPR_LIST_DECL_SINGLE(GPIOV6, GPIOV6, SIG_DESC_SET(SCUA0, 22)); | |
1233 | SIG_EXPR_LIST_DECL_SINGLE(RMII2CRSDV, RMII2, RMII2_DESC); | |
1234 | SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXD2, RGMII2); | |
1235 | MS_PIN_DECL_(D2, SIG_EXPR_LIST_PTR(GPIOV6), SIG_EXPR_LIST_PTR(RMII2CRSDV), | |
1236 | SIG_EXPR_LIST_PTR(RGMII2RXD2)); | |
1237 | ||
1238 | #define E6 175 | |
1239 | SIG_EXPR_LIST_DECL_SINGLE(GPIOV7, GPIOV7, SIG_DESC_SET(SCUA0, 23)); | |
1240 | SIG_EXPR_LIST_DECL_SINGLE(RMII2RXER, RMII2, RMII2_DESC); | |
1241 | SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXD3, RGMII2); | |
1242 | MS_PIN_DECL_(E6, SIG_EXPR_LIST_PTR(GPIOV7), SIG_EXPR_LIST_PTR(RMII2RXER), | |
1243 | SIG_EXPR_LIST_PTR(RGMII2RXD3)); | |
1244 | ||
1245 | FUNC_GROUP_DECL(RGMII2, B2, B1, A2, B3, D5, D4, C2, C1, C3, D1, D2, E6); | |
1246 | FUNC_GROUP_DECL(RMII2, B2, B1, A2, B3, C2, C3, D1, D2, E6); | |
1247 | ||
f1337856 AJ |
1248 | #define F4 176 |
1249 | SIG_EXPR_LIST_DECL_SINGLE(GPIOW0, GPIOW0, SIG_DESC_SET(SCUA0, 24)); | |
1250 | SIG_EXPR_LIST_DECL_SINGLE(ADC0, ADC0); | |
1251 | MS_PIN_DECL_(F4, SIG_EXPR_LIST_PTR(GPIOW0), SIG_EXPR_LIST_PTR(ADC0)); | |
1252 | FUNC_GROUP_DECL(ADC0, F4); | |
1253 | ||
1254 | #define F5 177 | |
1255 | SIG_EXPR_LIST_DECL_SINGLE(GPIOW1, GPIOW1, SIG_DESC_SET(SCUA0, 25)); | |
1256 | SIG_EXPR_LIST_DECL_SINGLE(ADC1, ADC1); | |
1257 | MS_PIN_DECL_(F5, SIG_EXPR_LIST_PTR(GPIOW1), SIG_EXPR_LIST_PTR(ADC1)); | |
1258 | FUNC_GROUP_DECL(ADC1, F5); | |
1259 | ||
1260 | #define E2 178 | |
1261 | SIG_EXPR_LIST_DECL_SINGLE(GPIOW2, GPIOW2, SIG_DESC_SET(SCUA0, 26)); | |
1262 | SIG_EXPR_LIST_DECL_SINGLE(ADC2, ADC2); | |
1263 | MS_PIN_DECL_(E2, SIG_EXPR_LIST_PTR(GPIOW2), SIG_EXPR_LIST_PTR(ADC2)); | |
1264 | FUNC_GROUP_DECL(ADC2, E2); | |
1265 | ||
1266 | #define E1 179 | |
1267 | SIG_EXPR_LIST_DECL_SINGLE(GPIOW3, GPIOW3, SIG_DESC_SET(SCUA0, 27)); | |
1268 | SIG_EXPR_LIST_DECL_SINGLE(ADC3, ADC3); | |
1269 | MS_PIN_DECL_(E1, SIG_EXPR_LIST_PTR(GPIOW3), SIG_EXPR_LIST_PTR(ADC3)); | |
1270 | FUNC_GROUP_DECL(ADC3, E1); | |
1271 | ||
1272 | #define F3 180 | |
1273 | SIG_EXPR_LIST_DECL_SINGLE(GPIOW4, GPIOW4, SIG_DESC_SET(SCUA0, 28)); | |
1274 | SIG_EXPR_LIST_DECL_SINGLE(ADC4, ADC4); | |
1275 | MS_PIN_DECL_(F3, SIG_EXPR_LIST_PTR(GPIOW4), SIG_EXPR_LIST_PTR(ADC4)); | |
1276 | FUNC_GROUP_DECL(ADC4, F3); | |
1277 | ||
1278 | #define E3 181 | |
1279 | SIG_EXPR_LIST_DECL_SINGLE(GPIOW5, GPIOW5, SIG_DESC_SET(SCUA0, 29)); | |
1280 | SIG_EXPR_LIST_DECL_SINGLE(ADC5, ADC5); | |
1281 | MS_PIN_DECL_(E3, SIG_EXPR_LIST_PTR(GPIOW5), SIG_EXPR_LIST_PTR(ADC5)); | |
1282 | FUNC_GROUP_DECL(ADC5, E3); | |
1283 | ||
1284 | #define G5 182 | |
1285 | SIG_EXPR_LIST_DECL_SINGLE(GPIOW6, GPIOW6, SIG_DESC_SET(SCUA0, 30)); | |
1286 | SIG_EXPR_LIST_DECL_SINGLE(ADC6, ADC6); | |
1287 | MS_PIN_DECL_(G5, SIG_EXPR_LIST_PTR(GPIOW6), SIG_EXPR_LIST_PTR(ADC6)); | |
1288 | FUNC_GROUP_DECL(ADC6, G5); | |
1289 | ||
1290 | #define G4 183 | |
1291 | SIG_EXPR_LIST_DECL_SINGLE(GPIOW7, GPIOW7, SIG_DESC_SET(SCUA0, 31)); | |
1292 | SIG_EXPR_LIST_DECL_SINGLE(ADC7, ADC7); | |
1293 | MS_PIN_DECL_(G4, SIG_EXPR_LIST_PTR(GPIOW7), SIG_EXPR_LIST_PTR(ADC7)); | |
1294 | FUNC_GROUP_DECL(ADC7, G4); | |
1295 | ||
1296 | #define F2 184 | |
1297 | SIG_EXPR_LIST_DECL_SINGLE(GPIOX0, GPIOX0, SIG_DESC_SET(SCUA4, 0)); | |
1298 | SIG_EXPR_LIST_DECL_SINGLE(ADC8, ADC8); | |
1299 | MS_PIN_DECL_(F2, SIG_EXPR_LIST_PTR(GPIOX0), SIG_EXPR_LIST_PTR(ADC8)); | |
1300 | FUNC_GROUP_DECL(ADC8, F2); | |
1301 | ||
1302 | #define G3 185 | |
1303 | SIG_EXPR_LIST_DECL_SINGLE(GPIOX1, GPIOX1, SIG_DESC_SET(SCUA4, 1)); | |
1304 | SIG_EXPR_LIST_DECL_SINGLE(ADC9, ADC9); | |
1305 | MS_PIN_DECL_(G3, SIG_EXPR_LIST_PTR(GPIOX1), SIG_EXPR_LIST_PTR(ADC9)); | |
1306 | FUNC_GROUP_DECL(ADC9, G3); | |
1307 | ||
1308 | #define G2 186 | |
1309 | SIG_EXPR_LIST_DECL_SINGLE(GPIOX2, GPIOX2, SIG_DESC_SET(SCUA4, 2)); | |
1310 | SIG_EXPR_LIST_DECL_SINGLE(ADC10, ADC10); | |
1311 | MS_PIN_DECL_(G2, SIG_EXPR_LIST_PTR(GPIOX2), SIG_EXPR_LIST_PTR(ADC10)); | |
1312 | FUNC_GROUP_DECL(ADC10, G2); | |
1313 | ||
1314 | #define F1 187 | |
1315 | SIG_EXPR_LIST_DECL_SINGLE(GPIOX3, GPIOX3, SIG_DESC_SET(SCUA4, 3)); | |
1316 | SIG_EXPR_LIST_DECL_SINGLE(ADC11, ADC11); | |
1317 | MS_PIN_DECL_(F1, SIG_EXPR_LIST_PTR(GPIOX3), SIG_EXPR_LIST_PTR(ADC11)); | |
1318 | FUNC_GROUP_DECL(ADC11, F1); | |
1319 | ||
1320 | #define H5 188 | |
1321 | SIG_EXPR_LIST_DECL_SINGLE(GPIOX4, GPIOX4, SIG_DESC_SET(SCUA4, 4)); | |
1322 | SIG_EXPR_LIST_DECL_SINGLE(ADC12, ADC12); | |
1323 | MS_PIN_DECL_(H5, SIG_EXPR_LIST_PTR(GPIOX4), SIG_EXPR_LIST_PTR(ADC12)); | |
1324 | FUNC_GROUP_DECL(ADC12, H5); | |
1325 | ||
1326 | #define G1 189 | |
1327 | SIG_EXPR_LIST_DECL_SINGLE(GPIOX5, GPIOX5, SIG_DESC_SET(SCUA4, 5)); | |
1328 | SIG_EXPR_LIST_DECL_SINGLE(ADC13, ADC13); | |
1329 | MS_PIN_DECL_(G1, SIG_EXPR_LIST_PTR(GPIOX5), SIG_EXPR_LIST_PTR(ADC13)); | |
1330 | FUNC_GROUP_DECL(ADC13, G1); | |
1331 | ||
1332 | #define H3 190 | |
1333 | SIG_EXPR_LIST_DECL_SINGLE(GPIOX6, GPIOX6, SIG_DESC_SET(SCUA4, 6)); | |
1334 | SIG_EXPR_LIST_DECL_SINGLE(ADC14, ADC14); | |
1335 | MS_PIN_DECL_(H3, SIG_EXPR_LIST_PTR(GPIOX6), SIG_EXPR_LIST_PTR(ADC14)); | |
1336 | FUNC_GROUP_DECL(ADC14, H3); | |
1337 | ||
1338 | #define H4 191 | |
1339 | SIG_EXPR_LIST_DECL_SINGLE(GPIOX7, GPIOX7, SIG_DESC_SET(SCUA4, 7)); | |
1340 | SIG_EXPR_LIST_DECL_SINGLE(ADC15, ADC15); | |
1341 | MS_PIN_DECL_(H4, SIG_EXPR_LIST_PTR(GPIOX7), SIG_EXPR_LIST_PTR(ADC15)); | |
1342 | FUNC_GROUP_DECL(ADC15, H4); | |
1343 | ||
1344 | #define ACPI_DESC SIG_DESC_SET(HW_STRAP1, 19) | |
1345 | ||
1346 | #define R22 192 | |
1347 | SIG_EXPR_DECL(SIOS3, SIOS3, SIG_DESC_SET(SCUA4, 8)); | |
1348 | SIG_EXPR_DECL(SIOS3, ACPI, ACPI_DESC); | |
1349 | SIG_EXPR_LIST_DECL_DUAL(SIOS3, SIOS3, ACPI); | |
1350 | SIG_EXPR_LIST_DECL_SINGLE(DASHR22, DASHR22, SIG_DESC_SET(SCU94, 10)); | |
1351 | MS_PIN_DECL(R22, GPIOY0, SIOS3, DASHR22); | |
1352 | FUNC_GROUP_DECL(SIOS3, R22); | |
1353 | ||
1354 | #define R21 193 | |
1355 | SIG_EXPR_DECL(SIOS5, SIOS5, SIG_DESC_SET(SCUA4, 9)); | |
1356 | SIG_EXPR_DECL(SIOS5, ACPI, ACPI_DESC); | |
1357 | SIG_EXPR_LIST_DECL_DUAL(SIOS5, SIOS5, ACPI); | |
1358 | SIG_EXPR_LIST_DECL_SINGLE(DASHR21, DASHR21, SIG_DESC_SET(SCU94, 10)); | |
1359 | MS_PIN_DECL(R21, GPIOY1, SIOS5, DASHR21); | |
1360 | FUNC_GROUP_DECL(SIOS5, R21); | |
1361 | ||
1362 | #define P22 194 | |
1363 | SIG_EXPR_DECL(SIOPWREQ, SIOPWREQ, SIG_DESC_SET(SCUA4, 10)); | |
1364 | SIG_EXPR_DECL(SIOPWREQ, ACPI, ACPI_DESC); | |
1365 | SIG_EXPR_LIST_DECL_DUAL(SIOPWREQ, SIOPWREQ, ACPI); | |
1366 | SIG_EXPR_LIST_DECL_SINGLE(DASHP22, DASHP22, SIG_DESC_SET(SCU94, 11)); | |
1367 | MS_PIN_DECL(P22, GPIOY2, SIOPWREQ, DASHP22); | |
1368 | FUNC_GROUP_DECL(SIOPWREQ, P22); | |
1369 | ||
1370 | #define P21 195 | |
1371 | SIG_EXPR_DECL(SIOONCTRL, SIOONCTRL, SIG_DESC_SET(SCUA4, 11)); | |
1372 | SIG_EXPR_DECL(SIOONCTRL, ACPI, ACPI_DESC); | |
1373 | SIG_EXPR_LIST_DECL_DUAL(SIOONCTRL, SIOONCTRL, ACPI); | |
1374 | SIG_EXPR_LIST_DECL_SINGLE(DASHP21, DASHP21, SIG_DESC_SET(SCU94, 11)); | |
1375 | MS_PIN_DECL(P21, GPIOY3, SIOONCTRL, DASHP21); | |
1376 | FUNC_GROUP_DECL(SIOONCTRL, P21); | |
1377 | ||
1378 | #define M18 196 | |
1379 | SSSF_PIN_DECL(M18, GPIOY4, SCL1, SIG_DESC_SET(SCUA4, 12)); | |
1380 | ||
1381 | #define M19 197 | |
1382 | SSSF_PIN_DECL(M19, GPIOY5, SDA1, SIG_DESC_SET(SCUA4, 13)); | |
1383 | ||
1384 | #define M20 198 | |
1385 | SSSF_PIN_DECL(M20, GPIOY6, SCL2, SIG_DESC_SET(SCUA4, 14)); | |
1386 | ||
1387 | #define P20 199 | |
1388 | SSSF_PIN_DECL(P20, GPIOY7, SDA2, SIG_DESC_SET(SCUA4, 15)); | |
1389 | ||
1390 | #define PNOR_DESC SIG_DESC_SET(SCU90, 31) | |
1391 | ||
1392 | #define Y20 200 | |
1393 | #define Y20_DESC SIG_DESC_SET(SCUA4, 16) | |
1394 | SIG_EXPR_DECL(VPOG2, VPO, Y20_DESC, VPO_DESC, CRT_DVO_EN_DESC); | |
1395 | SIG_EXPR_DECL(VPOG2, VPOOFF1, Y20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); | |
1396 | SIG_EXPR_DECL(VPOG2, VPOOFF2, Y20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); | |
1397 | SIG_EXPR_LIST_DECL(VPOG2, SIG_EXPR_PTR(VPOG2, VPO), | |
1398 | SIG_EXPR_PTR(VPOG2, VPOOFF1), SIG_EXPR_PTR(VPOG2, VPOOFF2)); | |
1399 | SIG_EXPR_DECL(SIOPBI, SIOPBI, Y20_DESC); | |
1400 | SIG_EXPR_DECL(SIOPBI, ACPI, Y20_DESC); | |
1401 | SIG_EXPR_LIST_DECL_DUAL(SIOPBI, SIOPBI, ACPI); | |
1402 | SIG_EXPR_LIST_DECL_SINGLE(NORA0, PNOR, PNOR_DESC); | |
1403 | SIG_EXPR_LIST_DECL_SINGLE(GPIOZ0, GPIOZ0); | |
1404 | MS_PIN_DECL_(Y20, SIG_EXPR_LIST_PTR(VPOG2), SIG_EXPR_LIST_PTR(SIOPBI), | |
1405 | SIG_EXPR_LIST_PTR(NORA0), SIG_EXPR_LIST_PTR(GPIOZ0)); | |
1406 | FUNC_GROUP_DECL(SIOPBI, Y20); | |
1407 | ||
1408 | #define AB20 201 | |
1409 | #define AB20_DESC SIG_DESC_SET(SCUA4, 17) | |
1410 | SIG_EXPR_DECL(VPOG3, VPO, AB20_DESC, VPO_DESC, CRT_DVO_EN_DESC); | |
1411 | SIG_EXPR_DECL(VPOG3, VPOOFF1, AB20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); | |
1412 | SIG_EXPR_DECL(VPOG3, VPOOFF2, AB20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); | |
1413 | SIG_EXPR_LIST_DECL(VPOG3, SIG_EXPR_PTR(VPOG3, VPO), | |
1414 | SIG_EXPR_PTR(VPOG3, VPOOFF1), SIG_EXPR_PTR(VPOG3, VPOOFF2)); | |
1415 | SIG_EXPR_DECL(SIOPWRGD, SIOPWRGD, AB20_DESC); | |
1416 | SIG_EXPR_DECL(SIOPWRGD, ACPI, AB20_DESC); | |
1417 | SIG_EXPR_LIST_DECL_DUAL(SIOPWRGD, SIOPWRGD, ACPI); | |
1418 | SIG_EXPR_LIST_DECL_SINGLE(NORA1, PNOR, PNOR_DESC); | |
1419 | SIG_EXPR_LIST_DECL_SINGLE(GPIOZ1, GPIOZ1); | |
1420 | MS_PIN_DECL_(AB20, SIG_EXPR_LIST_PTR(VPOG3), SIG_EXPR_LIST_PTR(SIOPWRGD), | |
1421 | SIG_EXPR_LIST_PTR(NORA1), SIG_EXPR_LIST_PTR(GPIOZ1)); | |
1422 | FUNC_GROUP_DECL(SIOPWRGD, AB20); | |
1423 | ||
1424 | #define AB21 202 | |
1425 | #define AB21_DESC SIG_DESC_SET(SCUA4, 18) | |
1426 | SIG_EXPR_DECL(VPOG4, VPO, AB21_DESC, VPO_DESC, CRT_DVO_EN_DESC); | |
1427 | SIG_EXPR_DECL(VPOG4, VPOOFF1, AB21_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); | |
1428 | SIG_EXPR_DECL(VPOG4, VPOOFF2, AB21_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); | |
1429 | SIG_EXPR_LIST_DECL(VPOG4, SIG_EXPR_PTR(VPOG4, VPO), | |
1430 | SIG_EXPR_PTR(VPOG4, VPOOFF1), SIG_EXPR_PTR(VPOG4, VPOOFF2)); | |
1431 | SIG_EXPR_DECL(SIOPBO, SIOPBO, AB21_DESC); | |
1432 | SIG_EXPR_DECL(SIOPBO, ACPI, AB21_DESC); | |
1433 | SIG_EXPR_LIST_DECL_DUAL(SIOPBO, SIOPBO, ACPI); | |
1434 | SIG_EXPR_LIST_DECL_SINGLE(NORA2, PNOR, PNOR_DESC); | |
1435 | SIG_EXPR_LIST_DECL_SINGLE(GPIOZ2, GPIOZ2); | |
1436 | MS_PIN_DECL_(AB21, SIG_EXPR_LIST_PTR(VPOG4), SIG_EXPR_LIST_PTR(SIOPBO), | |
1437 | SIG_EXPR_LIST_PTR(NORA2), SIG_EXPR_LIST_PTR(GPIOZ2)); | |
1438 | FUNC_GROUP_DECL(SIOPBO, AB21); | |
1439 | ||
1440 | #define AA21 203 | |
1441 | #define AA21_DESC SIG_DESC_SET(SCUA4, 19) | |
1442 | SIG_EXPR_DECL(VPOG5, VPO, AA21_DESC, VPO_DESC, CRT_DVO_EN_DESC); | |
1443 | SIG_EXPR_DECL(VPOG5, VPOOFF1, AA21_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); | |
1444 | SIG_EXPR_DECL(VPOG5, VPOOFF2, AA21_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); | |
1445 | SIG_EXPR_LIST_DECL(VPOG5, SIG_EXPR_PTR(VPOG5, VPO), | |
1446 | SIG_EXPR_PTR(VPOG5, VPOOFF1), SIG_EXPR_PTR(VPOG5, VPOOFF2)); | |
1447 | SIG_EXPR_DECL(SIOSCI, SIOSCI, AA21_DESC); | |
1448 | SIG_EXPR_DECL(SIOSCI, ACPI, AA21_DESC); | |
1449 | SIG_EXPR_LIST_DECL_DUAL(SIOSCI, SIOSCI, ACPI); | |
1450 | SIG_EXPR_LIST_DECL_SINGLE(NORA3, PNOR, PNOR_DESC); | |
1451 | SIG_EXPR_LIST_DECL_SINGLE(GPIOZ3, GPIOZ3); | |
1452 | MS_PIN_DECL_(AA21, SIG_EXPR_LIST_PTR(VPOG5), SIG_EXPR_LIST_PTR(SIOSCI), | |
1453 | SIG_EXPR_LIST_PTR(NORA3), SIG_EXPR_LIST_PTR(GPIOZ3)); | |
1454 | FUNC_GROUP_DECL(SIOSCI, AA21); | |
1455 | ||
1456 | FUNC_GROUP_DECL(ACPI, R22, R21, P22, P21, Y20, AB20, AB21, AA21); | |
1457 | ||
1458 | /* CRT DVO disabled, configured for single-edge mode */ | |
1459 | #define CRT_DVO_DS_DESC { ASPEED_IP_GFX, GFX064, GENMASK(7, 6), 0, 0 } | |
1460 | ||
1461 | /* CRT DVO disabled, configured for dual-edge mode */ | |
1462 | #define CRT_DVO_DD_DESC { ASPEED_IP_GFX, GFX064, GENMASK(7, 6), 1, 1 } | |
1463 | ||
1464 | /* CRT DVO enabled, configured for single-edge mode */ | |
1465 | #define CRT_DVO_ES_DESC { ASPEED_IP_GFX, GFX064, GENMASK(7, 6), 2, 2 } | |
1466 | ||
1467 | /* CRT DVO enabled, configured for dual-edge mode */ | |
1468 | #define CRT_DVO_ED_DESC { ASPEED_IP_GFX, GFX064, GENMASK(7, 6), 3, 3 } | |
1469 | ||
1470 | #define U21 204 | |
1471 | #define U21_DESC SIG_DESC_SET(SCUA4, 20) | |
1472 | SIG_EXPR_DECL(VPOG6, VPO, U21_DESC, VPO_DESC, CRT_DVO_ES_DESC); | |
1473 | SIG_EXPR_DECL(VPOG6, VPOOFF1, U21_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC); | |
1474 | SIG_EXPR_DECL(VPOG6, VPOOFF2, U21_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC); | |
1475 | SIG_EXPR_LIST_DECL(VPOG6, SIG_EXPR_PTR(VPOG6, VPO), | |
1476 | SIG_EXPR_PTR(VPOG6, VPOOFF1), SIG_EXPR_PTR(VPOG6, VPOOFF2)); | |
1477 | SIG_EXPR_LIST_DECL_SINGLE(NORA4, PNOR, PNOR_DESC); | |
1478 | MS_PIN_DECL(U21, GPIOZ4, VPOG6, NORA4); | |
1479 | ||
1480 | #define W22 205 | |
1481 | #define W22_DESC SIG_DESC_SET(SCUA4, 21) | |
1482 | SIG_EXPR_DECL(VPOG7, VPO, W22_DESC, VPO_DESC, CRT_DVO_ES_DESC); | |
1483 | SIG_EXPR_DECL(VPOG7, VPOOFF1, W22_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC); | |
1484 | SIG_EXPR_DECL(VPOG7, VPOOFF2, W22_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC); | |
1485 | SIG_EXPR_LIST_DECL(VPOG7, SIG_EXPR_PTR(VPOG7, VPO), | |
1486 | SIG_EXPR_PTR(VPOG7, VPOOFF1), SIG_EXPR_PTR(VPOG7, VPOOFF2)); | |
1487 | SIG_EXPR_LIST_DECL_SINGLE(NORA5, PNOR, PNOR_DESC); | |
1488 | MS_PIN_DECL(W22, GPIOZ5, VPOG7, NORA5); | |
1489 | ||
1490 | #define V22 206 | |
1491 | #define V22_DESC SIG_DESC_SET(SCUA4, 22) | |
1492 | SIG_EXPR_DECL(VPOG8, VPO, V22_DESC, VPO_DESC, CRT_DVO_ES_DESC); | |
1493 | SIG_EXPR_DECL(VPOG8, VPOOFF1, V22_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC); | |
1494 | SIG_EXPR_DECL(VPOG8, VPOOFF2, V22_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC); | |
1495 | SIG_EXPR_LIST_DECL(VPOG8, SIG_EXPR_PTR(VPOG8, VPO), | |
1496 | SIG_EXPR_PTR(VPOG8, VPOOFF1), SIG_EXPR_PTR(VPOG8, VPOOFF2)); | |
1497 | SIG_EXPR_LIST_DECL_SINGLE(NORA6, PNOR, PNOR_DESC); | |
1498 | MS_PIN_DECL(V22, GPIOZ6, VPOG8, NORA6); | |
1499 | ||
1500 | #define W21 207 | |
1501 | #define W21_DESC SIG_DESC_SET(SCUA4, 23) | |
1502 | SIG_EXPR_DECL(VPOG9, VPO, W21_DESC, VPO_DESC, CRT_DVO_ES_DESC); | |
1503 | SIG_EXPR_DECL(VPOG9, VPOOFF1, W21_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC); | |
1504 | SIG_EXPR_DECL(VPOG9, VPOOFF2, W21_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC); | |
1505 | SIG_EXPR_LIST_DECL(VPOG9, SIG_EXPR_PTR(VPOG9, VPO), | |
1506 | SIG_EXPR_PTR(VPOG9, VPOOFF1), SIG_EXPR_PTR(VPOG9, VPOOFF2)); | |
1507 | SIG_EXPR_LIST_DECL_SINGLE(NORA7, PNOR, PNOR_DESC); | |
1508 | MS_PIN_DECL(W21, GPIOZ7, VPOG9, NORA7); | |
1509 | ||
1510 | #define Y21 208 | |
1511 | #define Y21_DESC SIG_DESC_SET(SCUA4, 24) | |
1512 | SIG_EXPR_DECL(VPOR2, VPO, Y21_DESC, VPO_DESC, CRT_DVO_ES_DESC); | |
1513 | SIG_EXPR_DECL(VPOR2, VPOOFF1, Y21_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC); | |
1514 | SIG_EXPR_DECL(VPOR2, VPOOFF2, Y21_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC); | |
1515 | SIG_EXPR_LIST_DECL(VPOR2, SIG_EXPR_PTR(VPOR2, VPO), | |
1516 | SIG_EXPR_PTR(VPOR2, VPOOFF1), SIG_EXPR_PTR(VPOR2, VPOOFF2)); | |
1517 | SIG_EXPR_LIST_DECL_SINGLE(SALT7, SALT7, Y21_DESC); | |
1518 | SIG_EXPR_LIST_DECL_SINGLE(NORD0, PNOR, PNOR_DESC); | |
1519 | SIG_EXPR_LIST_DECL_SINGLE(GPIOAA0, GPIOAA0); | |
1520 | MS_PIN_DECL_(Y21, SIG_EXPR_LIST_PTR(VPOR2), SIG_EXPR_LIST_PTR(SALT7), | |
1521 | SIG_EXPR_LIST_PTR(NORD0), SIG_EXPR_LIST_PTR(GPIOAA0)); | |
1522 | FUNC_GROUP_DECL(SALT7, Y21); | |
1523 | ||
1524 | #define V21 209 | |
1525 | #define V21_DESC SIG_DESC_SET(SCUA4, 25) | |
1526 | SIG_EXPR_DECL(VPOR3, VPO, V21_DESC, VPO_DESC, CRT_DVO_ES_DESC); | |
1527 | SIG_EXPR_DECL(VPOR3, VPOOFF1, V21_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC); | |
1528 | SIG_EXPR_DECL(VPOR3, VPOOFF2, V21_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC); | |
1529 | SIG_EXPR_LIST_DECL(VPOR3, SIG_EXPR_PTR(VPOR3, VPO), | |
1530 | SIG_EXPR_PTR(VPOR3, VPOOFF1), SIG_EXPR_PTR(VPOR3, VPOOFF2)); | |
1531 | SIG_EXPR_LIST_DECL_SINGLE(SALT8, SALT8, V21_DESC); | |
1532 | SIG_EXPR_LIST_DECL_SINGLE(NORD1, PNOR, PNOR_DESC); | |
1533 | SIG_EXPR_LIST_DECL_SINGLE(GPIOAA1, GPIOAA1); | |
1534 | MS_PIN_DECL_(V21, SIG_EXPR_LIST_PTR(VPOR3), SIG_EXPR_LIST_PTR(SALT8), | |
1535 | SIG_EXPR_LIST_PTR(NORD1), SIG_EXPR_LIST_PTR(GPIOAA1)); | |
1536 | FUNC_GROUP_DECL(SALT8, V21); | |
1537 | ||
1538 | #define Y22 210 | |
1539 | #define Y22_DESC SIG_DESC_SET(SCUA4, 26) | |
1540 | SIG_EXPR_DECL(VPOR4, VPO, Y22_DESC, VPO_DESC, CRT_DVO_ES_DESC); | |
1541 | SIG_EXPR_DECL(VPOR4, VPOOFF1, Y22_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC); | |
1542 | SIG_EXPR_DECL(VPOR4, VPOOFF2, Y22_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC); | |
1543 | SIG_EXPR_LIST_DECL(VPOR4, SIG_EXPR_PTR(VPOR4, VPO), | |
1544 | SIG_EXPR_PTR(VPOR4, VPOOFF1), SIG_EXPR_PTR(VPOR4, VPOOFF2)); | |
1545 | SIG_EXPR_LIST_DECL_SINGLE(SALT9, SALT9, Y22_DESC); | |
1546 | SIG_EXPR_LIST_DECL_SINGLE(NORD2, PNOR, PNOR_DESC); | |
1547 | SIG_EXPR_LIST_DECL_SINGLE(GPIOAA2, GPIOAA2); | |
1548 | MS_PIN_DECL_(Y22, SIG_EXPR_LIST_PTR(VPOR4), SIG_EXPR_LIST_PTR(SALT9), | |
1549 | SIG_EXPR_LIST_PTR(NORD2), SIG_EXPR_LIST_PTR(GPIOAA2)); | |
1550 | FUNC_GROUP_DECL(SALT9, Y22); | |
1551 | ||
1552 | #define AA22 211 | |
1553 | #define AA22_DESC SIG_DESC_SET(SCUA4, 27) | |
1554 | SIG_EXPR_DECL(VPOR5, VPO, AA22_DESC, VPO_DESC, CRT_DVO_ES_DESC); | |
1555 | SIG_EXPR_DECL(VPOR5, VPOOFF1, AA22_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC); | |
1556 | SIG_EXPR_DECL(VPOR5, VPOOFF2, AA22_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC); | |
1557 | SIG_EXPR_LIST_DECL(VPOR5, SIG_EXPR_PTR(VPOR5, VPO), | |
1558 | SIG_EXPR_PTR(VPOR5, VPOOFF1), SIG_EXPR_PTR(VPOR5, VPOOFF2)); | |
1559 | SIG_EXPR_LIST_DECL_SINGLE(SALT10, SALT10, AA22_DESC); | |
1560 | SIG_EXPR_LIST_DECL_SINGLE(NORD3, PNOR, PNOR_DESC); | |
1561 | SIG_EXPR_LIST_DECL_SINGLE(GPIOAA3, GPIOAA3); | |
1562 | MS_PIN_DECL_(AA22, SIG_EXPR_LIST_PTR(VPOR5), SIG_EXPR_LIST_PTR(SALT10), | |
1563 | SIG_EXPR_LIST_PTR(NORD3), SIG_EXPR_LIST_PTR(GPIOAA3)); | |
1564 | FUNC_GROUP_DECL(SALT10, AA22); | |
1565 | ||
1566 | #define U22 212 | |
1567 | #define U22_DESC SIG_DESC_SET(SCUA4, 28) | |
1568 | SIG_EXPR_DECL(VPOR6, VPO, U22_DESC, VPO_DESC, CRT_DVO_ES_DESC); | |
1569 | SIG_EXPR_DECL(VPOR6, VPOOFF1, U22_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC); | |
1570 | SIG_EXPR_DECL(VPOR6, VPOOFF2, U22_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC); | |
1571 | SIG_EXPR_LIST_DECL(VPOR6, SIG_EXPR_PTR(VPOR6, VPO), | |
1572 | SIG_EXPR_PTR(VPOR6, VPOOFF1), SIG_EXPR_PTR(VPOR6, VPOOFF2)); | |
1573 | SIG_EXPR_LIST_DECL_SINGLE(SALT11, SALT11, U22_DESC); | |
1574 | SIG_EXPR_LIST_DECL_SINGLE(NORD4, PNOR, PNOR_DESC); | |
1575 | SIG_EXPR_LIST_DECL_SINGLE(GPIOAA4, GPIOAA4); | |
1576 | MS_PIN_DECL_(U22, SIG_EXPR_LIST_PTR(VPOR6), SIG_EXPR_LIST_PTR(SALT11), | |
1577 | SIG_EXPR_LIST_PTR(NORD4), SIG_EXPR_LIST_PTR(GPIOAA4)); | |
1578 | FUNC_GROUP_DECL(SALT11, U22); | |
1579 | ||
1580 | #define T20 213 | |
1581 | #define T20_DESC SIG_DESC_SET(SCUA4, 29) | |
1582 | SIG_EXPR_DECL(VPOR7, VPO, T20_DESC, VPO_DESC, CRT_DVO_ES_DESC); | |
1583 | SIG_EXPR_DECL(VPOR7, VPOOFF1, T20_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC); | |
1584 | SIG_EXPR_DECL(VPOR7, VPOOFF2, T20_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC); | |
1585 | SIG_EXPR_LIST_DECL(VPOR7, SIG_EXPR_PTR(VPOR7, VPO), | |
1586 | SIG_EXPR_PTR(VPOR7, VPOOFF1), SIG_EXPR_PTR(VPOR7, VPOOFF2)); | |
1587 | SIG_EXPR_LIST_DECL_SINGLE(SALT12, SALT12, T20_DESC); | |
1588 | SIG_EXPR_LIST_DECL_SINGLE(NORD5, PNOR, PNOR_DESC); | |
1589 | SIG_EXPR_LIST_DECL_SINGLE(GPIOAA5, GPIOAA5); | |
1590 | MS_PIN_DECL_(T20, SIG_EXPR_LIST_PTR(VPOR7), SIG_EXPR_LIST_PTR(SALT12), | |
1591 | SIG_EXPR_LIST_PTR(NORD5), SIG_EXPR_LIST_PTR(GPIOAA5)); | |
1592 | FUNC_GROUP_DECL(SALT12, T20); | |
1593 | ||
1594 | #define N18 214 | |
1595 | #define N18_DESC SIG_DESC_SET(SCUA4, 30) | |
1596 | SIG_EXPR_DECL(VPOR8, VPO, N18_DESC, VPO_DESC, CRT_DVO_ES_DESC); | |
1597 | SIG_EXPR_DECL(VPOR8, VPOOFF1, N18_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC); | |
1598 | SIG_EXPR_DECL(VPOR8, VPOOFF2, N18_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC); | |
1599 | SIG_EXPR_LIST_DECL(VPOR8, SIG_EXPR_PTR(VPOR8, VPO), | |
1600 | SIG_EXPR_PTR(VPOR8, VPOOFF1), SIG_EXPR_PTR(VPOR8, VPOOFF2)); | |
1601 | SIG_EXPR_LIST_DECL_SINGLE(SALT13, SALT13, N18_DESC); | |
1602 | SIG_EXPR_LIST_DECL_SINGLE(NORD6, PNOR, PNOR_DESC); | |
1603 | SIG_EXPR_LIST_DECL_SINGLE(GPIOAA6, GPIOAA6); | |
1604 | MS_PIN_DECL_(N18, SIG_EXPR_LIST_PTR(VPOR8), SIG_EXPR_LIST_PTR(SALT13), | |
1605 | SIG_EXPR_LIST_PTR(NORD6), SIG_EXPR_LIST_PTR(GPIOAA6)); | |
1606 | FUNC_GROUP_DECL(SALT13, N18); | |
1607 | ||
1608 | #define P19 215 | |
1609 | #define P19_DESC SIG_DESC_SET(SCUA4, 31) | |
1610 | SIG_EXPR_DECL(VPOR9, VPO, P19_DESC, VPO_DESC, CRT_DVO_ES_DESC); | |
1611 | SIG_EXPR_DECL(VPOR9, VPOOFF1, P19_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC); | |
1612 | SIG_EXPR_DECL(VPOR9, VPOOFF2, P19_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC); | |
1613 | SIG_EXPR_LIST_DECL(VPOR9, SIG_EXPR_PTR(VPOR9, VPO), | |
1614 | SIG_EXPR_PTR(VPOR9, VPOOFF1), SIG_EXPR_PTR(VPOR9, VPOOFF2)); | |
1615 | SIG_EXPR_LIST_DECL_SINGLE(SALT14, SALT14, P19_DESC); | |
1616 | SIG_EXPR_LIST_DECL_SINGLE(NORD7, PNOR, PNOR_DESC); | |
1617 | SIG_EXPR_LIST_DECL_SINGLE(GPIOAA7, GPIOAA7); | |
1618 | MS_PIN_DECL_(P19, SIG_EXPR_LIST_PTR(VPOR9), SIG_EXPR_LIST_PTR(SALT14), | |
1619 | SIG_EXPR_LIST_PTR(NORD7), SIG_EXPR_LIST_PTR(GPIOAA7)); | |
1620 | FUNC_GROUP_DECL(SALT14, P19); | |
1621 | ||
1622 | #define N19 216 | |
1623 | #define N19_DESC SIG_DESC_SET(SCUA8, 0) | |
1624 | SIG_EXPR_DECL(VPODE, VPO, N19_DESC, VPO_DESC, CRT_DVO_EN_DESC); | |
1625 | SIG_EXPR_DECL(VPODE, VPOOFF1, N19_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); | |
1626 | SIG_EXPR_DECL(VPODE, VPOOFF2, N19_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); | |
1627 | SIG_EXPR_LIST_DECL(VPODE, SIG_EXPR_PTR(VPODE, VPO), | |
1628 | SIG_EXPR_PTR(VPODE, VPOOFF1), SIG_EXPR_PTR(VPODE, VPOOFF2)); | |
1629 | SIG_EXPR_LIST_DECL_SINGLE(NOROE, PNOR, PNOR_DESC); | |
1630 | MS_PIN_DECL(N19, GPIOAB0, VPODE, NOROE); | |
1631 | ||
1632 | #define T21 217 | |
1633 | #define T21_DESC SIG_DESC_SET(SCUA8, 1) | |
1634 | SIG_EXPR_DECL(VPOHS, VPO, T21_DESC, VPO_DESC, CRT_DVO_EN_DESC); | |
1635 | SIG_EXPR_DECL(VPOHS, VPOOFF1, T21_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); | |
1636 | SIG_EXPR_DECL(VPOHS, VPOOFF2, T21_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); | |
1637 | SIG_EXPR_LIST_DECL(VPOHS, SIG_EXPR_PTR(VPOHS, VPO), | |
1638 | SIG_EXPR_PTR(VPOHS, VPOOFF1), SIG_EXPR_PTR(VPOHS, VPOOFF2)); | |
1639 | SIG_EXPR_LIST_DECL_SINGLE(NORWE, PNOR, PNOR_DESC); | |
1640 | MS_PIN_DECL(T21, GPIOAB1, VPOHS, NORWE); | |
1641 | ||
1642 | FUNC_GROUP_DECL(PNOR, Y20, AB20, AB21, AA21, U21, W22, V22, W21, Y21, V21, Y22, | |
1643 | AA22, U22, T20, N18, P19, N19, T21); | |
1644 | ||
1645 | #define T22 218 | |
1646 | #define T22_DESC SIG_DESC_SET(SCUA8, 2) | |
1647 | SIG_EXPR_DECL(VPOVS, VPO, T22_DESC, VPO_DESC, CRT_DVO_EN_DESC); | |
1648 | SIG_EXPR_DECL(VPOVS, VPOOFF1, T22_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); | |
1649 | SIG_EXPR_DECL(VPOVS, VPOOFF2, T22_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); | |
1650 | SIG_EXPR_LIST_DECL(VPOVS, SIG_EXPR_PTR(VPOVS, VPO), | |
1651 | SIG_EXPR_PTR(VPOVS, VPOOFF1), SIG_EXPR_PTR(VPOVS, VPOOFF2)); | |
1652 | SIG_EXPR_LIST_DECL_SINGLE(WDTRST1, WDTRST1, T22_DESC); | |
1653 | MS_PIN_DECL(T22, GPIOAB2, VPOVS, WDTRST1); | |
1654 | FUNC_GROUP_DECL(WDTRST1, T22); | |
1655 | ||
1656 | #define R20 219 | |
1657 | #define R20_DESC SIG_DESC_SET(SCUA8, 3) | |
1658 | SIG_EXPR_DECL(VPOCLK, VPO, R20_DESC, VPO_DESC, CRT_DVO_EN_DESC); | |
1659 | SIG_EXPR_DECL(VPOCLK, VPOOFF1, R20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); | |
1660 | SIG_EXPR_DECL(VPOCLK, VPOOFF2, R20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); | |
1661 | SIG_EXPR_LIST_DECL(VPOCLK, SIG_EXPR_PTR(VPOCLK, VPO), | |
1662 | SIG_EXPR_PTR(VPOCLK, VPOOFF1), SIG_EXPR_PTR(VPOCLK, VPOOFF2)); | |
1663 | SIG_EXPR_LIST_DECL_SINGLE(WDTRST2, WDTRST2, R20_DESC); | |
1664 | MS_PIN_DECL(R20, GPIOAB3, VPOCLK, WDTRST2); | |
1665 | FUNC_GROUP_DECL(WDTRST2, R20); | |
1666 | ||
1667 | FUNC_GROUP_DECL(VPO, V20, U19, R18, P18, R19, W20, U20, AA20, Y20, AB20, | |
1668 | AB21, AA21, U21, W22, V22, W21, Y21, V21, Y22, AA22, U22, T20, | |
1669 | N18, P19, N19, T21, T22, R20); | |
1670 | ||
1671 | #define ESPI_DESC SIG_DESC_SET(HW_STRAP1, 25) | |
1672 | ||
1673 | #define G21 224 | |
1674 | SIG_EXPR_LIST_DECL_SINGLE(ESPID0, ESPI, ESPI_DESC); | |
1675 | SIG_EXPR_LIST_DECL_SINGLE(LAD0, LAD0, SIG_DESC_SET(SCUAC, 0)); | |
1676 | MS_PIN_DECL(G21, GPIOAC0, ESPID0, LAD0); | |
1677 | FUNC_GROUP_DECL(LAD0, G21); | |
1678 | ||
1679 | #define G20 225 | |
1680 | SIG_EXPR_LIST_DECL_SINGLE(ESPID1, ESPI, ESPI_DESC); | |
1681 | SIG_EXPR_LIST_DECL_SINGLE(LAD1, LAD1, SIG_DESC_SET(SCUAC, 1)); | |
1682 | MS_PIN_DECL(G20, GPIOAC1, ESPID1, LAD1); | |
1683 | FUNC_GROUP_DECL(LAD1, G20); | |
1684 | ||
1685 | #define D22 226 | |
1686 | SIG_EXPR_LIST_DECL_SINGLE(ESPID2, ESPI, ESPI_DESC); | |
1687 | SIG_EXPR_LIST_DECL_SINGLE(LAD2, LAD2, SIG_DESC_SET(SCUAC, 2)); | |
1688 | MS_PIN_DECL(D22, GPIOAC2, ESPID2, LAD2); | |
1689 | FUNC_GROUP_DECL(LAD2, D22); | |
1690 | ||
1691 | #define E22 227 | |
1692 | SIG_EXPR_LIST_DECL_SINGLE(ESPID3, ESPI, ESPI_DESC); | |
1693 | SIG_EXPR_LIST_DECL_SINGLE(LAD3, LAD3, SIG_DESC_SET(SCUAC, 3)); | |
1694 | MS_PIN_DECL(E22, GPIOAC3, ESPID3, LAD3); | |
1695 | FUNC_GROUP_DECL(LAD3, E22); | |
1696 | ||
1697 | #define C22 228 | |
1698 | SIG_EXPR_LIST_DECL_SINGLE(ESPICK, ESPI, ESPI_DESC); | |
1699 | SIG_EXPR_LIST_DECL_SINGLE(LCLK, LCLK, SIG_DESC_SET(SCUAC, 4)); | |
1700 | MS_PIN_DECL(C22, GPIOAC4, ESPICK, LCLK); | |
1701 | FUNC_GROUP_DECL(LCLK, C22); | |
1702 | ||
1703 | #define F21 229 | |
1704 | SIG_EXPR_LIST_DECL_SINGLE(ESPICS, ESPI, ESPI_DESC); | |
1705 | SIG_EXPR_LIST_DECL_SINGLE(LFRAME, LFRAME, SIG_DESC_SET(SCUAC, 5)); | |
1706 | MS_PIN_DECL(F21, GPIOAC5, ESPICS, LFRAME); | |
1707 | FUNC_GROUP_DECL(LFRAME, F21); | |
1708 | ||
1709 | #define F22 230 | |
1710 | SIG_EXPR_LIST_DECL_SINGLE(ESPIALT, ESPI, ESPI_DESC); | |
1711 | SIG_EXPR_LIST_DECL_SINGLE(LSIRQ, LSIRQ, SIG_DESC_SET(SCUAC, 6)); | |
1712 | MS_PIN_DECL(F22, GPIOAC6, ESPIALT, LSIRQ); | |
1713 | FUNC_GROUP_DECL(LSIRQ, F22); | |
1714 | ||
1715 | #define G22 231 | |
1716 | SIG_EXPR_LIST_DECL_SINGLE(ESPIRST, ESPI, ESPI_DESC); | |
1717 | SIG_EXPR_LIST_DECL_SINGLE(LPCRST, LPCRST, SIG_DESC_SET(SCUAC, 7)); | |
1718 | MS_PIN_DECL(G22, GPIOAC7, ESPIRST, LPCRST); | |
1719 | FUNC_GROUP_DECL(LPCRST, G22); | |
1720 | ||
1721 | FUNC_GROUP_DECL(ESPI, G21, G20, D22, E22, C22, F21, F22, G22); | |
1722 | ||
9ffac449 AJ |
1723 | #define A7 232 |
1724 | SIG_EXPR_LIST_DECL_SINGLE(USB2AHDP, USB2AH, SIG_DESC_SET(SCU90, 29)); | |
1725 | SIG_EXPR_LIST_DECL_SINGLE(USB2ADDP, USB2AD, SIG_DESC_BIT(SCU90, 29, 0)); | |
1726 | MS_PIN_DECL_(A7, SIG_EXPR_LIST_PTR(USB2AHDP), SIG_EXPR_LIST_PTR(USB2ADDP)); | |
1727 | ||
1728 | #define A8 233 | |
1729 | SIG_EXPR_LIST_DECL_SINGLE(USB2AHDN, USB2AH, SIG_DESC_SET(SCU90, 29)); | |
1730 | SIG_EXPR_LIST_DECL_SINGLE(USB2ADDN, USB2AD, SIG_DESC_BIT(SCU90, 29, 0)); | |
1731 | MS_PIN_DECL_(A8, SIG_EXPR_LIST_PTR(USB2AHDN), SIG_EXPR_LIST_PTR(USB2ADDN)); | |
1732 | ||
1733 | FUNC_GROUP_DECL(USB2AH, A7, A8); | |
1734 | FUNC_GROUP_DECL(USB2AD, A7, A8); | |
1735 | ||
1736 | #define USB11BHID_DESC { ASPEED_IP_SCU, SCU94, GENMASK(14, 13), 0, 0 } | |
1737 | #define USB2BD_DESC { ASPEED_IP_SCU, SCU94, GENMASK(14, 13), 1, 0 } | |
1738 | #define USB2BH1_DESC { ASPEED_IP_SCU, SCU94, GENMASK(14, 13), 2, 0 } | |
1739 | #define USB2BH2_DESC { ASPEED_IP_SCU, SCU94, GENMASK(14, 13), 3, 0 } | |
1740 | ||
1741 | #define B6 234 | |
1742 | SIG_EXPR_LIST_DECL_SINGLE(USB11BDP, USB11BHID, USB11BHID_DESC); | |
1743 | SIG_EXPR_LIST_DECL_SINGLE(USB2BDDP, USB2BD, USB2BD_DESC); | |
1744 | SIG_EXPR_DECL(USB2BHDP1, USB2BH, USB2BH1_DESC); | |
1745 | SIG_EXPR_DECL(USB2BHDP2, USB2BH, USB2BH2_DESC); | |
1746 | SIG_EXPR_LIST_DECL(USB2BHDP, SIG_EXPR_PTR(USB2BHDP1, USB2BH), | |
1747 | SIG_EXPR_PTR(USB2BHDP2, USB2BH)); | |
1748 | MS_PIN_DECL_(B6, SIG_EXPR_LIST_PTR(USB11BDP), SIG_EXPR_LIST_PTR(USB2BDDP), | |
1749 | SIG_EXPR_LIST_PTR(USB2BHDP)); | |
1750 | ||
1751 | #define A6 235 | |
1752 | SIG_EXPR_LIST_DECL_SINGLE(USB11BDN, USB11BHID, USB11BHID_DESC); | |
1753 | SIG_EXPR_LIST_DECL_SINGLE(USB2BDN, USB2BD, USB2BD_DESC); | |
1754 | SIG_EXPR_DECL(USB2BHDN1, USB2BH, USB2BH1_DESC); | |
1755 | SIG_EXPR_DECL(USB2BHDN2, USB2BH, USB2BH2_DESC); | |
1756 | SIG_EXPR_LIST_DECL(USB2BHDN, SIG_EXPR_PTR(USB2BHDN1, USB2BH), | |
1757 | SIG_EXPR_PTR(USB2BHDN2, USB2BH)); | |
1758 | MS_PIN_DECL_(A6, SIG_EXPR_LIST_PTR(USB11BDN), SIG_EXPR_LIST_PTR(USB2BDN), | |
1759 | SIG_EXPR_LIST_PTR(USB2BHDN)); | |
1760 | ||
1761 | FUNC_GROUP_DECL(USB11BHID, B6, A6); | |
1762 | FUNC_GROUP_DECL(USB2BD, B6, A6); | |
1763 | FUNC_GROUP_DECL(USB2BH, B6, A6); | |
1764 | ||
56e57cb6 AJ |
1765 | /* Pins, groups and functions are sort(1):ed alphabetically for sanity */ |
1766 | ||
1767 | static struct pinctrl_pin_desc aspeed_g5_pins[ASPEED_G5_NR_PINS] = { | |
1768 | ASPEED_PINCTRL_PIN(A10), | |
1769 | ASPEED_PINCTRL_PIN(A11), | |
1770 | ASPEED_PINCTRL_PIN(A12), | |
1771 | ASPEED_PINCTRL_PIN(A13), | |
1772 | ASPEED_PINCTRL_PIN(A14), | |
8eb37aff | 1773 | ASPEED_PINCTRL_PIN(A15), |
f1337856 AJ |
1774 | ASPEED_PINCTRL_PIN(A16), |
1775 | ASPEED_PINCTRL_PIN(A17), | |
1776 | ASPEED_PINCTRL_PIN(A18), | |
1777 | ASPEED_PINCTRL_PIN(A19), | |
56e57cb6 | 1778 | ASPEED_PINCTRL_PIN(A2), |
f1337856 AJ |
1779 | ASPEED_PINCTRL_PIN(A20), |
1780 | ASPEED_PINCTRL_PIN(A21), | |
56e57cb6 AJ |
1781 | ASPEED_PINCTRL_PIN(A3), |
1782 | ASPEED_PINCTRL_PIN(A4), | |
1783 | ASPEED_PINCTRL_PIN(A5), | |
9ffac449 AJ |
1784 | ASPEED_PINCTRL_PIN(A6), |
1785 | ASPEED_PINCTRL_PIN(A7), | |
1786 | ASPEED_PINCTRL_PIN(A8), | |
56e57cb6 | 1787 | ASPEED_PINCTRL_PIN(A9), |
f1337856 AJ |
1788 | ASPEED_PINCTRL_PIN(AA1), |
1789 | ASPEED_PINCTRL_PIN(AA19), | |
1790 | ASPEED_PINCTRL_PIN(AA2), | |
1791 | ASPEED_PINCTRL_PIN(AA20), | |
1792 | ASPEED_PINCTRL_PIN(AA21), | |
1793 | ASPEED_PINCTRL_PIN(AA22), | |
56e57cb6 | 1794 | ASPEED_PINCTRL_PIN(AA3), |
f1337856 AJ |
1795 | ASPEED_PINCTRL_PIN(AA4), |
1796 | ASPEED_PINCTRL_PIN(AA5), | |
1797 | ASPEED_PINCTRL_PIN(AB2), | |
1798 | ASPEED_PINCTRL_PIN(AB20), | |
1799 | ASPEED_PINCTRL_PIN(AB21), | |
1800 | ASPEED_PINCTRL_PIN(AB3), | |
1801 | ASPEED_PINCTRL_PIN(AB4), | |
1802 | ASPEED_PINCTRL_PIN(AB5), | |
56e57cb6 AJ |
1803 | ASPEED_PINCTRL_PIN(B1), |
1804 | ASPEED_PINCTRL_PIN(B10), | |
1805 | ASPEED_PINCTRL_PIN(B11), | |
1806 | ASPEED_PINCTRL_PIN(B12), | |
1807 | ASPEED_PINCTRL_PIN(B13), | |
1808 | ASPEED_PINCTRL_PIN(B14), | |
8eb37aff AJ |
1809 | ASPEED_PINCTRL_PIN(B15), |
1810 | ASPEED_PINCTRL_PIN(B16), | |
f1337856 AJ |
1811 | ASPEED_PINCTRL_PIN(B17), |
1812 | ASPEED_PINCTRL_PIN(B18), | |
1813 | ASPEED_PINCTRL_PIN(B19), | |
56e57cb6 AJ |
1814 | ASPEED_PINCTRL_PIN(B2), |
1815 | ASPEED_PINCTRL_PIN(B20), | |
f1337856 AJ |
1816 | ASPEED_PINCTRL_PIN(B21), |
1817 | ASPEED_PINCTRL_PIN(B22), | |
56e57cb6 AJ |
1818 | ASPEED_PINCTRL_PIN(B3), |
1819 | ASPEED_PINCTRL_PIN(B4), | |
1820 | ASPEED_PINCTRL_PIN(B5), | |
9ffac449 | 1821 | ASPEED_PINCTRL_PIN(B6), |
56e57cb6 AJ |
1822 | ASPEED_PINCTRL_PIN(B9), |
1823 | ASPEED_PINCTRL_PIN(C1), | |
1824 | ASPEED_PINCTRL_PIN(C11), | |
1825 | ASPEED_PINCTRL_PIN(C12), | |
1826 | ASPEED_PINCTRL_PIN(C13), | |
1827 | ASPEED_PINCTRL_PIN(C14), | |
8eb37aff | 1828 | ASPEED_PINCTRL_PIN(C15), |
56e57cb6 | 1829 | ASPEED_PINCTRL_PIN(C16), |
f1337856 | 1830 | ASPEED_PINCTRL_PIN(C17), |
56e57cb6 | 1831 | ASPEED_PINCTRL_PIN(C18), |
f1337856 | 1832 | ASPEED_PINCTRL_PIN(C19), |
56e57cb6 AJ |
1833 | ASPEED_PINCTRL_PIN(C2), |
1834 | ASPEED_PINCTRL_PIN(C20), | |
f1337856 AJ |
1835 | ASPEED_PINCTRL_PIN(C21), |
1836 | ASPEED_PINCTRL_PIN(C22), | |
56e57cb6 AJ |
1837 | ASPEED_PINCTRL_PIN(C3), |
1838 | ASPEED_PINCTRL_PIN(C4), | |
1839 | ASPEED_PINCTRL_PIN(C5), | |
1840 | ASPEED_PINCTRL_PIN(D1), | |
1841 | ASPEED_PINCTRL_PIN(D10), | |
f1337856 AJ |
1842 | ASPEED_PINCTRL_PIN(D13), |
1843 | ASPEED_PINCTRL_PIN(D14), | |
1844 | ASPEED_PINCTRL_PIN(D15), | |
1845 | ASPEED_PINCTRL_PIN(D16), | |
1846 | ASPEED_PINCTRL_PIN(D17), | |
1847 | ASPEED_PINCTRL_PIN(D18), | |
1848 | ASPEED_PINCTRL_PIN(D19), | |
56e57cb6 AJ |
1849 | ASPEED_PINCTRL_PIN(D2), |
1850 | ASPEED_PINCTRL_PIN(D20), | |
f1337856 AJ |
1851 | ASPEED_PINCTRL_PIN(D21), |
1852 | ASPEED_PINCTRL_PIN(D22), | |
56e57cb6 AJ |
1853 | ASPEED_PINCTRL_PIN(D4), |
1854 | ASPEED_PINCTRL_PIN(D5), | |
1855 | ASPEED_PINCTRL_PIN(D6), | |
1856 | ASPEED_PINCTRL_PIN(D7), | |
1857 | ASPEED_PINCTRL_PIN(D8), | |
1858 | ASPEED_PINCTRL_PIN(D9), | |
f1337856 | 1859 | ASPEED_PINCTRL_PIN(E1), |
56e57cb6 AJ |
1860 | ASPEED_PINCTRL_PIN(E10), |
1861 | ASPEED_PINCTRL_PIN(E12), | |
1862 | ASPEED_PINCTRL_PIN(E13), | |
f1337856 | 1863 | ASPEED_PINCTRL_PIN(E14), |
56e57cb6 | 1864 | ASPEED_PINCTRL_PIN(E15), |
f1337856 AJ |
1865 | ASPEED_PINCTRL_PIN(E16), |
1866 | ASPEED_PINCTRL_PIN(E17), | |
1867 | ASPEED_PINCTRL_PIN(E18), | |
1868 | ASPEED_PINCTRL_PIN(E19), | |
1869 | ASPEED_PINCTRL_PIN(E2), | |
1870 | ASPEED_PINCTRL_PIN(E20), | |
56e57cb6 | 1871 | ASPEED_PINCTRL_PIN(E21), |
f1337856 AJ |
1872 | ASPEED_PINCTRL_PIN(E22), |
1873 | ASPEED_PINCTRL_PIN(E3), | |
56e57cb6 AJ |
1874 | ASPEED_PINCTRL_PIN(E6), |
1875 | ASPEED_PINCTRL_PIN(E7), | |
1876 | ASPEED_PINCTRL_PIN(E9), | |
f1337856 AJ |
1877 | ASPEED_PINCTRL_PIN(F1), |
1878 | ASPEED_PINCTRL_PIN(F17), | |
1879 | ASPEED_PINCTRL_PIN(F18), | |
56e57cb6 | 1880 | ASPEED_PINCTRL_PIN(F19), |
f1337856 | 1881 | ASPEED_PINCTRL_PIN(F2), |
97e8c3f5 | 1882 | ASPEED_PINCTRL_PIN(F20), |
f1337856 AJ |
1883 | ASPEED_PINCTRL_PIN(F21), |
1884 | ASPEED_PINCTRL_PIN(F22), | |
1885 | ASPEED_PINCTRL_PIN(F3), | |
1886 | ASPEED_PINCTRL_PIN(F4), | |
1887 | ASPEED_PINCTRL_PIN(F5), | |
56e57cb6 | 1888 | ASPEED_PINCTRL_PIN(F9), |
f1337856 AJ |
1889 | ASPEED_PINCTRL_PIN(G1), |
1890 | ASPEED_PINCTRL_PIN(G17), | |
1891 | ASPEED_PINCTRL_PIN(G18), | |
1892 | ASPEED_PINCTRL_PIN(G2), | |
1893 | ASPEED_PINCTRL_PIN(G20), | |
1894 | ASPEED_PINCTRL_PIN(G21), | |
1895 | ASPEED_PINCTRL_PIN(G22), | |
1896 | ASPEED_PINCTRL_PIN(G3), | |
1897 | ASPEED_PINCTRL_PIN(G4), | |
1898 | ASPEED_PINCTRL_PIN(G5), | |
1899 | ASPEED_PINCTRL_PIN(H18), | |
1900 | ASPEED_PINCTRL_PIN(H19), | |
56e57cb6 | 1901 | ASPEED_PINCTRL_PIN(H20), |
f1337856 AJ |
1902 | ASPEED_PINCTRL_PIN(H21), |
1903 | ASPEED_PINCTRL_PIN(H22), | |
1904 | ASPEED_PINCTRL_PIN(H3), | |
1905 | ASPEED_PINCTRL_PIN(H4), | |
1906 | ASPEED_PINCTRL_PIN(H5), | |
1907 | ASPEED_PINCTRL_PIN(J18), | |
1908 | ASPEED_PINCTRL_PIN(J19), | |
1909 | ASPEED_PINCTRL_PIN(J20), | |
1910 | ASPEED_PINCTRL_PIN(K18), | |
1911 | ASPEED_PINCTRL_PIN(K19), | |
56e57cb6 | 1912 | ASPEED_PINCTRL_PIN(L1), |
f1337856 AJ |
1913 | ASPEED_PINCTRL_PIN(L18), |
1914 | ASPEED_PINCTRL_PIN(L19), | |
56e57cb6 AJ |
1915 | ASPEED_PINCTRL_PIN(L2), |
1916 | ASPEED_PINCTRL_PIN(L3), | |
1917 | ASPEED_PINCTRL_PIN(L4), | |
f1337856 AJ |
1918 | ASPEED_PINCTRL_PIN(M18), |
1919 | ASPEED_PINCTRL_PIN(M19), | |
1920 | ASPEED_PINCTRL_PIN(M20), | |
56e57cb6 | 1921 | ASPEED_PINCTRL_PIN(N1), |
f1337856 AJ |
1922 | ASPEED_PINCTRL_PIN(N18), |
1923 | ASPEED_PINCTRL_PIN(N19), | |
56e57cb6 AJ |
1924 | ASPEED_PINCTRL_PIN(N2), |
1925 | ASPEED_PINCTRL_PIN(N20), | |
1926 | ASPEED_PINCTRL_PIN(N21), | |
1927 | ASPEED_PINCTRL_PIN(N22), | |
1928 | ASPEED_PINCTRL_PIN(N3), | |
1929 | ASPEED_PINCTRL_PIN(N4), | |
f1337856 | 1930 | ASPEED_PINCTRL_PIN(N5), |
56e57cb6 | 1931 | ASPEED_PINCTRL_PIN(P1), |
f1337856 AJ |
1932 | ASPEED_PINCTRL_PIN(P18), |
1933 | ASPEED_PINCTRL_PIN(P19), | |
56e57cb6 | 1934 | ASPEED_PINCTRL_PIN(P2), |
f1337856 AJ |
1935 | ASPEED_PINCTRL_PIN(P20), |
1936 | ASPEED_PINCTRL_PIN(P21), | |
1937 | ASPEED_PINCTRL_PIN(P22), | |
1938 | ASPEED_PINCTRL_PIN(P3), | |
1939 | ASPEED_PINCTRL_PIN(P4), | |
1940 | ASPEED_PINCTRL_PIN(P5), | |
56e57cb6 | 1941 | ASPEED_PINCTRL_PIN(R1), |
f1337856 AJ |
1942 | ASPEED_PINCTRL_PIN(R18), |
1943 | ASPEED_PINCTRL_PIN(R19), | |
1944 | ASPEED_PINCTRL_PIN(R2), | |
1945 | ASPEED_PINCTRL_PIN(R20), | |
1946 | ASPEED_PINCTRL_PIN(R21), | |
1947 | ASPEED_PINCTRL_PIN(R22), | |
1948 | ASPEED_PINCTRL_PIN(R3), | |
1949 | ASPEED_PINCTRL_PIN(R4), | |
1950 | ASPEED_PINCTRL_PIN(R5), | |
1951 | ASPEED_PINCTRL_PIN(T1), | |
1952 | ASPEED_PINCTRL_PIN(T17), | |
1953 | ASPEED_PINCTRL_PIN(T19), | |
1954 | ASPEED_PINCTRL_PIN(T2), | |
1955 | ASPEED_PINCTRL_PIN(T20), | |
1956 | ASPEED_PINCTRL_PIN(T21), | |
1957 | ASPEED_PINCTRL_PIN(T22), | |
1958 | ASPEED_PINCTRL_PIN(T3), | |
56e57cb6 | 1959 | ASPEED_PINCTRL_PIN(T4), |
f1337856 AJ |
1960 | ASPEED_PINCTRL_PIN(T5), |
1961 | ASPEED_PINCTRL_PIN(U1), | |
1962 | ASPEED_PINCTRL_PIN(U19), | |
1963 | ASPEED_PINCTRL_PIN(U2), | |
1964 | ASPEED_PINCTRL_PIN(U20), | |
1965 | ASPEED_PINCTRL_PIN(U21), | |
1966 | ASPEED_PINCTRL_PIN(U22), | |
56e57cb6 | 1967 | ASPEED_PINCTRL_PIN(U3), |
f1337856 AJ |
1968 | ASPEED_PINCTRL_PIN(U4), |
1969 | ASPEED_PINCTRL_PIN(U5), | |
1970 | ASPEED_PINCTRL_PIN(V1), | |
1971 | ASPEED_PINCTRL_PIN(V19), | |
56e57cb6 | 1972 | ASPEED_PINCTRL_PIN(V2), |
f1337856 AJ |
1973 | ASPEED_PINCTRL_PIN(V20), |
1974 | ASPEED_PINCTRL_PIN(V21), | |
1975 | ASPEED_PINCTRL_PIN(V22), | |
56e57cb6 | 1976 | ASPEED_PINCTRL_PIN(V3), |
f1337856 AJ |
1977 | ASPEED_PINCTRL_PIN(V4), |
1978 | ASPEED_PINCTRL_PIN(V5), | |
56e57cb6 | 1979 | ASPEED_PINCTRL_PIN(V6), |
f1337856 AJ |
1980 | ASPEED_PINCTRL_PIN(W1), |
1981 | ASPEED_PINCTRL_PIN(W19), | |
56e57cb6 | 1982 | ASPEED_PINCTRL_PIN(W2), |
f1337856 AJ |
1983 | ASPEED_PINCTRL_PIN(W20), |
1984 | ASPEED_PINCTRL_PIN(W21), | |
1985 | ASPEED_PINCTRL_PIN(W22), | |
56e57cb6 | 1986 | ASPEED_PINCTRL_PIN(W3), |
f1337856 AJ |
1987 | ASPEED_PINCTRL_PIN(W4), |
1988 | ASPEED_PINCTRL_PIN(W5), | |
1989 | ASPEED_PINCTRL_PIN(W6), | |
1990 | ASPEED_PINCTRL_PIN(Y1), | |
1991 | ASPEED_PINCTRL_PIN(Y19), | |
1992 | ASPEED_PINCTRL_PIN(Y2), | |
1993 | ASPEED_PINCTRL_PIN(Y20), | |
1994 | ASPEED_PINCTRL_PIN(Y21), | |
1995 | ASPEED_PINCTRL_PIN(Y22), | |
56e57cb6 | 1996 | ASPEED_PINCTRL_PIN(Y3), |
f1337856 AJ |
1997 | ASPEED_PINCTRL_PIN(Y4), |
1998 | ASPEED_PINCTRL_PIN(Y5), | |
1999 | ASPEED_PINCTRL_PIN(Y6), | |
56e57cb6 AJ |
2000 | }; |
2001 | ||
2002 | static const struct aspeed_pin_group aspeed_g5_groups[] = { | |
f1337856 AJ |
2003 | ASPEED_PINCTRL_GROUP(ACPI), |
2004 | ASPEED_PINCTRL_GROUP(ADC0), | |
2005 | ASPEED_PINCTRL_GROUP(ADC1), | |
2006 | ASPEED_PINCTRL_GROUP(ADC10), | |
2007 | ASPEED_PINCTRL_GROUP(ADC11), | |
2008 | ASPEED_PINCTRL_GROUP(ADC12), | |
2009 | ASPEED_PINCTRL_GROUP(ADC13), | |
2010 | ASPEED_PINCTRL_GROUP(ADC14), | |
2011 | ASPEED_PINCTRL_GROUP(ADC15), | |
2012 | ASPEED_PINCTRL_GROUP(ADC2), | |
2013 | ASPEED_PINCTRL_GROUP(ADC3), | |
2014 | ASPEED_PINCTRL_GROUP(ADC4), | |
2015 | ASPEED_PINCTRL_GROUP(ADC5), | |
2016 | ASPEED_PINCTRL_GROUP(ADC6), | |
2017 | ASPEED_PINCTRL_GROUP(ADC7), | |
2018 | ASPEED_PINCTRL_GROUP(ADC8), | |
2019 | ASPEED_PINCTRL_GROUP(ADC9), | |
2020 | ASPEED_PINCTRL_GROUP(BMCINT), | |
2021 | ASPEED_PINCTRL_GROUP(DDCCLK), | |
2022 | ASPEED_PINCTRL_GROUP(DDCDAT), | |
2023 | ASPEED_PINCTRL_GROUP(ESPI), | |
2024 | ASPEED_PINCTRL_GROUP(FWSPICS1), | |
2025 | ASPEED_PINCTRL_GROUP(FWSPICS2), | |
56e57cb6 AJ |
2026 | ASPEED_PINCTRL_GROUP(GPID0), |
2027 | ASPEED_PINCTRL_GROUP(GPID2), | |
f1337856 AJ |
2028 | ASPEED_PINCTRL_GROUP(GPID4), |
2029 | ASPEED_PINCTRL_GROUP(GPID6), | |
56e57cb6 | 2030 | ASPEED_PINCTRL_GROUP(GPIE0), |
f1337856 AJ |
2031 | ASPEED_PINCTRL_GROUP(GPIE2), |
2032 | ASPEED_PINCTRL_GROUP(GPIE4), | |
2033 | ASPEED_PINCTRL_GROUP(GPIE6), | |
56e57cb6 AJ |
2034 | ASPEED_PINCTRL_GROUP(I2C10), |
2035 | ASPEED_PINCTRL_GROUP(I2C11), | |
2036 | ASPEED_PINCTRL_GROUP(I2C12), | |
2037 | ASPEED_PINCTRL_GROUP(I2C13), | |
2038 | ASPEED_PINCTRL_GROUP(I2C14), | |
2039 | ASPEED_PINCTRL_GROUP(I2C3), | |
2040 | ASPEED_PINCTRL_GROUP(I2C4), | |
2041 | ASPEED_PINCTRL_GROUP(I2C5), | |
2042 | ASPEED_PINCTRL_GROUP(I2C6), | |
2043 | ASPEED_PINCTRL_GROUP(I2C7), | |
2044 | ASPEED_PINCTRL_GROUP(I2C8), | |
2045 | ASPEED_PINCTRL_GROUP(I2C9), | |
f1337856 AJ |
2046 | ASPEED_PINCTRL_GROUP(LAD0), |
2047 | ASPEED_PINCTRL_GROUP(LAD1), | |
2048 | ASPEED_PINCTRL_GROUP(LAD2), | |
2049 | ASPEED_PINCTRL_GROUP(LAD3), | |
2050 | ASPEED_PINCTRL_GROUP(LCLK), | |
2051 | ASPEED_PINCTRL_GROUP(LFRAME), | |
2052 | ASPEED_PINCTRL_GROUP(LPCHC), | |
2053 | ASPEED_PINCTRL_GROUP(LPCPD), | |
2054 | ASPEED_PINCTRL_GROUP(LPCPLUS), | |
2055 | ASPEED_PINCTRL_GROUP(LPCPME), | |
2056 | ASPEED_PINCTRL_GROUP(LPCRST), | |
2057 | ASPEED_PINCTRL_GROUP(LPCSMI), | |
2058 | ASPEED_PINCTRL_GROUP(LSIRQ), | |
56e57cb6 | 2059 | ASPEED_PINCTRL_GROUP(MAC1LINK), |
f1337856 | 2060 | ASPEED_PINCTRL_GROUP(MAC2LINK), |
56e57cb6 AJ |
2061 | ASPEED_PINCTRL_GROUP(MDIO1), |
2062 | ASPEED_PINCTRL_GROUP(MDIO2), | |
f1337856 AJ |
2063 | ASPEED_PINCTRL_GROUP(NCTS1), |
2064 | ASPEED_PINCTRL_GROUP(NCTS2), | |
2065 | ASPEED_PINCTRL_GROUP(NCTS3), | |
2066 | ASPEED_PINCTRL_GROUP(NCTS4), | |
2067 | ASPEED_PINCTRL_GROUP(NDCD1), | |
2068 | ASPEED_PINCTRL_GROUP(NDCD2), | |
2069 | ASPEED_PINCTRL_GROUP(NDCD3), | |
2070 | ASPEED_PINCTRL_GROUP(NDCD4), | |
2071 | ASPEED_PINCTRL_GROUP(NDSR1), | |
2072 | ASPEED_PINCTRL_GROUP(NDSR2), | |
2073 | ASPEED_PINCTRL_GROUP(NDSR3), | |
2074 | ASPEED_PINCTRL_GROUP(NDSR4), | |
2075 | ASPEED_PINCTRL_GROUP(NDTR1), | |
2076 | ASPEED_PINCTRL_GROUP(NDTR2), | |
2077 | ASPEED_PINCTRL_GROUP(NDTR3), | |
2078 | ASPEED_PINCTRL_GROUP(NDTR4), | |
2079 | ASPEED_PINCTRL_GROUP(NRI1), | |
2080 | ASPEED_PINCTRL_GROUP(NRI2), | |
2081 | ASPEED_PINCTRL_GROUP(NRI3), | |
2082 | ASPEED_PINCTRL_GROUP(NRI4), | |
2083 | ASPEED_PINCTRL_GROUP(NRTS1), | |
2084 | ASPEED_PINCTRL_GROUP(NRTS2), | |
2085 | ASPEED_PINCTRL_GROUP(NRTS3), | |
2086 | ASPEED_PINCTRL_GROUP(NRTS4), | |
56e57cb6 AJ |
2087 | ASPEED_PINCTRL_GROUP(OSCCLK), |
2088 | ASPEED_PINCTRL_GROUP(PEWAKE), | |
f1337856 | 2089 | ASPEED_PINCTRL_GROUP(PNOR), |
56e57cb6 AJ |
2090 | ASPEED_PINCTRL_GROUP(PWM0), |
2091 | ASPEED_PINCTRL_GROUP(PWM1), | |
2092 | ASPEED_PINCTRL_GROUP(PWM2), | |
2093 | ASPEED_PINCTRL_GROUP(PWM3), | |
2094 | ASPEED_PINCTRL_GROUP(PWM4), | |
2095 | ASPEED_PINCTRL_GROUP(PWM5), | |
2096 | ASPEED_PINCTRL_GROUP(PWM6), | |
2097 | ASPEED_PINCTRL_GROUP(PWM7), | |
2098 | ASPEED_PINCTRL_GROUP(RGMII1), | |
2099 | ASPEED_PINCTRL_GROUP(RGMII2), | |
2100 | ASPEED_PINCTRL_GROUP(RMII1), | |
2101 | ASPEED_PINCTRL_GROUP(RMII2), | |
f1337856 AJ |
2102 | ASPEED_PINCTRL_GROUP(RXD1), |
2103 | ASPEED_PINCTRL_GROUP(RXD2), | |
2104 | ASPEED_PINCTRL_GROUP(RXD3), | |
2105 | ASPEED_PINCTRL_GROUP(RXD4), | |
2106 | ASPEED_PINCTRL_GROUP(SALT1), | |
2107 | ASPEED_PINCTRL_GROUP(SALT10), | |
2108 | ASPEED_PINCTRL_GROUP(SALT11), | |
2109 | ASPEED_PINCTRL_GROUP(SALT12), | |
2110 | ASPEED_PINCTRL_GROUP(SALT13), | |
2111 | ASPEED_PINCTRL_GROUP(SALT14), | |
2112 | ASPEED_PINCTRL_GROUP(SALT2), | |
2113 | ASPEED_PINCTRL_GROUP(SALT3), | |
2114 | ASPEED_PINCTRL_GROUP(SALT4), | |
2115 | ASPEED_PINCTRL_GROUP(SALT5), | |
2116 | ASPEED_PINCTRL_GROUP(SALT6), | |
2117 | ASPEED_PINCTRL_GROUP(SALT7), | |
2118 | ASPEED_PINCTRL_GROUP(SALT8), | |
2119 | ASPEED_PINCTRL_GROUP(SALT9), | |
2120 | ASPEED_PINCTRL_GROUP(SCL1), | |
2121 | ASPEED_PINCTRL_GROUP(SCL2), | |
56e57cb6 | 2122 | ASPEED_PINCTRL_GROUP(SD1), |
f1337856 AJ |
2123 | ASPEED_PINCTRL_GROUP(SD2), |
2124 | ASPEED_PINCTRL_GROUP(SDA1), | |
2125 | ASPEED_PINCTRL_GROUP(SDA2), | |
2126 | ASPEED_PINCTRL_GROUP(SGPS1), | |
2127 | ASPEED_PINCTRL_GROUP(SGPS2), | |
2128 | ASPEED_PINCTRL_GROUP(SIOONCTRL), | |
2129 | ASPEED_PINCTRL_GROUP(SIOPBI), | |
2130 | ASPEED_PINCTRL_GROUP(SIOPBO), | |
2131 | ASPEED_PINCTRL_GROUP(SIOPWREQ), | |
2132 | ASPEED_PINCTRL_GROUP(SIOPWRGD), | |
2133 | ASPEED_PINCTRL_GROUP(SIOS3), | |
2134 | ASPEED_PINCTRL_GROUP(SIOS5), | |
2135 | ASPEED_PINCTRL_GROUP(SIOSCI), | |
56e57cb6 | 2136 | ASPEED_PINCTRL_GROUP(SPI1), |
f1337856 | 2137 | ASPEED_PINCTRL_GROUP(SPI1CS1), |
8eb37aff AJ |
2138 | ASPEED_PINCTRL_GROUP(SPI1DEBUG), |
2139 | ASPEED_PINCTRL_GROUP(SPI1PASSTHRU), | |
f1337856 AJ |
2140 | ASPEED_PINCTRL_GROUP(SPI2CK), |
2141 | ASPEED_PINCTRL_GROUP(SPI2CS0), | |
2142 | ASPEED_PINCTRL_GROUP(SPI2CS1), | |
2143 | ASPEED_PINCTRL_GROUP(SPI2MISO), | |
2144 | ASPEED_PINCTRL_GROUP(SPI2MOSI), | |
2145 | ASPEED_PINCTRL_GROUP(TIMER3), | |
56e57cb6 AJ |
2146 | ASPEED_PINCTRL_GROUP(TIMER4), |
2147 | ASPEED_PINCTRL_GROUP(TIMER5), | |
2148 | ASPEED_PINCTRL_GROUP(TIMER6), | |
2149 | ASPEED_PINCTRL_GROUP(TIMER7), | |
2150 | ASPEED_PINCTRL_GROUP(TIMER8), | |
f1337856 AJ |
2151 | ASPEED_PINCTRL_GROUP(TXD1), |
2152 | ASPEED_PINCTRL_GROUP(TXD2), | |
2153 | ASPEED_PINCTRL_GROUP(TXD3), | |
2154 | ASPEED_PINCTRL_GROUP(TXD4), | |
2155 | ASPEED_PINCTRL_GROUP(UART6), | |
9ffac449 AJ |
2156 | ASPEED_PINCTRL_GROUP(USB11BHID), |
2157 | ASPEED_PINCTRL_GROUP(USB2AD), | |
2158 | ASPEED_PINCTRL_GROUP(USB2AH), | |
2159 | ASPEED_PINCTRL_GROUP(USB2BD), | |
2160 | ASPEED_PINCTRL_GROUP(USB2BH), | |
f1337856 | 2161 | ASPEED_PINCTRL_GROUP(USBCKI), |
8eb37aff | 2162 | ASPEED_PINCTRL_GROUP(VGABIOSROM), |
f1337856 AJ |
2163 | ASPEED_PINCTRL_GROUP(VGAHS), |
2164 | ASPEED_PINCTRL_GROUP(VGAVS), | |
2165 | ASPEED_PINCTRL_GROUP(VPI24), | |
2166 | ASPEED_PINCTRL_GROUP(VPO), | |
2167 | ASPEED_PINCTRL_GROUP(WDTRST1), | |
2168 | ASPEED_PINCTRL_GROUP(WDTRST2), | |
56e57cb6 AJ |
2169 | }; |
2170 | ||
2171 | static const struct aspeed_pin_function aspeed_g5_functions[] = { | |
f1337856 AJ |
2172 | ASPEED_PINCTRL_FUNC(ACPI), |
2173 | ASPEED_PINCTRL_FUNC(ADC0), | |
2174 | ASPEED_PINCTRL_FUNC(ADC1), | |
2175 | ASPEED_PINCTRL_FUNC(ADC10), | |
2176 | ASPEED_PINCTRL_FUNC(ADC11), | |
2177 | ASPEED_PINCTRL_FUNC(ADC12), | |
2178 | ASPEED_PINCTRL_FUNC(ADC13), | |
2179 | ASPEED_PINCTRL_FUNC(ADC14), | |
2180 | ASPEED_PINCTRL_FUNC(ADC15), | |
2181 | ASPEED_PINCTRL_FUNC(ADC2), | |
2182 | ASPEED_PINCTRL_FUNC(ADC3), | |
2183 | ASPEED_PINCTRL_FUNC(ADC4), | |
2184 | ASPEED_PINCTRL_FUNC(ADC5), | |
2185 | ASPEED_PINCTRL_FUNC(ADC6), | |
2186 | ASPEED_PINCTRL_FUNC(ADC7), | |
2187 | ASPEED_PINCTRL_FUNC(ADC8), | |
2188 | ASPEED_PINCTRL_FUNC(ADC9), | |
2189 | ASPEED_PINCTRL_FUNC(BMCINT), | |
2190 | ASPEED_PINCTRL_FUNC(DDCCLK), | |
2191 | ASPEED_PINCTRL_FUNC(DDCDAT), | |
2192 | ASPEED_PINCTRL_FUNC(ESPI), | |
2193 | ASPEED_PINCTRL_FUNC(FWSPICS1), | |
2194 | ASPEED_PINCTRL_FUNC(FWSPICS2), | |
56e57cb6 AJ |
2195 | ASPEED_PINCTRL_FUNC(GPID0), |
2196 | ASPEED_PINCTRL_FUNC(GPID2), | |
f1337856 AJ |
2197 | ASPEED_PINCTRL_FUNC(GPID4), |
2198 | ASPEED_PINCTRL_FUNC(GPID6), | |
56e57cb6 | 2199 | ASPEED_PINCTRL_FUNC(GPIE0), |
f1337856 AJ |
2200 | ASPEED_PINCTRL_FUNC(GPIE2), |
2201 | ASPEED_PINCTRL_FUNC(GPIE4), | |
2202 | ASPEED_PINCTRL_FUNC(GPIE6), | |
56e57cb6 AJ |
2203 | ASPEED_PINCTRL_FUNC(I2C10), |
2204 | ASPEED_PINCTRL_FUNC(I2C11), | |
2205 | ASPEED_PINCTRL_FUNC(I2C12), | |
2206 | ASPEED_PINCTRL_FUNC(I2C13), | |
2207 | ASPEED_PINCTRL_FUNC(I2C14), | |
2208 | ASPEED_PINCTRL_FUNC(I2C3), | |
2209 | ASPEED_PINCTRL_FUNC(I2C4), | |
2210 | ASPEED_PINCTRL_FUNC(I2C5), | |
2211 | ASPEED_PINCTRL_FUNC(I2C6), | |
2212 | ASPEED_PINCTRL_FUNC(I2C7), | |
2213 | ASPEED_PINCTRL_FUNC(I2C8), | |
2214 | ASPEED_PINCTRL_FUNC(I2C9), | |
f1337856 AJ |
2215 | ASPEED_PINCTRL_FUNC(LAD0), |
2216 | ASPEED_PINCTRL_FUNC(LAD1), | |
2217 | ASPEED_PINCTRL_FUNC(LAD2), | |
2218 | ASPEED_PINCTRL_FUNC(LAD3), | |
2219 | ASPEED_PINCTRL_FUNC(LCLK), | |
2220 | ASPEED_PINCTRL_FUNC(LFRAME), | |
2221 | ASPEED_PINCTRL_FUNC(LPCHC), | |
2222 | ASPEED_PINCTRL_FUNC(LPCPD), | |
2223 | ASPEED_PINCTRL_FUNC(LPCPLUS), | |
2224 | ASPEED_PINCTRL_FUNC(LPCPME), | |
2225 | ASPEED_PINCTRL_FUNC(LPCRST), | |
2226 | ASPEED_PINCTRL_FUNC(LPCSMI), | |
2227 | ASPEED_PINCTRL_FUNC(LSIRQ), | |
56e57cb6 | 2228 | ASPEED_PINCTRL_FUNC(MAC1LINK), |
f1337856 | 2229 | ASPEED_PINCTRL_FUNC(MAC2LINK), |
56e57cb6 AJ |
2230 | ASPEED_PINCTRL_FUNC(MDIO1), |
2231 | ASPEED_PINCTRL_FUNC(MDIO2), | |
f1337856 AJ |
2232 | ASPEED_PINCTRL_FUNC(NCTS1), |
2233 | ASPEED_PINCTRL_FUNC(NCTS2), | |
2234 | ASPEED_PINCTRL_FUNC(NCTS3), | |
2235 | ASPEED_PINCTRL_FUNC(NCTS4), | |
2236 | ASPEED_PINCTRL_FUNC(NDCD1), | |
2237 | ASPEED_PINCTRL_FUNC(NDCD2), | |
2238 | ASPEED_PINCTRL_FUNC(NDCD3), | |
2239 | ASPEED_PINCTRL_FUNC(NDCD4), | |
2240 | ASPEED_PINCTRL_FUNC(NDSR1), | |
2241 | ASPEED_PINCTRL_FUNC(NDSR2), | |
2242 | ASPEED_PINCTRL_FUNC(NDSR3), | |
2243 | ASPEED_PINCTRL_FUNC(NDSR4), | |
2244 | ASPEED_PINCTRL_FUNC(NDTR1), | |
2245 | ASPEED_PINCTRL_FUNC(NDTR2), | |
2246 | ASPEED_PINCTRL_FUNC(NDTR3), | |
2247 | ASPEED_PINCTRL_FUNC(NDTR4), | |
2248 | ASPEED_PINCTRL_FUNC(NRI1), | |
2249 | ASPEED_PINCTRL_FUNC(NRI2), | |
2250 | ASPEED_PINCTRL_FUNC(NRI3), | |
2251 | ASPEED_PINCTRL_FUNC(NRI4), | |
2252 | ASPEED_PINCTRL_FUNC(NRTS1), | |
2253 | ASPEED_PINCTRL_FUNC(NRTS2), | |
2254 | ASPEED_PINCTRL_FUNC(NRTS3), | |
2255 | ASPEED_PINCTRL_FUNC(NRTS4), | |
56e57cb6 AJ |
2256 | ASPEED_PINCTRL_FUNC(OSCCLK), |
2257 | ASPEED_PINCTRL_FUNC(PEWAKE), | |
f1337856 | 2258 | ASPEED_PINCTRL_FUNC(PNOR), |
56e57cb6 AJ |
2259 | ASPEED_PINCTRL_FUNC(PWM0), |
2260 | ASPEED_PINCTRL_FUNC(PWM1), | |
2261 | ASPEED_PINCTRL_FUNC(PWM2), | |
2262 | ASPEED_PINCTRL_FUNC(PWM3), | |
2263 | ASPEED_PINCTRL_FUNC(PWM4), | |
2264 | ASPEED_PINCTRL_FUNC(PWM5), | |
2265 | ASPEED_PINCTRL_FUNC(PWM6), | |
2266 | ASPEED_PINCTRL_FUNC(PWM7), | |
2267 | ASPEED_PINCTRL_FUNC(RGMII1), | |
2268 | ASPEED_PINCTRL_FUNC(RGMII2), | |
2269 | ASPEED_PINCTRL_FUNC(RMII1), | |
2270 | ASPEED_PINCTRL_FUNC(RMII2), | |
f1337856 AJ |
2271 | ASPEED_PINCTRL_FUNC(RXD1), |
2272 | ASPEED_PINCTRL_FUNC(RXD2), | |
2273 | ASPEED_PINCTRL_FUNC(RXD3), | |
2274 | ASPEED_PINCTRL_FUNC(RXD4), | |
2275 | ASPEED_PINCTRL_FUNC(SALT1), | |
2276 | ASPEED_PINCTRL_FUNC(SALT10), | |
2277 | ASPEED_PINCTRL_FUNC(SALT11), | |
2278 | ASPEED_PINCTRL_FUNC(SALT12), | |
2279 | ASPEED_PINCTRL_FUNC(SALT13), | |
2280 | ASPEED_PINCTRL_FUNC(SALT14), | |
2281 | ASPEED_PINCTRL_FUNC(SALT2), | |
2282 | ASPEED_PINCTRL_FUNC(SALT3), | |
2283 | ASPEED_PINCTRL_FUNC(SALT4), | |
2284 | ASPEED_PINCTRL_FUNC(SALT5), | |
2285 | ASPEED_PINCTRL_FUNC(SALT6), | |
2286 | ASPEED_PINCTRL_FUNC(SALT7), | |
2287 | ASPEED_PINCTRL_FUNC(SALT8), | |
2288 | ASPEED_PINCTRL_FUNC(SALT9), | |
2289 | ASPEED_PINCTRL_FUNC(SCL1), | |
2290 | ASPEED_PINCTRL_FUNC(SCL2), | |
56e57cb6 | 2291 | ASPEED_PINCTRL_FUNC(SD1), |
f1337856 AJ |
2292 | ASPEED_PINCTRL_FUNC(SD2), |
2293 | ASPEED_PINCTRL_FUNC(SDA1), | |
2294 | ASPEED_PINCTRL_FUNC(SDA2), | |
2295 | ASPEED_PINCTRL_FUNC(SGPS1), | |
2296 | ASPEED_PINCTRL_FUNC(SGPS2), | |
2297 | ASPEED_PINCTRL_FUNC(SIOONCTRL), | |
2298 | ASPEED_PINCTRL_FUNC(SIOPBI), | |
2299 | ASPEED_PINCTRL_FUNC(SIOPBO), | |
2300 | ASPEED_PINCTRL_FUNC(SIOPWREQ), | |
2301 | ASPEED_PINCTRL_FUNC(SIOPWRGD), | |
2302 | ASPEED_PINCTRL_FUNC(SIOS3), | |
2303 | ASPEED_PINCTRL_FUNC(SIOS5), | |
2304 | ASPEED_PINCTRL_FUNC(SIOSCI), | |
56e57cb6 | 2305 | ASPEED_PINCTRL_FUNC(SPI1), |
f1337856 | 2306 | ASPEED_PINCTRL_FUNC(SPI1CS1), |
8eb37aff AJ |
2307 | ASPEED_PINCTRL_FUNC(SPI1DEBUG), |
2308 | ASPEED_PINCTRL_FUNC(SPI1PASSTHRU), | |
f1337856 AJ |
2309 | ASPEED_PINCTRL_FUNC(SPI2CK), |
2310 | ASPEED_PINCTRL_FUNC(SPI2CS0), | |
2311 | ASPEED_PINCTRL_FUNC(SPI2CS1), | |
2312 | ASPEED_PINCTRL_FUNC(SPI2MISO), | |
2313 | ASPEED_PINCTRL_FUNC(SPI2MOSI), | |
2314 | ASPEED_PINCTRL_FUNC(TIMER3), | |
56e57cb6 AJ |
2315 | ASPEED_PINCTRL_FUNC(TIMER4), |
2316 | ASPEED_PINCTRL_FUNC(TIMER5), | |
2317 | ASPEED_PINCTRL_FUNC(TIMER6), | |
2318 | ASPEED_PINCTRL_FUNC(TIMER7), | |
2319 | ASPEED_PINCTRL_FUNC(TIMER8), | |
f1337856 AJ |
2320 | ASPEED_PINCTRL_FUNC(TXD1), |
2321 | ASPEED_PINCTRL_FUNC(TXD2), | |
2322 | ASPEED_PINCTRL_FUNC(TXD3), | |
2323 | ASPEED_PINCTRL_FUNC(TXD4), | |
2324 | ASPEED_PINCTRL_FUNC(UART6), | |
9ffac449 AJ |
2325 | ASPEED_PINCTRL_FUNC(USB11BHID), |
2326 | ASPEED_PINCTRL_FUNC(USB2AD), | |
2327 | ASPEED_PINCTRL_FUNC(USB2AH), | |
2328 | ASPEED_PINCTRL_FUNC(USB2BD), | |
2329 | ASPEED_PINCTRL_FUNC(USB2BH), | |
f1337856 | 2330 | ASPEED_PINCTRL_FUNC(USBCKI), |
8eb37aff | 2331 | ASPEED_PINCTRL_FUNC(VGABIOSROM), |
f1337856 AJ |
2332 | ASPEED_PINCTRL_FUNC(VGAHS), |
2333 | ASPEED_PINCTRL_FUNC(VGAVS), | |
2334 | ASPEED_PINCTRL_FUNC(VPI24), | |
2335 | ASPEED_PINCTRL_FUNC(VPO), | |
2336 | ASPEED_PINCTRL_FUNC(WDTRST1), | |
2337 | ASPEED_PINCTRL_FUNC(WDTRST2), | |
56e57cb6 AJ |
2338 | }; |
2339 | ||
d0639d39 AJ |
2340 | static struct aspeed_pin_config aspeed_g5_configs[] = { |
2341 | /* GPIOA, GPIOQ */ | |
2342 | { PIN_CONFIG_BIAS_PULL_DOWN, { B14, B13 }, SCU8C, 16 }, | |
2343 | { PIN_CONFIG_BIAS_DISABLE, { B14, B13 }, SCU8C, 16 }, | |
2344 | { PIN_CONFIG_BIAS_PULL_DOWN, { A11, N20 }, SCU8C, 16 }, | |
2345 | { PIN_CONFIG_BIAS_DISABLE, { A11, N20 }, SCU8C, 16 }, | |
2346 | ||
2347 | /* GPIOB, GPIOR */ | |
2348 | { PIN_CONFIG_BIAS_PULL_DOWN, { K19, H20 }, SCU8C, 17 }, | |
2349 | { PIN_CONFIG_BIAS_DISABLE, { K19, H20 }, SCU8C, 17 }, | |
2350 | { PIN_CONFIG_BIAS_PULL_DOWN, { AA19, E10 }, SCU8C, 17 }, | |
2351 | { PIN_CONFIG_BIAS_DISABLE, { AA19, E10 }, SCU8C, 17 }, | |
2352 | ||
2353 | /* GPIOC, GPIOS*/ | |
2354 | { PIN_CONFIG_BIAS_PULL_DOWN, { C12, B11 }, SCU8C, 18 }, | |
2355 | { PIN_CONFIG_BIAS_DISABLE, { C12, B11 }, SCU8C, 18 }, | |
2356 | { PIN_CONFIG_BIAS_PULL_DOWN, { V20, AA20 }, SCU8C, 18 }, | |
2357 | { PIN_CONFIG_BIAS_DISABLE, { V20, AA20 }, SCU8C, 18 }, | |
2358 | ||
2359 | /* GPIOD, GPIOY */ | |
2360 | { PIN_CONFIG_BIAS_PULL_DOWN, { F19, C21 }, SCU8C, 19 }, | |
2361 | { PIN_CONFIG_BIAS_DISABLE, { F19, C21 }, SCU8C, 19 }, | |
2362 | { PIN_CONFIG_BIAS_PULL_DOWN, { R22, P20 }, SCU8C, 19 }, | |
2363 | { PIN_CONFIG_BIAS_DISABLE, { R22, P20 }, SCU8C, 19 }, | |
2364 | ||
2365 | /* GPIOE, GPIOZ */ | |
2366 | { PIN_CONFIG_BIAS_PULL_DOWN, { B20, B19 }, SCU8C, 20 }, | |
2367 | { PIN_CONFIG_BIAS_DISABLE, { B20, B19 }, SCU8C, 20 }, | |
2368 | { PIN_CONFIG_BIAS_PULL_DOWN, { Y20, W21 }, SCU8C, 20 }, | |
2369 | { PIN_CONFIG_BIAS_DISABLE, { Y20, W21 }, SCU8C, 20 }, | |
2370 | ||
2371 | /* GPIOF, GPIOAA */ | |
2372 | { PIN_CONFIG_BIAS_PULL_DOWN, { J19, H18 }, SCU8C, 21 }, | |
2373 | { PIN_CONFIG_BIAS_DISABLE, { J19, H18 }, SCU8C, 21 }, | |
2374 | { PIN_CONFIG_BIAS_PULL_DOWN, { Y21, P19 }, SCU8C, 21 }, | |
2375 | { PIN_CONFIG_BIAS_DISABLE, { Y21, P19 }, SCU8C, 21 }, | |
2376 | ||
2377 | /* GPIOG, GPIOAB */ | |
2378 | { PIN_CONFIG_BIAS_PULL_DOWN, { A19, E14 }, SCU8C, 22 }, | |
2379 | { PIN_CONFIG_BIAS_DISABLE, { A19, E14 }, SCU8C, 22 }, | |
2380 | { PIN_CONFIG_BIAS_PULL_DOWN, { N19, R20 }, SCU8C, 22 }, | |
2381 | { PIN_CONFIG_BIAS_DISABLE, { N19, R20 }, SCU8C, 22 }, | |
2382 | ||
2383 | /* GPIOH, GPIOAC */ | |
2384 | { PIN_CONFIG_BIAS_PULL_DOWN, { A18, D18 }, SCU8C, 23 }, | |
2385 | { PIN_CONFIG_BIAS_DISABLE, { A18, D18 }, SCU8C, 23 }, | |
2386 | { PIN_CONFIG_BIAS_PULL_DOWN, { G21, G22 }, SCU8C, 23 }, | |
2387 | { PIN_CONFIG_BIAS_DISABLE, { G21, G22 }, SCU8C, 23 }, | |
2388 | ||
2389 | /* GPIOs [I, P] */ | |
2390 | { PIN_CONFIG_BIAS_PULL_DOWN, { C18, A15 }, SCU8C, 24 }, | |
2391 | { PIN_CONFIG_BIAS_DISABLE, { C18, A15 }, SCU8C, 24 }, | |
2392 | { PIN_CONFIG_BIAS_PULL_DOWN, { R2, T3 }, SCU8C, 25 }, | |
2393 | { PIN_CONFIG_BIAS_DISABLE, { R2, T3 }, SCU8C, 25 }, | |
2394 | { PIN_CONFIG_BIAS_PULL_DOWN, { L3, R1 }, SCU8C, 26 }, | |
2395 | { PIN_CONFIG_BIAS_DISABLE, { L3, R1 }, SCU8C, 26 }, | |
2396 | { PIN_CONFIG_BIAS_PULL_DOWN, { T2, W1 }, SCU8C, 27 }, | |
2397 | { PIN_CONFIG_BIAS_DISABLE, { T2, W1 }, SCU8C, 27 }, | |
2398 | { PIN_CONFIG_BIAS_PULL_DOWN, { Y1, T5 }, SCU8C, 28 }, | |
2399 | { PIN_CONFIG_BIAS_DISABLE, { Y1, T5 }, SCU8C, 28 }, | |
2400 | { PIN_CONFIG_BIAS_PULL_DOWN, { V2, T4 }, SCU8C, 29 }, | |
2401 | { PIN_CONFIG_BIAS_DISABLE, { V2, T4 }, SCU8C, 29 }, | |
2402 | { PIN_CONFIG_BIAS_PULL_DOWN, { U5, W4 }, SCU8C, 30 }, | |
2403 | { PIN_CONFIG_BIAS_DISABLE, { U5, W4 }, SCU8C, 30 }, | |
2404 | { PIN_CONFIG_BIAS_PULL_DOWN, { V4, V6 }, SCU8C, 31 }, | |
2405 | { PIN_CONFIG_BIAS_DISABLE, { V4, V6 }, SCU8C, 31 }, | |
2406 | ||
2407 | /* GPIOs T[0-5] (RGMII1 Tx pins) */ | |
2408 | { PIN_CONFIG_DRIVE_STRENGTH, { B5, B5 }, SCU90, 8 }, | |
2409 | { PIN_CONFIG_DRIVE_STRENGTH, { E9, A5 }, SCU90, 9 }, | |
2410 | { PIN_CONFIG_BIAS_PULL_DOWN, { B5, D7 }, SCU90, 12 }, | |
2411 | { PIN_CONFIG_BIAS_DISABLE, { B5, D7 }, SCU90, 12 }, | |
2412 | ||
2413 | /* GPIOs T[6-7], U[0-3] (RGMII2 TX pins) */ | |
2414 | { PIN_CONFIG_DRIVE_STRENGTH, { B2, B2 }, SCU90, 10 }, | |
2415 | { PIN_CONFIG_DRIVE_STRENGTH, { B1, B3 }, SCU90, 11 }, | |
2416 | { PIN_CONFIG_BIAS_PULL_DOWN, { B2, D4 }, SCU90, 14 }, | |
2417 | { PIN_CONFIG_BIAS_DISABLE, { B2, D4 }, SCU90, 14 }, | |
2418 | ||
2419 | /* GPIOs U[4-7], V[0-1] (RGMII1 Rx pins) */ | |
2420 | { PIN_CONFIG_BIAS_PULL_DOWN, { B4, C4 }, SCU90, 13 }, | |
2421 | { PIN_CONFIG_BIAS_DISABLE, { B4, C4 }, SCU90, 13 }, | |
2422 | ||
2423 | /* GPIOs V[2-7] (RGMII2 Rx pins) */ | |
2424 | { PIN_CONFIG_BIAS_PULL_DOWN, { C2, E6 }, SCU90, 15 }, | |
2425 | { PIN_CONFIG_BIAS_DISABLE, { C2, E6 }, SCU90, 15 }, | |
2426 | ||
2427 | /* ADC pull-downs (SCUA8[19:4]) */ | |
2428 | { PIN_CONFIG_BIAS_PULL_DOWN, { F4, F4 }, SCUA8, 4 }, | |
2429 | { PIN_CONFIG_BIAS_DISABLE, { F4, F4 }, SCUA8, 4 }, | |
2430 | { PIN_CONFIG_BIAS_PULL_DOWN, { F5, F5 }, SCUA8, 5 }, | |
2431 | { PIN_CONFIG_BIAS_DISABLE, { F5, F5 }, SCUA8, 5 }, | |
2432 | { PIN_CONFIG_BIAS_PULL_DOWN, { E2, E2 }, SCUA8, 6 }, | |
2433 | { PIN_CONFIG_BIAS_DISABLE, { E2, E2 }, SCUA8, 6 }, | |
2434 | { PIN_CONFIG_BIAS_PULL_DOWN, { E1, E1 }, SCUA8, 7 }, | |
2435 | { PIN_CONFIG_BIAS_DISABLE, { E1, E1 }, SCUA8, 7 }, | |
2436 | { PIN_CONFIG_BIAS_PULL_DOWN, { F3, F3 }, SCUA8, 8 }, | |
2437 | { PIN_CONFIG_BIAS_DISABLE, { F3, F3 }, SCUA8, 8 }, | |
2438 | { PIN_CONFIG_BIAS_PULL_DOWN, { E3, E3 }, SCUA8, 9 }, | |
2439 | { PIN_CONFIG_BIAS_DISABLE, { E3, E3 }, SCUA8, 9 }, | |
2440 | { PIN_CONFIG_BIAS_PULL_DOWN, { G5, G5 }, SCUA8, 10 }, | |
2441 | { PIN_CONFIG_BIAS_DISABLE, { G5, G5 }, SCUA8, 10 }, | |
2442 | { PIN_CONFIG_BIAS_PULL_DOWN, { G4, G4 }, SCUA8, 11 }, | |
2443 | { PIN_CONFIG_BIAS_DISABLE, { G4, G4 }, SCUA8, 11 }, | |
2444 | { PIN_CONFIG_BIAS_PULL_DOWN, { F2, F2 }, SCUA8, 12 }, | |
2445 | { PIN_CONFIG_BIAS_DISABLE, { F2, F2 }, SCUA8, 12 }, | |
2446 | { PIN_CONFIG_BIAS_PULL_DOWN, { G3, G3 }, SCUA8, 13 }, | |
2447 | { PIN_CONFIG_BIAS_DISABLE, { G3, G3 }, SCUA8, 13 }, | |
2448 | { PIN_CONFIG_BIAS_PULL_DOWN, { G2, G2 }, SCUA8, 14 }, | |
2449 | { PIN_CONFIG_BIAS_DISABLE, { G2, G2 }, SCUA8, 14 }, | |
2450 | { PIN_CONFIG_BIAS_PULL_DOWN, { F1, F1 }, SCUA8, 15 }, | |
2451 | { PIN_CONFIG_BIAS_DISABLE, { F1, F1 }, SCUA8, 15 }, | |
2452 | { PIN_CONFIG_BIAS_PULL_DOWN, { H5, H5 }, SCUA8, 16 }, | |
2453 | { PIN_CONFIG_BIAS_DISABLE, { H5, H5 }, SCUA8, 16 }, | |
2454 | { PIN_CONFIG_BIAS_PULL_DOWN, { G1, G1 }, SCUA8, 17 }, | |
2455 | { PIN_CONFIG_BIAS_DISABLE, { G1, G1 }, SCUA8, 17 }, | |
2456 | { PIN_CONFIG_BIAS_PULL_DOWN, { H3, H3 }, SCUA8, 18 }, | |
2457 | { PIN_CONFIG_BIAS_DISABLE, { H3, H3 }, SCUA8, 18 }, | |
2458 | { PIN_CONFIG_BIAS_PULL_DOWN, { H4, H4 }, SCUA8, 19 }, | |
2459 | { PIN_CONFIG_BIAS_DISABLE, { H4, H4 }, SCUA8, 19 }, | |
2460 | ||
2461 | /* | |
2462 | * Debounce settings for GPIOs D and E passthrough mode are in | |
2463 | * SCUA8[27:20] and so are managed by pinctrl. Normal GPIO debounce for | |
2464 | * banks D and E is handled by the GPIO driver - GPIO passthrough is | |
2465 | * treated like any other non-GPIO mux function. There is a catch | |
2466 | * however, in that the debounce period is configured in the GPIO | |
2467 | * controller. Due to this tangle between GPIO and pinctrl we don't yet | |
2468 | * fully support pass-through debounce. | |
2469 | */ | |
2470 | { PIN_CONFIG_INPUT_DEBOUNCE, { F19, E21 }, SCUA8, 20 }, | |
2471 | { PIN_CONFIG_INPUT_DEBOUNCE, { F20, D20 }, SCUA8, 21 }, | |
2472 | { PIN_CONFIG_INPUT_DEBOUNCE, { D21, E20 }, SCUA8, 22 }, | |
2473 | { PIN_CONFIG_INPUT_DEBOUNCE, { G18, C21 }, SCUA8, 23 }, | |
2474 | { PIN_CONFIG_INPUT_DEBOUNCE, { B20, C20 }, SCUA8, 24 }, | |
2475 | { PIN_CONFIG_INPUT_DEBOUNCE, { F18, F17 }, SCUA8, 25 }, | |
2476 | { PIN_CONFIG_INPUT_DEBOUNCE, { E18, D19 }, SCUA8, 26 }, | |
2477 | { PIN_CONFIG_INPUT_DEBOUNCE, { A20, B19 }, SCUA8, 27 }, | |
2478 | }; | |
2479 | ||
56e57cb6 AJ |
2480 | static struct aspeed_pinctrl_data aspeed_g5_pinctrl_data = { |
2481 | .pins = aspeed_g5_pins, | |
2482 | .npins = ARRAY_SIZE(aspeed_g5_pins), | |
2483 | .groups = aspeed_g5_groups, | |
2484 | .ngroups = ARRAY_SIZE(aspeed_g5_groups), | |
2485 | .functions = aspeed_g5_functions, | |
2486 | .nfunctions = ARRAY_SIZE(aspeed_g5_functions), | |
d0639d39 AJ |
2487 | .configs = aspeed_g5_configs, |
2488 | .nconfigs = ARRAY_SIZE(aspeed_g5_configs), | |
56e57cb6 AJ |
2489 | }; |
2490 | ||
0192fffe | 2491 | static const struct pinmux_ops aspeed_g5_pinmux_ops = { |
56e57cb6 AJ |
2492 | .get_functions_count = aspeed_pinmux_get_fn_count, |
2493 | .get_function_name = aspeed_pinmux_get_fn_name, | |
2494 | .get_function_groups = aspeed_pinmux_get_fn_groups, | |
2495 | .set_mux = aspeed_pinmux_set_mux, | |
2496 | .gpio_request_enable = aspeed_gpio_request_enable, | |
2497 | .strict = true, | |
2498 | }; | |
2499 | ||
0192fffe | 2500 | static const struct pinctrl_ops aspeed_g5_pinctrl_ops = { |
56e57cb6 AJ |
2501 | .get_groups_count = aspeed_pinctrl_get_groups_count, |
2502 | .get_group_name = aspeed_pinctrl_get_group_name, | |
2503 | .get_group_pins = aspeed_pinctrl_get_group_pins, | |
2504 | .pin_dbg_show = aspeed_pinctrl_pin_dbg_show, | |
d0639d39 | 2505 | .dt_node_to_map = pinconf_generic_dt_node_to_map_all, |
56e57cb6 AJ |
2506 | .dt_free_map = pinctrl_utils_free_map, |
2507 | }; | |
2508 | ||
0192fffe | 2509 | static const struct pinconf_ops aspeed_g5_conf_ops = { |
d0639d39 AJ |
2510 | .is_generic = true, |
2511 | .pin_config_get = aspeed_pin_config_get, | |
2512 | .pin_config_set = aspeed_pin_config_set, | |
2513 | .pin_config_group_get = aspeed_pin_config_group_get, | |
2514 | .pin_config_group_set = aspeed_pin_config_group_set, | |
2515 | }; | |
2516 | ||
56e57cb6 AJ |
2517 | static struct pinctrl_desc aspeed_g5_pinctrl_desc = { |
2518 | .name = "aspeed-g5-pinctrl", | |
2519 | .pins = aspeed_g5_pins, | |
2520 | .npins = ARRAY_SIZE(aspeed_g5_pins), | |
2521 | .pctlops = &aspeed_g5_pinctrl_ops, | |
2522 | .pmxops = &aspeed_g5_pinmux_ops, | |
d0639d39 | 2523 | .confops = &aspeed_g5_conf_ops, |
56e57cb6 AJ |
2524 | }; |
2525 | ||
2526 | static int aspeed_g5_pinctrl_probe(struct platform_device *pdev) | |
2527 | { | |
2528 | int i; | |
7d29ed88 AJ |
2529 | struct regmap *map; |
2530 | struct device_node *node; | |
56e57cb6 AJ |
2531 | |
2532 | for (i = 0; i < ARRAY_SIZE(aspeed_g5_pins); i++) | |
2533 | aspeed_g5_pins[i].number = i; | |
2534 | ||
7d29ed88 AJ |
2535 | node = of_parse_phandle(pdev->dev.of_node, "aspeed,external-nodes", 0); |
2536 | map = syscon_node_to_regmap(node); | |
2537 | of_node_put(node); | |
2538 | if (IS_ERR(map)) { | |
2539 | dev_warn(&pdev->dev, "No GFX phandle found, some mux configurations may fail\n"); | |
2540 | map = NULL; | |
2541 | } | |
2542 | aspeed_g5_pinctrl_data.maps[ASPEED_IP_GFX] = map; | |
2543 | ||
2544 | node = of_parse_phandle(pdev->dev.of_node, "aspeed,external-nodes", 1); | |
2545 | if (node) { | |
2546 | map = syscon_node_to_regmap(node->parent); | |
2547 | if (IS_ERR(map)) { | |
2548 | dev_warn(&pdev->dev, "LHC parent is not a syscon, some mux configurations may fail\n"); | |
2549 | map = NULL; | |
2550 | } | |
2551 | } else { | |
2552 | dev_warn(&pdev->dev, "No LHC phandle found, some mux configurations may fail\n"); | |
2553 | map = NULL; | |
2554 | } | |
2555 | of_node_put(node); | |
2556 | aspeed_g5_pinctrl_data.maps[ASPEED_IP_LPC] = map; | |
2557 | ||
56e57cb6 AJ |
2558 | return aspeed_pinctrl_probe(pdev, &aspeed_g5_pinctrl_desc, |
2559 | &aspeed_g5_pinctrl_data); | |
2560 | } | |
2561 | ||
2562 | static const struct of_device_id aspeed_g5_pinctrl_of_match[] = { | |
2563 | { .compatible = "aspeed,ast2500-pinctrl", }, | |
2564 | { .compatible = "aspeed,g5-pinctrl", }, | |
2565 | { }, | |
2566 | }; | |
2567 | ||
2568 | static struct platform_driver aspeed_g5_pinctrl_driver = { | |
2569 | .probe = aspeed_g5_pinctrl_probe, | |
2570 | .driver = { | |
2571 | .name = "aspeed-g5-pinctrl", | |
2572 | .of_match_table = aspeed_g5_pinctrl_of_match, | |
2573 | }, | |
2574 | }; | |
2575 | ||
2576 | static int aspeed_g5_pinctrl_init(void) | |
2577 | { | |
2578 | return platform_driver_register(&aspeed_g5_pinctrl_driver); | |
2579 | } | |
2580 | ||
2581 | arch_initcall(aspeed_g5_pinctrl_init); |