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[mirror_ubuntu-artful-kernel.git] / drivers / pinctrl / bcm / pinctrl-bcm2835.c
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e1b2dc70
SA		 1/*
2 * Driver for Broadcom BCM2835 GPIO unit (pinctrl + GPIO)
3 *
4 * Copyright (C) 2012 Chris Boot, Simon Arlott, Stephen Warren
5 *
6 * This driver is inspired by:
7 * pinctrl-nomadik.c, please see original file for copyright information
8 * pinctrl-tegra.c, please see original file for copyright information
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 */
20
21#include <linux/bitmap.h>
22#include <linux/bug.h>
23#include <linux/delay.h>
24#include <linux/device.h>
25#include <linux/err.h>
26#include <linux/gpio.h>
27#include <linux/interrupt.h>
28#include <linux/io.h>
29#include <linux/irq.h>
30#include <linux/irqdesc.h>
31#include <linux/irqdomain.h>
e1b2dc70
SA		 32#include <linux/module.h>
33#include <linux/of_address.h>
34#include <linux/of.h>
35#include <linux/of_irq.h>
36#include <linux/pinctrl/consumer.h>
37#include <linux/pinctrl/machine.h>
38#include <linux/pinctrl/pinconf.h>
39#include <linux/pinctrl/pinctrl.h>
40#include <linux/pinctrl/pinmux.h>
41#include <linux/platform_device.h>
42#include <linux/seq_file.h>
43#include <linux/slab.h>
44#include <linux/spinlock.h>
45#include <linux/types.h>
46
47#define MODULE_NAME "pinctrl-bcm2835"
48#define BCM2835_NUM_GPIOS 54
49#define BCM2835_NUM_BANKS 2
50
51#define BCM2835_PIN_BITMAP_SZ \
52 DIV_ROUND_UP(BCM2835_NUM_GPIOS, sizeof(unsigned long) * 8)
53
54/* GPIO register offsets */
55#define GPFSEL0 0x0 /* Function Select */
56#define GPSET0 0x1c /* Pin Output Set */
57#define GPCLR0 0x28 /* Pin Output Clear */
58#define GPLEV0 0x34 /* Pin Level */
59#define GPEDS0 0x40 /* Pin Event Detect Status */
60#define GPREN0 0x4c /* Pin Rising Edge Detect Enable */
61#define GPFEN0 0x58 /* Pin Falling Edge Detect Enable */
62#define GPHEN0 0x64 /* Pin High Detect Enable */
63#define GPLEN0 0x70 /* Pin Low Detect Enable */
64#define GPAREN0 0x7c /* Pin Async Rising Edge Detect */
65#define GPAFEN0 0x88 /* Pin Async Falling Edge Detect */
66#define GPPUD 0x94 /* Pin Pull-up/down Enable */
67#define GPPUDCLK0 0x98 /* Pin Pull-up/down Enable Clock */
68
69#define FSEL_REG(p) (GPFSEL0 + (((p) / 10) * 4))
70#define FSEL_SHIFT(p) (((p) % 10) * 3)
71#define GPIO_REG_OFFSET(p) ((p) / 32)
72#define GPIO_REG_SHIFT(p) ((p) % 32)
73
74enum bcm2835_pinconf_param {
75 /* argument: bcm2835_pinconf_pull */
76 BCM2835_PINCONF_PARAM_PULL,
77};
78
79enum bcm2835_pinconf_pull {
80 BCM2835_PINCONFIG_PULL_NONE,
81 BCM2835_PINCONFIG_PULL_DOWN,
82 BCM2835_PINCONFIG_PULL_UP,
83};
84
85#define BCM2835_PINCONF_PACK(_param_, _arg_) ((_param_) << 16 | (_arg_))
86#define BCM2835_PINCONF_UNPACK_PARAM(_conf_) ((_conf_) >> 16)
87#define BCM2835_PINCONF_UNPACK_ARG(_conf_) ((_conf_) & 0xffff)
88
89struct bcm2835_gpio_irqdata {
90 struct bcm2835_pinctrl *pc;
91 int bank;
92};
93
94struct bcm2835_pinctrl {
95 struct device *dev;
96 void __iomem *base;
97 int irq[BCM2835_NUM_BANKS];
98
99 /* note: locking assumes each bank will have its own unsigned long */
100 unsigned long enabled_irq_map[BCM2835_NUM_BANKS];
101 unsigned int irq_type[BCM2835_NUM_GPIOS];
102
103 struct pinctrl_dev *pctl_dev;
104 struct irq_domain *irq_domain;
105 struct gpio_chip gpio_chip;
106 struct pinctrl_gpio_range gpio_range;
107
108 struct bcm2835_gpio_irqdata irq_data[BCM2835_NUM_BANKS];
109 spinlock_t irq_lock[BCM2835_NUM_BANKS];
110};
111
112static struct lock_class_key gpio_lock_class;
113
114/* pins are just named GPIO0..GPIO53 */
115#define BCM2835_GPIO_PIN(a) PINCTRL_PIN(a, "gpio" #a)
e8ed912e 116static struct pinctrl_pin_desc bcm2835_gpio_pins[] = {
e1b2dc70
SA		 117 BCM2835_GPIO_PIN(0),
118 BCM2835_GPIO_PIN(1),
119 BCM2835_GPIO_PIN(2),
120 BCM2835_GPIO_PIN(3),
121 BCM2835_GPIO_PIN(4),
122 BCM2835_GPIO_PIN(5),
123 BCM2835_GPIO_PIN(6),
124 BCM2835_GPIO_PIN(7),
125 BCM2835_GPIO_PIN(8),
126 BCM2835_GPIO_PIN(9),
127 BCM2835_GPIO_PIN(10),
128 BCM2835_GPIO_PIN(11),
129 BCM2835_GPIO_PIN(12),
130 BCM2835_GPIO_PIN(13),
131 BCM2835_GPIO_PIN(14),
132 BCM2835_GPIO_PIN(15),
133 BCM2835_GPIO_PIN(16),
134 BCM2835_GPIO_PIN(17),
135 BCM2835_GPIO_PIN(18),
136 BCM2835_GPIO_PIN(19),
137 BCM2835_GPIO_PIN(20),
138 BCM2835_GPIO_PIN(21),
139 BCM2835_GPIO_PIN(22),
140 BCM2835_GPIO_PIN(23),
141 BCM2835_GPIO_PIN(24),
142 BCM2835_GPIO_PIN(25),
143 BCM2835_GPIO_PIN(26),
144 BCM2835_GPIO_PIN(27),
145 BCM2835_GPIO_PIN(28),
146 BCM2835_GPIO_PIN(29),
147 BCM2835_GPIO_PIN(30),
148 BCM2835_GPIO_PIN(31),
149 BCM2835_GPIO_PIN(32),
150 BCM2835_GPIO_PIN(33),
151 BCM2835_GPIO_PIN(34),
152 BCM2835_GPIO_PIN(35),
153 BCM2835_GPIO_PIN(36),
154 BCM2835_GPIO_PIN(37),
155 BCM2835_GPIO_PIN(38),
156 BCM2835_GPIO_PIN(39),
157 BCM2835_GPIO_PIN(40),
158 BCM2835_GPIO_PIN(41),
159 BCM2835_GPIO_PIN(42),
160 BCM2835_GPIO_PIN(43),
161 BCM2835_GPIO_PIN(44),
162 BCM2835_GPIO_PIN(45),
163 BCM2835_GPIO_PIN(46),
164 BCM2835_GPIO_PIN(47),
165 BCM2835_GPIO_PIN(48),
166 BCM2835_GPIO_PIN(49),
167 BCM2835_GPIO_PIN(50),
168 BCM2835_GPIO_PIN(51),
169 BCM2835_GPIO_PIN(52),
170 BCM2835_GPIO_PIN(53),
171};
172
173/* one pin per group */
174static const char * const bcm2835_gpio_groups[] = {
175 "gpio0",
176 "gpio1",
177 "gpio2",
178 "gpio3",
179 "gpio4",
180 "gpio5",
181 "gpio6",
182 "gpio7",
183 "gpio8",
184 "gpio9",
185 "gpio10",
186 "gpio11",
187 "gpio12",
188 "gpio13",
189 "gpio14",
190 "gpio15",
191 "gpio16",
192 "gpio17",
193 "gpio18",
194 "gpio19",
195 "gpio20",
196 "gpio21",
197 "gpio22",
198 "gpio23",
199 "gpio24",
200 "gpio25",
201 "gpio26",
202 "gpio27",
203 "gpio28",
204 "gpio29",
205 "gpio30",
206 "gpio31",
207 "gpio32",
208 "gpio33",
209 "gpio34",
210 "gpio35",
211 "gpio36",
212 "gpio37",
213 "gpio38",
214 "gpio39",
215 "gpio40",
216 "gpio41",
217 "gpio42",
218 "gpio43",
219 "gpio44",
220 "gpio45",
221 "gpio46",
222 "gpio47",
223 "gpio48",
224 "gpio49",
225 "gpio50",
226 "gpio51",
227 "gpio52",
228 "gpio53",
229};
230
231enum bcm2835_fsel {
232 BCM2835_FSEL_GPIO_IN = 0,
233 BCM2835_FSEL_GPIO_OUT = 1,
234 BCM2835_FSEL_ALT0 = 4,
235 BCM2835_FSEL_ALT1 = 5,
236 BCM2835_FSEL_ALT2 = 6,
237 BCM2835_FSEL_ALT3 = 7,
238 BCM2835_FSEL_ALT4 = 3,
239 BCM2835_FSEL_ALT5 = 2,
240 BCM2835_FSEL_COUNT = 8,
241 BCM2835_FSEL_MASK = 0x7,
242};
243
244static const char * const bcm2835_functions[BCM2835_FSEL_COUNT] = {
245 [BCM2835_FSEL_GPIO_IN] = "gpio_in",
246 [BCM2835_FSEL_GPIO_OUT] = "gpio_out",
247 [BCM2835_FSEL_ALT0] = "alt0",
248 [BCM2835_FSEL_ALT1] = "alt1",
249 [BCM2835_FSEL_ALT2] = "alt2",
250 [BCM2835_FSEL_ALT3] = "alt3",
251 [BCM2835_FSEL_ALT4] = "alt4",
252 [BCM2835_FSEL_ALT5] = "alt5",
253};
254
255static const char * const irq_type_names[] = {
256 [IRQ_TYPE_NONE] = "none",
257 [IRQ_TYPE_EDGE_RISING] = "edge-rising",
258 [IRQ_TYPE_EDGE_FALLING] = "edge-falling",
259 [IRQ_TYPE_EDGE_BOTH] = "edge-both",
260 [IRQ_TYPE_LEVEL_HIGH] = "level-high",
261 [IRQ_TYPE_LEVEL_LOW] = "level-low",
262};
263
264static inline u32 bcm2835_gpio_rd(struct bcm2835_pinctrl *pc, unsigned reg)
265{
266 return readl(pc->base + reg);
267}
268
269static inline void bcm2835_gpio_wr(struct bcm2835_pinctrl *pc, unsigned reg,
270 u32 val)
271{
272 writel(val, pc->base + reg);
273}
274
275static inline int bcm2835_gpio_get_bit(struct bcm2835_pinctrl *pc, unsigned reg,
276 unsigned bit)
277{
278 reg += GPIO_REG_OFFSET(bit) * 4;
279 return (bcm2835_gpio_rd(pc, reg) >> GPIO_REG_SHIFT(bit)) & 1;
280}
281
282/* note NOT a read/modify/write cycle */
283static inline void bcm2835_gpio_set_bit(struct bcm2835_pinctrl *pc,
284 unsigned reg, unsigned bit)
285{
286 reg += GPIO_REG_OFFSET(bit) * 4;
287 bcm2835_gpio_wr(pc, reg, BIT(GPIO_REG_SHIFT(bit)));
288}
289
290static inline enum bcm2835_fsel bcm2835_pinctrl_fsel_get(
291 struct bcm2835_pinctrl *pc, unsigned pin)
292{
293 u32 val = bcm2835_gpio_rd(pc, FSEL_REG(pin));
294 enum bcm2835_fsel status = (val >> FSEL_SHIFT(pin)) & BCM2835_FSEL_MASK;
295
296 dev_dbg(pc->dev, "get %08x (%u => %s)\n", val, pin,
297 bcm2835_functions[status]);
298
299 return status;
300}
301
302static inline void bcm2835_pinctrl_fsel_set(
303 struct bcm2835_pinctrl *pc, unsigned pin,
304 enum bcm2835_fsel fsel)
305{
306 u32 val = bcm2835_gpio_rd(pc, FSEL_REG(pin));
307 enum bcm2835_fsel cur = (val >> FSEL_SHIFT(pin)) & BCM2835_FSEL_MASK;
308
309 dev_dbg(pc->dev, "read %08x (%u => %s)\n", val, pin,
310 bcm2835_functions[cur]);
311
312 if (cur == fsel)
313 return;
314
315 if (cur != BCM2835_FSEL_GPIO_IN && fsel != BCM2835_FSEL_GPIO_IN) {
316 /* always transition through GPIO_IN */
317 val &= ~(BCM2835_FSEL_MASK << FSEL_SHIFT(pin));
318 val |= BCM2835_FSEL_GPIO_IN << FSEL_SHIFT(pin);
319
320 dev_dbg(pc->dev, "trans %08x (%u <= %s)\n", val, pin,
321 bcm2835_functions[BCM2835_FSEL_GPIO_IN]);
322 bcm2835_gpio_wr(pc, FSEL_REG(pin), val);
323 }
324
325 val &= ~(BCM2835_FSEL_MASK << FSEL_SHIFT(pin));
326 val |= fsel << FSEL_SHIFT(pin);
327
328 dev_dbg(pc->dev, "write %08x (%u <= %s)\n", val, pin,
329 bcm2835_functions[fsel]);
330 bcm2835_gpio_wr(pc, FSEL_REG(pin), val);
331}
332
e1b2dc70
SA		 333static int bcm2835_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
334{
335 return pinctrl_gpio_direction_input(chip->base + offset);
336}
337
338static int bcm2835_gpio_get(struct gpio_chip *chip, unsigned offset)
339{
340 struct bcm2835_pinctrl *pc = dev_get_drvdata(chip->dev);
341
342 return bcm2835_gpio_get_bit(pc, GPLEV0, offset);
343}
344
345static int bcm2835_gpio_direction_output(struct gpio_chip *chip,
346 unsigned offset, int value)
347{
348 return pinctrl_gpio_direction_output(chip->base + offset);
349}
350
351static void bcm2835_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
352{
353 struct bcm2835_pinctrl *pc = dev_get_drvdata(chip->dev);
354
355 bcm2835_gpio_set_bit(pc, value ? GPSET0 : GPCLR0, offset);
356}
357
358static int bcm2835_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
359{
360 struct bcm2835_pinctrl *pc = dev_get_drvdata(chip->dev);
361
362 return irq_linear_revmap(pc->irq_domain, offset);
363}
364
84db00ba 365static struct gpio_chip bcm2835_gpio_chip = {
e1b2dc70
SA		 366 .label = MODULE_NAME,
367 .owner = THIS_MODULE,
98c85d58
JG		 368 .request = gpiochip_generic_request,
369 .free = gpiochip_generic_free,
e1b2dc70
SA		 370 .direction_input = bcm2835_gpio_direction_input,
371 .direction_output = bcm2835_gpio_direction_output,
372 .get = bcm2835_gpio_get,
373 .set = bcm2835_gpio_set,
374 .to_irq = bcm2835_gpio_to_irq,
375 .base = -1,
376 .ngpio = BCM2835_NUM_GPIOS,
9fb1f39e 377 .can_sleep = false,
e1b2dc70
SA		 378};
379
380static irqreturn_t bcm2835_gpio_irq_handler(int irq, void *dev_id)
381{
382 struct bcm2835_gpio_irqdata *irqdata = dev_id;
383 struct bcm2835_pinctrl *pc = irqdata->pc;
384 int bank = irqdata->bank;
385 unsigned long events;
386 unsigned offset;
387 unsigned gpio;
388 unsigned int type;
389
390 events = bcm2835_gpio_rd(pc, GPEDS0 + bank * 4);
391 events &= pc->enabled_irq_map[bank];
392 for_each_set_bit(offset, &events, 32) {
393 gpio = (32 * bank) + offset;
394 type = pc->irq_type[gpio];
395
e1b2dc70 396 generic_handle_irq(irq_linear_revmap(pc->irq_domain, gpio));
e1b2dc70
SA		 397 }
398 return events ? IRQ_HANDLED : IRQ_NONE;
399}
400
401static inline void __bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc,
402 unsigned reg, unsigned offset, bool enable)
403{
404 u32 value;
405 reg += GPIO_REG_OFFSET(offset) * 4;
406 value = bcm2835_gpio_rd(pc, reg);
407 if (enable)
408 value |= BIT(GPIO_REG_SHIFT(offset));
409 else
410 value &= ~(BIT(GPIO_REG_SHIFT(offset)));
411 bcm2835_gpio_wr(pc, reg, value);
412}
413
414/* fast path for IRQ handler */
415static void bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc,
416 unsigned offset, bool enable)
417{
418 switch (pc->irq_type[offset]) {
419 case IRQ_TYPE_EDGE_RISING:
420 __bcm2835_gpio_irq_config(pc, GPREN0, offset, enable);
421 break;
422
423 case IRQ_TYPE_EDGE_FALLING:
424 __bcm2835_gpio_irq_config(pc, GPFEN0, offset, enable);
425 break;
426
427 case IRQ_TYPE_EDGE_BOTH:
428 __bcm2835_gpio_irq_config(pc, GPREN0, offset, enable);
429 __bcm2835_gpio_irq_config(pc, GPFEN0, offset, enable);
430 break;
431
432 case IRQ_TYPE_LEVEL_HIGH:
433 __bcm2835_gpio_irq_config(pc, GPHEN0, offset, enable);
434 break;
435
436 case IRQ_TYPE_LEVEL_LOW:
437 __bcm2835_gpio_irq_config(pc, GPLEN0, offset, enable);
438 break;
439 }
440}
441
442static void bcm2835_gpio_irq_enable(struct irq_data *data)
443{
444 struct bcm2835_pinctrl *pc = irq_data_get_irq_chip_data(data);
445 unsigned gpio = irqd_to_hwirq(data);
446 unsigned offset = GPIO_REG_SHIFT(gpio);
447 unsigned bank = GPIO_REG_OFFSET(gpio);
448 unsigned long flags;
449
450 spin_lock_irqsave(&pc->irq_lock[bank], flags);
451 set_bit(offset, &pc->enabled_irq_map[bank]);
452 bcm2835_gpio_irq_config(pc, gpio, true);
453 spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
454}
455
456static void bcm2835_gpio_irq_disable(struct irq_data *data)
457{
458 struct bcm2835_pinctrl *pc = irq_data_get_irq_chip_data(data);
459 unsigned gpio = irqd_to_hwirq(data);
460 unsigned offset = GPIO_REG_SHIFT(gpio);
461 unsigned bank = GPIO_REG_OFFSET(gpio);
462 unsigned long flags;
463
464 spin_lock_irqsave(&pc->irq_lock[bank], flags);
465 bcm2835_gpio_irq_config(pc, gpio, false);
714b1dd8
JB		 466 /* Clear events that were latched prior to clearing event sources */
467 bcm2835_gpio_set_bit(pc, GPEDS0, gpio);
e1b2dc70
SA		 468 clear_bit(offset, &pc->enabled_irq_map[bank]);
469 spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
470}
471
472static int __bcm2835_gpio_irq_set_type_disabled(struct bcm2835_pinctrl *pc,
473 unsigned offset, unsigned int type)
474{
475 switch (type) {
476 case IRQ_TYPE_NONE:
477 case IRQ_TYPE_EDGE_RISING:
478 case IRQ_TYPE_EDGE_FALLING:
479 case IRQ_TYPE_EDGE_BOTH:
480 case IRQ_TYPE_LEVEL_HIGH:
481 case IRQ_TYPE_LEVEL_LOW:
482 pc->irq_type[offset] = type;
483 break;
484
485 default:
486 return -EINVAL;
487 }
488 return 0;
489}
490
491/* slower path for reconfiguring IRQ type */
492static int __bcm2835_gpio_irq_set_type_enabled(struct bcm2835_pinctrl *pc,
493 unsigned offset, unsigned int type)
494{
495 switch (type) {
496 case IRQ_TYPE_NONE:
497 if (pc->irq_type[offset] != type) {
498 bcm2835_gpio_irq_config(pc, offset, false);
499 pc->irq_type[offset] = type;
500 }
501 break;
502
503 case IRQ_TYPE_EDGE_RISING:
504 if (pc->irq_type[offset] == IRQ_TYPE_EDGE_BOTH) {
505 /* RISING already enabled, disable FALLING */
506 pc->irq_type[offset] = IRQ_TYPE_EDGE_FALLING;
507 bcm2835_gpio_irq_config(pc, offset, false);
508 pc->irq_type[offset] = type;
509 } else if (pc->irq_type[offset] != type) {
510 bcm2835_gpio_irq_config(pc, offset, false);
511 pc->irq_type[offset] = type;
512 bcm2835_gpio_irq_config(pc, offset, true);
513 }
514 break;
515
516 case IRQ_TYPE_EDGE_FALLING:
517 if (pc->irq_type[offset] == IRQ_TYPE_EDGE_BOTH) {
518 /* FALLING already enabled, disable RISING */
519 pc->irq_type[offset] = IRQ_TYPE_EDGE_RISING;
520 bcm2835_gpio_irq_config(pc, offset, false);
521 pc->irq_type[offset] = type;
522 } else if (pc->irq_type[offset] != type) {
523 bcm2835_gpio_irq_config(pc, offset, false);
524 pc->irq_type[offset] = type;
525 bcm2835_gpio_irq_config(pc, offset, true);
526 }
527 break;
528
529 case IRQ_TYPE_EDGE_BOTH:
530 if (pc->irq_type[offset] == IRQ_TYPE_EDGE_RISING) {
531 /* RISING already enabled, enable FALLING too */
532 pc->irq_type[offset] = IRQ_TYPE_EDGE_FALLING;
533 bcm2835_gpio_irq_config(pc, offset, true);
534 pc->irq_type[offset] = type;
535 } else if (pc->irq_type[offset] == IRQ_TYPE_EDGE_FALLING) {
536 /* FALLING already enabled, enable RISING too */
537 pc->irq_type[offset] = IRQ_TYPE_EDGE_RISING;
538 bcm2835_gpio_irq_config(pc, offset, true);
539 pc->irq_type[offset] = type;
540 } else if (pc->irq_type[offset] != type) {
541 bcm2835_gpio_irq_config(pc, offset, false);
542 pc->irq_type[offset] = type;
543 bcm2835_gpio_irq_config(pc, offset, true);
544 }
545 break;
546
547 case IRQ_TYPE_LEVEL_HIGH:
548 case IRQ_TYPE_LEVEL_LOW:
549 if (pc->irq_type[offset] != type) {
550 bcm2835_gpio_irq_config(pc, offset, false);
551 pc->irq_type[offset] = type;
552 bcm2835_gpio_irq_config(pc, offset, true);
553 }
554 break;
555
556 default:
557 return -EINVAL;
558 }
559 return 0;
560}
561
562static int bcm2835_gpio_irq_set_type(struct irq_data *data, unsigned int type)
563{
564 struct bcm2835_pinctrl *pc = irq_data_get_irq_chip_data(data);
565 unsigned gpio = irqd_to_hwirq(data);
566 unsigned offset = GPIO_REG_SHIFT(gpio);
567 unsigned bank = GPIO_REG_OFFSET(gpio);
568 unsigned long flags;
569 int ret;
570
571 spin_lock_irqsave(&pc->irq_lock[bank], flags);
572
573 if (test_bit(offset, &pc->enabled_irq_map[bank]))
574 ret = __bcm2835_gpio_irq_set_type_enabled(pc, gpio, type);
575 else
576 ret = __bcm2835_gpio_irq_set_type_disabled(pc, gpio, type);
577
b8a19382 578 if (type & IRQ_TYPE_EDGE_BOTH)
1aa74fd0 579 irq_set_handler_locked(data, handle_edge_irq);
b8a19382 580 else
1aa74fd0 581 irq_set_handler_locked(data, handle_level_irq);
b8a19382 582
e1b2dc70
SA		 583 spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
584
585 return ret;
586}
587
b8a19382
CK		 588static void bcm2835_gpio_irq_ack(struct irq_data *data)
589{
590 struct bcm2835_pinctrl *pc = irq_data_get_irq_chip_data(data);
591 unsigned gpio = irqd_to_hwirq(data);
592
593 bcm2835_gpio_set_bit(pc, GPEDS0, gpio);
594}
595
e1b2dc70
SA		 596static struct irq_chip bcm2835_gpio_irq_chip = {
597 .name = MODULE_NAME,
598 .irq_enable = bcm2835_gpio_irq_enable,
599 .irq_disable = bcm2835_gpio_irq_disable,
600 .irq_set_type = bcm2835_gpio_irq_set_type,
b8a19382
CK		 601 .irq_ack = bcm2835_gpio_irq_ack,
602 .irq_mask = bcm2835_gpio_irq_disable,
603 .irq_unmask = bcm2835_gpio_irq_enable,
e1b2dc70
SA		 604};
605
606static int bcm2835_pctl_get_groups_count(struct pinctrl_dev *pctldev)
607{
608 return ARRAY_SIZE(bcm2835_gpio_groups);
609}
610
611static const char *bcm2835_pctl_get_group_name(struct pinctrl_dev *pctldev,
612 unsigned selector)
613{
614 return bcm2835_gpio_groups[selector];
615}
616
617static int bcm2835_pctl_get_group_pins(struct pinctrl_dev *pctldev,
618 unsigned selector,
619 const unsigned **pins,
620 unsigned *num_pins)
621{
622 *pins = &bcm2835_gpio_pins[selector].number;
623 *num_pins = 1;
624
625 return 0;
626}
627
628static void bcm2835_pctl_pin_dbg_show(struct pinctrl_dev *pctldev,
629 struct seq_file *s,
630 unsigned offset)
631{
632 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
633 enum bcm2835_fsel fsel = bcm2835_pinctrl_fsel_get(pc, offset);
634 const char *fname = bcm2835_functions[fsel];
635 int value = bcm2835_gpio_get_bit(pc, GPLEV0, offset);
636 int irq = irq_find_mapping(pc->irq_domain, offset);
637
638 seq_printf(s, "function %s in %s; irq %d (%s)",
639 fname, value ? "hi" : "lo",
640 irq, irq_type_names[pc->irq_type[offset]]);
641}
642
643static void bcm2835_pctl_dt_free_map(struct pinctrl_dev *pctldev,
644 struct pinctrl_map *maps, unsigned num_maps)
645{
646 int i;
647
648 for (i = 0; i < num_maps; i++)
649 if (maps[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
650 kfree(maps[i].data.configs.configs);
651
652 kfree(maps);
653}
654
655static int bcm2835_pctl_dt_node_to_map_func(struct bcm2835_pinctrl *pc,
656 struct device_node *np, u32 pin, u32 fnum,
657 struct pinctrl_map **maps)
658{
659 struct pinctrl_map *map = *maps;
660
661 if (fnum >= ARRAY_SIZE(bcm2835_functions)) {
662 dev_err(pc->dev, "%s: invalid brcm,function %d\n",
663 of_node_full_name(np), fnum);
664 return -EINVAL;
665 }
666
667 map->type = PIN_MAP_TYPE_MUX_GROUP;
668 map->data.mux.group = bcm2835_gpio_groups[pin];
669 map->data.mux.function = bcm2835_functions[fnum];
670 (*maps)++;
671
672 return 0;
673}
674
675static int bcm2835_pctl_dt_node_to_map_pull(struct bcm2835_pinctrl *pc,
676 struct device_node *np, u32 pin, u32 pull,
677 struct pinctrl_map **maps)
678{
679 struct pinctrl_map *map = *maps;
680 unsigned long *configs;
681
682 if (pull > 2) {
683 dev_err(pc->dev, "%s: invalid brcm,pull %d\n",
684 of_node_full_name(np), pull);
685 return -EINVAL;
686 }
687
688 configs = kzalloc(sizeof(*configs), GFP_KERNEL);
689 if (!configs)
690 return -ENOMEM;
691 configs[0] = BCM2835_PINCONF_PACK(BCM2835_PINCONF_PARAM_PULL, pull);
692
693 map->type = PIN_MAP_TYPE_CONFIGS_PIN;
694 map->data.configs.group_or_pin = bcm2835_gpio_pins[pin].name;
695 map->data.configs.configs = configs;
696 map->data.configs.num_configs = 1;
697 (*maps)++;
698
699 return 0;
700}
701
e1b2dc70
SA		 702static int bcm2835_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
703 struct device_node *np,
704 struct pinctrl_map **map, unsigned *num_maps)
705{
706 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
707 struct property *pins, *funcs, *pulls;
708 int num_pins, num_funcs, num_pulls, maps_per_pin;
709 struct pinctrl_map *maps, *cur_map;
710 int i, err;
711 u32 pin, func, pull;
712
713 pins = of_find_property(np, "brcm,pins", NULL);
714 if (!pins) {
715 dev_err(pc->dev, "%s: missing brcm,pins property\n",
716 of_node_full_name(np));
717 return -EINVAL;
718 }
719
720 funcs = of_find_property(np, "brcm,function", NULL);
721 pulls = of_find_property(np, "brcm,pull", NULL);
722
723 if (!funcs && !pulls) {
724 dev_err(pc->dev,
725 "%s: neither brcm,function nor brcm,pull specified\n",
726 of_node_full_name(np));
727 return -EINVAL;
728 }
729
730 num_pins = pins->length / 4;
731 num_funcs = funcs ? (funcs->length / 4) : 0;
732 num_pulls = pulls ? (pulls->length / 4) : 0;
733
734 if (num_funcs > 1 && num_funcs != num_pins) {
735 dev_err(pc->dev,
736 "%s: brcm,function must have 1 or %d entries\n",
737 of_node_full_name(np), num_pins);
738 return -EINVAL;
739 }
740
741 if (num_pulls > 1 && num_pulls != num_pins) {
742 dev_err(pc->dev,
743 "%s: brcm,pull must have 1 or %d entries\n",
744 of_node_full_name(np), num_pins);
745 return -EINVAL;
746 }
747
748 maps_per_pin = 0;
749 if (num_funcs)
750 maps_per_pin++;
751 if (num_pulls)
752 maps_per_pin++;
753 cur_map = maps = kzalloc(num_pins * maps_per_pin * sizeof(*maps),
754 GFP_KERNEL);
755 if (!maps)
756 return -ENOMEM;
757
758 for (i = 0; i < num_pins; i++) {
ce63d6d4
SW		 759 err = of_property_read_u32_index(np, "brcm,pins", i, &pin);
760 if (err)
761 goto out;
e1b2dc70
SA		 762 if (pin >= ARRAY_SIZE(bcm2835_gpio_pins)) {
763 dev_err(pc->dev, "%s: invalid brcm,pins value %d\n",
764 of_node_full_name(np), pin);
765 err = -EINVAL;
766 goto out;
767 }
768
769 if (num_funcs) {
ce63d6d4
SW		 770 err = of_property_read_u32_index(np, "brcm,function",
771 (num_funcs > 1) ? i : 0, &func);
772 if (err)
773 goto out;
e1b2dc70
SA		 774 err = bcm2835_pctl_dt_node_to_map_func(pc, np, pin,
775 func, &cur_map);
776 if (err)
777 goto out;
778 }
779 if (num_pulls) {
ce63d6d4
SW		 780 err = of_property_read_u32_index(np, "brcm,pull",
781 (num_funcs > 1) ? i : 0, &pull);
782 if (err)
783 goto out;
e1b2dc70
SA		 784 err = bcm2835_pctl_dt_node_to_map_pull(pc, np, pin,
785 pull, &cur_map);
786 if (err)
787 goto out;
788 }
789 }
790
791 *map = maps;
792 *num_maps = num_pins * maps_per_pin;
793
794 return 0;
795
796out:
797 kfree(maps);
798 return err;
799}
800
022ab148 801static const struct pinctrl_ops bcm2835_pctl_ops = {
e1b2dc70
SA		 802 .get_groups_count = bcm2835_pctl_get_groups_count,
803 .get_group_name = bcm2835_pctl_get_group_name,
804 .get_group_pins = bcm2835_pctl_get_group_pins,
805 .pin_dbg_show = bcm2835_pctl_pin_dbg_show,
806 .dt_node_to_map = bcm2835_pctl_dt_node_to_map,
807 .dt_free_map = bcm2835_pctl_dt_free_map,
808};
809
810static int bcm2835_pmx_get_functions_count(struct pinctrl_dev *pctldev)
811{
812 return BCM2835_FSEL_COUNT;
813}
814
815static const char *bcm2835_pmx_get_function_name(struct pinctrl_dev *pctldev,
816 unsigned selector)
817{
818 return bcm2835_functions[selector];
819}
820
821static int bcm2835_pmx_get_function_groups(struct pinctrl_dev *pctldev,
822 unsigned selector,
823 const char * const **groups,
824 unsigned * const num_groups)
825{
826 /* every pin can do every function */
827 *groups = bcm2835_gpio_groups;
828 *num_groups = ARRAY_SIZE(bcm2835_gpio_groups);
829
830 return 0;
831}
832
03e9f0ca 833static int bcm2835_pmx_set(struct pinctrl_dev *pctldev,
e1b2dc70
SA		 834 unsigned func_selector,
835 unsigned group_selector)
836{
837 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
838
839 bcm2835_pinctrl_fsel_set(pc, group_selector, func_selector);
840
841 return 0;
842}
843
e1b2dc70
SA		 844static void bcm2835_pmx_gpio_disable_free(struct pinctrl_dev *pctldev,
845 struct pinctrl_gpio_range *range,
846 unsigned offset)
847{
848 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
849
850 /* disable by setting to GPIO_IN */
851 bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_IN);
852}
853
854static int bcm2835_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
855 struct pinctrl_gpio_range *range,
856 unsigned offset,
857 bool input)
858{
859 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
860 enum bcm2835_fsel fsel = input ?
861 BCM2835_FSEL_GPIO_IN : BCM2835_FSEL_GPIO_OUT;
862
863 bcm2835_pinctrl_fsel_set(pc, offset, fsel);
864
865 return 0;
866}
867
022ab148 868static const struct pinmux_ops bcm2835_pmx_ops = {
e1b2dc70
SA		 869 .get_functions_count = bcm2835_pmx_get_functions_count,
870 .get_function_name = bcm2835_pmx_get_function_name,
871 .get_function_groups = bcm2835_pmx_get_function_groups,
03e9f0ca 872 .set_mux = bcm2835_pmx_set,
e1b2dc70
SA		 873 .gpio_disable_free = bcm2835_pmx_gpio_disable_free,
874 .gpio_set_direction = bcm2835_pmx_gpio_set_direction,
875};
876
877static int bcm2835_pinconf_get(struct pinctrl_dev *pctldev,
878 unsigned pin, unsigned long *config)
879{
880 /* No way to read back config in HW */
881 return -ENOTSUPP;
882}
883
884static int bcm2835_pinconf_set(struct pinctrl_dev *pctldev,
03b054e9
SY		 885 unsigned pin, unsigned long *configs,
886 unsigned num_configs)
e1b2dc70
SA		 887{
888 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
03b054e9
SY		 889 enum bcm2835_pinconf_param param;
890 u16 arg;
e1b2dc70 891 u32 off, bit;
03b054e9 892 int i;
e1b2dc70 893
03b054e9
SY		 894 for (i = 0; i < num_configs; i++) {
895 param = BCM2835_PINCONF_UNPACK_PARAM(configs[i]);
896 arg = BCM2835_PINCONF_UNPACK_ARG(configs[i]);
897
898 if (param != BCM2835_PINCONF_PARAM_PULL)
899 return -EINVAL;
900
901 off = GPIO_REG_OFFSET(pin);
902 bit = GPIO_REG_SHIFT(pin);
903
904 bcm2835_gpio_wr(pc, GPPUD, arg & 3);
905 /*
906 * Docs say to wait 150 cycles, but not of what. We assume a
907 * 1 MHz clock here, which is pretty slow...
908 */
909 udelay(150);
910 bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), BIT(bit));
911 udelay(150);
912 bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), 0);
913 } /* for each config */
e1b2dc70
SA		 914
915 return 0;
916}
917
022ab148 918static const struct pinconf_ops bcm2835_pinconf_ops = {
e1b2dc70
SA		 919 .pin_config_get = bcm2835_pinconf_get,
920 .pin_config_set = bcm2835_pinconf_set,
921};
922
923static struct pinctrl_desc bcm2835_pinctrl_desc = {
924 .name = MODULE_NAME,
925 .pins = bcm2835_gpio_pins,
926 .npins = ARRAY_SIZE(bcm2835_gpio_pins),
927 .pctlops = &bcm2835_pctl_ops,
928 .pmxops = &bcm2835_pmx_ops,
929 .confops = &bcm2835_pinconf_ops,
930 .owner = THIS_MODULE,
931};
932
84db00ba 933static struct pinctrl_gpio_range bcm2835_pinctrl_gpio_range = {
e1b2dc70
SA		 934 .name = MODULE_NAME,
935 .npins = BCM2835_NUM_GPIOS,
936};
937
150632b0 938static int bcm2835_pinctrl_probe(struct platform_device *pdev)
e1b2dc70
SA		 939{
940 struct device *dev = &pdev->dev;
941 struct device_node *np = dev->of_node;
942 struct bcm2835_pinctrl *pc;
943 struct resource iomem;
944 int err, i;
945 BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_pins) != BCM2835_NUM_GPIOS);
946 BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_groups) != BCM2835_NUM_GPIOS);
947
948 pc = devm_kzalloc(dev, sizeof(*pc), GFP_KERNEL);
949 if (!pc)
950 return -ENOMEM;
951
952 platform_set_drvdata(pdev, pc);
953 pc->dev = dev;
954
955 err = of_address_to_resource(np, 0, &iomem);
956 if (err) {
957 dev_err(dev, "could not get IO memory\n");
958 return err;
959 }
960
9e0c1fb2
TR		 961 pc->base = devm_ioremap_resource(dev, &iomem);
962 if (IS_ERR(pc->base))
963 return PTR_ERR(pc->base);
e1b2dc70
SA		 964
965 pc->gpio_chip = bcm2835_gpio_chip;
966 pc->gpio_chip.dev = dev;
967 pc->gpio_chip.of_node = np;
968
969 pc->irq_domain = irq_domain_add_linear(np, BCM2835_NUM_GPIOS,
970 &irq_domain_simple_ops, NULL);
971 if (!pc->irq_domain) {
972 dev_err(dev, "could not create IRQ domain\n");
973 return -ENOMEM;
974 }
975
976 for (i = 0; i < BCM2835_NUM_GPIOS; i++) {
977 int irq = irq_create_mapping(pc->irq_domain, i);
978 irq_set_lockdep_class(irq, &gpio_lock_class);
979 irq_set_chip_and_handler(irq, &bcm2835_gpio_irq_chip,
b8a19382 980 handle_level_irq);
e1b2dc70 981 irq_set_chip_data(irq, pc);
e1b2dc70
SA		 982 }
983
984 for (i = 0; i < BCM2835_NUM_BANKS; i++) {
985 unsigned long events;
986 unsigned offset;
987 int len;
988 char *name;
989
990 /* clear event detection flags */
991 bcm2835_gpio_wr(pc, GPREN0 + i * 4, 0);
992 bcm2835_gpio_wr(pc, GPFEN0 + i * 4, 0);
993 bcm2835_gpio_wr(pc, GPHEN0 + i * 4, 0);
994 bcm2835_gpio_wr(pc, GPLEN0 + i * 4, 0);
995 bcm2835_gpio_wr(pc, GPAREN0 + i * 4, 0);
996 bcm2835_gpio_wr(pc, GPAFEN0 + i * 4, 0);
997
998 /* clear all the events */
999 events = bcm2835_gpio_rd(pc, GPEDS0 + i * 4);
1000 for_each_set_bit(offset, &events, 32)
1001 bcm2835_gpio_wr(pc, GPEDS0 + i * 4, BIT(offset));
1002
1003 pc->irq[i] = irq_of_parse_and_map(np, i);
1004 pc->irq_data[i].pc = pc;
1005 pc->irq_data[i].bank = i;
1006 spin_lock_init(&pc->irq_lock[i]);
1007
1008 len = strlen(dev_name(pc->dev)) + 16;
1009 name = devm_kzalloc(pc->dev, len, GFP_KERNEL);
1010 if (!name)
1011 return -ENOMEM;
1012 snprintf(name, len, "%s:bank%d", dev_name(pc->dev), i);
1013
1014 err = devm_request_irq(dev, pc->irq[i],
1015 bcm2835_gpio_irq_handler, IRQF_SHARED,
1016 name, &pc->irq_data[i]);
1017 if (err) {
1018 dev_err(dev, "unable to request IRQ %d\n", pc->irq[i]);
1019 return err;
1020 }
1021 }
1022
1023 err = gpiochip_add(&pc->gpio_chip);
1024 if (err) {
1025 dev_err(dev, "could not add GPIO chip\n");
1026 return err;
1027 }
1028
1029 pc->pctl_dev = pinctrl_register(&bcm2835_pinctrl_desc, dev, pc);
323de9ef 1030 if (IS_ERR(pc->pctl_dev)) {
e1b2dc70 1031 gpiochip_remove(&pc->gpio_chip);
323de9ef 1032 return PTR_ERR(pc->pctl_dev);
e1b2dc70
SA		 1033 }
1034
1035 pc->gpio_range = bcm2835_pinctrl_gpio_range;
1036 pc->gpio_range.base = pc->gpio_chip.base;
1037 pc->gpio_range.gc = &pc->gpio_chip;
1038 pinctrl_add_gpio_range(pc->pctl_dev, &pc->gpio_range);
1039
1040 return 0;
1041}
1042
f90f54b3 1043static int bcm2835_pinctrl_remove(struct platform_device *pdev)
e1b2dc70
SA		 1044{
1045 struct bcm2835_pinctrl *pc = platform_get_drvdata(pdev);
1046
1047 pinctrl_unregister(pc->pctl_dev);
1048 gpiochip_remove(&pc->gpio_chip);
1049
1050 return 0;
1051}
1052
baa9946e 1053static const struct of_device_id bcm2835_pinctrl_match[] = {
e1b2dc70
SA		 1054 { .compatible = "brcm,bcm2835-gpio" },
1055 {}
1056};
1057MODULE_DEVICE_TABLE(of, bcm2835_pinctrl_match);
1058
1059static struct platform_driver bcm2835_pinctrl_driver = {
1060 .probe = bcm2835_pinctrl_probe,
1061 .remove = bcm2835_pinctrl_remove,
1062 .driver = {
1063 .name = MODULE_NAME,
e1b2dc70
SA		 1064 .of_match_table = bcm2835_pinctrl_match,
1065 },
1066};
1067module_platform_driver(bcm2835_pinctrl_driver);
1068
1069MODULE_AUTHOR("Chris Boot, Simon Arlott, Stephen Warren");
1070MODULE_DESCRIPTION("BCM2835 Pin control driver");
1071MODULE_LICENSE("GPL");
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