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Merge tag 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mst/vhost
[mirror_ubuntu-artful-kernel.git] / drivers / pinctrl / bcm / pinctrl-bcm2835.c
CommitLineData
e1b2dc70
SA		 1/*
2 * Driver for Broadcom BCM2835 GPIO unit (pinctrl + GPIO)
3 *
4 * Copyright (C) 2012 Chris Boot, Simon Arlott, Stephen Warren
5 *
6 * This driver is inspired by:
7 * pinctrl-nomadik.c, please see original file for copyright information
8 * pinctrl-tegra.c, please see original file for copyright information
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 */
20
21#include <linux/bitmap.h>
22#include <linux/bug.h>
23#include <linux/delay.h>
24#include <linux/device.h>
25#include <linux/err.h>
e19a5f79 26#include <linux/gpio/driver.h>
e1b2dc70
SA		 27#include <linux/io.h>
28#include <linux/irq.h>
29#include <linux/irqdesc.h>
e1b2dc70
SA		 30#include <linux/module.h>
31#include <linux/of_address.h>
32#include <linux/of.h>
33#include <linux/of_irq.h>
34#include <linux/pinctrl/consumer.h>
35#include <linux/pinctrl/machine.h>
36#include <linux/pinctrl/pinconf.h>
37#include <linux/pinctrl/pinctrl.h>
38#include <linux/pinctrl/pinmux.h>
39#include <linux/platform_device.h>
40#include <linux/seq_file.h>
41#include <linux/slab.h>
42#include <linux/spinlock.h>
43#include <linux/types.h>
44
45#define MODULE_NAME "pinctrl-bcm2835"
46#define BCM2835_NUM_GPIOS 54
47#define BCM2835_NUM_BANKS 2
00445b5d 48#define BCM2835_NUM_IRQS 3
e1b2dc70
SA		 49
50#define BCM2835_PIN_BITMAP_SZ \
51 DIV_ROUND_UP(BCM2835_NUM_GPIOS, sizeof(unsigned long) * 8)
52
53/* GPIO register offsets */
54#define GPFSEL0 0x0 /* Function Select */
55#define GPSET0 0x1c /* Pin Output Set */
56#define GPCLR0 0x28 /* Pin Output Clear */
57#define GPLEV0 0x34 /* Pin Level */
58#define GPEDS0 0x40 /* Pin Event Detect Status */
59#define GPREN0 0x4c /* Pin Rising Edge Detect Enable */
60#define GPFEN0 0x58 /* Pin Falling Edge Detect Enable */
61#define GPHEN0 0x64 /* Pin High Detect Enable */
62#define GPLEN0 0x70 /* Pin Low Detect Enable */
63#define GPAREN0 0x7c /* Pin Async Rising Edge Detect */
64#define GPAFEN0 0x88 /* Pin Async Falling Edge Detect */
65#define GPPUD 0x94 /* Pin Pull-up/down Enable */
66#define GPPUDCLK0 0x98 /* Pin Pull-up/down Enable Clock */
67
68#define FSEL_REG(p) (GPFSEL0 + (((p) / 10) * 4))
69#define FSEL_SHIFT(p) (((p) % 10) * 3)
70#define GPIO_REG_OFFSET(p) ((p) / 32)
71#define GPIO_REG_SHIFT(p) ((p) % 32)
72
73enum bcm2835_pinconf_param {
74 /* argument: bcm2835_pinconf_pull */
75 BCM2835_PINCONF_PARAM_PULL,
76};
77
e1b2dc70
SA		 78#define BCM2835_PINCONF_PACK(_param_, _arg_) ((_param_) << 16 | (_arg_))
79#define BCM2835_PINCONF_UNPACK_PARAM(_conf_) ((_conf_) >> 16)
80#define BCM2835_PINCONF_UNPACK_ARG(_conf_) ((_conf_) & 0xffff)
81
e1b2dc70
SA		 82struct bcm2835_pinctrl {
83 struct device *dev;
84 void __iomem *base;
00445b5d 85 int irq[BCM2835_NUM_IRQS];
e1b2dc70
SA		 86
87 /* note: locking assumes each bank will have its own unsigned long */
88 unsigned long enabled_irq_map[BCM2835_NUM_BANKS];
89 unsigned int irq_type[BCM2835_NUM_GPIOS];
90
91 struct pinctrl_dev *pctl_dev;
e1b2dc70
SA		 92 struct gpio_chip gpio_chip;
93 struct pinctrl_gpio_range gpio_range;
94
85ae9e51 95 int irq_group[BCM2835_NUM_IRQS];
e1b2dc70
SA		 96 spinlock_t irq_lock[BCM2835_NUM_BANKS];
97};
98
e1b2dc70
SA		 99/* pins are just named GPIO0..GPIO53 */
100#define BCM2835_GPIO_PIN(a) PINCTRL_PIN(a, "gpio" #a)
e8ed912e 101static struct pinctrl_pin_desc bcm2835_gpio_pins[] = {
e1b2dc70
SA		 102 BCM2835_GPIO_PIN(0),
103 BCM2835_GPIO_PIN(1),
104 BCM2835_GPIO_PIN(2),
105 BCM2835_GPIO_PIN(3),
106 BCM2835_GPIO_PIN(4),
107 BCM2835_GPIO_PIN(5),
108 BCM2835_GPIO_PIN(6),
109 BCM2835_GPIO_PIN(7),
110 BCM2835_GPIO_PIN(8),
111 BCM2835_GPIO_PIN(9),
112 BCM2835_GPIO_PIN(10),
113 BCM2835_GPIO_PIN(11),
114 BCM2835_GPIO_PIN(12),
115 BCM2835_GPIO_PIN(13),
116 BCM2835_GPIO_PIN(14),
117 BCM2835_GPIO_PIN(15),
118 BCM2835_GPIO_PIN(16),
119 BCM2835_GPIO_PIN(17),
120 BCM2835_GPIO_PIN(18),
121 BCM2835_GPIO_PIN(19),
122 BCM2835_GPIO_PIN(20),
123 BCM2835_GPIO_PIN(21),
124 BCM2835_GPIO_PIN(22),
125 BCM2835_GPIO_PIN(23),
126 BCM2835_GPIO_PIN(24),
127 BCM2835_GPIO_PIN(25),
128 BCM2835_GPIO_PIN(26),
129 BCM2835_GPIO_PIN(27),
130 BCM2835_GPIO_PIN(28),
131 BCM2835_GPIO_PIN(29),
132 BCM2835_GPIO_PIN(30),
133 BCM2835_GPIO_PIN(31),
134 BCM2835_GPIO_PIN(32),
135 BCM2835_GPIO_PIN(33),
136 BCM2835_GPIO_PIN(34),
137 BCM2835_GPIO_PIN(35),
138 BCM2835_GPIO_PIN(36),
139 BCM2835_GPIO_PIN(37),
140 BCM2835_GPIO_PIN(38),
141 BCM2835_GPIO_PIN(39),
142 BCM2835_GPIO_PIN(40),
143 BCM2835_GPIO_PIN(41),
144 BCM2835_GPIO_PIN(42),
145 BCM2835_GPIO_PIN(43),
146 BCM2835_GPIO_PIN(44),
147 BCM2835_GPIO_PIN(45),
148 BCM2835_GPIO_PIN(46),
149 BCM2835_GPIO_PIN(47),
150 BCM2835_GPIO_PIN(48),
151 BCM2835_GPIO_PIN(49),
152 BCM2835_GPIO_PIN(50),
153 BCM2835_GPIO_PIN(51),
154 BCM2835_GPIO_PIN(52),
155 BCM2835_GPIO_PIN(53),
156};
157
158/* one pin per group */
159static const char * const bcm2835_gpio_groups[] = {
160 "gpio0",
161 "gpio1",
162 "gpio2",
163 "gpio3",
164 "gpio4",
165 "gpio5",
166 "gpio6",
167 "gpio7",
168 "gpio8",
169 "gpio9",
170 "gpio10",
171 "gpio11",
172 "gpio12",
173 "gpio13",
174 "gpio14",
175 "gpio15",
176 "gpio16",
177 "gpio17",
178 "gpio18",
179 "gpio19",
180 "gpio20",
181 "gpio21",
182 "gpio22",
183 "gpio23",
184 "gpio24",
185 "gpio25",
186 "gpio26",
187 "gpio27",
188 "gpio28",
189 "gpio29",
190 "gpio30",
191 "gpio31",
192 "gpio32",
193 "gpio33",
194 "gpio34",
195 "gpio35",
196 "gpio36",
197 "gpio37",
198 "gpio38",
199 "gpio39",
200 "gpio40",
201 "gpio41",
202 "gpio42",
203 "gpio43",
204 "gpio44",
205 "gpio45",
206 "gpio46",
207 "gpio47",
208 "gpio48",
209 "gpio49",
210 "gpio50",
211 "gpio51",
212 "gpio52",
213 "gpio53",
214};
215
216enum bcm2835_fsel {
217 BCM2835_FSEL_GPIO_IN = 0,
218 BCM2835_FSEL_GPIO_OUT = 1,
219 BCM2835_FSEL_ALT0 = 4,
220 BCM2835_FSEL_ALT1 = 5,
221 BCM2835_FSEL_ALT2 = 6,
222 BCM2835_FSEL_ALT3 = 7,
223 BCM2835_FSEL_ALT4 = 3,
224 BCM2835_FSEL_ALT5 = 2,
225 BCM2835_FSEL_COUNT = 8,
226 BCM2835_FSEL_MASK = 0x7,
227};
228
229static const char * const bcm2835_functions[BCM2835_FSEL_COUNT] = {
230 [BCM2835_FSEL_GPIO_IN] = "gpio_in",
231 [BCM2835_FSEL_GPIO_OUT] = "gpio_out",
232 [BCM2835_FSEL_ALT0] = "alt0",
233 [BCM2835_FSEL_ALT1] = "alt1",
234 [BCM2835_FSEL_ALT2] = "alt2",
235 [BCM2835_FSEL_ALT3] = "alt3",
236 [BCM2835_FSEL_ALT4] = "alt4",
237 [BCM2835_FSEL_ALT5] = "alt5",
238};
239
240static const char * const irq_type_names[] = {
241 [IRQ_TYPE_NONE] = "none",
242 [IRQ_TYPE_EDGE_RISING] = "edge-rising",
243 [IRQ_TYPE_EDGE_FALLING] = "edge-falling",
244 [IRQ_TYPE_EDGE_BOTH] = "edge-both",
245 [IRQ_TYPE_LEVEL_HIGH] = "level-high",
246 [IRQ_TYPE_LEVEL_LOW] = "level-low",
247};
248
249static inline u32 bcm2835_gpio_rd(struct bcm2835_pinctrl *pc, unsigned reg)
250{
251 return readl(pc->base + reg);
252}
253
254static inline void bcm2835_gpio_wr(struct bcm2835_pinctrl *pc, unsigned reg,
255 u32 val)
256{
257 writel(val, pc->base + reg);
258}
259
260static inline int bcm2835_gpio_get_bit(struct bcm2835_pinctrl *pc, unsigned reg,
261 unsigned bit)
262{
263 reg += GPIO_REG_OFFSET(bit) * 4;
264 return (bcm2835_gpio_rd(pc, reg) >> GPIO_REG_SHIFT(bit)) & 1;
265}
266
267/* note NOT a read/modify/write cycle */
268static inline void bcm2835_gpio_set_bit(struct bcm2835_pinctrl *pc,
269 unsigned reg, unsigned bit)
270{
271 reg += GPIO_REG_OFFSET(bit) * 4;
272 bcm2835_gpio_wr(pc, reg, BIT(GPIO_REG_SHIFT(bit)));
273}
274
275static inline enum bcm2835_fsel bcm2835_pinctrl_fsel_get(
276 struct bcm2835_pinctrl *pc, unsigned pin)
277{
278 u32 val = bcm2835_gpio_rd(pc, FSEL_REG(pin));
279 enum bcm2835_fsel status = (val >> FSEL_SHIFT(pin)) & BCM2835_FSEL_MASK;
280
281 dev_dbg(pc->dev, "get %08x (%u => %s)\n", val, pin,
282 bcm2835_functions[status]);
283
284 return status;
285}
286
287static inline void bcm2835_pinctrl_fsel_set(
288 struct bcm2835_pinctrl *pc, unsigned pin,
289 enum bcm2835_fsel fsel)
290{
291 u32 val = bcm2835_gpio_rd(pc, FSEL_REG(pin));
292 enum bcm2835_fsel cur = (val >> FSEL_SHIFT(pin)) & BCM2835_FSEL_MASK;
293
294 dev_dbg(pc->dev, "read %08x (%u => %s)\n", val, pin,
295 bcm2835_functions[cur]);
296
297 if (cur == fsel)
298 return;
299
300 if (cur != BCM2835_FSEL_GPIO_IN && fsel != BCM2835_FSEL_GPIO_IN) {
301 /* always transition through GPIO_IN */
302 val &= ~(BCM2835_FSEL_MASK << FSEL_SHIFT(pin));
303 val |= BCM2835_FSEL_GPIO_IN << FSEL_SHIFT(pin);
304
305 dev_dbg(pc->dev, "trans %08x (%u <= %s)\n", val, pin,
306 bcm2835_functions[BCM2835_FSEL_GPIO_IN]);
307 bcm2835_gpio_wr(pc, FSEL_REG(pin), val);
308 }
309
310 val &= ~(BCM2835_FSEL_MASK << FSEL_SHIFT(pin));
311 val |= fsel << FSEL_SHIFT(pin);
312
313 dev_dbg(pc->dev, "write %08x (%u <= %s)\n", val, pin,
314 bcm2835_functions[fsel]);
315 bcm2835_gpio_wr(pc, FSEL_REG(pin), val);
316}
317
e1b2dc70
SA		 318static int bcm2835_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
319{
320 return pinctrl_gpio_direction_input(chip->base + offset);
321}
322
323static int bcm2835_gpio_get(struct gpio_chip *chip, unsigned offset)
324{
e19a5f79 325 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
e1b2dc70
SA		 326
327 return bcm2835_gpio_get_bit(pc, GPLEV0, offset);
328}
329
20b3d2a7
SW		 330static int bcm2835_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
331{
332 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
333 enum bcm2835_fsel fsel = bcm2835_pinctrl_fsel_get(pc, offset);
334
335 /* Alternative function doesn't clearly provide a direction */
336 if (fsel > BCM2835_FSEL_GPIO_OUT)
337 return -EINVAL;
338
339 return (fsel == BCM2835_FSEL_GPIO_IN);
340}
341
e1b2dc70
SA		 342static void bcm2835_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
343{
e19a5f79 344 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
e1b2dc70
SA		 345
346 bcm2835_gpio_set_bit(pc, value ? GPSET0 : GPCLR0, offset);
347}
348
4c02cba1
SW		 349static int bcm2835_gpio_direction_output(struct gpio_chip *chip,
350 unsigned offset, int value)
351{
352 bcm2835_gpio_set(chip, offset, value);
353 return pinctrl_gpio_direction_output(chip->base + offset);
354}
355
84db00ba 356static struct gpio_chip bcm2835_gpio_chip = {
e1b2dc70
SA		 357 .label = MODULE_NAME,
358 .owner = THIS_MODULE,
98c85d58
JG		 359 .request = gpiochip_generic_request,
360 .free = gpiochip_generic_free,
e1b2dc70
SA		 361 .direction_input = bcm2835_gpio_direction_input,
362 .direction_output = bcm2835_gpio_direction_output,
20b3d2a7 363 .get_direction = bcm2835_gpio_get_direction,
e1b2dc70
SA		 364 .get = bcm2835_gpio_get,
365 .set = bcm2835_gpio_set,
e1b2dc70
SA		 366 .base = -1,
367 .ngpio = BCM2835_NUM_GPIOS,
9fb1f39e 368 .can_sleep = false,
e1b2dc70
SA		 369};
370
85ae9e51
LW		 371static void bcm2835_gpio_irq_handle_bank(struct bcm2835_pinctrl *pc,
372 unsigned int bank, u32 mask)
e1b2dc70 373{
e1b2dc70
SA		 374 unsigned long events;
375 unsigned offset;
376 unsigned gpio;
377 unsigned int type;
378
379 events = bcm2835_gpio_rd(pc, GPEDS0 + bank * 4);
00445b5d 380 events &= mask;
e1b2dc70
SA		 381 events &= pc->enabled_irq_map[bank];
382 for_each_set_bit(offset, &events, 32) {
383 gpio = (32 * bank) + offset;
85ae9e51 384 /* FIXME: no clue why the code looks up the type here */
e1b2dc70
SA		 385 type = pc->irq_type[gpio];
386
85ae9e51
LW		 387 generic_handle_irq(irq_linear_revmap(pc->gpio_chip.irqdomain,
388 gpio));
e1b2dc70 389 }
00445b5d
PE		 390}
391
85ae9e51 392static void bcm2835_gpio_irq_handler(struct irq_desc *desc)
00445b5d 393{
85ae9e51
LW		 394 struct gpio_chip *chip = irq_desc_get_handler_data(desc);
395 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
396 struct irq_chip *host_chip = irq_desc_get_chip(desc);
397 int irq = irq_desc_get_irq(desc);
398 int group;
399 int i;
400
401 for (i = 0; i < ARRAY_SIZE(pc->irq); i++) {
402 if (pc->irq[i] == irq) {
403 group = pc->irq_group[i];
404 break;
405 }
406 }
407 /* This should not happen, every IRQ has a bank */
408 if (i == ARRAY_SIZE(pc->irq))
409 BUG();
00445b5d 410
85ae9e51
LW		 411 chained_irq_enter(host_chip, desc);
412
413 switch (group) {
00445b5d 414 case 0: /* IRQ0 covers GPIOs 0-27 */
85ae9e51 415 bcm2835_gpio_irq_handle_bank(pc, 0, 0x0fffffff);
00445b5d
PE		 416 break;
417 case 1: /* IRQ1 covers GPIOs 28-45 */
85ae9e51
LW		 418 bcm2835_gpio_irq_handle_bank(pc, 0, 0xf0000000);
419 bcm2835_gpio_irq_handle_bank(pc, 1, 0x00003fff);
00445b5d
PE		 420 break;
421 case 2: /* IRQ2 covers GPIOs 46-53 */
85ae9e51 422 bcm2835_gpio_irq_handle_bank(pc, 1, 0x003fc000);
00445b5d
PE		 423 break;
424 }
425
85ae9e51 426 chained_irq_exit(host_chip, desc);
e1b2dc70
SA		 427}
428
429static inline void __bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc,
430 unsigned reg, unsigned offset, bool enable)
431{
432 u32 value;
433 reg += GPIO_REG_OFFSET(offset) * 4;
434 value = bcm2835_gpio_rd(pc, reg);
435 if (enable)
436 value |= BIT(GPIO_REG_SHIFT(offset));
437 else
438 value &= ~(BIT(GPIO_REG_SHIFT(offset)));
439 bcm2835_gpio_wr(pc, reg, value);
440}
441
442/* fast path for IRQ handler */
443static void bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc,
444 unsigned offset, bool enable)
445{
446 switch (pc->irq_type[offset]) {
447 case IRQ_TYPE_EDGE_RISING:
448 __bcm2835_gpio_irq_config(pc, GPREN0, offset, enable);
449 break;
450
451 case IRQ_TYPE_EDGE_FALLING:
452 __bcm2835_gpio_irq_config(pc, GPFEN0, offset, enable);
453 break;
454
455 case IRQ_TYPE_EDGE_BOTH:
456 __bcm2835_gpio_irq_config(pc, GPREN0, offset, enable);
457 __bcm2835_gpio_irq_config(pc, GPFEN0, offset, enable);
458 break;
459
460 case IRQ_TYPE_LEVEL_HIGH:
461 __bcm2835_gpio_irq_config(pc, GPHEN0, offset, enable);
462 break;
463
464 case IRQ_TYPE_LEVEL_LOW:
465 __bcm2835_gpio_irq_config(pc, GPLEN0, offset, enable);
466 break;
467 }
468}
469
470static void bcm2835_gpio_irq_enable(struct irq_data *data)
471{
85ae9e51
LW		 472 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
473 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
e1b2dc70
SA		 474 unsigned gpio = irqd_to_hwirq(data);
475 unsigned offset = GPIO_REG_SHIFT(gpio);
476 unsigned bank = GPIO_REG_OFFSET(gpio);
477 unsigned long flags;
478
479 spin_lock_irqsave(&pc->irq_lock[bank], flags);
480 set_bit(offset, &pc->enabled_irq_map[bank]);
481 bcm2835_gpio_irq_config(pc, gpio, true);
482 spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
483}
484
485static void bcm2835_gpio_irq_disable(struct irq_data *data)
486{
85ae9e51
LW		 487 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
488 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
e1b2dc70
SA		 489 unsigned gpio = irqd_to_hwirq(data);
490 unsigned offset = GPIO_REG_SHIFT(gpio);
491 unsigned bank = GPIO_REG_OFFSET(gpio);
492 unsigned long flags;
493
494 spin_lock_irqsave(&pc->irq_lock[bank], flags);
495 bcm2835_gpio_irq_config(pc, gpio, false);
714b1dd8
JB		 496 /* Clear events that were latched prior to clearing event sources */
497 bcm2835_gpio_set_bit(pc, GPEDS0, gpio);
e1b2dc70
SA		 498 clear_bit(offset, &pc->enabled_irq_map[bank]);
499 spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
500}
501
502static int __bcm2835_gpio_irq_set_type_disabled(struct bcm2835_pinctrl *pc,
503 unsigned offset, unsigned int type)
504{
505 switch (type) {
506 case IRQ_TYPE_NONE:
507 case IRQ_TYPE_EDGE_RISING:
508 case IRQ_TYPE_EDGE_FALLING:
509 case IRQ_TYPE_EDGE_BOTH:
510 case IRQ_TYPE_LEVEL_HIGH:
511 case IRQ_TYPE_LEVEL_LOW:
512 pc->irq_type[offset] = type;
513 break;
514
515 default:
516 return -EINVAL;
517 }
518 return 0;
519}
520
521/* slower path for reconfiguring IRQ type */
522static int __bcm2835_gpio_irq_set_type_enabled(struct bcm2835_pinctrl *pc,
523 unsigned offset, unsigned int type)
524{
525 switch (type) {
526 case IRQ_TYPE_NONE:
527 if (pc->irq_type[offset] != type) {
528 bcm2835_gpio_irq_config(pc, offset, false);
529 pc->irq_type[offset] = type;
530 }
531 break;
532
533 case IRQ_TYPE_EDGE_RISING:
534 if (pc->irq_type[offset] == IRQ_TYPE_EDGE_BOTH) {
535 /* RISING already enabled, disable FALLING */
536 pc->irq_type[offset] = IRQ_TYPE_EDGE_FALLING;
537 bcm2835_gpio_irq_config(pc, offset, false);
538 pc->irq_type[offset] = type;
539 } else if (pc->irq_type[offset] != type) {
540 bcm2835_gpio_irq_config(pc, offset, false);
541 pc->irq_type[offset] = type;
542 bcm2835_gpio_irq_config(pc, offset, true);
543 }
544 break;
545
546 case IRQ_TYPE_EDGE_FALLING:
547 if (pc->irq_type[offset] == IRQ_TYPE_EDGE_BOTH) {
548 /* FALLING already enabled, disable RISING */
549 pc->irq_type[offset] = IRQ_TYPE_EDGE_RISING;
550 bcm2835_gpio_irq_config(pc, offset, false);
551 pc->irq_type[offset] = type;
552 } else if (pc->irq_type[offset] != type) {
553 bcm2835_gpio_irq_config(pc, offset, false);
554 pc->irq_type[offset] = type;
555 bcm2835_gpio_irq_config(pc, offset, true);
556 }
557 break;
558
559 case IRQ_TYPE_EDGE_BOTH:
560 if (pc->irq_type[offset] == IRQ_TYPE_EDGE_RISING) {
561 /* RISING already enabled, enable FALLING too */
562 pc->irq_type[offset] = IRQ_TYPE_EDGE_FALLING;
563 bcm2835_gpio_irq_config(pc, offset, true);
564 pc->irq_type[offset] = type;
565 } else if (pc->irq_type[offset] == IRQ_TYPE_EDGE_FALLING) {
566 /* FALLING already enabled, enable RISING too */
567 pc->irq_type[offset] = IRQ_TYPE_EDGE_RISING;
568 bcm2835_gpio_irq_config(pc, offset, true);
569 pc->irq_type[offset] = type;
570 } else if (pc->irq_type[offset] != type) {
571 bcm2835_gpio_irq_config(pc, offset, false);
572 pc->irq_type[offset] = type;
573 bcm2835_gpio_irq_config(pc, offset, true);
574 }
575 break;
576
577 case IRQ_TYPE_LEVEL_HIGH:
578 case IRQ_TYPE_LEVEL_LOW:
579 if (pc->irq_type[offset] != type) {
580 bcm2835_gpio_irq_config(pc, offset, false);
581 pc->irq_type[offset] = type;
582 bcm2835_gpio_irq_config(pc, offset, true);
583 }
584 break;
585
586 default:
587 return -EINVAL;
588 }
589 return 0;
590}
591
592static int bcm2835_gpio_irq_set_type(struct irq_data *data, unsigned int type)
593{
85ae9e51
LW		 594 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
595 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
e1b2dc70
SA		 596 unsigned gpio = irqd_to_hwirq(data);
597 unsigned offset = GPIO_REG_SHIFT(gpio);
598 unsigned bank = GPIO_REG_OFFSET(gpio);
599 unsigned long flags;
600 int ret;
601
602 spin_lock_irqsave(&pc->irq_lock[bank], flags);
603
604 if (test_bit(offset, &pc->enabled_irq_map[bank]))
605 ret = __bcm2835_gpio_irq_set_type_enabled(pc, gpio, type);
606 else
607 ret = __bcm2835_gpio_irq_set_type_disabled(pc, gpio, type);
608
b8a19382 609 if (type & IRQ_TYPE_EDGE_BOTH)
1aa74fd0 610 irq_set_handler_locked(data, handle_edge_irq);
b8a19382 611 else
1aa74fd0 612 irq_set_handler_locked(data, handle_level_irq);
b8a19382 613
e1b2dc70
SA		 614 spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
615
616 return ret;
617}
618
b8a19382
CK		 619static void bcm2835_gpio_irq_ack(struct irq_data *data)
620{
85ae9e51
LW		 621 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
622 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
b8a19382
CK		 623 unsigned gpio = irqd_to_hwirq(data);
624
625 bcm2835_gpio_set_bit(pc, GPEDS0, gpio);
626}
627
e1b2dc70
SA		 628static struct irq_chip bcm2835_gpio_irq_chip = {
629 .name = MODULE_NAME,
630 .irq_enable = bcm2835_gpio_irq_enable,
631 .irq_disable = bcm2835_gpio_irq_disable,
632 .irq_set_type = bcm2835_gpio_irq_set_type,
b8a19382
CK		 633 .irq_ack = bcm2835_gpio_irq_ack,
634 .irq_mask = bcm2835_gpio_irq_disable,
635 .irq_unmask = bcm2835_gpio_irq_enable,
e1b2dc70
SA		 636};
637
638static int bcm2835_pctl_get_groups_count(struct pinctrl_dev *pctldev)
639{
640 return ARRAY_SIZE(bcm2835_gpio_groups);
641}
642
643static const char *bcm2835_pctl_get_group_name(struct pinctrl_dev *pctldev,
644 unsigned selector)
645{
646 return bcm2835_gpio_groups[selector];
647}
648
649static int bcm2835_pctl_get_group_pins(struct pinctrl_dev *pctldev,
650 unsigned selector,
651 const unsigned **pins,
652 unsigned *num_pins)
653{
654 *pins = &bcm2835_gpio_pins[selector].number;
655 *num_pins = 1;
656
657 return 0;
658}
659
660static void bcm2835_pctl_pin_dbg_show(struct pinctrl_dev *pctldev,
661 struct seq_file *s,
662 unsigned offset)
663{
664 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
85ae9e51 665 struct gpio_chip *chip = &pc->gpio_chip;
e1b2dc70
SA		 666 enum bcm2835_fsel fsel = bcm2835_pinctrl_fsel_get(pc, offset);
667 const char *fname = bcm2835_functions[fsel];
668 int value = bcm2835_gpio_get_bit(pc, GPLEV0, offset);
85ae9e51 669 int irq = irq_find_mapping(chip->irqdomain, offset);
e1b2dc70
SA		 670
671 seq_printf(s, "function %s in %s; irq %d (%s)",
672 fname, value ? "hi" : "lo",
673 irq, irq_type_names[pc->irq_type[offset]]);
674}
675
676static void bcm2835_pctl_dt_free_map(struct pinctrl_dev *pctldev,
677 struct pinctrl_map *maps, unsigned num_maps)
678{
679 int i;
680
681 for (i = 0; i < num_maps; i++)
682 if (maps[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
683 kfree(maps[i].data.configs.configs);
684
685 kfree(maps);
686}
687
688static int bcm2835_pctl_dt_node_to_map_func(struct bcm2835_pinctrl *pc,
689 struct device_node *np, u32 pin, u32 fnum,
690 struct pinctrl_map **maps)
691{
692 struct pinctrl_map *map = *maps;
693
694 if (fnum >= ARRAY_SIZE(bcm2835_functions)) {
695 dev_err(pc->dev, "%s: invalid brcm,function %d\n",
696 of_node_full_name(np), fnum);
697 return -EINVAL;
698 }
699
700 map->type = PIN_MAP_TYPE_MUX_GROUP;
701 map->data.mux.group = bcm2835_gpio_groups[pin];
702 map->data.mux.function = bcm2835_functions[fnum];
703 (*maps)++;
704
705 return 0;
706}
707
708static int bcm2835_pctl_dt_node_to_map_pull(struct bcm2835_pinctrl *pc,
709 struct device_node *np, u32 pin, u32 pull,
710 struct pinctrl_map **maps)
711{
712 struct pinctrl_map *map = *maps;
713 unsigned long *configs;
714
715 if (pull > 2) {
716 dev_err(pc->dev, "%s: invalid brcm,pull %d\n",
717 of_node_full_name(np), pull);
718 return -EINVAL;
719 }
720
721 configs = kzalloc(sizeof(*configs), GFP_KERNEL);
722 if (!configs)
723 return -ENOMEM;
724 configs[0] = BCM2835_PINCONF_PACK(BCM2835_PINCONF_PARAM_PULL, pull);
725
726 map->type = PIN_MAP_TYPE_CONFIGS_PIN;
727 map->data.configs.group_or_pin = bcm2835_gpio_pins[pin].name;
728 map->data.configs.configs = configs;
729 map->data.configs.num_configs = 1;
730 (*maps)++;
731
732 return 0;
733}
734
e1b2dc70
SA		 735static int bcm2835_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
736 struct device_node *np,
737 struct pinctrl_map **map, unsigned *num_maps)
738{
739 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
740 struct property *pins, *funcs, *pulls;
741 int num_pins, num_funcs, num_pulls, maps_per_pin;
742 struct pinctrl_map *maps, *cur_map;
743 int i, err;
744 u32 pin, func, pull;
745
746 pins = of_find_property(np, "brcm,pins", NULL);
747 if (!pins) {
748 dev_err(pc->dev, "%s: missing brcm,pins property\n",
749 of_node_full_name(np));
750 return -EINVAL;
751 }
752
753 funcs = of_find_property(np, "brcm,function", NULL);
754 pulls = of_find_property(np, "brcm,pull", NULL);
755
756 if (!funcs && !pulls) {
757 dev_err(pc->dev,
758 "%s: neither brcm,function nor brcm,pull specified\n",
759 of_node_full_name(np));
760 return -EINVAL;
761 }
762
763 num_pins = pins->length / 4;
764 num_funcs = funcs ? (funcs->length / 4) : 0;
765 num_pulls = pulls ? (pulls->length / 4) : 0;
766
767 if (num_funcs > 1 && num_funcs != num_pins) {
768 dev_err(pc->dev,
769 "%s: brcm,function must have 1 or %d entries\n",
770 of_node_full_name(np), num_pins);
771 return -EINVAL;
772 }
773
774 if (num_pulls > 1 && num_pulls != num_pins) {
775 dev_err(pc->dev,
776 "%s: brcm,pull must have 1 or %d entries\n",
777 of_node_full_name(np), num_pins);
778 return -EINVAL;
779 }
780
781 maps_per_pin = 0;
782 if (num_funcs)
783 maps_per_pin++;
784 if (num_pulls)
785 maps_per_pin++;
786 cur_map = maps = kzalloc(num_pins * maps_per_pin * sizeof(*maps),
787 GFP_KERNEL);
788 if (!maps)
789 return -ENOMEM;
790
791 for (i = 0; i < num_pins; i++) {
ce63d6d4
SW		 792 err = of_property_read_u32_index(np, "brcm,pins", i, &pin);
793 if (err)
794 goto out;
e1b2dc70
SA		 795 if (pin >= ARRAY_SIZE(bcm2835_gpio_pins)) {
796 dev_err(pc->dev, "%s: invalid brcm,pins value %d\n",
797 of_node_full_name(np), pin);
798 err = -EINVAL;
799 goto out;
800 }
801
802 if (num_funcs) {
ce63d6d4
SW		 803 err = of_property_read_u32_index(np, "brcm,function",
804 (num_funcs > 1) ? i : 0, &func);
805 if (err)
806 goto out;
e1b2dc70
SA		 807 err = bcm2835_pctl_dt_node_to_map_func(pc, np, pin,
808 func, &cur_map);
809 if (err)
810 goto out;
811 }
812 if (num_pulls) {
ce63d6d4 813 err = of_property_read_u32_index(np, "brcm,pull",
2c7e3306 814 (num_pulls > 1) ? i : 0, &pull);
ce63d6d4
SW		 815 if (err)
816 goto out;
e1b2dc70
SA		 817 err = bcm2835_pctl_dt_node_to_map_pull(pc, np, pin,
818 pull, &cur_map);
819 if (err)
820 goto out;
821 }
822 }
823
824 *map = maps;
825 *num_maps = num_pins * maps_per_pin;
826
827 return 0;
828
829out:
53653c6b 830 bcm2835_pctl_dt_free_map(pctldev, maps, num_pins * maps_per_pin);
e1b2dc70
SA		 831 return err;
832}
833
022ab148 834static const struct pinctrl_ops bcm2835_pctl_ops = {
e1b2dc70
SA		 835 .get_groups_count = bcm2835_pctl_get_groups_count,
836 .get_group_name = bcm2835_pctl_get_group_name,
837 .get_group_pins = bcm2835_pctl_get_group_pins,
838 .pin_dbg_show = bcm2835_pctl_pin_dbg_show,
839 .dt_node_to_map = bcm2835_pctl_dt_node_to_map,
840 .dt_free_map = bcm2835_pctl_dt_free_map,
841};
842
ccca1ad5
PE		 843static int bcm2835_pmx_free(struct pinctrl_dev *pctldev,
844 unsigned offset)
845{
846 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
847
848 /* disable by setting to GPIO_IN */
849 bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_IN);
850 return 0;
851}
852
e1b2dc70
SA		 853static int bcm2835_pmx_get_functions_count(struct pinctrl_dev *pctldev)
854{
855 return BCM2835_FSEL_COUNT;
856}
857
858static const char *bcm2835_pmx_get_function_name(struct pinctrl_dev *pctldev,
859 unsigned selector)
860{
861 return bcm2835_functions[selector];
862}
863
864static int bcm2835_pmx_get_function_groups(struct pinctrl_dev *pctldev,
865 unsigned selector,
866 const char * const **groups,
867 unsigned * const num_groups)
868{
869 /* every pin can do every function */
870 *groups = bcm2835_gpio_groups;
871 *num_groups = ARRAY_SIZE(bcm2835_gpio_groups);
872
873 return 0;
874}
875
03e9f0ca 876static int bcm2835_pmx_set(struct pinctrl_dev *pctldev,
e1b2dc70
SA		 877 unsigned func_selector,
878 unsigned group_selector)
879{
880 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
881
882 bcm2835_pinctrl_fsel_set(pc, group_selector, func_selector);
883
884 return 0;
885}
886
e1b2dc70
SA		 887static void bcm2835_pmx_gpio_disable_free(struct pinctrl_dev *pctldev,
888 struct pinctrl_gpio_range *range,
889 unsigned offset)
890{
891 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
892
893 /* disable by setting to GPIO_IN */
894 bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_IN);
895}
896
897static int bcm2835_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
898 struct pinctrl_gpio_range *range,
899 unsigned offset,
900 bool input)
901{
902 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
903 enum bcm2835_fsel fsel = input ?
904 BCM2835_FSEL_GPIO_IN : BCM2835_FSEL_GPIO_OUT;
905
906 bcm2835_pinctrl_fsel_set(pc, offset, fsel);
907
908 return 0;
909}
910
022ab148 911static const struct pinmux_ops bcm2835_pmx_ops = {
ccca1ad5 912 .free = bcm2835_pmx_free,
e1b2dc70
SA		 913 .get_functions_count = bcm2835_pmx_get_functions_count,
914 .get_function_name = bcm2835_pmx_get_function_name,
915 .get_function_groups = bcm2835_pmx_get_function_groups,
03e9f0ca 916 .set_mux = bcm2835_pmx_set,
e1b2dc70
SA		 917 .gpio_disable_free = bcm2835_pmx_gpio_disable_free,
918 .gpio_set_direction = bcm2835_pmx_gpio_set_direction,
919};
920
921static int bcm2835_pinconf_get(struct pinctrl_dev *pctldev,
922 unsigned pin, unsigned long *config)
923{
924 /* No way to read back config in HW */
925 return -ENOTSUPP;
926}
927
928static int bcm2835_pinconf_set(struct pinctrl_dev *pctldev,
03b054e9
SY		 929 unsigned pin, unsigned long *configs,
930 unsigned num_configs)
e1b2dc70
SA		 931{
932 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
03b054e9
SY		 933 enum bcm2835_pinconf_param param;
934 u16 arg;
e1b2dc70 935 u32 off, bit;
03b054e9 936 int i;
e1b2dc70 937
03b054e9
SY		 938 for (i = 0; i < num_configs; i++) {
939 param = BCM2835_PINCONF_UNPACK_PARAM(configs[i]);
940 arg = BCM2835_PINCONF_UNPACK_ARG(configs[i]);
941
942 if (param != BCM2835_PINCONF_PARAM_PULL)
943 return -EINVAL;
944
945 off = GPIO_REG_OFFSET(pin);
946 bit = GPIO_REG_SHIFT(pin);
947
948 bcm2835_gpio_wr(pc, GPPUD, arg & 3);
949 /*
b83bd893
SW		 950 * BCM2835 datasheet say to wait 150 cycles, but not of what.
951 * But the VideoCore firmware delay for this operation
952 * based nearly on the same amount of VPU cycles and this clock
953 * runs at 250 MHz.
03b054e9 954 */
b83bd893 955 udelay(1);
03b054e9 956 bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), BIT(bit));
b83bd893 957 udelay(1);
03b054e9
SY		 958 bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), 0);
959 } /* for each config */
e1b2dc70
SA		 960
961 return 0;
962}
963
022ab148 964static const struct pinconf_ops bcm2835_pinconf_ops = {
e1b2dc70
SA		 965 .pin_config_get = bcm2835_pinconf_get,
966 .pin_config_set = bcm2835_pinconf_set,
967};
968
969static struct pinctrl_desc bcm2835_pinctrl_desc = {
970 .name = MODULE_NAME,
971 .pins = bcm2835_gpio_pins,
972 .npins = ARRAY_SIZE(bcm2835_gpio_pins),
973 .pctlops = &bcm2835_pctl_ops,
974 .pmxops = &bcm2835_pmx_ops,
975 .confops = &bcm2835_pinconf_ops,
976 .owner = THIS_MODULE,
977};
978
84db00ba 979static struct pinctrl_gpio_range bcm2835_pinctrl_gpio_range = {
e1b2dc70
SA		 980 .name = MODULE_NAME,
981 .npins = BCM2835_NUM_GPIOS,
982};
983
150632b0 984static int bcm2835_pinctrl_probe(struct platform_device *pdev)
e1b2dc70
SA		 985{
986 struct device *dev = &pdev->dev;
987 struct device_node *np = dev->of_node;
988 struct bcm2835_pinctrl *pc;
989 struct resource iomem;
990 int err, i;
991 BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_pins) != BCM2835_NUM_GPIOS);
992 BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_groups) != BCM2835_NUM_GPIOS);
993
994 pc = devm_kzalloc(dev, sizeof(*pc), GFP_KERNEL);
995 if (!pc)
996 return -ENOMEM;
997
998 platform_set_drvdata(pdev, pc);
999 pc->dev = dev;
1000
1001 err = of_address_to_resource(np, 0, &iomem);
1002 if (err) {
1003 dev_err(dev, "could not get IO memory\n");
1004 return err;
1005 }
1006
9e0c1fb2
TR		 1007 pc->base = devm_ioremap_resource(dev, &iomem);
1008 if (IS_ERR(pc->base))
1009 return PTR_ERR(pc->base);
e1b2dc70
SA		 1010
1011 pc->gpio_chip = bcm2835_gpio_chip;
58383c78 1012 pc->gpio_chip.parent = dev;
e1b2dc70
SA		 1013 pc->gpio_chip.of_node = np;
1014
e1b2dc70
SA		 1015 for (i = 0; i < BCM2835_NUM_BANKS; i++) {
1016 unsigned long events;
1017 unsigned offset;
e1b2dc70
SA		 1018
1019 /* clear event detection flags */
1020 bcm2835_gpio_wr(pc, GPREN0 + i * 4, 0);
1021 bcm2835_gpio_wr(pc, GPFEN0 + i * 4, 0);
1022 bcm2835_gpio_wr(pc, GPHEN0 + i * 4, 0);
1023 bcm2835_gpio_wr(pc, GPLEN0 + i * 4, 0);
1024 bcm2835_gpio_wr(pc, GPAREN0 + i * 4, 0);
1025 bcm2835_gpio_wr(pc, GPAFEN0 + i * 4, 0);
1026
1027 /* clear all the events */
1028 events = bcm2835_gpio_rd(pc, GPEDS0 + i * 4);
1029 for_each_set_bit(offset, &events, 32)
1030 bcm2835_gpio_wr(pc, GPEDS0 + i * 4, BIT(offset));
1031
00445b5d
PE		 1032 spin_lock_init(&pc->irq_lock[i]);
1033 }
1034
e19a5f79 1035 err = gpiochip_add_data(&pc->gpio_chip, pc);
e1b2dc70
SA		 1036 if (err) {
1037 dev_err(dev, "could not add GPIO chip\n");
1038 return err;
1039 }
1040
85ae9e51
LW		 1041 err = gpiochip_irqchip_add(&pc->gpio_chip, &bcm2835_gpio_irq_chip,
1042 0, handle_level_irq, IRQ_TYPE_NONE);
1043 if (err) {
1044 dev_info(dev, "could not add irqchip\n");
1045 return err;
1046 }
1047
1048 for (i = 0; i < BCM2835_NUM_IRQS; i++) {
1049 pc->irq[i] = irq_of_parse_and_map(np, i);
1050 pc->irq_group[i] = i;
1051 /*
1052 * Use the same handler for all groups: this is necessary
1053 * since we use one gpiochip to cover all lines - the
1054 * irq handler then needs to figure out which group and
1055 * bank that was firing the IRQ and look up the per-group
1056 * and bank data.
1057 */
1058 gpiochip_set_chained_irqchip(&pc->gpio_chip,
1059 &bcm2835_gpio_irq_chip,
1060 pc->irq[i],
1061 bcm2835_gpio_irq_handler);
1062 }
1063
5f276f67 1064 pc->pctl_dev = devm_pinctrl_register(dev, &bcm2835_pinctrl_desc, pc);
323de9ef 1065 if (IS_ERR(pc->pctl_dev)) {
e1b2dc70 1066 gpiochip_remove(&pc->gpio_chip);
323de9ef 1067 return PTR_ERR(pc->pctl_dev);
e1b2dc70
SA		 1068 }
1069
1070 pc->gpio_range = bcm2835_pinctrl_gpio_range;
1071 pc->gpio_range.base = pc->gpio_chip.base;
1072 pc->gpio_range.gc = &pc->gpio_chip;
1073 pinctrl_add_gpio_range(pc->pctl_dev, &pc->gpio_range);
1074
1075 return 0;
1076}
1077
f90f54b3 1078static int bcm2835_pinctrl_remove(struct platform_device *pdev)
e1b2dc70
SA		 1079{
1080 struct bcm2835_pinctrl *pc = platform_get_drvdata(pdev);
1081
e1b2dc70
SA		 1082 gpiochip_remove(&pc->gpio_chip);
1083
1084 return 0;
1085}
1086
baa9946e 1087static const struct of_device_id bcm2835_pinctrl_match[] = {
e1b2dc70
SA		 1088 { .compatible = "brcm,bcm2835-gpio" },
1089 {}
1090};
1091MODULE_DEVICE_TABLE(of, bcm2835_pinctrl_match);
1092
1093static struct platform_driver bcm2835_pinctrl_driver = {
1094 .probe = bcm2835_pinctrl_probe,
1095 .remove = bcm2835_pinctrl_remove,
1096 .driver = {
1097 .name = MODULE_NAME,
e1b2dc70
SA		 1098 .of_match_table = bcm2835_pinctrl_match,
1099 },
1100};
1101module_platform_driver(bcm2835_pinctrl_driver);
1102
1103MODULE_AUTHOR("Chris Boot, Simon Arlott, Stephen Warren");
1104MODULE_DESCRIPTION("BCM2835 Pin control driver");
1105MODULE_LICENSE("GPL");
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