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ae75ff81 DA |
1 | /* |
2 | * Core driver for the imx pin controller | |
3 | * | |
4 | * Copyright (C) 2012 Freescale Semiconductor, Inc. | |
5 | * Copyright (C) 2012 Linaro Ltd. | |
6 | * | |
7 | * Author: Dong Aisheng <dong.aisheng@linaro.org> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; either version 2 of the License, or | |
12 | * (at your option) any later version. | |
13 | */ | |
14 | ||
15 | #include <linux/err.h> | |
16 | #include <linux/init.h> | |
17 | #include <linux/io.h> | |
8626ada8 | 18 | #include <linux/mfd/syscon.h> |
ae75ff81 DA |
19 | #include <linux/of.h> |
20 | #include <linux/of_device.h> | |
26d8cde5 | 21 | #include <linux/of_address.h> |
ae75ff81 DA |
22 | #include <linux/pinctrl/machine.h> |
23 | #include <linux/pinctrl/pinconf.h> | |
24 | #include <linux/pinctrl/pinctrl.h> | |
25 | #include <linux/pinctrl/pinmux.h> | |
26 | #include <linux/slab.h> | |
8626ada8 | 27 | #include <linux/regmap.h> |
ae75ff81 | 28 | |
edad3b2a | 29 | #include "../core.h" |
ae75ff81 DA |
30 | #include "pinctrl-imx.h" |
31 | ||
ae75ff81 DA |
32 | /* The bits in CONFIG cell defined in binding doc*/ |
33 | #define IMX_NO_PAD_CTL 0x80000000 /* no pin config need */ | |
34 | #define IMX_PAD_SION 0x40000000 /* set SION */ | |
35 | ||
36 | /** | |
37 | * @dev: a pointer back to containing device | |
38 | * @base: the offset to the controller in virtual memory | |
39 | */ | |
40 | struct imx_pinctrl { | |
41 | struct device *dev; | |
42 | struct pinctrl_dev *pctl; | |
43 | void __iomem *base; | |
26d8cde5 | 44 | void __iomem *input_sel_base; |
ae75ff81 DA |
45 | const struct imx_pinctrl_soc_info *info; |
46 | }; | |
47 | ||
56411f3c | 48 | static inline const struct imx_pin_group *imx_pinctrl_find_group_by_name( |
ae75ff81 DA |
49 | const struct imx_pinctrl_soc_info *info, |
50 | const char *name) | |
51 | { | |
52 | const struct imx_pin_group *grp = NULL; | |
53 | int i; | |
54 | ||
55 | for (i = 0; i < info->ngroups; i++) { | |
56 | if (!strcmp(info->groups[i].name, name)) { | |
57 | grp = &info->groups[i]; | |
58 | break; | |
59 | } | |
60 | } | |
61 | ||
62 | return grp; | |
63 | } | |
64 | ||
65 | static int imx_get_groups_count(struct pinctrl_dev *pctldev) | |
66 | { | |
67 | struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); | |
68 | const struct imx_pinctrl_soc_info *info = ipctl->info; | |
69 | ||
70 | return info->ngroups; | |
71 | } | |
72 | ||
73 | static const char *imx_get_group_name(struct pinctrl_dev *pctldev, | |
74 | unsigned selector) | |
75 | { | |
76 | struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); | |
77 | const struct imx_pinctrl_soc_info *info = ipctl->info; | |
78 | ||
79 | return info->groups[selector].name; | |
80 | } | |
81 | ||
82 | static int imx_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, | |
83 | const unsigned **pins, | |
84 | unsigned *npins) | |
85 | { | |
86 | struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); | |
87 | const struct imx_pinctrl_soc_info *info = ipctl->info; | |
88 | ||
89 | if (selector >= info->ngroups) | |
90 | return -EINVAL; | |
91 | ||
8f903f8a | 92 | *pins = info->groups[selector].pin_ids; |
ae75ff81 DA |
93 | *npins = info->groups[selector].npins; |
94 | ||
95 | return 0; | |
96 | } | |
97 | ||
98 | static void imx_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, | |
99 | unsigned offset) | |
100 | { | |
101 | seq_printf(s, "%s", dev_name(pctldev->dev)); | |
102 | } | |
103 | ||
104 | static int imx_dt_node_to_map(struct pinctrl_dev *pctldev, | |
105 | struct device_node *np, | |
106 | struct pinctrl_map **map, unsigned *num_maps) | |
107 | { | |
108 | struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); | |
109 | const struct imx_pinctrl_soc_info *info = ipctl->info; | |
110 | const struct imx_pin_group *grp; | |
111 | struct pinctrl_map *new_map; | |
112 | struct device_node *parent; | |
113 | int map_num = 1; | |
18071610 | 114 | int i, j; |
ae75ff81 DA |
115 | |
116 | /* | |
117 | * first find the group of this node and check if we need create | |
118 | * config maps for pins | |
119 | */ | |
120 | grp = imx_pinctrl_find_group_by_name(info, np->name); | |
121 | if (!grp) { | |
122 | dev_err(info->dev, "unable to find group for node %s\n", | |
123 | np->name); | |
124 | return -EINVAL; | |
125 | } | |
126 | ||
127 | for (i = 0; i < grp->npins; i++) { | |
8f903f8a | 128 | if (!(grp->pins[i].config & IMX_NO_PAD_CTL)) |
ae75ff81 DA |
129 | map_num++; |
130 | } | |
131 | ||
132 | new_map = kmalloc(sizeof(struct pinctrl_map) * map_num, GFP_KERNEL); | |
133 | if (!new_map) | |
134 | return -ENOMEM; | |
135 | ||
136 | *map = new_map; | |
137 | *num_maps = map_num; | |
138 | ||
139 | /* create mux map */ | |
140 | parent = of_get_parent(np); | |
c71157c5 DN |
141 | if (!parent) { |
142 | kfree(new_map); | |
ae75ff81 | 143 | return -EINVAL; |
c71157c5 | 144 | } |
ae75ff81 DA |
145 | new_map[0].type = PIN_MAP_TYPE_MUX_GROUP; |
146 | new_map[0].data.mux.function = parent->name; | |
147 | new_map[0].data.mux.group = np->name; | |
148 | of_node_put(parent); | |
149 | ||
150 | /* create config map */ | |
151 | new_map++; | |
18071610 | 152 | for (i = j = 0; i < grp->npins; i++) { |
8f903f8a | 153 | if (!(grp->pins[i].config & IMX_NO_PAD_CTL)) { |
18071610 HW |
154 | new_map[j].type = PIN_MAP_TYPE_CONFIGS_PIN; |
155 | new_map[j].data.configs.group_or_pin = | |
8f903f8a SH |
156 | pin_get_name(pctldev, grp->pins[i].pin); |
157 | new_map[j].data.configs.configs = &grp->pins[i].config; | |
18071610 HW |
158 | new_map[j].data.configs.num_configs = 1; |
159 | j++; | |
ae75ff81 DA |
160 | } |
161 | } | |
162 | ||
163 | dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n", | |
67695f2e | 164 | (*map)->data.mux.function, (*map)->data.mux.group, map_num); |
ae75ff81 DA |
165 | |
166 | return 0; | |
167 | } | |
168 | ||
169 | static void imx_dt_free_map(struct pinctrl_dev *pctldev, | |
170 | struct pinctrl_map *map, unsigned num_maps) | |
171 | { | |
3a86a5f8 | 172 | kfree(map); |
ae75ff81 DA |
173 | } |
174 | ||
022ab148 | 175 | static const struct pinctrl_ops imx_pctrl_ops = { |
ae75ff81 DA |
176 | .get_groups_count = imx_get_groups_count, |
177 | .get_group_name = imx_get_group_name, | |
178 | .get_group_pins = imx_get_group_pins, | |
179 | .pin_dbg_show = imx_pin_dbg_show, | |
180 | .dt_node_to_map = imx_dt_node_to_map, | |
181 | .dt_free_map = imx_dt_free_map, | |
182 | ||
183 | }; | |
184 | ||
03e9f0ca LW |
185 | static int imx_pmx_set(struct pinctrl_dev *pctldev, unsigned selector, |
186 | unsigned group) | |
ae75ff81 DA |
187 | { |
188 | struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); | |
189 | const struct imx_pinctrl_soc_info *info = ipctl->info; | |
190 | const struct imx_pin_reg *pin_reg; | |
ae75ff81 DA |
191 | unsigned int npins, pin_id; |
192 | int i; | |
8f903f8a | 193 | struct imx_pin_group *grp; |
ae75ff81 DA |
194 | |
195 | /* | |
196 | * Configure the mux mode for each pin in the group for a specific | |
197 | * function. | |
198 | */ | |
8f903f8a SH |
199 | grp = &info->groups[group]; |
200 | npins = grp->npins; | |
ae75ff81 DA |
201 | |
202 | dev_dbg(ipctl->dev, "enable function %s group %s\n", | |
8f903f8a | 203 | info->functions[selector].name, grp->name); |
ae75ff81 DA |
204 | |
205 | for (i = 0; i < npins; i++) { | |
8f903f8a SH |
206 | struct imx_pin *pin = &grp->pins[i]; |
207 | pin_id = pin->pin; | |
e1641531 | 208 | pin_reg = &info->pin_regs[pin_id]; |
ae75ff81 | 209 | |
3dac1918 | 210 | if (pin_reg->mux_reg == -1) { |
ba562d5e | 211 | dev_dbg(ipctl->dev, "Pin(%s) does not support mux function\n", |
ae75ff81 | 212 | info->pins[pin_id].name); |
ba562d5e | 213 | continue; |
ae75ff81 DA |
214 | } |
215 | ||
bf5a5309 JL |
216 | if (info->flags & SHARE_MUX_CONF_REG) { |
217 | u32 reg; | |
218 | reg = readl(ipctl->base + pin_reg->mux_reg); | |
219 | reg &= ~(0x7 << 20); | |
8f903f8a | 220 | reg |= (pin->mux_mode << 20); |
bf5a5309 JL |
221 | writel(reg, ipctl->base + pin_reg->mux_reg); |
222 | } else { | |
8f903f8a | 223 | writel(pin->mux_mode, ipctl->base + pin_reg->mux_reg); |
bf5a5309 | 224 | } |
ae75ff81 | 225 | dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n", |
8f903f8a | 226 | pin_reg->mux_reg, pin->mux_mode); |
ae75ff81 | 227 | |
94176faf SG |
228 | /* |
229 | * If the select input value begins with 0xff, it's a quirky | |
230 | * select input and the value should be interpreted as below. | |
231 | * 31 23 15 7 0 | |
232 | * | 0xff | shift | width | select | | |
233 | * It's used to work around the problem that the select | |
234 | * input for some pin is not implemented in the select | |
235 | * input register but in some general purpose register. | |
236 | * We encode the select input value, width and shift of | |
237 | * the bit field into input_val cell of pin function ID | |
238 | * in device tree, and then decode them here for setting | |
239 | * up the select input bits in general purpose register. | |
240 | */ | |
8f903f8a SH |
241 | if (pin->input_val >> 24 == 0xff) { |
242 | u32 val = pin->input_val; | |
94176faf SG |
243 | u8 select = val & 0xff; |
244 | u8 width = (val >> 8) & 0xff; | |
245 | u8 shift = (val >> 16) & 0xff; | |
246 | u32 mask = ((1 << width) - 1) << shift; | |
247 | /* | |
248 | * The input_reg[i] here is actually some IOMUXC general | |
249 | * purpose register, not regular select input register. | |
250 | */ | |
a3183c60 | 251 | val = readl(ipctl->base + pin->input_reg); |
94176faf SG |
252 | val &= ~mask; |
253 | val |= select << shift; | |
a3183c60 PC |
254 | writel(val, ipctl->base + pin->input_reg); |
255 | } else if (pin->input_reg) { | |
94176faf SG |
256 | /* |
257 | * Regular select input register can never be at offset | |
258 | * 0, and we only print register value for regular case. | |
259 | */ | |
26d8cde5 AA |
260 | if (ipctl->input_sel_base) |
261 | writel(pin->input_val, ipctl->input_sel_base + | |
262 | pin->input_reg); | |
263 | else | |
264 | writel(pin->input_val, ipctl->base + | |
265 | pin->input_reg); | |
ae75ff81 DA |
266 | dev_dbg(ipctl->dev, |
267 | "==>select_input: offset 0x%x val 0x%x\n", | |
8f903f8a | 268 | pin->input_reg, pin->input_val); |
ae75ff81 DA |
269 | } |
270 | } | |
271 | ||
272 | return 0; | |
273 | } | |
274 | ||
ae75ff81 DA |
275 | static int imx_pmx_get_funcs_count(struct pinctrl_dev *pctldev) |
276 | { | |
277 | struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); | |
278 | const struct imx_pinctrl_soc_info *info = ipctl->info; | |
279 | ||
280 | return info->nfunctions; | |
281 | } | |
282 | ||
283 | static const char *imx_pmx_get_func_name(struct pinctrl_dev *pctldev, | |
284 | unsigned selector) | |
285 | { | |
286 | struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); | |
287 | const struct imx_pinctrl_soc_info *info = ipctl->info; | |
288 | ||
289 | return info->functions[selector].name; | |
290 | } | |
291 | ||
292 | static int imx_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector, | |
293 | const char * const **groups, | |
294 | unsigned * const num_groups) | |
295 | { | |
296 | struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); | |
297 | const struct imx_pinctrl_soc_info *info = ipctl->info; | |
298 | ||
299 | *groups = info->functions[selector].groups; | |
300 | *num_groups = info->functions[selector].num_groups; | |
301 | ||
302 | return 0; | |
303 | } | |
304 | ||
1f2b0452 SA |
305 | static int imx_pmx_gpio_request_enable(struct pinctrl_dev *pctldev, |
306 | struct pinctrl_gpio_range *range, unsigned offset) | |
307 | { | |
308 | struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); | |
309 | const struct imx_pinctrl_soc_info *info = ipctl->info; | |
310 | const struct imx_pin_reg *pin_reg; | |
311 | struct imx_pin_group *grp; | |
312 | struct imx_pin *imx_pin; | |
313 | unsigned int pin, group; | |
314 | u32 reg; | |
315 | ||
316 | /* Currently implementation only for shared mux/conf register */ | |
317 | if (!(info->flags & SHARE_MUX_CONF_REG)) | |
430be10d | 318 | return 0; |
1f2b0452 SA |
319 | |
320 | pin_reg = &info->pin_regs[offset]; | |
321 | if (pin_reg->mux_reg == -1) | |
322 | return -EINVAL; | |
323 | ||
324 | /* Find the pinctrl config with GPIO mux mode for the requested pin */ | |
325 | for (group = 0; group < info->ngroups; group++) { | |
326 | grp = &info->groups[group]; | |
327 | for (pin = 0; pin < grp->npins; pin++) { | |
328 | imx_pin = &grp->pins[pin]; | |
329 | if (imx_pin->pin == offset && !imx_pin->mux_mode) | |
330 | goto mux_pin; | |
331 | } | |
332 | } | |
333 | ||
334 | return -EINVAL; | |
335 | ||
336 | mux_pin: | |
337 | reg = readl(ipctl->base + pin_reg->mux_reg); | |
338 | reg &= ~(0x7 << 20); | |
339 | reg |= imx_pin->config; | |
340 | writel(reg, ipctl->base + pin_reg->mux_reg); | |
341 | ||
342 | return 0; | |
343 | } | |
344 | ||
23c3960d SA |
345 | static void imx_pmx_gpio_disable_free(struct pinctrl_dev *pctldev, |
346 | struct pinctrl_gpio_range *range, unsigned offset) | |
347 | { | |
348 | struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); | |
349 | const struct imx_pinctrl_soc_info *info = ipctl->info; | |
350 | const struct imx_pin_reg *pin_reg; | |
351 | u32 reg; | |
352 | ||
353 | /* | |
354 | * Only Vybrid has the input/output buffer enable flags (IBE/OBE) | |
355 | * They are part of the shared mux/conf register. | |
356 | */ | |
357 | if (!(info->flags & SHARE_MUX_CONF_REG)) | |
358 | return; | |
359 | ||
360 | pin_reg = &info->pin_regs[offset]; | |
361 | if (pin_reg->mux_reg == -1) | |
362 | return; | |
363 | ||
364 | /* Clear IBE/OBE/PUE to disable the pin (Hi-Z) */ | |
365 | reg = readl(ipctl->base + pin_reg->mux_reg); | |
366 | reg &= ~0x7; | |
367 | writel(reg, ipctl->base + pin_reg->mux_reg); | |
368 | } | |
369 | ||
1f2b0452 SA |
370 | static int imx_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, |
371 | struct pinctrl_gpio_range *range, unsigned offset, bool input) | |
372 | { | |
373 | struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); | |
374 | const struct imx_pinctrl_soc_info *info = ipctl->info; | |
375 | const struct imx_pin_reg *pin_reg; | |
376 | u32 reg; | |
377 | ||
378 | /* | |
379 | * Only Vybrid has the input/output buffer enable flags (IBE/OBE) | |
380 | * They are part of the shared mux/conf register. | |
381 | */ | |
382 | if (!(info->flags & SHARE_MUX_CONF_REG)) | |
430be10d | 383 | return 0; |
1f2b0452 SA |
384 | |
385 | pin_reg = &info->pin_regs[offset]; | |
386 | if (pin_reg->mux_reg == -1) | |
387 | return -EINVAL; | |
388 | ||
389 | /* IBE always enabled allows us to read the value "on the wire" */ | |
390 | reg = readl(ipctl->base + pin_reg->mux_reg); | |
391 | if (input) | |
392 | reg &= ~0x2; | |
393 | else | |
394 | reg |= 0x2; | |
395 | writel(reg, ipctl->base + pin_reg->mux_reg); | |
396 | ||
397 | return 0; | |
398 | } | |
399 | ||
022ab148 | 400 | static const struct pinmux_ops imx_pmx_ops = { |
ae75ff81 DA |
401 | .get_functions_count = imx_pmx_get_funcs_count, |
402 | .get_function_name = imx_pmx_get_func_name, | |
403 | .get_function_groups = imx_pmx_get_groups, | |
03e9f0ca | 404 | .set_mux = imx_pmx_set, |
1f2b0452 | 405 | .gpio_request_enable = imx_pmx_gpio_request_enable, |
23c3960d | 406 | .gpio_disable_free = imx_pmx_gpio_disable_free, |
1f2b0452 | 407 | .gpio_set_direction = imx_pmx_gpio_set_direction, |
ae75ff81 DA |
408 | }; |
409 | ||
410 | static int imx_pinconf_get(struct pinctrl_dev *pctldev, | |
411 | unsigned pin_id, unsigned long *config) | |
412 | { | |
413 | struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); | |
414 | const struct imx_pinctrl_soc_info *info = ipctl->info; | |
e1641531 | 415 | const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id]; |
ae75ff81 | 416 | |
3dac1918 | 417 | if (pin_reg->conf_reg == -1) { |
ae75ff81 DA |
418 | dev_err(info->dev, "Pin(%s) does not support config function\n", |
419 | info->pins[pin_id].name); | |
420 | return -EINVAL; | |
421 | } | |
422 | ||
423 | *config = readl(ipctl->base + pin_reg->conf_reg); | |
424 | ||
bf5a5309 JL |
425 | if (info->flags & SHARE_MUX_CONF_REG) |
426 | *config &= 0xffff; | |
427 | ||
ae75ff81 DA |
428 | return 0; |
429 | } | |
430 | ||
431 | static int imx_pinconf_set(struct pinctrl_dev *pctldev, | |
03b054e9 SY |
432 | unsigned pin_id, unsigned long *configs, |
433 | unsigned num_configs) | |
ae75ff81 DA |
434 | { |
435 | struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); | |
436 | const struct imx_pinctrl_soc_info *info = ipctl->info; | |
e1641531 | 437 | const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id]; |
03b054e9 | 438 | int i; |
ae75ff81 | 439 | |
3dac1918 | 440 | if (pin_reg->conf_reg == -1) { |
ae75ff81 DA |
441 | dev_err(info->dev, "Pin(%s) does not support config function\n", |
442 | info->pins[pin_id].name); | |
443 | return -EINVAL; | |
444 | } | |
445 | ||
446 | dev_dbg(ipctl->dev, "pinconf set pin %s\n", | |
447 | info->pins[pin_id].name); | |
448 | ||
03b054e9 SY |
449 | for (i = 0; i < num_configs; i++) { |
450 | if (info->flags & SHARE_MUX_CONF_REG) { | |
451 | u32 reg; | |
452 | reg = readl(ipctl->base + pin_reg->conf_reg); | |
453 | reg &= ~0xffff; | |
454 | reg |= configs[i]; | |
455 | writel(reg, ipctl->base + pin_reg->conf_reg); | |
456 | } else { | |
457 | writel(configs[i], ipctl->base + pin_reg->conf_reg); | |
458 | } | |
459 | dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%lx\n", | |
460 | pin_reg->conf_reg, configs[i]); | |
461 | } /* for each config */ | |
ae75ff81 DA |
462 | |
463 | return 0; | |
464 | } | |
465 | ||
466 | static void imx_pinconf_dbg_show(struct pinctrl_dev *pctldev, | |
467 | struct seq_file *s, unsigned pin_id) | |
468 | { | |
469 | struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); | |
470 | const struct imx_pinctrl_soc_info *info = ipctl->info; | |
e1641531 | 471 | const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id]; |
ae75ff81 DA |
472 | unsigned long config; |
473 | ||
4ff0f034 | 474 | if (!pin_reg || pin_reg->conf_reg == -1) { |
ae75ff81 DA |
475 | seq_printf(s, "N/A"); |
476 | return; | |
477 | } | |
478 | ||
479 | config = readl(ipctl->base + pin_reg->conf_reg); | |
480 | seq_printf(s, "0x%lx", config); | |
481 | } | |
482 | ||
483 | static void imx_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, | |
484 | struct seq_file *s, unsigned group) | |
485 | { | |
486 | struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); | |
487 | const struct imx_pinctrl_soc_info *info = ipctl->info; | |
488 | struct imx_pin_group *grp; | |
489 | unsigned long config; | |
490 | const char *name; | |
491 | int i, ret; | |
492 | ||
493 | if (group > info->ngroups) | |
494 | return; | |
495 | ||
496 | seq_printf(s, "\n"); | |
497 | grp = &info->groups[group]; | |
498 | for (i = 0; i < grp->npins; i++) { | |
8f903f8a SH |
499 | struct imx_pin *pin = &grp->pins[i]; |
500 | name = pin_get_name(pctldev, pin->pin); | |
501 | ret = imx_pinconf_get(pctldev, pin->pin, &config); | |
ae75ff81 DA |
502 | if (ret) |
503 | return; | |
a2d16a21 | 504 | seq_printf(s, " %s: 0x%lx\n", name, config); |
ae75ff81 DA |
505 | } |
506 | } | |
507 | ||
022ab148 | 508 | static const struct pinconf_ops imx_pinconf_ops = { |
ae75ff81 DA |
509 | .pin_config_get = imx_pinconf_get, |
510 | .pin_config_set = imx_pinconf_set, | |
511 | .pin_config_dbg_show = imx_pinconf_dbg_show, | |
512 | .pin_config_group_dbg_show = imx_pinconf_group_dbg_show, | |
513 | }; | |
514 | ||
e1641531 SG |
515 | /* |
516 | * Each pin represented in fsl,pins consists of 5 u32 PIN_FUNC_ID and | |
517 | * 1 u32 CONFIG, so 24 types in total for each pin. | |
518 | */ | |
519 | #define FSL_PIN_SIZE 24 | |
bf5a5309 | 520 | #define SHARE_FSL_PIN_SIZE 20 |
ae75ff81 | 521 | |
150632b0 GKH |
522 | static int imx_pinctrl_parse_groups(struct device_node *np, |
523 | struct imx_pin_group *grp, | |
524 | struct imx_pinctrl_soc_info *info, | |
525 | u32 index) | |
ae75ff81 | 526 | { |
bf5a5309 | 527 | int size, pin_size; |
a695145b | 528 | const __be32 *list; |
e1641531 | 529 | int i; |
ae75ff81 DA |
530 | u32 config; |
531 | ||
532 | dev_dbg(info->dev, "group(%d): %s\n", index, np->name); | |
533 | ||
bf5a5309 JL |
534 | if (info->flags & SHARE_MUX_CONF_REG) |
535 | pin_size = SHARE_FSL_PIN_SIZE; | |
536 | else | |
537 | pin_size = FSL_PIN_SIZE; | |
ae75ff81 DA |
538 | /* Initialise group */ |
539 | grp->name = np->name; | |
540 | ||
541 | /* | |
542 | * the binding format is fsl,pins = <PIN_FUNC_ID CONFIG ...>, | |
543 | * do sanity check and calculate pins number | |
544 | */ | |
545 | list = of_get_property(np, "fsl,pins", &size); | |
1bf1fea9 SH |
546 | if (!list) { |
547 | dev_err(info->dev, "no fsl,pins property in node %s\n", np->full_name); | |
548 | return -EINVAL; | |
549 | } | |
550 | ||
ae75ff81 | 551 | /* we do not check return since it's safe node passed down */ |
bf5a5309 | 552 | if (!size || size % pin_size) { |
01312513 | 553 | dev_err(info->dev, "Invalid fsl,pins property in node %s\n", np->full_name); |
ae75ff81 DA |
554 | return -EINVAL; |
555 | } | |
556 | ||
bf5a5309 | 557 | grp->npins = size / pin_size; |
8f903f8a | 558 | grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(struct imx_pin), |
ae75ff81 | 559 | GFP_KERNEL); |
8f903f8a | 560 | grp->pin_ids = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int), |
ae75ff81 | 561 | GFP_KERNEL); |
8f903f8a SH |
562 | if (!grp->pins || ! grp->pin_ids) |
563 | return -ENOMEM; | |
564 | ||
e1641531 SG |
565 | for (i = 0; i < grp->npins; i++) { |
566 | u32 mux_reg = be32_to_cpu(*list++); | |
bf5a5309 JL |
567 | u32 conf_reg; |
568 | unsigned int pin_id; | |
569 | struct imx_pin_reg *pin_reg; | |
8f903f8a | 570 | struct imx_pin *pin = &grp->pins[i]; |
e1641531 | 571 | |
e7b37a52 AA |
572 | if (!(info->flags & ZERO_OFFSET_VALID) && !mux_reg) |
573 | mux_reg = -1; | |
574 | ||
16837f95 | 575 | if (info->flags & SHARE_MUX_CONF_REG) { |
bf5a5309 | 576 | conf_reg = mux_reg; |
16837f95 | 577 | } else { |
bf5a5309 | 578 | conf_reg = be32_to_cpu(*list++); |
16837f95 MP |
579 | if (!conf_reg) |
580 | conf_reg = -1; | |
581 | } | |
bf5a5309 | 582 | |
e7b37a52 | 583 | pin_id = (mux_reg != -1) ? mux_reg / 4 : conf_reg / 4; |
bf5a5309 | 584 | pin_reg = &info->pin_regs[pin_id]; |
8f903f8a SH |
585 | pin->pin = pin_id; |
586 | grp->pin_ids[i] = pin_id; | |
e1641531 SG |
587 | pin_reg->mux_reg = mux_reg; |
588 | pin_reg->conf_reg = conf_reg; | |
8f903f8a SH |
589 | pin->input_reg = be32_to_cpu(*list++); |
590 | pin->mux_mode = be32_to_cpu(*list++); | |
591 | pin->input_val = be32_to_cpu(*list++); | |
e1641531 | 592 | |
ae75ff81 DA |
593 | /* SION bit is in mux register */ |
594 | config = be32_to_cpu(*list++); | |
595 | if (config & IMX_PAD_SION) | |
8f903f8a SH |
596 | pin->mux_mode |= IOMUXC_CONFIG_SION; |
597 | pin->config = config & ~IMX_PAD_SION; | |
ae75ff81 | 598 | |
08b51953 | 599 | dev_dbg(info->dev, "%s: 0x%x 0x%08lx", info->pins[pin_id].name, |
40604469 SH |
600 | pin->mux_mode, pin->config); |
601 | } | |
3a86a5f8 | 602 | |
ae75ff81 DA |
603 | return 0; |
604 | } | |
605 | ||
150632b0 GKH |
606 | static int imx_pinctrl_parse_functions(struct device_node *np, |
607 | struct imx_pinctrl_soc_info *info, | |
608 | u32 index) | |
ae75ff81 DA |
609 | { |
610 | struct device_node *child; | |
611 | struct imx_pmx_func *func; | |
612 | struct imx_pin_group *grp; | |
ae75ff81 DA |
613 | u32 i = 0; |
614 | ||
615 | dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name); | |
616 | ||
617 | func = &info->functions[index]; | |
618 | ||
619 | /* Initialise function */ | |
620 | func->name = np->name; | |
621 | func->num_groups = of_get_child_count(np); | |
9eedfd68 | 622 | if (func->num_groups == 0) { |
01312513 | 623 | dev_err(info->dev, "no groups defined in %s\n", np->full_name); |
ae75ff81 DA |
624 | return -EINVAL; |
625 | } | |
626 | func->groups = devm_kzalloc(info->dev, | |
627 | func->num_groups * sizeof(char *), GFP_KERNEL); | |
628 | ||
629 | for_each_child_of_node(np, child) { | |
630 | func->groups[i] = child->name; | |
ee163518 | 631 | grp = &info->groups[info->group_index++]; |
5e13762c | 632 | imx_pinctrl_parse_groups(child, grp, info, i++); |
ae75ff81 DA |
633 | } |
634 | ||
635 | return 0; | |
636 | } | |
637 | ||
5fcdf6a7 MP |
638 | /* |
639 | * Check if the DT contains pins in the direct child nodes. This indicates the | |
640 | * newer DT format to store pins. This function returns true if the first found | |
641 | * fsl,pins property is in a child of np. Otherwise false is returned. | |
642 | */ | |
643 | static bool imx_pinctrl_dt_is_flat_functions(struct device_node *np) | |
644 | { | |
645 | struct device_node *function_np; | |
646 | struct device_node *pinctrl_np; | |
647 | ||
648 | for_each_child_of_node(np, function_np) { | |
649 | if (of_property_read_bool(function_np, "fsl,pins")) | |
650 | return true; | |
651 | ||
652 | for_each_child_of_node(function_np, pinctrl_np) { | |
653 | if (of_property_read_bool(pinctrl_np, "fsl,pins")) | |
654 | return false; | |
655 | } | |
656 | } | |
657 | ||
658 | return true; | |
659 | } | |
660 | ||
150632b0 | 661 | static int imx_pinctrl_probe_dt(struct platform_device *pdev, |
ae75ff81 DA |
662 | struct imx_pinctrl_soc_info *info) |
663 | { | |
664 | struct device_node *np = pdev->dev.of_node; | |
665 | struct device_node *child; | |
ae75ff81 DA |
666 | u32 nfuncs = 0; |
667 | u32 i = 0; | |
5fcdf6a7 | 668 | bool flat_funcs; |
ae75ff81 DA |
669 | |
670 | if (!np) | |
671 | return -ENODEV; | |
672 | ||
5fcdf6a7 MP |
673 | flat_funcs = imx_pinctrl_dt_is_flat_functions(np); |
674 | if (flat_funcs) { | |
675 | nfuncs = 1; | |
676 | } else { | |
677 | nfuncs = of_get_child_count(np); | |
678 | if (nfuncs <= 0) { | |
679 | dev_err(&pdev->dev, "no functions defined\n"); | |
680 | return -EINVAL; | |
681 | } | |
ae75ff81 DA |
682 | } |
683 | ||
684 | info->nfunctions = nfuncs; | |
685 | info->functions = devm_kzalloc(&pdev->dev, nfuncs * sizeof(struct imx_pmx_func), | |
686 | GFP_KERNEL); | |
687 | if (!info->functions) | |
688 | return -ENOMEM; | |
689 | ||
9999fe5d | 690 | info->group_index = 0; |
5fcdf6a7 MP |
691 | if (flat_funcs) { |
692 | info->ngroups = of_get_child_count(np); | |
693 | } else { | |
694 | info->ngroups = 0; | |
695 | for_each_child_of_node(np, child) | |
696 | info->ngroups += of_get_child_count(child); | |
697 | } | |
ae75ff81 DA |
698 | info->groups = devm_kzalloc(&pdev->dev, info->ngroups * sizeof(struct imx_pin_group), |
699 | GFP_KERNEL); | |
700 | if (!info->groups) | |
701 | return -ENOMEM; | |
702 | ||
5fcdf6a7 MP |
703 | if (flat_funcs) { |
704 | imx_pinctrl_parse_functions(np, info, 0); | |
705 | } else { | |
706 | for_each_child_of_node(np, child) | |
707 | imx_pinctrl_parse_functions(child, info, i++); | |
708 | } | |
ae75ff81 DA |
709 | |
710 | return 0; | |
711 | } | |
712 | ||
150632b0 GKH |
713 | int imx_pinctrl_probe(struct platform_device *pdev, |
714 | struct imx_pinctrl_soc_info *info) | |
ae75ff81 | 715 | { |
8626ada8 | 716 | struct regmap_config config = { .name = "gpr" }; |
26d8cde5 | 717 | struct device_node *dev_np = pdev->dev.of_node; |
6e408ed8 | 718 | struct pinctrl_desc *imx_pinctrl_desc; |
26d8cde5 | 719 | struct device_node *np; |
ae75ff81 DA |
720 | struct imx_pinctrl *ipctl; |
721 | struct resource *res; | |
8626ada8 | 722 | struct regmap *gpr; |
4691dd01 | 723 | int ret, i; |
ae75ff81 | 724 | |
e1641531 | 725 | if (!info || !info->pins || !info->npins) { |
ae75ff81 DA |
726 | dev_err(&pdev->dev, "wrong pinctrl info\n"); |
727 | return -EINVAL; | |
728 | } | |
729 | info->dev = &pdev->dev; | |
730 | ||
8626ada8 PZ |
731 | if (info->gpr_compatible) { |
732 | gpr = syscon_regmap_lookup_by_compatible(info->gpr_compatible); | |
733 | if (!IS_ERR(gpr)) | |
734 | regmap_attach_dev(&pdev->dev, gpr, &config); | |
735 | } | |
736 | ||
ae75ff81 DA |
737 | /* Create state holders etc for this driver */ |
738 | ipctl = devm_kzalloc(&pdev->dev, sizeof(*ipctl), GFP_KERNEL); | |
739 | if (!ipctl) | |
740 | return -ENOMEM; | |
741 | ||
3dac1918 | 742 | info->pin_regs = devm_kmalloc(&pdev->dev, sizeof(*info->pin_regs) * |
e1641531 SG |
743 | info->npins, GFP_KERNEL); |
744 | if (!info->pin_regs) | |
745 | return -ENOMEM; | |
4691dd01 SA |
746 | |
747 | for (i = 0; i < info->npins; i++) { | |
748 | info->pin_regs[i].mux_reg = -1; | |
749 | info->pin_regs[i].conf_reg = -1; | |
750 | } | |
e1641531 | 751 | |
ae75ff81 | 752 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
9e0c1fb2 TR |
753 | ipctl->base = devm_ioremap_resource(&pdev->dev, res); |
754 | if (IS_ERR(ipctl->base)) | |
755 | return PTR_ERR(ipctl->base); | |
ae75ff81 | 756 | |
26d8cde5 AA |
757 | if (of_property_read_bool(dev_np, "fsl,input-sel")) { |
758 | np = of_parse_phandle(dev_np, "fsl,input-sel", 0); | |
9a4f4245 | 759 | if (!np) { |
26d8cde5 AA |
760 | dev_err(&pdev->dev, "iomuxc fsl,input-sel property not found\n"); |
761 | return -EINVAL; | |
762 | } | |
9a4f4245 VZ |
763 | |
764 | ipctl->input_sel_base = of_iomap(np, 0); | |
26d8cde5 | 765 | of_node_put(np); |
9a4f4245 VZ |
766 | if (!ipctl->input_sel_base) { |
767 | dev_err(&pdev->dev, | |
768 | "iomuxc input select base address not found\n"); | |
769 | return -ENOMEM; | |
770 | } | |
26d8cde5 AA |
771 | } |
772 | ||
6e408ed8 PF |
773 | imx_pinctrl_desc = devm_kzalloc(&pdev->dev, sizeof(*imx_pinctrl_desc), |
774 | GFP_KERNEL); | |
775 | if (!imx_pinctrl_desc) | |
776 | return -ENOMEM; | |
777 | ||
778 | imx_pinctrl_desc->name = dev_name(&pdev->dev); | |
779 | imx_pinctrl_desc->pins = info->pins; | |
780 | imx_pinctrl_desc->npins = info->npins; | |
8f5983ad GB |
781 | imx_pinctrl_desc->pctlops = &imx_pctrl_ops; |
782 | imx_pinctrl_desc->pmxops = &imx_pmx_ops; | |
783 | imx_pinctrl_desc->confops = &imx_pinconf_ops; | |
784 | imx_pinctrl_desc->owner = THIS_MODULE; | |
ae75ff81 DA |
785 | |
786 | ret = imx_pinctrl_probe_dt(pdev, info); | |
787 | if (ret) { | |
788 | dev_err(&pdev->dev, "fail to probe dt properties\n"); | |
789 | return ret; | |
790 | } | |
791 | ||
792 | ipctl->info = info; | |
793 | ipctl->dev = info->dev; | |
794 | platform_set_drvdata(pdev, ipctl); | |
6e408ed8 PF |
795 | ipctl->pctl = devm_pinctrl_register(&pdev->dev, |
796 | imx_pinctrl_desc, ipctl); | |
323de9ef | 797 | if (IS_ERR(ipctl->pctl)) { |
ae75ff81 | 798 | dev_err(&pdev->dev, "could not register IMX pinctrl driver\n"); |
323de9ef | 799 | return PTR_ERR(ipctl->pctl); |
ae75ff81 DA |
800 | } |
801 | ||
802 | dev_info(&pdev->dev, "initialized IMX pinctrl driver\n"); | |
803 | ||
804 | return 0; | |
805 | } |