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ae75ff81 DA |
1 | /* |
2 | * Core driver for the imx pin controller | |
3 | * | |
4 | * Copyright (C) 2012 Freescale Semiconductor, Inc. | |
5 | * Copyright (C) 2012 Linaro Ltd. | |
6 | * | |
7 | * Author: Dong Aisheng <dong.aisheng@linaro.org> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; either version 2 of the License, or | |
12 | * (at your option) any later version. | |
13 | */ | |
14 | ||
15 | #include <linux/err.h> | |
16 | #include <linux/init.h> | |
17 | #include <linux/io.h> | |
8626ada8 | 18 | #include <linux/mfd/syscon.h> |
ae75ff81 DA |
19 | #include <linux/module.h> |
20 | #include <linux/of.h> | |
21 | #include <linux/of_device.h> | |
26d8cde5 | 22 | #include <linux/of_address.h> |
ae75ff81 DA |
23 | #include <linux/pinctrl/machine.h> |
24 | #include <linux/pinctrl/pinconf.h> | |
25 | #include <linux/pinctrl/pinctrl.h> | |
26 | #include <linux/pinctrl/pinmux.h> | |
27 | #include <linux/slab.h> | |
8626ada8 | 28 | #include <linux/regmap.h> |
ae75ff81 | 29 | |
edad3b2a | 30 | #include "../core.h" |
ae75ff81 DA |
31 | #include "pinctrl-imx.h" |
32 | ||
ae75ff81 DA |
33 | /* The bits in CONFIG cell defined in binding doc*/ |
34 | #define IMX_NO_PAD_CTL 0x80000000 /* no pin config need */ | |
35 | #define IMX_PAD_SION 0x40000000 /* set SION */ | |
36 | ||
37 | /** | |
38 | * @dev: a pointer back to containing device | |
39 | * @base: the offset to the controller in virtual memory | |
40 | */ | |
41 | struct imx_pinctrl { | |
42 | struct device *dev; | |
43 | struct pinctrl_dev *pctl; | |
44 | void __iomem *base; | |
26d8cde5 | 45 | void __iomem *input_sel_base; |
ae75ff81 DA |
46 | const struct imx_pinctrl_soc_info *info; |
47 | }; | |
48 | ||
ae75ff81 DA |
49 | static const inline struct imx_pin_group *imx_pinctrl_find_group_by_name( |
50 | const struct imx_pinctrl_soc_info *info, | |
51 | const char *name) | |
52 | { | |
53 | const struct imx_pin_group *grp = NULL; | |
54 | int i; | |
55 | ||
56 | for (i = 0; i < info->ngroups; i++) { | |
57 | if (!strcmp(info->groups[i].name, name)) { | |
58 | grp = &info->groups[i]; | |
59 | break; | |
60 | } | |
61 | } | |
62 | ||
63 | return grp; | |
64 | } | |
65 | ||
66 | static int imx_get_groups_count(struct pinctrl_dev *pctldev) | |
67 | { | |
68 | struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); | |
69 | const struct imx_pinctrl_soc_info *info = ipctl->info; | |
70 | ||
71 | return info->ngroups; | |
72 | } | |
73 | ||
74 | static const char *imx_get_group_name(struct pinctrl_dev *pctldev, | |
75 | unsigned selector) | |
76 | { | |
77 | struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); | |
78 | const struct imx_pinctrl_soc_info *info = ipctl->info; | |
79 | ||
80 | return info->groups[selector].name; | |
81 | } | |
82 | ||
83 | static int imx_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, | |
84 | const unsigned **pins, | |
85 | unsigned *npins) | |
86 | { | |
87 | struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); | |
88 | const struct imx_pinctrl_soc_info *info = ipctl->info; | |
89 | ||
90 | if (selector >= info->ngroups) | |
91 | return -EINVAL; | |
92 | ||
8f903f8a | 93 | *pins = info->groups[selector].pin_ids; |
ae75ff81 DA |
94 | *npins = info->groups[selector].npins; |
95 | ||
96 | return 0; | |
97 | } | |
98 | ||
99 | static void imx_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, | |
100 | unsigned offset) | |
101 | { | |
102 | seq_printf(s, "%s", dev_name(pctldev->dev)); | |
103 | } | |
104 | ||
105 | static int imx_dt_node_to_map(struct pinctrl_dev *pctldev, | |
106 | struct device_node *np, | |
107 | struct pinctrl_map **map, unsigned *num_maps) | |
108 | { | |
109 | struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); | |
110 | const struct imx_pinctrl_soc_info *info = ipctl->info; | |
111 | const struct imx_pin_group *grp; | |
112 | struct pinctrl_map *new_map; | |
113 | struct device_node *parent; | |
114 | int map_num = 1; | |
18071610 | 115 | int i, j; |
ae75ff81 DA |
116 | |
117 | /* | |
118 | * first find the group of this node and check if we need create | |
119 | * config maps for pins | |
120 | */ | |
121 | grp = imx_pinctrl_find_group_by_name(info, np->name); | |
122 | if (!grp) { | |
123 | dev_err(info->dev, "unable to find group for node %s\n", | |
124 | np->name); | |
125 | return -EINVAL; | |
126 | } | |
127 | ||
128 | for (i = 0; i < grp->npins; i++) { | |
8f903f8a | 129 | if (!(grp->pins[i].config & IMX_NO_PAD_CTL)) |
ae75ff81 DA |
130 | map_num++; |
131 | } | |
132 | ||
133 | new_map = kmalloc(sizeof(struct pinctrl_map) * map_num, GFP_KERNEL); | |
134 | if (!new_map) | |
135 | return -ENOMEM; | |
136 | ||
137 | *map = new_map; | |
138 | *num_maps = map_num; | |
139 | ||
140 | /* create mux map */ | |
141 | parent = of_get_parent(np); | |
c71157c5 DN |
142 | if (!parent) { |
143 | kfree(new_map); | |
ae75ff81 | 144 | return -EINVAL; |
c71157c5 | 145 | } |
ae75ff81 DA |
146 | new_map[0].type = PIN_MAP_TYPE_MUX_GROUP; |
147 | new_map[0].data.mux.function = parent->name; | |
148 | new_map[0].data.mux.group = np->name; | |
149 | of_node_put(parent); | |
150 | ||
151 | /* create config map */ | |
152 | new_map++; | |
18071610 | 153 | for (i = j = 0; i < grp->npins; i++) { |
8f903f8a | 154 | if (!(grp->pins[i].config & IMX_NO_PAD_CTL)) { |
18071610 HW |
155 | new_map[j].type = PIN_MAP_TYPE_CONFIGS_PIN; |
156 | new_map[j].data.configs.group_or_pin = | |
8f903f8a SH |
157 | pin_get_name(pctldev, grp->pins[i].pin); |
158 | new_map[j].data.configs.configs = &grp->pins[i].config; | |
18071610 HW |
159 | new_map[j].data.configs.num_configs = 1; |
160 | j++; | |
ae75ff81 DA |
161 | } |
162 | } | |
163 | ||
164 | dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n", | |
67695f2e | 165 | (*map)->data.mux.function, (*map)->data.mux.group, map_num); |
ae75ff81 DA |
166 | |
167 | return 0; | |
168 | } | |
169 | ||
170 | static void imx_dt_free_map(struct pinctrl_dev *pctldev, | |
171 | struct pinctrl_map *map, unsigned num_maps) | |
172 | { | |
3a86a5f8 | 173 | kfree(map); |
ae75ff81 DA |
174 | } |
175 | ||
022ab148 | 176 | static const struct pinctrl_ops imx_pctrl_ops = { |
ae75ff81 DA |
177 | .get_groups_count = imx_get_groups_count, |
178 | .get_group_name = imx_get_group_name, | |
179 | .get_group_pins = imx_get_group_pins, | |
180 | .pin_dbg_show = imx_pin_dbg_show, | |
181 | .dt_node_to_map = imx_dt_node_to_map, | |
182 | .dt_free_map = imx_dt_free_map, | |
183 | ||
184 | }; | |
185 | ||
03e9f0ca LW |
186 | static int imx_pmx_set(struct pinctrl_dev *pctldev, unsigned selector, |
187 | unsigned group) | |
ae75ff81 DA |
188 | { |
189 | struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); | |
190 | const struct imx_pinctrl_soc_info *info = ipctl->info; | |
191 | const struct imx_pin_reg *pin_reg; | |
ae75ff81 DA |
192 | unsigned int npins, pin_id; |
193 | int i; | |
8f903f8a | 194 | struct imx_pin_group *grp; |
ae75ff81 DA |
195 | |
196 | /* | |
197 | * Configure the mux mode for each pin in the group for a specific | |
198 | * function. | |
199 | */ | |
8f903f8a SH |
200 | grp = &info->groups[group]; |
201 | npins = grp->npins; | |
ae75ff81 DA |
202 | |
203 | dev_dbg(ipctl->dev, "enable function %s group %s\n", | |
8f903f8a | 204 | info->functions[selector].name, grp->name); |
ae75ff81 DA |
205 | |
206 | for (i = 0; i < npins; i++) { | |
8f903f8a SH |
207 | struct imx_pin *pin = &grp->pins[i]; |
208 | pin_id = pin->pin; | |
e1641531 | 209 | pin_reg = &info->pin_regs[pin_id]; |
ae75ff81 | 210 | |
3dac1918 | 211 | if (pin_reg->mux_reg == -1) { |
ae75ff81 DA |
212 | dev_err(ipctl->dev, "Pin(%s) does not support mux function\n", |
213 | info->pins[pin_id].name); | |
214 | return -EINVAL; | |
215 | } | |
216 | ||
bf5a5309 JL |
217 | if (info->flags & SHARE_MUX_CONF_REG) { |
218 | u32 reg; | |
219 | reg = readl(ipctl->base + pin_reg->mux_reg); | |
220 | reg &= ~(0x7 << 20); | |
8f903f8a | 221 | reg |= (pin->mux_mode << 20); |
bf5a5309 JL |
222 | writel(reg, ipctl->base + pin_reg->mux_reg); |
223 | } else { | |
8f903f8a | 224 | writel(pin->mux_mode, ipctl->base + pin_reg->mux_reg); |
bf5a5309 | 225 | } |
ae75ff81 | 226 | dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n", |
8f903f8a | 227 | pin_reg->mux_reg, pin->mux_mode); |
ae75ff81 | 228 | |
94176faf SG |
229 | /* |
230 | * If the select input value begins with 0xff, it's a quirky | |
231 | * select input and the value should be interpreted as below. | |
232 | * 31 23 15 7 0 | |
233 | * | 0xff | shift | width | select | | |
234 | * It's used to work around the problem that the select | |
235 | * input for some pin is not implemented in the select | |
236 | * input register but in some general purpose register. | |
237 | * We encode the select input value, width and shift of | |
238 | * the bit field into input_val cell of pin function ID | |
239 | * in device tree, and then decode them here for setting | |
240 | * up the select input bits in general purpose register. | |
241 | */ | |
8f903f8a SH |
242 | if (pin->input_val >> 24 == 0xff) { |
243 | u32 val = pin->input_val; | |
94176faf SG |
244 | u8 select = val & 0xff; |
245 | u8 width = (val >> 8) & 0xff; | |
246 | u8 shift = (val >> 16) & 0xff; | |
247 | u32 mask = ((1 << width) - 1) << shift; | |
248 | /* | |
249 | * The input_reg[i] here is actually some IOMUXC general | |
250 | * purpose register, not regular select input register. | |
251 | */ | |
a3183c60 | 252 | val = readl(ipctl->base + pin->input_reg); |
94176faf SG |
253 | val &= ~mask; |
254 | val |= select << shift; | |
a3183c60 PC |
255 | writel(val, ipctl->base + pin->input_reg); |
256 | } else if (pin->input_reg) { | |
94176faf SG |
257 | /* |
258 | * Regular select input register can never be at offset | |
259 | * 0, and we only print register value for regular case. | |
260 | */ | |
26d8cde5 AA |
261 | if (ipctl->input_sel_base) |
262 | writel(pin->input_val, ipctl->input_sel_base + | |
263 | pin->input_reg); | |
264 | else | |
265 | writel(pin->input_val, ipctl->base + | |
266 | pin->input_reg); | |
ae75ff81 DA |
267 | dev_dbg(ipctl->dev, |
268 | "==>select_input: offset 0x%x val 0x%x\n", | |
8f903f8a | 269 | pin->input_reg, pin->input_val); |
ae75ff81 DA |
270 | } |
271 | } | |
272 | ||
273 | return 0; | |
274 | } | |
275 | ||
ae75ff81 DA |
276 | static int imx_pmx_get_funcs_count(struct pinctrl_dev *pctldev) |
277 | { | |
278 | struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); | |
279 | const struct imx_pinctrl_soc_info *info = ipctl->info; | |
280 | ||
281 | return info->nfunctions; | |
282 | } | |
283 | ||
284 | static const char *imx_pmx_get_func_name(struct pinctrl_dev *pctldev, | |
285 | unsigned selector) | |
286 | { | |
287 | struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); | |
288 | const struct imx_pinctrl_soc_info *info = ipctl->info; | |
289 | ||
290 | return info->functions[selector].name; | |
291 | } | |
292 | ||
293 | static int imx_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector, | |
294 | const char * const **groups, | |
295 | unsigned * const num_groups) | |
296 | { | |
297 | struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); | |
298 | const struct imx_pinctrl_soc_info *info = ipctl->info; | |
299 | ||
300 | *groups = info->functions[selector].groups; | |
301 | *num_groups = info->functions[selector].num_groups; | |
302 | ||
303 | return 0; | |
304 | } | |
305 | ||
1f2b0452 SA |
306 | static int imx_pmx_gpio_request_enable(struct pinctrl_dev *pctldev, |
307 | struct pinctrl_gpio_range *range, unsigned offset) | |
308 | { | |
309 | struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); | |
310 | const struct imx_pinctrl_soc_info *info = ipctl->info; | |
311 | const struct imx_pin_reg *pin_reg; | |
312 | struct imx_pin_group *grp; | |
313 | struct imx_pin *imx_pin; | |
314 | unsigned int pin, group; | |
315 | u32 reg; | |
316 | ||
317 | /* Currently implementation only for shared mux/conf register */ | |
318 | if (!(info->flags & SHARE_MUX_CONF_REG)) | |
319 | return -EINVAL; | |
320 | ||
321 | pin_reg = &info->pin_regs[offset]; | |
322 | if (pin_reg->mux_reg == -1) | |
323 | return -EINVAL; | |
324 | ||
325 | /* Find the pinctrl config with GPIO mux mode for the requested pin */ | |
326 | for (group = 0; group < info->ngroups; group++) { | |
327 | grp = &info->groups[group]; | |
328 | for (pin = 0; pin < grp->npins; pin++) { | |
329 | imx_pin = &grp->pins[pin]; | |
330 | if (imx_pin->pin == offset && !imx_pin->mux_mode) | |
331 | goto mux_pin; | |
332 | } | |
333 | } | |
334 | ||
335 | return -EINVAL; | |
336 | ||
337 | mux_pin: | |
338 | reg = readl(ipctl->base + pin_reg->mux_reg); | |
339 | reg &= ~(0x7 << 20); | |
340 | reg |= imx_pin->config; | |
341 | writel(reg, ipctl->base + pin_reg->mux_reg); | |
342 | ||
343 | return 0; | |
344 | } | |
345 | ||
23c3960d SA |
346 | static void imx_pmx_gpio_disable_free(struct pinctrl_dev *pctldev, |
347 | struct pinctrl_gpio_range *range, unsigned offset) | |
348 | { | |
349 | struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); | |
350 | const struct imx_pinctrl_soc_info *info = ipctl->info; | |
351 | const struct imx_pin_reg *pin_reg; | |
352 | u32 reg; | |
353 | ||
354 | /* | |
355 | * Only Vybrid has the input/output buffer enable flags (IBE/OBE) | |
356 | * They are part of the shared mux/conf register. | |
357 | */ | |
358 | if (!(info->flags & SHARE_MUX_CONF_REG)) | |
359 | return; | |
360 | ||
361 | pin_reg = &info->pin_regs[offset]; | |
362 | if (pin_reg->mux_reg == -1) | |
363 | return; | |
364 | ||
365 | /* Clear IBE/OBE/PUE to disable the pin (Hi-Z) */ | |
366 | reg = readl(ipctl->base + pin_reg->mux_reg); | |
367 | reg &= ~0x7; | |
368 | writel(reg, ipctl->base + pin_reg->mux_reg); | |
369 | } | |
370 | ||
1f2b0452 SA |
371 | static int imx_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, |
372 | struct pinctrl_gpio_range *range, unsigned offset, bool input) | |
373 | { | |
374 | struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); | |
375 | const struct imx_pinctrl_soc_info *info = ipctl->info; | |
376 | const struct imx_pin_reg *pin_reg; | |
377 | u32 reg; | |
378 | ||
379 | /* | |
380 | * Only Vybrid has the input/output buffer enable flags (IBE/OBE) | |
381 | * They are part of the shared mux/conf register. | |
382 | */ | |
383 | if (!(info->flags & SHARE_MUX_CONF_REG)) | |
384 | return -EINVAL; | |
385 | ||
386 | pin_reg = &info->pin_regs[offset]; | |
387 | if (pin_reg->mux_reg == -1) | |
388 | return -EINVAL; | |
389 | ||
390 | /* IBE always enabled allows us to read the value "on the wire" */ | |
391 | reg = readl(ipctl->base + pin_reg->mux_reg); | |
392 | if (input) | |
393 | reg &= ~0x2; | |
394 | else | |
395 | reg |= 0x2; | |
396 | writel(reg, ipctl->base + pin_reg->mux_reg); | |
397 | ||
398 | return 0; | |
399 | } | |
400 | ||
022ab148 | 401 | static const struct pinmux_ops imx_pmx_ops = { |
ae75ff81 DA |
402 | .get_functions_count = imx_pmx_get_funcs_count, |
403 | .get_function_name = imx_pmx_get_func_name, | |
404 | .get_function_groups = imx_pmx_get_groups, | |
03e9f0ca | 405 | .set_mux = imx_pmx_set, |
1f2b0452 | 406 | .gpio_request_enable = imx_pmx_gpio_request_enable, |
23c3960d | 407 | .gpio_disable_free = imx_pmx_gpio_disable_free, |
1f2b0452 | 408 | .gpio_set_direction = imx_pmx_gpio_set_direction, |
ae75ff81 DA |
409 | }; |
410 | ||
411 | static int imx_pinconf_get(struct pinctrl_dev *pctldev, | |
412 | unsigned pin_id, unsigned long *config) | |
413 | { | |
414 | struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); | |
415 | const struct imx_pinctrl_soc_info *info = ipctl->info; | |
e1641531 | 416 | const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id]; |
ae75ff81 | 417 | |
3dac1918 | 418 | if (pin_reg->conf_reg == -1) { |
ae75ff81 DA |
419 | dev_err(info->dev, "Pin(%s) does not support config function\n", |
420 | info->pins[pin_id].name); | |
421 | return -EINVAL; | |
422 | } | |
423 | ||
424 | *config = readl(ipctl->base + pin_reg->conf_reg); | |
425 | ||
bf5a5309 JL |
426 | if (info->flags & SHARE_MUX_CONF_REG) |
427 | *config &= 0xffff; | |
428 | ||
ae75ff81 DA |
429 | return 0; |
430 | } | |
431 | ||
432 | static int imx_pinconf_set(struct pinctrl_dev *pctldev, | |
03b054e9 SY |
433 | unsigned pin_id, unsigned long *configs, |
434 | unsigned num_configs) | |
ae75ff81 DA |
435 | { |
436 | struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); | |
437 | const struct imx_pinctrl_soc_info *info = ipctl->info; | |
e1641531 | 438 | const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id]; |
03b054e9 | 439 | int i; |
ae75ff81 | 440 | |
3dac1918 | 441 | if (pin_reg->conf_reg == -1) { |
ae75ff81 DA |
442 | dev_err(info->dev, "Pin(%s) does not support config function\n", |
443 | info->pins[pin_id].name); | |
444 | return -EINVAL; | |
445 | } | |
446 | ||
447 | dev_dbg(ipctl->dev, "pinconf set pin %s\n", | |
448 | info->pins[pin_id].name); | |
449 | ||
03b054e9 SY |
450 | for (i = 0; i < num_configs; i++) { |
451 | if (info->flags & SHARE_MUX_CONF_REG) { | |
452 | u32 reg; | |
453 | reg = readl(ipctl->base + pin_reg->conf_reg); | |
454 | reg &= ~0xffff; | |
455 | reg |= configs[i]; | |
456 | writel(reg, ipctl->base + pin_reg->conf_reg); | |
457 | } else { | |
458 | writel(configs[i], ipctl->base + pin_reg->conf_reg); | |
459 | } | |
460 | dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%lx\n", | |
461 | pin_reg->conf_reg, configs[i]); | |
462 | } /* for each config */ | |
ae75ff81 DA |
463 | |
464 | return 0; | |
465 | } | |
466 | ||
467 | static void imx_pinconf_dbg_show(struct pinctrl_dev *pctldev, | |
468 | struct seq_file *s, unsigned pin_id) | |
469 | { | |
470 | struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); | |
471 | const struct imx_pinctrl_soc_info *info = ipctl->info; | |
e1641531 | 472 | const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id]; |
ae75ff81 DA |
473 | unsigned long config; |
474 | ||
4ff0f034 | 475 | if (!pin_reg || pin_reg->conf_reg == -1) { |
ae75ff81 DA |
476 | seq_printf(s, "N/A"); |
477 | return; | |
478 | } | |
479 | ||
480 | config = readl(ipctl->base + pin_reg->conf_reg); | |
481 | seq_printf(s, "0x%lx", config); | |
482 | } | |
483 | ||
484 | static void imx_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, | |
485 | struct seq_file *s, unsigned group) | |
486 | { | |
487 | struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); | |
488 | const struct imx_pinctrl_soc_info *info = ipctl->info; | |
489 | struct imx_pin_group *grp; | |
490 | unsigned long config; | |
491 | const char *name; | |
492 | int i, ret; | |
493 | ||
494 | if (group > info->ngroups) | |
495 | return; | |
496 | ||
497 | seq_printf(s, "\n"); | |
498 | grp = &info->groups[group]; | |
499 | for (i = 0; i < grp->npins; i++) { | |
8f903f8a SH |
500 | struct imx_pin *pin = &grp->pins[i]; |
501 | name = pin_get_name(pctldev, pin->pin); | |
502 | ret = imx_pinconf_get(pctldev, pin->pin, &config); | |
ae75ff81 DA |
503 | if (ret) |
504 | return; | |
505 | seq_printf(s, "%s: 0x%lx", name, config); | |
506 | } | |
507 | } | |
508 | ||
022ab148 | 509 | static const struct pinconf_ops imx_pinconf_ops = { |
ae75ff81 DA |
510 | .pin_config_get = imx_pinconf_get, |
511 | .pin_config_set = imx_pinconf_set, | |
512 | .pin_config_dbg_show = imx_pinconf_dbg_show, | |
513 | .pin_config_group_dbg_show = imx_pinconf_group_dbg_show, | |
514 | }; | |
515 | ||
516 | static struct pinctrl_desc imx_pinctrl_desc = { | |
517 | .pctlops = &imx_pctrl_ops, | |
518 | .pmxops = &imx_pmx_ops, | |
519 | .confops = &imx_pinconf_ops, | |
520 | .owner = THIS_MODULE, | |
521 | }; | |
522 | ||
e1641531 SG |
523 | /* |
524 | * Each pin represented in fsl,pins consists of 5 u32 PIN_FUNC_ID and | |
525 | * 1 u32 CONFIG, so 24 types in total for each pin. | |
526 | */ | |
527 | #define FSL_PIN_SIZE 24 | |
bf5a5309 | 528 | #define SHARE_FSL_PIN_SIZE 20 |
ae75ff81 | 529 | |
150632b0 GKH |
530 | static int imx_pinctrl_parse_groups(struct device_node *np, |
531 | struct imx_pin_group *grp, | |
532 | struct imx_pinctrl_soc_info *info, | |
533 | u32 index) | |
ae75ff81 | 534 | { |
bf5a5309 | 535 | int size, pin_size; |
a695145b | 536 | const __be32 *list; |
e1641531 | 537 | int i; |
ae75ff81 DA |
538 | u32 config; |
539 | ||
540 | dev_dbg(info->dev, "group(%d): %s\n", index, np->name); | |
541 | ||
bf5a5309 JL |
542 | if (info->flags & SHARE_MUX_CONF_REG) |
543 | pin_size = SHARE_FSL_PIN_SIZE; | |
544 | else | |
545 | pin_size = FSL_PIN_SIZE; | |
ae75ff81 DA |
546 | /* Initialise group */ |
547 | grp->name = np->name; | |
548 | ||
549 | /* | |
550 | * the binding format is fsl,pins = <PIN_FUNC_ID CONFIG ...>, | |
551 | * do sanity check and calculate pins number | |
552 | */ | |
553 | list = of_get_property(np, "fsl,pins", &size); | |
1bf1fea9 SH |
554 | if (!list) { |
555 | dev_err(info->dev, "no fsl,pins property in node %s\n", np->full_name); | |
556 | return -EINVAL; | |
557 | } | |
558 | ||
ae75ff81 | 559 | /* we do not check return since it's safe node passed down */ |
bf5a5309 | 560 | if (!size || size % pin_size) { |
01312513 | 561 | dev_err(info->dev, "Invalid fsl,pins property in node %s\n", np->full_name); |
ae75ff81 DA |
562 | return -EINVAL; |
563 | } | |
564 | ||
bf5a5309 | 565 | grp->npins = size / pin_size; |
8f903f8a | 566 | grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(struct imx_pin), |
ae75ff81 | 567 | GFP_KERNEL); |
8f903f8a | 568 | grp->pin_ids = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int), |
ae75ff81 | 569 | GFP_KERNEL); |
8f903f8a SH |
570 | if (!grp->pins || ! grp->pin_ids) |
571 | return -ENOMEM; | |
572 | ||
e1641531 SG |
573 | for (i = 0; i < grp->npins; i++) { |
574 | u32 mux_reg = be32_to_cpu(*list++); | |
bf5a5309 JL |
575 | u32 conf_reg; |
576 | unsigned int pin_id; | |
577 | struct imx_pin_reg *pin_reg; | |
8f903f8a | 578 | struct imx_pin *pin = &grp->pins[i]; |
e1641531 | 579 | |
e7b37a52 AA |
580 | if (!(info->flags & ZERO_OFFSET_VALID) && !mux_reg) |
581 | mux_reg = -1; | |
582 | ||
16837f95 | 583 | if (info->flags & SHARE_MUX_CONF_REG) { |
bf5a5309 | 584 | conf_reg = mux_reg; |
16837f95 | 585 | } else { |
bf5a5309 | 586 | conf_reg = be32_to_cpu(*list++); |
16837f95 MP |
587 | if (!conf_reg) |
588 | conf_reg = -1; | |
589 | } | |
bf5a5309 | 590 | |
e7b37a52 | 591 | pin_id = (mux_reg != -1) ? mux_reg / 4 : conf_reg / 4; |
bf5a5309 | 592 | pin_reg = &info->pin_regs[pin_id]; |
8f903f8a SH |
593 | pin->pin = pin_id; |
594 | grp->pin_ids[i] = pin_id; | |
e1641531 SG |
595 | pin_reg->mux_reg = mux_reg; |
596 | pin_reg->conf_reg = conf_reg; | |
8f903f8a SH |
597 | pin->input_reg = be32_to_cpu(*list++); |
598 | pin->mux_mode = be32_to_cpu(*list++); | |
599 | pin->input_val = be32_to_cpu(*list++); | |
e1641531 | 600 | |
ae75ff81 DA |
601 | /* SION bit is in mux register */ |
602 | config = be32_to_cpu(*list++); | |
603 | if (config & IMX_PAD_SION) | |
8f903f8a SH |
604 | pin->mux_mode |= IOMUXC_CONFIG_SION; |
605 | pin->config = config & ~IMX_PAD_SION; | |
ae75ff81 | 606 | |
08b51953 | 607 | dev_dbg(info->dev, "%s: 0x%x 0x%08lx", info->pins[pin_id].name, |
40604469 SH |
608 | pin->mux_mode, pin->config); |
609 | } | |
3a86a5f8 | 610 | |
ae75ff81 DA |
611 | return 0; |
612 | } | |
613 | ||
150632b0 GKH |
614 | static int imx_pinctrl_parse_functions(struct device_node *np, |
615 | struct imx_pinctrl_soc_info *info, | |
616 | u32 index) | |
ae75ff81 DA |
617 | { |
618 | struct device_node *child; | |
619 | struct imx_pmx_func *func; | |
620 | struct imx_pin_group *grp; | |
ae75ff81 DA |
621 | u32 i = 0; |
622 | ||
623 | dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name); | |
624 | ||
625 | func = &info->functions[index]; | |
626 | ||
627 | /* Initialise function */ | |
628 | func->name = np->name; | |
629 | func->num_groups = of_get_child_count(np); | |
9eedfd68 | 630 | if (func->num_groups == 0) { |
01312513 | 631 | dev_err(info->dev, "no groups defined in %s\n", np->full_name); |
ae75ff81 DA |
632 | return -EINVAL; |
633 | } | |
634 | func->groups = devm_kzalloc(info->dev, | |
635 | func->num_groups * sizeof(char *), GFP_KERNEL); | |
636 | ||
637 | for_each_child_of_node(np, child) { | |
638 | func->groups[i] = child->name; | |
ee163518 | 639 | grp = &info->groups[info->group_index++]; |
5e13762c | 640 | imx_pinctrl_parse_groups(child, grp, info, i++); |
ae75ff81 DA |
641 | } |
642 | ||
643 | return 0; | |
644 | } | |
645 | ||
5fcdf6a7 MP |
646 | /* |
647 | * Check if the DT contains pins in the direct child nodes. This indicates the | |
648 | * newer DT format to store pins. This function returns true if the first found | |
649 | * fsl,pins property is in a child of np. Otherwise false is returned. | |
650 | */ | |
651 | static bool imx_pinctrl_dt_is_flat_functions(struct device_node *np) | |
652 | { | |
653 | struct device_node *function_np; | |
654 | struct device_node *pinctrl_np; | |
655 | ||
656 | for_each_child_of_node(np, function_np) { | |
657 | if (of_property_read_bool(function_np, "fsl,pins")) | |
658 | return true; | |
659 | ||
660 | for_each_child_of_node(function_np, pinctrl_np) { | |
661 | if (of_property_read_bool(pinctrl_np, "fsl,pins")) | |
662 | return false; | |
663 | } | |
664 | } | |
665 | ||
666 | return true; | |
667 | } | |
668 | ||
150632b0 | 669 | static int imx_pinctrl_probe_dt(struct platform_device *pdev, |
ae75ff81 DA |
670 | struct imx_pinctrl_soc_info *info) |
671 | { | |
672 | struct device_node *np = pdev->dev.of_node; | |
673 | struct device_node *child; | |
ae75ff81 DA |
674 | u32 nfuncs = 0; |
675 | u32 i = 0; | |
5fcdf6a7 | 676 | bool flat_funcs; |
ae75ff81 DA |
677 | |
678 | if (!np) | |
679 | return -ENODEV; | |
680 | ||
5fcdf6a7 MP |
681 | flat_funcs = imx_pinctrl_dt_is_flat_functions(np); |
682 | if (flat_funcs) { | |
683 | nfuncs = 1; | |
684 | } else { | |
685 | nfuncs = of_get_child_count(np); | |
686 | if (nfuncs <= 0) { | |
687 | dev_err(&pdev->dev, "no functions defined\n"); | |
688 | return -EINVAL; | |
689 | } | |
ae75ff81 DA |
690 | } |
691 | ||
692 | info->nfunctions = nfuncs; | |
693 | info->functions = devm_kzalloc(&pdev->dev, nfuncs * sizeof(struct imx_pmx_func), | |
694 | GFP_KERNEL); | |
695 | if (!info->functions) | |
696 | return -ENOMEM; | |
697 | ||
5fcdf6a7 MP |
698 | if (flat_funcs) { |
699 | info->ngroups = of_get_child_count(np); | |
700 | } else { | |
701 | info->ngroups = 0; | |
702 | for_each_child_of_node(np, child) | |
703 | info->ngroups += of_get_child_count(child); | |
704 | } | |
ae75ff81 DA |
705 | info->groups = devm_kzalloc(&pdev->dev, info->ngroups * sizeof(struct imx_pin_group), |
706 | GFP_KERNEL); | |
707 | if (!info->groups) | |
708 | return -ENOMEM; | |
709 | ||
5fcdf6a7 MP |
710 | if (flat_funcs) { |
711 | imx_pinctrl_parse_functions(np, info, 0); | |
712 | } else { | |
713 | for_each_child_of_node(np, child) | |
714 | imx_pinctrl_parse_functions(child, info, i++); | |
715 | } | |
ae75ff81 DA |
716 | |
717 | return 0; | |
718 | } | |
719 | ||
150632b0 GKH |
720 | int imx_pinctrl_probe(struct platform_device *pdev, |
721 | struct imx_pinctrl_soc_info *info) | |
ae75ff81 | 722 | { |
8626ada8 | 723 | struct regmap_config config = { .name = "gpr" }; |
26d8cde5 AA |
724 | struct device_node *dev_np = pdev->dev.of_node; |
725 | struct device_node *np; | |
ae75ff81 DA |
726 | struct imx_pinctrl *ipctl; |
727 | struct resource *res; | |
8626ada8 | 728 | struct regmap *gpr; |
4691dd01 | 729 | int ret, i; |
ae75ff81 | 730 | |
e1641531 | 731 | if (!info || !info->pins || !info->npins) { |
ae75ff81 DA |
732 | dev_err(&pdev->dev, "wrong pinctrl info\n"); |
733 | return -EINVAL; | |
734 | } | |
735 | info->dev = &pdev->dev; | |
736 | ||
8626ada8 PZ |
737 | if (info->gpr_compatible) { |
738 | gpr = syscon_regmap_lookup_by_compatible(info->gpr_compatible); | |
739 | if (!IS_ERR(gpr)) | |
740 | regmap_attach_dev(&pdev->dev, gpr, &config); | |
741 | } | |
742 | ||
ae75ff81 DA |
743 | /* Create state holders etc for this driver */ |
744 | ipctl = devm_kzalloc(&pdev->dev, sizeof(*ipctl), GFP_KERNEL); | |
745 | if (!ipctl) | |
746 | return -ENOMEM; | |
747 | ||
3dac1918 | 748 | info->pin_regs = devm_kmalloc(&pdev->dev, sizeof(*info->pin_regs) * |
e1641531 SG |
749 | info->npins, GFP_KERNEL); |
750 | if (!info->pin_regs) | |
751 | return -ENOMEM; | |
4691dd01 SA |
752 | |
753 | for (i = 0; i < info->npins; i++) { | |
754 | info->pin_regs[i].mux_reg = -1; | |
755 | info->pin_regs[i].conf_reg = -1; | |
756 | } | |
e1641531 | 757 | |
ae75ff81 | 758 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
9e0c1fb2 TR |
759 | ipctl->base = devm_ioremap_resource(&pdev->dev, res); |
760 | if (IS_ERR(ipctl->base)) | |
761 | return PTR_ERR(ipctl->base); | |
ae75ff81 | 762 | |
26d8cde5 AA |
763 | if (of_property_read_bool(dev_np, "fsl,input-sel")) { |
764 | np = of_parse_phandle(dev_np, "fsl,input-sel", 0); | |
765 | if (np) { | |
766 | ipctl->input_sel_base = of_iomap(np, 0); | |
767 | if (IS_ERR(ipctl->input_sel_base)) { | |
768 | of_node_put(np); | |
769 | dev_err(&pdev->dev, | |
770 | "iomuxc input select base address not found\n"); | |
771 | return PTR_ERR(ipctl->input_sel_base); | |
772 | } | |
773 | } else { | |
774 | dev_err(&pdev->dev, "iomuxc fsl,input-sel property not found\n"); | |
775 | return -EINVAL; | |
776 | } | |
777 | of_node_put(np); | |
778 | } | |
779 | ||
ae75ff81 DA |
780 | imx_pinctrl_desc.name = dev_name(&pdev->dev); |
781 | imx_pinctrl_desc.pins = info->pins; | |
782 | imx_pinctrl_desc.npins = info->npins; | |
783 | ||
784 | ret = imx_pinctrl_probe_dt(pdev, info); | |
785 | if (ret) { | |
786 | dev_err(&pdev->dev, "fail to probe dt properties\n"); | |
787 | return ret; | |
788 | } | |
789 | ||
790 | ipctl->info = info; | |
791 | ipctl->dev = info->dev; | |
792 | platform_set_drvdata(pdev, ipctl); | |
793 | ipctl->pctl = pinctrl_register(&imx_pinctrl_desc, &pdev->dev, ipctl); | |
323de9ef | 794 | if (IS_ERR(ipctl->pctl)) { |
ae75ff81 | 795 | dev_err(&pdev->dev, "could not register IMX pinctrl driver\n"); |
323de9ef | 796 | return PTR_ERR(ipctl->pctl); |
ae75ff81 DA |
797 | } |
798 | ||
799 | dev_info(&pdev->dev, "initialized IMX pinctrl driver\n"); | |
800 | ||
801 | return 0; | |
802 | } | |
803 | ||
f90f54b3 | 804 | int imx_pinctrl_remove(struct platform_device *pdev) |
ae75ff81 DA |
805 | { |
806 | struct imx_pinctrl *ipctl = platform_get_drvdata(pdev); | |
807 | ||
808 | pinctrl_unregister(ipctl->pctl); | |
809 | ||
810 | return 0; | |
811 | } |