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Commit | Line | Data |
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ae75ff81 DA |
1 | /* |
2 | * Core driver for the imx pin controller | |
3 | * | |
4 | * Copyright (C) 2012 Freescale Semiconductor, Inc. | |
5 | * Copyright (C) 2012 Linaro Ltd. | |
6 | * | |
7 | * Author: Dong Aisheng <dong.aisheng@linaro.org> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; either version 2 of the License, or | |
12 | * (at your option) any later version. | |
13 | */ | |
14 | ||
15 | #include <linux/err.h> | |
16 | #include <linux/init.h> | |
17 | #include <linux/io.h> | |
8626ada8 | 18 | #include <linux/mfd/syscon.h> |
ae75ff81 DA |
19 | #include <linux/of.h> |
20 | #include <linux/of_device.h> | |
26d8cde5 | 21 | #include <linux/of_address.h> |
ae75ff81 DA |
22 | #include <linux/pinctrl/machine.h> |
23 | #include <linux/pinctrl/pinconf.h> | |
24 | #include <linux/pinctrl/pinctrl.h> | |
25 | #include <linux/pinctrl/pinmux.h> | |
26 | #include <linux/slab.h> | |
8626ada8 | 27 | #include <linux/regmap.h> |
ae75ff81 | 28 | |
edad3b2a | 29 | #include "../core.h" |
a5cadbbb | 30 | #include "../pinconf.h" |
3fd6d6ad | 31 | #include "../pinmux.h" |
ae75ff81 DA |
32 | #include "pinctrl-imx.h" |
33 | ||
ae75ff81 DA |
34 | /* The bits in CONFIG cell defined in binding doc*/ |
35 | #define IMX_NO_PAD_CTL 0x80000000 /* no pin config need */ | |
36 | #define IMX_PAD_SION 0x40000000 /* set SION */ | |
37 | ||
38 | /** | |
39 | * @dev: a pointer back to containing device | |
40 | * @base: the offset to the controller in virtual memory | |
41 | */ | |
42 | struct imx_pinctrl { | |
43 | struct device *dev; | |
44 | struct pinctrl_dev *pctl; | |
45 | void __iomem *base; | |
26d8cde5 | 46 | void __iomem *input_sel_base; |
b28742be | 47 | struct imx_pinctrl_soc_info *info; |
ae75ff81 DA |
48 | }; |
49 | ||
e566fc11 GB |
50 | static inline const struct group_desc *imx_pinctrl_find_group_by_name( |
51 | struct pinctrl_dev *pctldev, | |
ae75ff81 DA |
52 | const char *name) |
53 | { | |
e566fc11 | 54 | const struct group_desc *grp = NULL; |
ae75ff81 DA |
55 | int i; |
56 | ||
e566fc11 GB |
57 | for (i = 0; i < pctldev->num_groups; i++) { |
58 | grp = pinctrl_generic_get_group(pctldev, i); | |
a51c158b | 59 | if (grp && !strcmp(grp->name, name)) |
ae75ff81 | 60 | break; |
ae75ff81 DA |
61 | } |
62 | ||
63 | return grp; | |
64 | } | |
65 | ||
ae75ff81 DA |
66 | static void imx_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, |
67 | unsigned offset) | |
68 | { | |
69 | seq_printf(s, "%s", dev_name(pctldev->dev)); | |
70 | } | |
71 | ||
72 | static int imx_dt_node_to_map(struct pinctrl_dev *pctldev, | |
73 | struct device_node *np, | |
74 | struct pinctrl_map **map, unsigned *num_maps) | |
75 | { | |
76 | struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); | |
b28742be | 77 | struct imx_pinctrl_soc_info *info = ipctl->info; |
e566fc11 | 78 | const struct group_desc *grp; |
ae75ff81 DA |
79 | struct pinctrl_map *new_map; |
80 | struct device_node *parent; | |
81 | int map_num = 1; | |
18071610 | 82 | int i, j; |
ae75ff81 DA |
83 | |
84 | /* | |
85 | * first find the group of this node and check if we need create | |
86 | * config maps for pins | |
87 | */ | |
e566fc11 | 88 | grp = imx_pinctrl_find_group_by_name(pctldev, np->name); |
ae75ff81 DA |
89 | if (!grp) { |
90 | dev_err(info->dev, "unable to find group for node %s\n", | |
91 | np->name); | |
92 | return -EINVAL; | |
93 | } | |
94 | ||
e566fc11 GB |
95 | for (i = 0; i < grp->num_pins; i++) { |
96 | struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i]; | |
97 | ||
98 | if (!(pin->config & IMX_NO_PAD_CTL)) | |
ae75ff81 DA |
99 | map_num++; |
100 | } | |
101 | ||
102 | new_map = kmalloc(sizeof(struct pinctrl_map) * map_num, GFP_KERNEL); | |
103 | if (!new_map) | |
104 | return -ENOMEM; | |
105 | ||
106 | *map = new_map; | |
107 | *num_maps = map_num; | |
108 | ||
109 | /* create mux map */ | |
110 | parent = of_get_parent(np); | |
c71157c5 DN |
111 | if (!parent) { |
112 | kfree(new_map); | |
ae75ff81 | 113 | return -EINVAL; |
c71157c5 | 114 | } |
ae75ff81 DA |
115 | new_map[0].type = PIN_MAP_TYPE_MUX_GROUP; |
116 | new_map[0].data.mux.function = parent->name; | |
117 | new_map[0].data.mux.group = np->name; | |
118 | of_node_put(parent); | |
119 | ||
120 | /* create config map */ | |
121 | new_map++; | |
e566fc11 GB |
122 | for (i = j = 0; i < grp->num_pins; i++) { |
123 | struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i]; | |
124 | ||
125 | if (!(pin->config & IMX_NO_PAD_CTL)) { | |
18071610 HW |
126 | new_map[j].type = PIN_MAP_TYPE_CONFIGS_PIN; |
127 | new_map[j].data.configs.group_or_pin = | |
e566fc11 GB |
128 | pin_get_name(pctldev, pin->pin); |
129 | new_map[j].data.configs.configs = &pin->config; | |
18071610 HW |
130 | new_map[j].data.configs.num_configs = 1; |
131 | j++; | |
ae75ff81 DA |
132 | } |
133 | } | |
134 | ||
135 | dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n", | |
67695f2e | 136 | (*map)->data.mux.function, (*map)->data.mux.group, map_num); |
ae75ff81 DA |
137 | |
138 | return 0; | |
139 | } | |
140 | ||
141 | static void imx_dt_free_map(struct pinctrl_dev *pctldev, | |
142 | struct pinctrl_map *map, unsigned num_maps) | |
143 | { | |
3a86a5f8 | 144 | kfree(map); |
ae75ff81 DA |
145 | } |
146 | ||
022ab148 | 147 | static const struct pinctrl_ops imx_pctrl_ops = { |
e566fc11 GB |
148 | .get_groups_count = pinctrl_generic_get_group_count, |
149 | .get_group_name = pinctrl_generic_get_group_name, | |
150 | .get_group_pins = pinctrl_generic_get_group_pins, | |
ae75ff81 DA |
151 | .pin_dbg_show = imx_pin_dbg_show, |
152 | .dt_node_to_map = imx_dt_node_to_map, | |
153 | .dt_free_map = imx_dt_free_map, | |
154 | ||
155 | }; | |
156 | ||
03e9f0ca LW |
157 | static int imx_pmx_set(struct pinctrl_dev *pctldev, unsigned selector, |
158 | unsigned group) | |
ae75ff81 DA |
159 | { |
160 | struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); | |
b28742be | 161 | struct imx_pinctrl_soc_info *info = ipctl->info; |
ae75ff81 | 162 | const struct imx_pin_reg *pin_reg; |
ae75ff81 DA |
163 | unsigned int npins, pin_id; |
164 | int i; | |
e566fc11 | 165 | struct group_desc *grp = NULL; |
3fd6d6ad | 166 | struct function_desc *func = NULL; |
ae75ff81 DA |
167 | |
168 | /* | |
169 | * Configure the mux mode for each pin in the group for a specific | |
170 | * function. | |
171 | */ | |
e566fc11 | 172 | grp = pinctrl_generic_get_group(pctldev, group); |
a51c158b GB |
173 | if (!grp) |
174 | return -EINVAL; | |
175 | ||
3fd6d6ad | 176 | func = pinmux_generic_get_function(pctldev, selector); |
a51c158b GB |
177 | if (!func) |
178 | return -EINVAL; | |
179 | ||
e566fc11 | 180 | npins = grp->num_pins; |
ae75ff81 DA |
181 | |
182 | dev_dbg(ipctl->dev, "enable function %s group %s\n", | |
a51c158b | 183 | func->name, grp->name); |
ae75ff81 DA |
184 | |
185 | for (i = 0; i < npins; i++) { | |
e566fc11 GB |
186 | struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i]; |
187 | ||
8f903f8a | 188 | pin_id = pin->pin; |
e1641531 | 189 | pin_reg = &info->pin_regs[pin_id]; |
ae75ff81 | 190 | |
3dac1918 | 191 | if (pin_reg->mux_reg == -1) { |
ba562d5e | 192 | dev_dbg(ipctl->dev, "Pin(%s) does not support mux function\n", |
ae75ff81 | 193 | info->pins[pin_id].name); |
ba562d5e | 194 | continue; |
ae75ff81 DA |
195 | } |
196 | ||
bf5a5309 JL |
197 | if (info->flags & SHARE_MUX_CONF_REG) { |
198 | u32 reg; | |
199 | reg = readl(ipctl->base + pin_reg->mux_reg); | |
200 | reg &= ~(0x7 << 20); | |
8f903f8a | 201 | reg |= (pin->mux_mode << 20); |
bf5a5309 | 202 | writel(reg, ipctl->base + pin_reg->mux_reg); |
66b54e3a DA |
203 | dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n", |
204 | pin_reg->mux_reg, reg); | |
bf5a5309 | 205 | } else { |
8f903f8a | 206 | writel(pin->mux_mode, ipctl->base + pin_reg->mux_reg); |
66b54e3a DA |
207 | dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n", |
208 | pin_reg->mux_reg, pin->mux_mode); | |
bf5a5309 | 209 | } |
ae75ff81 | 210 | |
94176faf SG |
211 | /* |
212 | * If the select input value begins with 0xff, it's a quirky | |
213 | * select input and the value should be interpreted as below. | |
214 | * 31 23 15 7 0 | |
215 | * | 0xff | shift | width | select | | |
216 | * It's used to work around the problem that the select | |
217 | * input for some pin is not implemented in the select | |
218 | * input register but in some general purpose register. | |
219 | * We encode the select input value, width and shift of | |
220 | * the bit field into input_val cell of pin function ID | |
221 | * in device tree, and then decode them here for setting | |
222 | * up the select input bits in general purpose register. | |
223 | */ | |
8f903f8a SH |
224 | if (pin->input_val >> 24 == 0xff) { |
225 | u32 val = pin->input_val; | |
94176faf SG |
226 | u8 select = val & 0xff; |
227 | u8 width = (val >> 8) & 0xff; | |
228 | u8 shift = (val >> 16) & 0xff; | |
229 | u32 mask = ((1 << width) - 1) << shift; | |
230 | /* | |
231 | * The input_reg[i] here is actually some IOMUXC general | |
232 | * purpose register, not regular select input register. | |
233 | */ | |
a3183c60 | 234 | val = readl(ipctl->base + pin->input_reg); |
94176faf SG |
235 | val &= ~mask; |
236 | val |= select << shift; | |
a3183c60 PC |
237 | writel(val, ipctl->base + pin->input_reg); |
238 | } else if (pin->input_reg) { | |
94176faf SG |
239 | /* |
240 | * Regular select input register can never be at offset | |
241 | * 0, and we only print register value for regular case. | |
242 | */ | |
26d8cde5 AA |
243 | if (ipctl->input_sel_base) |
244 | writel(pin->input_val, ipctl->input_sel_base + | |
245 | pin->input_reg); | |
246 | else | |
247 | writel(pin->input_val, ipctl->base + | |
248 | pin->input_reg); | |
ae75ff81 DA |
249 | dev_dbg(ipctl->dev, |
250 | "==>select_input: offset 0x%x val 0x%x\n", | |
8f903f8a | 251 | pin->input_reg, pin->input_val); |
ae75ff81 DA |
252 | } |
253 | } | |
254 | ||
255 | return 0; | |
256 | } | |
257 | ||
1f2b0452 SA |
258 | static int imx_pmx_gpio_request_enable(struct pinctrl_dev *pctldev, |
259 | struct pinctrl_gpio_range *range, unsigned offset) | |
260 | { | |
261 | struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); | |
b28742be | 262 | struct imx_pinctrl_soc_info *info = ipctl->info; |
1f2b0452 | 263 | const struct imx_pin_reg *pin_reg; |
e566fc11 | 264 | struct group_desc *grp; |
1f2b0452 SA |
265 | struct imx_pin *imx_pin; |
266 | unsigned int pin, group; | |
267 | u32 reg; | |
268 | ||
269 | /* Currently implementation only for shared mux/conf register */ | |
270 | if (!(info->flags & SHARE_MUX_CONF_REG)) | |
430be10d | 271 | return 0; |
1f2b0452 SA |
272 | |
273 | pin_reg = &info->pin_regs[offset]; | |
274 | if (pin_reg->mux_reg == -1) | |
275 | return -EINVAL; | |
276 | ||
277 | /* Find the pinctrl config with GPIO mux mode for the requested pin */ | |
e566fc11 GB |
278 | for (group = 0; group < pctldev->num_groups; group++) { |
279 | grp = pinctrl_generic_get_group(pctldev, group); | |
a51c158b GB |
280 | if (!grp) |
281 | continue; | |
e566fc11 GB |
282 | for (pin = 0; pin < grp->num_pins; pin++) { |
283 | imx_pin = &((struct imx_pin *)(grp->data))[pin]; | |
1f2b0452 SA |
284 | if (imx_pin->pin == offset && !imx_pin->mux_mode) |
285 | goto mux_pin; | |
286 | } | |
287 | } | |
288 | ||
289 | return -EINVAL; | |
290 | ||
291 | mux_pin: | |
292 | reg = readl(ipctl->base + pin_reg->mux_reg); | |
293 | reg &= ~(0x7 << 20); | |
294 | reg |= imx_pin->config; | |
295 | writel(reg, ipctl->base + pin_reg->mux_reg); | |
296 | ||
297 | return 0; | |
298 | } | |
299 | ||
23c3960d SA |
300 | static void imx_pmx_gpio_disable_free(struct pinctrl_dev *pctldev, |
301 | struct pinctrl_gpio_range *range, unsigned offset) | |
302 | { | |
303 | struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); | |
b28742be | 304 | struct imx_pinctrl_soc_info *info = ipctl->info; |
23c3960d SA |
305 | const struct imx_pin_reg *pin_reg; |
306 | u32 reg; | |
307 | ||
308 | /* | |
309 | * Only Vybrid has the input/output buffer enable flags (IBE/OBE) | |
310 | * They are part of the shared mux/conf register. | |
311 | */ | |
312 | if (!(info->flags & SHARE_MUX_CONF_REG)) | |
313 | return; | |
314 | ||
315 | pin_reg = &info->pin_regs[offset]; | |
316 | if (pin_reg->mux_reg == -1) | |
317 | return; | |
318 | ||
319 | /* Clear IBE/OBE/PUE to disable the pin (Hi-Z) */ | |
320 | reg = readl(ipctl->base + pin_reg->mux_reg); | |
321 | reg &= ~0x7; | |
322 | writel(reg, ipctl->base + pin_reg->mux_reg); | |
323 | } | |
324 | ||
1f2b0452 SA |
325 | static int imx_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, |
326 | struct pinctrl_gpio_range *range, unsigned offset, bool input) | |
327 | { | |
328 | struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); | |
b28742be | 329 | struct imx_pinctrl_soc_info *info = ipctl->info; |
1f2b0452 SA |
330 | const struct imx_pin_reg *pin_reg; |
331 | u32 reg; | |
332 | ||
333 | /* | |
334 | * Only Vybrid has the input/output buffer enable flags (IBE/OBE) | |
335 | * They are part of the shared mux/conf register. | |
336 | */ | |
337 | if (!(info->flags & SHARE_MUX_CONF_REG)) | |
430be10d | 338 | return 0; |
1f2b0452 SA |
339 | |
340 | pin_reg = &info->pin_regs[offset]; | |
341 | if (pin_reg->mux_reg == -1) | |
342 | return -EINVAL; | |
343 | ||
344 | /* IBE always enabled allows us to read the value "on the wire" */ | |
345 | reg = readl(ipctl->base + pin_reg->mux_reg); | |
346 | if (input) | |
347 | reg &= ~0x2; | |
348 | else | |
349 | reg |= 0x2; | |
350 | writel(reg, ipctl->base + pin_reg->mux_reg); | |
351 | ||
352 | return 0; | |
353 | } | |
354 | ||
022ab148 | 355 | static const struct pinmux_ops imx_pmx_ops = { |
3fd6d6ad GB |
356 | .get_functions_count = pinmux_generic_get_function_count, |
357 | .get_function_name = pinmux_generic_get_function_name, | |
358 | .get_function_groups = pinmux_generic_get_function_groups, | |
03e9f0ca | 359 | .set_mux = imx_pmx_set, |
1f2b0452 | 360 | .gpio_request_enable = imx_pmx_gpio_request_enable, |
23c3960d | 361 | .gpio_disable_free = imx_pmx_gpio_disable_free, |
1f2b0452 | 362 | .gpio_set_direction = imx_pmx_gpio_set_direction, |
ae75ff81 DA |
363 | }; |
364 | ||
a5cadbbb DA |
365 | /* decode generic config into raw register values */ |
366 | static u32 imx_pinconf_decode_generic_config(struct imx_pinctrl *ipctl, | |
367 | unsigned long *configs, | |
368 | unsigned int num_configs) | |
369 | { | |
370 | struct imx_pinctrl_soc_info *info = ipctl->info; | |
371 | struct imx_cfg_params_decode *decode; | |
372 | enum pin_config_param param; | |
373 | u32 raw_config = 0; | |
374 | u32 param_val; | |
375 | int i, j; | |
376 | ||
377 | WARN_ON(num_configs > info->num_decodes); | |
378 | ||
379 | for (i = 0; i < num_configs; i++) { | |
380 | param = pinconf_to_config_param(configs[i]); | |
381 | param_val = pinconf_to_config_argument(configs[i]); | |
382 | decode = info->decodes; | |
383 | for (j = 0; j < info->num_decodes; j++) { | |
384 | if (param == decode->param) { | |
385 | if (decode->invert) | |
386 | param_val = !param_val; | |
387 | raw_config |= (param_val << decode->shift) | |
388 | & decode->mask; | |
389 | break; | |
390 | } | |
391 | decode++; | |
392 | } | |
393 | } | |
394 | ||
395 | if (info->fixup) | |
396 | info->fixup(configs, num_configs, &raw_config); | |
397 | ||
398 | return raw_config; | |
399 | } | |
400 | ||
401 | static u32 imx_pinconf_parse_generic_config(struct device_node *np, | |
402 | struct imx_pinctrl *ipctl) | |
403 | { | |
404 | struct imx_pinctrl_soc_info *info = ipctl->info; | |
405 | struct pinctrl_dev *pctl = ipctl->pctl; | |
406 | unsigned int num_configs; | |
407 | unsigned long *configs; | |
408 | int ret; | |
409 | ||
410 | if (!info->generic_pinconf) | |
411 | return 0; | |
412 | ||
413 | ret = pinconf_generic_parse_dt_config(np, pctl, &configs, | |
414 | &num_configs); | |
415 | if (ret) | |
416 | return 0; | |
417 | ||
418 | return imx_pinconf_decode_generic_config(ipctl, configs, num_configs); | |
419 | } | |
420 | ||
ae75ff81 DA |
421 | static int imx_pinconf_get(struct pinctrl_dev *pctldev, |
422 | unsigned pin_id, unsigned long *config) | |
423 | { | |
424 | struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); | |
b28742be | 425 | struct imx_pinctrl_soc_info *info = ipctl->info; |
e1641531 | 426 | const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id]; |
ae75ff81 | 427 | |
3dac1918 | 428 | if (pin_reg->conf_reg == -1) { |
ae75ff81 DA |
429 | dev_err(info->dev, "Pin(%s) does not support config function\n", |
430 | info->pins[pin_id].name); | |
431 | return -EINVAL; | |
432 | } | |
433 | ||
434 | *config = readl(ipctl->base + pin_reg->conf_reg); | |
435 | ||
bf5a5309 JL |
436 | if (info->flags & SHARE_MUX_CONF_REG) |
437 | *config &= 0xffff; | |
438 | ||
ae75ff81 DA |
439 | return 0; |
440 | } | |
441 | ||
442 | static int imx_pinconf_set(struct pinctrl_dev *pctldev, | |
03b054e9 SY |
443 | unsigned pin_id, unsigned long *configs, |
444 | unsigned num_configs) | |
ae75ff81 DA |
445 | { |
446 | struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); | |
b28742be | 447 | struct imx_pinctrl_soc_info *info = ipctl->info; |
e1641531 | 448 | const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id]; |
03b054e9 | 449 | int i; |
ae75ff81 | 450 | |
3dac1918 | 451 | if (pin_reg->conf_reg == -1) { |
ae75ff81 DA |
452 | dev_err(info->dev, "Pin(%s) does not support config function\n", |
453 | info->pins[pin_id].name); | |
454 | return -EINVAL; | |
455 | } | |
456 | ||
457 | dev_dbg(ipctl->dev, "pinconf set pin %s\n", | |
458 | info->pins[pin_id].name); | |
459 | ||
03b054e9 SY |
460 | for (i = 0; i < num_configs; i++) { |
461 | if (info->flags & SHARE_MUX_CONF_REG) { | |
462 | u32 reg; | |
463 | reg = readl(ipctl->base + pin_reg->conf_reg); | |
464 | reg &= ~0xffff; | |
465 | reg |= configs[i]; | |
466 | writel(reg, ipctl->base + pin_reg->conf_reg); | |
66b54e3a DA |
467 | dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n", |
468 | pin_reg->conf_reg, reg); | |
03b054e9 SY |
469 | } else { |
470 | writel(configs[i], ipctl->base + pin_reg->conf_reg); | |
66b54e3a DA |
471 | dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%lx\n", |
472 | pin_reg->conf_reg, configs[i]); | |
03b054e9 | 473 | } |
03b054e9 | 474 | } /* for each config */ |
ae75ff81 DA |
475 | |
476 | return 0; | |
477 | } | |
478 | ||
479 | static void imx_pinconf_dbg_show(struct pinctrl_dev *pctldev, | |
480 | struct seq_file *s, unsigned pin_id) | |
481 | { | |
482 | struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); | |
b28742be | 483 | struct imx_pinctrl_soc_info *info = ipctl->info; |
e1641531 | 484 | const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id]; |
ae75ff81 DA |
485 | unsigned long config; |
486 | ||
4ff0f034 | 487 | if (!pin_reg || pin_reg->conf_reg == -1) { |
ae75ff81 DA |
488 | seq_printf(s, "N/A"); |
489 | return; | |
490 | } | |
491 | ||
492 | config = readl(ipctl->base + pin_reg->conf_reg); | |
493 | seq_printf(s, "0x%lx", config); | |
494 | } | |
495 | ||
496 | static void imx_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, | |
497 | struct seq_file *s, unsigned group) | |
498 | { | |
e566fc11 | 499 | struct group_desc *grp; |
ae75ff81 DA |
500 | unsigned long config; |
501 | const char *name; | |
502 | int i, ret; | |
503 | ||
e566fc11 | 504 | if (group > pctldev->num_groups) |
ae75ff81 DA |
505 | return; |
506 | ||
507 | seq_printf(s, "\n"); | |
e566fc11 | 508 | grp = pinctrl_generic_get_group(pctldev, group); |
a51c158b GB |
509 | if (!grp) |
510 | return; | |
511 | ||
e566fc11 GB |
512 | for (i = 0; i < grp->num_pins; i++) { |
513 | struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i]; | |
514 | ||
8f903f8a SH |
515 | name = pin_get_name(pctldev, pin->pin); |
516 | ret = imx_pinconf_get(pctldev, pin->pin, &config); | |
ae75ff81 DA |
517 | if (ret) |
518 | return; | |
a2d16a21 | 519 | seq_printf(s, " %s: 0x%lx\n", name, config); |
ae75ff81 DA |
520 | } |
521 | } | |
522 | ||
022ab148 | 523 | static const struct pinconf_ops imx_pinconf_ops = { |
ae75ff81 DA |
524 | .pin_config_get = imx_pinconf_get, |
525 | .pin_config_set = imx_pinconf_set, | |
526 | .pin_config_dbg_show = imx_pinconf_dbg_show, | |
527 | .pin_config_group_dbg_show = imx_pinconf_group_dbg_show, | |
528 | }; | |
529 | ||
e1641531 SG |
530 | /* |
531 | * Each pin represented in fsl,pins consists of 5 u32 PIN_FUNC_ID and | |
532 | * 1 u32 CONFIG, so 24 types in total for each pin. | |
533 | */ | |
534 | #define FSL_PIN_SIZE 24 | |
bf5a5309 | 535 | #define SHARE_FSL_PIN_SIZE 20 |
ae75ff81 | 536 | |
150632b0 | 537 | static int imx_pinctrl_parse_groups(struct device_node *np, |
e566fc11 | 538 | struct group_desc *grp, |
a5cadbbb | 539 | struct imx_pinctrl *ipctl, |
150632b0 | 540 | u32 index) |
ae75ff81 | 541 | { |
a5cadbbb | 542 | struct imx_pinctrl_soc_info *info = ipctl->info; |
bf5a5309 | 543 | int size, pin_size; |
a695145b | 544 | const __be32 *list; |
e1641531 | 545 | int i; |
ae75ff81 DA |
546 | u32 config; |
547 | ||
548 | dev_dbg(info->dev, "group(%d): %s\n", index, np->name); | |
549 | ||
bf5a5309 JL |
550 | if (info->flags & SHARE_MUX_CONF_REG) |
551 | pin_size = SHARE_FSL_PIN_SIZE; | |
552 | else | |
553 | pin_size = FSL_PIN_SIZE; | |
a5cadbbb DA |
554 | |
555 | if (info->generic_pinconf) | |
556 | pin_size -= 4; | |
557 | ||
ae75ff81 DA |
558 | /* Initialise group */ |
559 | grp->name = np->name; | |
560 | ||
561 | /* | |
562 | * the binding format is fsl,pins = <PIN_FUNC_ID CONFIG ...>, | |
563 | * do sanity check and calculate pins number | |
a5cadbbb DA |
564 | * |
565 | * First try legacy 'fsl,pins' property, then fall back to the | |
566 | * generic 'pins'. | |
567 | * | |
568 | * Note: for generic 'pins' case, there's no CONFIG part in | |
569 | * the binding format. | |
ae75ff81 DA |
570 | */ |
571 | list = of_get_property(np, "fsl,pins", &size); | |
1bf1fea9 | 572 | if (!list) { |
a5cadbbb DA |
573 | list = of_get_property(np, "pins", &size); |
574 | if (!list) { | |
575 | dev_err(info->dev, | |
576 | "no fsl,pins and pins property in node %s\n", | |
577 | np->full_name); | |
578 | return -EINVAL; | |
579 | } | |
1bf1fea9 SH |
580 | } |
581 | ||
ae75ff81 | 582 | /* we do not check return since it's safe node passed down */ |
bf5a5309 | 583 | if (!size || size % pin_size) { |
a5cadbbb DA |
584 | dev_err(info->dev, "Invalid fsl,pins or pins property in node %s\n", |
585 | np->full_name); | |
ae75ff81 DA |
586 | return -EINVAL; |
587 | } | |
588 | ||
a5cadbbb DA |
589 | /* first try to parse the generic pin config */ |
590 | config = imx_pinconf_parse_generic_config(np, ipctl); | |
591 | ||
e566fc11 GB |
592 | grp->num_pins = size / pin_size; |
593 | grp->data = devm_kzalloc(info->dev, grp->num_pins * | |
594 | sizeof(struct imx_pin), GFP_KERNEL); | |
595 | grp->pins = devm_kzalloc(info->dev, grp->num_pins * | |
596 | sizeof(unsigned int), GFP_KERNEL); | |
597 | if (!grp->pins || !grp->data) | |
8f903f8a SH |
598 | return -ENOMEM; |
599 | ||
e566fc11 | 600 | for (i = 0; i < grp->num_pins; i++) { |
e1641531 | 601 | u32 mux_reg = be32_to_cpu(*list++); |
bf5a5309 JL |
602 | u32 conf_reg; |
603 | unsigned int pin_id; | |
604 | struct imx_pin_reg *pin_reg; | |
e566fc11 | 605 | struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i]; |
e1641531 | 606 | |
e7b37a52 AA |
607 | if (!(info->flags & ZERO_OFFSET_VALID) && !mux_reg) |
608 | mux_reg = -1; | |
609 | ||
16837f95 | 610 | if (info->flags & SHARE_MUX_CONF_REG) { |
bf5a5309 | 611 | conf_reg = mux_reg; |
16837f95 | 612 | } else { |
bf5a5309 | 613 | conf_reg = be32_to_cpu(*list++); |
16837f95 MP |
614 | if (!conf_reg) |
615 | conf_reg = -1; | |
616 | } | |
bf5a5309 | 617 | |
e7b37a52 | 618 | pin_id = (mux_reg != -1) ? mux_reg / 4 : conf_reg / 4; |
bf5a5309 | 619 | pin_reg = &info->pin_regs[pin_id]; |
8f903f8a | 620 | pin->pin = pin_id; |
e566fc11 | 621 | grp->pins[i] = pin_id; |
e1641531 SG |
622 | pin_reg->mux_reg = mux_reg; |
623 | pin_reg->conf_reg = conf_reg; | |
8f903f8a SH |
624 | pin->input_reg = be32_to_cpu(*list++); |
625 | pin->mux_mode = be32_to_cpu(*list++); | |
626 | pin->input_val = be32_to_cpu(*list++); | |
e1641531 | 627 | |
a5cadbbb DA |
628 | if (info->generic_pinconf) { |
629 | /* generic pin config decoded */ | |
630 | pin->config = config; | |
631 | } else { | |
632 | /* legacy pin config read from devicetree */ | |
633 | config = be32_to_cpu(*list++); | |
634 | ||
635 | /* SION bit is in mux register */ | |
636 | if (config & IMX_PAD_SION) | |
637 | pin->mux_mode |= IOMUXC_CONFIG_SION; | |
638 | pin->config = config & ~IMX_PAD_SION; | |
639 | } | |
ae75ff81 | 640 | |
08b51953 | 641 | dev_dbg(info->dev, "%s: 0x%x 0x%08lx", info->pins[pin_id].name, |
40604469 SH |
642 | pin->mux_mode, pin->config); |
643 | } | |
3a86a5f8 | 644 | |
ae75ff81 DA |
645 | return 0; |
646 | } | |
647 | ||
150632b0 | 648 | static int imx_pinctrl_parse_functions(struct device_node *np, |
e566fc11 | 649 | struct imx_pinctrl *ipctl, |
150632b0 | 650 | u32 index) |
ae75ff81 | 651 | { |
e566fc11 GB |
652 | struct pinctrl_dev *pctl = ipctl->pctl; |
653 | struct imx_pinctrl_soc_info *info = ipctl->info; | |
ae75ff81 | 654 | struct device_node *child; |
3fd6d6ad | 655 | struct function_desc *func; |
e566fc11 | 656 | struct group_desc *grp; |
ae75ff81 DA |
657 | u32 i = 0; |
658 | ||
659 | dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name); | |
660 | ||
3fd6d6ad | 661 | func = pinmux_generic_get_function(pctl, index); |
a51c158b GB |
662 | if (!func) |
663 | return -EINVAL; | |
ae75ff81 DA |
664 | |
665 | /* Initialise function */ | |
666 | func->name = np->name; | |
3fd6d6ad GB |
667 | func->num_group_names = of_get_child_count(np); |
668 | if (func->num_group_names == 0) { | |
01312513 | 669 | dev_err(info->dev, "no groups defined in %s\n", np->full_name); |
ae75ff81 DA |
670 | return -EINVAL; |
671 | } | |
49af64e6 | 672 | func->group_names = devm_kcalloc(info->dev, func->num_group_names, |
3fd6d6ad | 673 | sizeof(char *), GFP_KERNEL); |
49af64e6 CJ |
674 | if (!func->group_names) |
675 | return -ENOMEM; | |
ae75ff81 DA |
676 | |
677 | for_each_child_of_node(np, child) { | |
3fd6d6ad | 678 | func->group_names[i] = child->name; |
a51c158b | 679 | |
e566fc11 | 680 | grp = devm_kzalloc(info->dev, sizeof(struct group_desc), |
a51c158b GB |
681 | GFP_KERNEL); |
682 | if (!grp) | |
683 | return -ENOMEM; | |
684 | ||
685 | mutex_lock(&info->mutex); | |
e566fc11 GB |
686 | radix_tree_insert(&pctl->pin_group_tree, |
687 | info->group_index++, grp); | |
a51c158b GB |
688 | mutex_unlock(&info->mutex); |
689 | ||
a5cadbbb | 690 | imx_pinctrl_parse_groups(child, grp, ipctl, i++); |
ae75ff81 DA |
691 | } |
692 | ||
693 | return 0; | |
694 | } | |
695 | ||
5fcdf6a7 MP |
696 | /* |
697 | * Check if the DT contains pins in the direct child nodes. This indicates the | |
698 | * newer DT format to store pins. This function returns true if the first found | |
699 | * fsl,pins property is in a child of np. Otherwise false is returned. | |
700 | */ | |
701 | static bool imx_pinctrl_dt_is_flat_functions(struct device_node *np) | |
702 | { | |
703 | struct device_node *function_np; | |
704 | struct device_node *pinctrl_np; | |
705 | ||
706 | for_each_child_of_node(np, function_np) { | |
707 | if (of_property_read_bool(function_np, "fsl,pins")) | |
708 | return true; | |
709 | ||
710 | for_each_child_of_node(function_np, pinctrl_np) { | |
711 | if (of_property_read_bool(pinctrl_np, "fsl,pins")) | |
712 | return false; | |
713 | } | |
714 | } | |
715 | ||
716 | return true; | |
717 | } | |
718 | ||
150632b0 | 719 | static int imx_pinctrl_probe_dt(struct platform_device *pdev, |
e566fc11 | 720 | struct imx_pinctrl *ipctl) |
ae75ff81 DA |
721 | { |
722 | struct device_node *np = pdev->dev.of_node; | |
723 | struct device_node *child; | |
e566fc11 GB |
724 | struct pinctrl_dev *pctl = ipctl->pctl; |
725 | struct imx_pinctrl_soc_info *info = ipctl->info; | |
ae75ff81 DA |
726 | u32 nfuncs = 0; |
727 | u32 i = 0; | |
5fcdf6a7 | 728 | bool flat_funcs; |
ae75ff81 DA |
729 | |
730 | if (!np) | |
731 | return -ENODEV; | |
732 | ||
5fcdf6a7 MP |
733 | flat_funcs = imx_pinctrl_dt_is_flat_functions(np); |
734 | if (flat_funcs) { | |
735 | nfuncs = 1; | |
736 | } else { | |
737 | nfuncs = of_get_child_count(np); | |
738 | if (nfuncs <= 0) { | |
739 | dev_err(&pdev->dev, "no functions defined\n"); | |
740 | return -EINVAL; | |
741 | } | |
ae75ff81 DA |
742 | } |
743 | ||
a51c158b | 744 | for (i = 0; i < nfuncs; i++) { |
3fd6d6ad | 745 | struct function_desc *function; |
a51c158b GB |
746 | |
747 | function = devm_kzalloc(&pdev->dev, sizeof(*function), | |
ae75ff81 | 748 | GFP_KERNEL); |
a51c158b GB |
749 | if (!function) |
750 | return -ENOMEM; | |
751 | ||
752 | mutex_lock(&info->mutex); | |
3fd6d6ad | 753 | radix_tree_insert(&pctl->pin_function_tree, i, function); |
a51c158b GB |
754 | mutex_unlock(&info->mutex); |
755 | } | |
3fd6d6ad | 756 | pctl->num_functions = nfuncs; |
ae75ff81 | 757 | |
9999fe5d | 758 | info->group_index = 0; |
5fcdf6a7 | 759 | if (flat_funcs) { |
e566fc11 | 760 | pctl->num_groups = of_get_child_count(np); |
5fcdf6a7 | 761 | } else { |
e566fc11 | 762 | pctl->num_groups = 0; |
5fcdf6a7 | 763 | for_each_child_of_node(np, child) |
e566fc11 | 764 | pctl->num_groups += of_get_child_count(child); |
5fcdf6a7 | 765 | } |
ae75ff81 | 766 | |
5fcdf6a7 | 767 | if (flat_funcs) { |
e566fc11 | 768 | imx_pinctrl_parse_functions(np, ipctl, 0); |
5fcdf6a7 | 769 | } else { |
a51c158b | 770 | i = 0; |
5fcdf6a7 | 771 | for_each_child_of_node(np, child) |
e566fc11 | 772 | imx_pinctrl_parse_functions(child, ipctl, i++); |
5fcdf6a7 | 773 | } |
ae75ff81 DA |
774 | |
775 | return 0; | |
776 | } | |
777 | ||
a51c158b GB |
778 | /* |
779 | * imx_free_resources() - free memory used by this driver | |
780 | * @info: info driver instance | |
781 | */ | |
782 | static void imx_free_resources(struct imx_pinctrl *ipctl) | |
783 | { | |
784 | if (ipctl->pctl) | |
785 | pinctrl_unregister(ipctl->pctl); | |
a51c158b GB |
786 | } |
787 | ||
150632b0 GKH |
788 | int imx_pinctrl_probe(struct platform_device *pdev, |
789 | struct imx_pinctrl_soc_info *info) | |
ae75ff81 | 790 | { |
8626ada8 | 791 | struct regmap_config config = { .name = "gpr" }; |
26d8cde5 | 792 | struct device_node *dev_np = pdev->dev.of_node; |
6e408ed8 | 793 | struct pinctrl_desc *imx_pinctrl_desc; |
26d8cde5 | 794 | struct device_node *np; |
ae75ff81 DA |
795 | struct imx_pinctrl *ipctl; |
796 | struct resource *res; | |
8626ada8 | 797 | struct regmap *gpr; |
4691dd01 | 798 | int ret, i; |
ae75ff81 | 799 | |
e1641531 | 800 | if (!info || !info->pins || !info->npins) { |
ae75ff81 DA |
801 | dev_err(&pdev->dev, "wrong pinctrl info\n"); |
802 | return -EINVAL; | |
803 | } | |
804 | info->dev = &pdev->dev; | |
805 | ||
8626ada8 PZ |
806 | if (info->gpr_compatible) { |
807 | gpr = syscon_regmap_lookup_by_compatible(info->gpr_compatible); | |
808 | if (!IS_ERR(gpr)) | |
809 | regmap_attach_dev(&pdev->dev, gpr, &config); | |
810 | } | |
811 | ||
ae75ff81 DA |
812 | /* Create state holders etc for this driver */ |
813 | ipctl = devm_kzalloc(&pdev->dev, sizeof(*ipctl), GFP_KERNEL); | |
814 | if (!ipctl) | |
815 | return -ENOMEM; | |
816 | ||
3dac1918 | 817 | info->pin_regs = devm_kmalloc(&pdev->dev, sizeof(*info->pin_regs) * |
e1641531 SG |
818 | info->npins, GFP_KERNEL); |
819 | if (!info->pin_regs) | |
820 | return -ENOMEM; | |
4691dd01 SA |
821 | |
822 | for (i = 0; i < info->npins; i++) { | |
823 | info->pin_regs[i].mux_reg = -1; | |
824 | info->pin_regs[i].conf_reg = -1; | |
825 | } | |
e1641531 | 826 | |
ae75ff81 | 827 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
9e0c1fb2 TR |
828 | ipctl->base = devm_ioremap_resource(&pdev->dev, res); |
829 | if (IS_ERR(ipctl->base)) | |
830 | return PTR_ERR(ipctl->base); | |
ae75ff81 | 831 | |
26d8cde5 AA |
832 | if (of_property_read_bool(dev_np, "fsl,input-sel")) { |
833 | np = of_parse_phandle(dev_np, "fsl,input-sel", 0); | |
9a4f4245 | 834 | if (!np) { |
26d8cde5 AA |
835 | dev_err(&pdev->dev, "iomuxc fsl,input-sel property not found\n"); |
836 | return -EINVAL; | |
837 | } | |
9a4f4245 VZ |
838 | |
839 | ipctl->input_sel_base = of_iomap(np, 0); | |
26d8cde5 | 840 | of_node_put(np); |
9a4f4245 VZ |
841 | if (!ipctl->input_sel_base) { |
842 | dev_err(&pdev->dev, | |
843 | "iomuxc input select base address not found\n"); | |
844 | return -ENOMEM; | |
845 | } | |
26d8cde5 AA |
846 | } |
847 | ||
6e408ed8 PF |
848 | imx_pinctrl_desc = devm_kzalloc(&pdev->dev, sizeof(*imx_pinctrl_desc), |
849 | GFP_KERNEL); | |
850 | if (!imx_pinctrl_desc) | |
851 | return -ENOMEM; | |
852 | ||
853 | imx_pinctrl_desc->name = dev_name(&pdev->dev); | |
854 | imx_pinctrl_desc->pins = info->pins; | |
855 | imx_pinctrl_desc->npins = info->npins; | |
8f5983ad GB |
856 | imx_pinctrl_desc->pctlops = &imx_pctrl_ops; |
857 | imx_pinctrl_desc->pmxops = &imx_pmx_ops; | |
858 | imx_pinctrl_desc->confops = &imx_pinconf_ops; | |
859 | imx_pinctrl_desc->owner = THIS_MODULE; | |
ae75ff81 | 860 | |
a5cadbbb DA |
861 | /* for generic pinconf */ |
862 | imx_pinctrl_desc->custom_params = info->custom_params; | |
863 | imx_pinctrl_desc->num_custom_params = info->num_custom_params; | |
864 | ||
a51c158b GB |
865 | mutex_init(&info->mutex); |
866 | ||
ae75ff81 DA |
867 | ipctl->info = info; |
868 | ipctl->dev = info->dev; | |
869 | platform_set_drvdata(pdev, ipctl); | |
950b0d91 TL |
870 | ret = devm_pinctrl_register_and_init(&pdev->dev, |
871 | imx_pinctrl_desc, ipctl, | |
872 | &ipctl->pctl); | |
873 | if (ret) { | |
ae75ff81 | 874 | dev_err(&pdev->dev, "could not register IMX pinctrl driver\n"); |
a51c158b | 875 | goto free; |
ae75ff81 DA |
876 | } |
877 | ||
e566fc11 GB |
878 | ret = imx_pinctrl_probe_dt(pdev, ipctl); |
879 | if (ret) { | |
880 | dev_err(&pdev->dev, "fail to probe dt properties\n"); | |
881 | goto free; | |
882 | } | |
883 | ||
ae75ff81 DA |
884 | dev_info(&pdev->dev, "initialized IMX pinctrl driver\n"); |
885 | ||
61187142 | 886 | return pinctrl_enable(ipctl->pctl); |
a51c158b GB |
887 | |
888 | free: | |
889 | imx_free_resources(ipctl); | |
890 | ||
891 | return ret; | |
ae75ff81 | 892 | } |