[mirror_ubuntu-artful-kernel.git] / drivers / pinctrl / intel / pinctrl-baytrail.c

/*
 * Pinctrl GPIO driver for Intel Baytrail
 * Copyright (c) 2012-2013, Intel Corporation.
 *
 * Author: Mathias Nyman <mathias.nyman@linux.intel.com>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program; if not, write to the Free Software Foundation, Inc.,
 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
 *
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/types.h>
#include <linux/bitops.h>
#include <linux/interrupt.h>
#include <linux/gpio.h>
#include <linux/acpi.h>
#include <linux/platform_device.h>
#include <linux/seq_file.h>
#include <linux/io.h>
#include <linux/pm_runtime.h>
#include <linux/pinctrl/pinctrl.h>

/* memory mapped register offsets */
#define BYT_CONF0_REG		0x000
#define BYT_CONF1_REG		0x004
#define BYT_VAL_REG		0x008
#define BYT_DFT_REG		0x00c
#define BYT_INT_STAT_REG	0x800

/* BYT_CONF0_REG register bits */
#define BYT_IODEN		BIT(31)
#define BYT_DIRECT_IRQ_EN	BIT(27)
#define BYT_TRIG_NEG		BIT(26)
#define BYT_TRIG_POS		BIT(25)
#define BYT_TRIG_LVL		BIT(24)
#define BYT_PULL_STR_SHIFT	9
#define BYT_PULL_STR_MASK	(3 << BYT_PULL_STR_SHIFT)
#define BYT_PULL_STR_2K		(0 << BYT_PULL_STR_SHIFT)
#define BYT_PULL_STR_10K	(1 << BYT_PULL_STR_SHIFT)
#define BYT_PULL_STR_20K	(2 << BYT_PULL_STR_SHIFT)
#define BYT_PULL_STR_40K	(3 << BYT_PULL_STR_SHIFT)
#define BYT_PULL_ASSIGN_SHIFT	7
#define BYT_PULL_ASSIGN_MASK	(3 << BYT_PULL_ASSIGN_SHIFT)
#define BYT_PULL_ASSIGN_UP	(1 << BYT_PULL_ASSIGN_SHIFT)
#define BYT_PULL_ASSIGN_DOWN	(2 << BYT_PULL_ASSIGN_SHIFT)
#define BYT_PIN_MUX		0x07

/* BYT_VAL_REG register bits */
#define BYT_INPUT_EN		BIT(2)  /* 0: input enabled (active low)*/
#define BYT_OUTPUT_EN		BIT(1)  /* 0: output enabled (active low)*/
#define BYT_LEVEL		BIT(0)

#define BYT_DIR_MASK		(BIT(1) | BIT(2))
#define BYT_TRIG_MASK		(BIT(26) | BIT(25) | BIT(24))

#define BYT_NGPIO_SCORE		102
#define BYT_NGPIO_NCORE		28
#define BYT_NGPIO_SUS		44

#define BYT_SCORE_ACPI_UID	"1"
#define BYT_NCORE_ACPI_UID	"2"
#define BYT_SUS_ACPI_UID	"3"

/*
 * Baytrail gpio controller consist of three separate sub-controllers called
 * SCORE, NCORE and SUS. The sub-controllers are identified by their acpi UID.
 *
 * GPIO numbering is _not_ ordered meaning that gpio # 0 in ACPI namespace does
 * _not_ correspond to the first gpio register at controller's gpio base.
 * There is no logic or pattern in mapping gpio numbers to registers (pads) so
 * each sub-controller needs to have its own mapping table
 */

/* score_pins[gpio_nr] = pad_nr */

static unsigned const score_pins[BYT_NGPIO_SCORE] = {
	85, 89, 93, 96, 99, 102, 98, 101, 34, 37,
	36, 38, 39, 35, 40, 84, 62, 61, 64, 59,
	54, 56, 60, 55, 63, 57, 51, 50, 53, 47,
	52, 49, 48, 43, 46, 41, 45, 42, 58, 44,
	95, 105, 70, 68, 67, 66, 69, 71, 65, 72,
	86, 90, 88, 92, 103, 77, 79, 83, 78, 81,
	80, 82, 13, 12, 15, 14, 17, 18, 19, 16,
	2, 1, 0, 4, 6, 7, 9, 8, 33, 32,
	31, 30, 29, 27, 25, 28, 26, 23, 21, 20,
	24, 22, 5, 3, 10, 11, 106, 87, 91, 104,
	97, 100,
};

static unsigned const ncore_pins[BYT_NGPIO_NCORE] = {
	19, 18, 17, 20, 21, 22, 24, 25, 23, 16,
	14, 15, 12, 26, 27, 1, 4, 8, 11, 0,
	3, 6, 10, 13, 2, 5, 9, 7,
};

static unsigned const sus_pins[BYT_NGPIO_SUS] = {
	29, 33, 30, 31, 32, 34, 36, 35, 38, 37,
	18, 7, 11, 20, 17, 1, 8, 10, 19, 12,
	0, 2, 23, 39, 28, 27, 22, 21, 24, 25,
	26, 51, 56, 54, 49, 55, 48, 57, 50, 58,
	52, 53, 59, 40,
};

static struct pinctrl_gpio_range byt_ranges[] = {
	{
		.name = BYT_SCORE_ACPI_UID, /* match with acpi _UID in probe */
		.npins = BYT_NGPIO_SCORE,
		.pins = score_pins,
	},
	{
		.name = BYT_NCORE_ACPI_UID,
		.npins = BYT_NGPIO_NCORE,
		.pins = ncore_pins,
	},
	{
		.name = BYT_SUS_ACPI_UID,
		.npins = BYT_NGPIO_SUS,
		.pins = sus_pins,
	},
	{
	},
};

struct byt_gpio {
	struct gpio_chip		chip;
	struct platform_device		*pdev;
	spinlock_t			lock;
	void __iomem			*reg_base;
	struct pinctrl_gpio_range	*range;
};

#define to_byt_gpio(c)	container_of(c, struct byt_gpio, chip)

static void __iomem *byt_gpio_reg(struct gpio_chip *chip, unsigned offset,
				 int reg)
{
	struct byt_gpio *vg = to_byt_gpio(chip);
	u32 reg_offset;

	if (reg == BYT_INT_STAT_REG)
		reg_offset = (offset / 32) * 4;
	else
		reg_offset = vg->range->pins[offset] * 16;

	return vg->reg_base + reg_offset + reg;
}

static void byt_gpio_clear_triggering(struct byt_gpio *vg, unsigned offset)
{
	void __iomem *reg = byt_gpio_reg(&vg->chip, offset, BYT_CONF0_REG);
	unsigned long flags;
	u32 value;

	spin_lock_irqsave(&vg->lock, flags);
	value = readl(reg);
	value &= ~(BYT_TRIG_POS | BYT_TRIG_NEG | BYT_TRIG_LVL);
	writel(value, reg);
	spin_unlock_irqrestore(&vg->lock, flags);
}

static u32 byt_get_gpio_mux(struct byt_gpio *vg, unsigned offset)
{
	/* SCORE pin 92-93 */
	if (!strcmp(vg->range->name, BYT_SCORE_ACPI_UID) &&
		offset >= 92 && offset <= 93)
		return 1;

	/* SUS pin 11-21 */
	if (!strcmp(vg->range->name, BYT_SUS_ACPI_UID) &&
		offset >= 11 && offset <= 21)
		return 1;

	return 0;
}

static int byt_gpio_request(struct gpio_chip *chip, unsigned offset)
{
	struct byt_gpio *vg = to_byt_gpio(chip);
	void __iomem *reg = byt_gpio_reg(chip, offset, BYT_CONF0_REG);
	u32 value, gpio_mux;

	/*
	 * In most cases, func pin mux 000 means GPIO function.
	 * But, some pins may have func pin mux 001 represents
	 * GPIO function.
	 *
	 * Because there are devices out there where some pins were not
	 * configured correctly we allow changing the mux value from
	 * request (but print out warning about that).
	 */
	value = readl(reg) & BYT_PIN_MUX;
	gpio_mux = byt_get_gpio_mux(vg, offset);
	if (WARN_ON(gpio_mux != value)) {
		unsigned long flags;

		spin_lock_irqsave(&vg->lock, flags);
		value = readl(reg) & ~BYT_PIN_MUX;
		value |= gpio_mux;
		writel(value, reg);
		spin_unlock_irqrestore(&vg->lock, flags);

		dev_warn(&vg->pdev->dev,
			 "pin %u forcibly re-configured as GPIO\n", offset);
	}

	pm_runtime_get(&vg->pdev->dev);

	return 0;
}

static void byt_gpio_free(struct gpio_chip *chip, unsigned offset)
{
	struct byt_gpio *vg = to_byt_gpio(chip);

	byt_gpio_clear_triggering(vg, offset);
	pm_runtime_put(&vg->pdev->dev);
}

static int byt_irq_type(struct irq_data *d, unsigned type)
{
	struct byt_gpio *vg = to_byt_gpio(irq_data_get_irq_chip_data(d));
	u32 offset = irqd_to_hwirq(d);
	u32 value;
	unsigned long flags;
	void __iomem *reg = byt_gpio_reg(&vg->chip, offset, BYT_CONF0_REG);

	if (offset >= vg->chip.ngpio)
		return -EINVAL;

	spin_lock_irqsave(&vg->lock, flags);
	value = readl(reg);

	WARN(value & BYT_DIRECT_IRQ_EN,
		"Bad pad config for io mode, force direct_irq_en bit clearing");

	/* For level trigges the BYT_TRIG_POS and BYT_TRIG_NEG bits
	 * are used to indicate high and low level triggering
	 */
	value &= ~(BYT_DIRECT_IRQ_EN | BYT_TRIG_POS | BYT_TRIG_NEG |
		   BYT_TRIG_LVL);

	writel(value, reg);

	if (type & IRQ_TYPE_EDGE_BOTH)
		__irq_set_handler_locked(d->irq, handle_edge_irq);
	else if (type & IRQ_TYPE_LEVEL_MASK)
		__irq_set_handler_locked(d->irq, handle_level_irq);

	spin_unlock_irqrestore(&vg->lock, flags);

	return 0;
}

static int byt_gpio_get(struct gpio_chip *chip, unsigned offset)
{
	void __iomem *reg = byt_gpio_reg(chip, offset, BYT_VAL_REG);
	return readl(reg) & BYT_LEVEL;
}

static void byt_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
	struct byt_gpio *vg = to_byt_gpio(chip);
	void __iomem *reg = byt_gpio_reg(chip, offset, BYT_VAL_REG);
	unsigned long flags;
	u32 old_val;

	spin_lock_irqsave(&vg->lock, flags);

	old_val = readl(reg);

	if (value)
		writel(old_val | BYT_LEVEL, reg);
	else
		writel(old_val & ~BYT_LEVEL, reg);

	spin_unlock_irqrestore(&vg->lock, flags);
}

static int byt_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
{
	struct byt_gpio *vg = to_byt_gpio(chip);
	void __iomem *reg = byt_gpio_reg(chip, offset, BYT_VAL_REG);
	unsigned long flags;
	u32 value;

	spin_lock_irqsave(&vg->lock, flags);

	value = readl(reg) | BYT_DIR_MASK;
	value &= ~BYT_INPUT_EN;		/* active low */
	writel(value, reg);

	spin_unlock_irqrestore(&vg->lock, flags);

	return 0;
}

static int byt_gpio_direction_output(struct gpio_chip *chip,
				     unsigned gpio, int value)
{
	struct byt_gpio *vg = to_byt_gpio(chip);
	void __iomem *conf_reg = byt_gpio_reg(chip, gpio, BYT_CONF0_REG);
	void __iomem *reg = byt_gpio_reg(chip, gpio, BYT_VAL_REG);
	unsigned long flags;
	u32 reg_val;

	spin_lock_irqsave(&vg->lock, flags);

	/*
	 * Before making any direction modifications, do a check if gpio
	 * is set for direct IRQ.  On baytrail, setting GPIO to output does
	 * not make sense, so let's at least warn the caller before they shoot
	 * themselves in the foot.
	 */
	WARN(readl(conf_reg) & BYT_DIRECT_IRQ_EN,
		"Potential Error: Setting GPIO with direct_irq_en to output");

	reg_val = readl(reg) | BYT_DIR_MASK;
	reg_val &= ~(BYT_OUTPUT_EN | BYT_INPUT_EN);

	if (value)
		writel(reg_val | BYT_LEVEL, reg);
	else
		writel(reg_val & ~BYT_LEVEL, reg);

	spin_unlock_irqrestore(&vg->lock, flags);

	return 0;
}

static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
{
	struct byt_gpio *vg = to_byt_gpio(chip);
	int i;
	unsigned long flags;
	u32 conf0, val, offs;

	spin_lock_irqsave(&vg->lock, flags);

	for (i = 0; i < vg->chip.ngpio; i++) {
		const char *pull_str = NULL;
		const char *pull = NULL;
		const char *label;
		offs = vg->range->pins[i] * 16;
		conf0 = readl(vg->reg_base + offs + BYT_CONF0_REG);
		val = readl(vg->reg_base + offs + BYT_VAL_REG);

		label = gpiochip_is_requested(chip, i);
		if (!label)
			label = "Unrequested";

		switch (conf0 & BYT_PULL_ASSIGN_MASK) {
		case BYT_PULL_ASSIGN_UP:
			pull = "up";
			break;
		case BYT_PULL_ASSIGN_DOWN:
			pull = "down";
			break;
		}

		switch (conf0 & BYT_PULL_STR_MASK) {
		case BYT_PULL_STR_2K:
			pull_str = "2k";
			break;
		case BYT_PULL_STR_10K:
			pull_str = "10k";
			break;
		case BYT_PULL_STR_20K:
			pull_str = "20k";
			break;
		case BYT_PULL_STR_40K:
			pull_str = "40k";
			break;
		}

		seq_printf(s,
			   " gpio-%-3d (%-20.20s) %s %s %s pad-%-3d offset:0x%03x mux:%d %s%s%s",
			   i,
			   label,
			   val & BYT_INPUT_EN ? "  " : "in",
			   val & BYT_OUTPUT_EN ? "   " : "out",
			   val & BYT_LEVEL ? "hi" : "lo",
			   vg->range->pins[i], offs,
			   conf0 & 0x7,
			   conf0 & BYT_TRIG_NEG ? " fall" : "     ",
			   conf0 & BYT_TRIG_POS ? " rise" : "     ",
			   conf0 & BYT_TRIG_LVL ? " level" : "      ");

		if (pull && pull_str)
			seq_printf(s, " %-4s %-3s", pull, pull_str);
		else
			seq_puts(s, "          ");

		if (conf0 & BYT_IODEN)
			seq_puts(s, " open-drain");

		seq_puts(s, "\n");
	}
	spin_unlock_irqrestore(&vg->lock, flags);
}

static void byt_gpio_irq_handler(unsigned irq, struct irq_desc *desc)
{
	struct irq_data *data = irq_desc_get_irq_data(desc);
	struct byt_gpio *vg = to_byt_gpio(irq_desc_get_handler_data(desc));
	struct irq_chip *chip = irq_data_get_irq_chip(data);
	u32 base, pin;
	void __iomem *reg;
	unsigned long pending;
	unsigned virq;

	/* check from GPIO controller which pin triggered the interrupt */
	for (base = 0; base < vg->chip.ngpio; base += 32) {
		reg = byt_gpio_reg(&vg->chip, base, BYT_INT_STAT_REG);
		pending = readl(reg);
		for_each_set_bit(pin, &pending, 32) {
			virq = irq_find_mapping(vg->chip.irqdomain, base + pin);
			generic_handle_irq(virq);
		}
	}
	chip->irq_eoi(data);
}

static void byt_irq_ack(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct byt_gpio *vg = to_byt_gpio(gc);
	unsigned offset = irqd_to_hwirq(d);
	void __iomem *reg;

	reg = byt_gpio_reg(&vg->chip, offset, BYT_INT_STAT_REG);
	writel(BIT(offset % 32), reg);
}

static void byt_irq_unmask(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct byt_gpio *vg = to_byt_gpio(gc);
	unsigned offset = irqd_to_hwirq(d);
	unsigned long flags;
	void __iomem *reg;
	u32 value;

	spin_lock_irqsave(&vg->lock, flags);

	reg = byt_gpio_reg(&vg->chip, offset, BYT_CONF0_REG);
	value = readl(reg);

	switch (irqd_get_trigger_type(d)) {
	case IRQ_TYPE_LEVEL_HIGH:
		value |= BYT_TRIG_LVL;
	case IRQ_TYPE_EDGE_RISING:
		value |= BYT_TRIG_POS;
		break;
	case IRQ_TYPE_LEVEL_LOW:
		value |= BYT_TRIG_LVL;
	case IRQ_TYPE_EDGE_FALLING:
		value |= BYT_TRIG_NEG;
		break;
	case IRQ_TYPE_EDGE_BOTH:
		value |= (BYT_TRIG_NEG | BYT_TRIG_POS);
		break;
	}

	writel(value, reg);

	spin_unlock_irqrestore(&vg->lock, flags);
}

static void byt_irq_mask(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct byt_gpio *vg = to_byt_gpio(gc);

	byt_gpio_clear_triggering(vg, irqd_to_hwirq(d));
}

static struct irq_chip byt_irqchip = {
	.name = "BYT-GPIO",
	.irq_ack = byt_irq_ack,
	.irq_mask = byt_irq_mask,
	.irq_unmask = byt_irq_unmask,
	.irq_set_type = byt_irq_type,
	.flags = IRQCHIP_SKIP_SET_WAKE,
};

static void byt_gpio_irq_init_hw(struct byt_gpio *vg)
{
	void __iomem *reg;
	u32 base, value;
	int i;

	/*
	 * Clear interrupt triggers for all pins that are GPIOs and
	 * do not use direct IRQ mode. This will prevent spurious
	 * interrupts from misconfigured pins.
	 */
	for (i = 0; i < vg->chip.ngpio; i++) {
		value = readl(byt_gpio_reg(&vg->chip, i, BYT_CONF0_REG));
		if ((value & BYT_PIN_MUX) == byt_get_gpio_mux(vg, i) &&
		    !(value & BYT_DIRECT_IRQ_EN)) {
			byt_gpio_clear_triggering(vg, i);
			dev_dbg(&vg->pdev->dev, "disabling GPIO %d\n", i);
		}
	}

	/* clear interrupt status trigger registers */
	for (base = 0; base < vg->chip.ngpio; base += 32) {
		reg = byt_gpio_reg(&vg->chip, base, BYT_INT_STAT_REG);
		writel(0xffffffff, reg);
		/* make sure trigger bits are cleared, if not then a pin
		   might be misconfigured in bios */
		value = readl(reg);
		if (value)
			dev_err(&vg->pdev->dev,
				"GPIO interrupt error, pins misconfigured\n");
	}
}

static int byt_gpio_probe(struct platform_device *pdev)
{
	struct byt_gpio *vg;
	struct gpio_chip *gc;
	struct resource *mem_rc, *irq_rc;
	struct device *dev = &pdev->dev;
	struct acpi_device *acpi_dev;
	struct pinctrl_gpio_range *range;
	acpi_handle handle = ACPI_HANDLE(dev);
	int ret;

	if (acpi_bus_get_device(handle, &acpi_dev))
		return -ENODEV;

	vg = devm_kzalloc(dev, sizeof(struct byt_gpio), GFP_KERNEL);
	if (!vg) {
		dev_err(&pdev->dev, "can't allocate byt_gpio chip data\n");
		return -ENOMEM;
	}

	for (range = byt_ranges; range->name; range++) {
		if (!strcmp(acpi_dev->pnp.unique_id, range->name)) {
			vg->chip.ngpio = range->npins;
			vg->range = range;
			break;
		}
	}

	if (!vg->chip.ngpio || !vg->range)
		return -ENODEV;

	vg->pdev = pdev;
	platform_set_drvdata(pdev, vg);

	mem_rc = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	vg->reg_base = devm_ioremap_resource(dev, mem_rc);
	if (IS_ERR(vg->reg_base))
		return PTR_ERR(vg->reg_base);

	spin_lock_init(&vg->lock);

	gc = &vg->chip;
	gc->label = dev_name(&pdev->dev);
	gc->owner = THIS_MODULE;
	gc->request = byt_gpio_request;
	gc->free = byt_gpio_free;
	gc->direction_input = byt_gpio_direction_input;
	gc->direction_output = byt_gpio_direction_output;
	gc->get = byt_gpio_get;
	gc->set = byt_gpio_set;
	gc->dbg_show = byt_gpio_dbg_show;
	gc->base = -1;
	gc->can_sleep = false;
	gc->dev = dev;

	ret = gpiochip_add(gc);
	if (ret) {
		dev_err(&pdev->dev, "failed adding byt-gpio chip\n");
		return ret;
	}

	/* set up interrupts  */
	irq_rc = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
	if (irq_rc && irq_rc->start) {
		byt_gpio_irq_init_hw(vg);
		ret = gpiochip_irqchip_add(gc, &byt_irqchip, 0,
					   handle_simple_irq, IRQ_TYPE_NONE);
		if (ret) {
			dev_err(dev, "failed to add irqchip\n");
			gpiochip_remove(gc);
			return ret;
		}

		gpiochip_set_chained_irqchip(gc, &byt_irqchip,
					     (unsigned)irq_rc->start,
					     byt_gpio_irq_handler);
	}

	pm_runtime_enable(dev);

	return 0;
}

static int byt_gpio_runtime_suspend(struct device *dev)
{
	return 0;
}

static int byt_gpio_runtime_resume(struct device *dev)
{
	return 0;
}

static const struct dev_pm_ops byt_gpio_pm_ops = {
	.runtime_suspend = byt_gpio_runtime_suspend,
	.runtime_resume = byt_gpio_runtime_resume,
};

static const struct acpi_device_id byt_gpio_acpi_match[] = {
	{ "INT33B2", 0 },
	{ "INT33FC", 0 },
	{ }
};
MODULE_DEVICE_TABLE(acpi, byt_gpio_acpi_match);

static int byt_gpio_remove(struct platform_device *pdev)
{
	struct byt_gpio *vg = platform_get_drvdata(pdev);

	pm_runtime_disable(&pdev->dev);
	gpiochip_remove(&vg->chip);

	return 0;
}

static struct platform_driver byt_gpio_driver = {
	.probe          = byt_gpio_probe,
	.remove         = byt_gpio_remove,
	.driver         = {
		.name   = "byt_gpio",
		.pm	= &byt_gpio_pm_ops,
		.acpi_match_table = ACPI_PTR(byt_gpio_acpi_match),
	},
};

static int __init byt_gpio_init(void)
{
	return platform_driver_register(&byt_gpio_driver);
}
subsys_initcall(byt_gpio_init);

static void __exit byt_gpio_exit(void)
{
	platform_driver_unregister(&byt_gpio_driver);
}
module_exit(byt_gpio_exit);
Commit	Line	Data
a5d811bb MN	1	/*
	2	* Pinctrl GPIO driver for Intel Baytrail
	3	* Copyright (c) 2012-2013, Intel Corporation.
	4	*
	5	* Author: Mathias Nyman <mathias.nyman@linux.intel.com>
	6	*
	7	* This program is free software; you can redistribute it and/or modify it
	8	* under the terms and conditions of the GNU General Public License,
	9	* version 2, as published by the Free Software Foundation.
	10	*
	11	* This program is distributed in the hope it will be useful, but WITHOUT
	12	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	13	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	14	* more details.
	15	*
	16	* You should have received a copy of the GNU General Public License along with
	17	* this program; if not, write to the Free Software Foundation, Inc.,
	18	* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
	19	*
	20	*/
	21
	22	#include <linux/kernel.h>
	23	#include <linux/module.h>
	24	#include <linux/init.h>
	25	#include <linux/types.h>
	26	#include <linux/bitops.h>
	27	#include <linux/interrupt.h>
a5d811bb	28	#include <linux/gpio.h>
a5d811bb	29	#include <linux/acpi.h>
a5d811bb MN	30	#include <linux/platform_device.h>
	31	#include <linux/seq_file.h>
	32	#include <linux/io.h>
	33	#include <linux/pm_runtime.h>
	34	#include <linux/pinctrl/pinctrl.h>
	35
	36	/* memory mapped register offsets */
	37	#define BYT_CONF0_REG 0x000
	38	#define BYT_CONF1_REG 0x004
	39	#define BYT_VAL_REG 0x008
	40	#define BYT_DFT_REG 0x00c
	41	#define BYT_INT_STAT_REG 0x800
	42
	43	/* BYT_CONF0_REG register bits */
3ff95885	44	#define BYT_IODEN BIT(31)
ff998356	45	#define BYT_DIRECT_IRQ_EN BIT(27)
a5d811bb MN	46	#define BYT_TRIG_NEG BIT(26)
	47	#define BYT_TRIG_POS BIT(25)
	48	#define BYT_TRIG_LVL BIT(24)
3ff95885 MW	49	#define BYT_PULL_STR_SHIFT 9
	50	#define BYT_PULL_STR_MASK (3 << BYT_PULL_STR_SHIFT)
	51	#define BYT_PULL_STR_2K (0 << BYT_PULL_STR_SHIFT)
	52	#define BYT_PULL_STR_10K (1 << BYT_PULL_STR_SHIFT)
	53	#define BYT_PULL_STR_20K (2 << BYT_PULL_STR_SHIFT)
	54	#define BYT_PULL_STR_40K (3 << BYT_PULL_STR_SHIFT)
	55	#define BYT_PULL_ASSIGN_SHIFT 7
	56	#define BYT_PULL_ASSIGN_MASK (3 << BYT_PULL_ASSIGN_SHIFT)
	57	#define BYT_PULL_ASSIGN_UP (1 << BYT_PULL_ASSIGN_SHIFT)
	58	#define BYT_PULL_ASSIGN_DOWN (2 << BYT_PULL_ASSIGN_SHIFT)
a5d811bb MN	59	#define BYT_PIN_MUX 0x07
	60
	61	/* BYT_VAL_REG register bits */
	62	#define BYT_INPUT_EN BIT(2) /* 0: input enabled (active low)*/
	63	#define BYT_OUTPUT_EN BIT(1) /* 0: output enabled (active low)*/
	64	#define BYT_LEVEL BIT(0)
	65
	66	#define BYT_DIR_MASK (BIT(1) \| BIT(2))
	67	#define BYT_TRIG_MASK (BIT(26) \| BIT(25) \| BIT(24))
	68
	69	#define BYT_NGPIO_SCORE 102
	70	#define BYT_NGPIO_NCORE 28
	71	#define BYT_NGPIO_SUS 44
	72
42bd0070 CKH	73	#define BYT_SCORE_ACPI_UID "1"
	74	#define BYT_NCORE_ACPI_UID "2"
	75	#define BYT_SUS_ACPI_UID "3"
	76
a5d811bb MN	77	/*
	78	* Baytrail gpio controller consist of three separate sub-controllers called
	79	* SCORE, NCORE and SUS. The sub-controllers are identified by their acpi UID.
	80	*
	81	* GPIO numbering is _not_ ordered meaning that gpio # 0 in ACPI namespace does
	82	* _not_ correspond to the first gpio register at controller's gpio base.
	83	* There is no logic or pattern in mapping gpio numbers to registers (pads) so
	84	* each sub-controller needs to have its own mapping table
	85	*/
	86
	87	/* score_pins[gpio_nr] = pad_nr */
	88
	89	static unsigned const score_pins[BYT_NGPIO_SCORE] = {
	90	85, 89, 93, 96, 99, 102, 98, 101, 34, 37,
	91	36, 38, 39, 35, 40, 84, 62, 61, 64, 59,
	92	54, 56, 60, 55, 63, 57, 51, 50, 53, 47,
	93	52, 49, 48, 43, 46, 41, 45, 42, 58, 44,
	94	95, 105, 70, 68, 67, 66, 69, 71, 65, 72,
	95	86, 90, 88, 92, 103, 77, 79, 83, 78, 81,
	96	80, 82, 13, 12, 15, 14, 17, 18, 19, 16,
	97	2, 1, 0, 4, 6, 7, 9, 8, 33, 32,
	98	31, 30, 29, 27, 25, 28, 26, 23, 21, 20,
	99	24, 22, 5, 3, 10, 11, 106, 87, 91, 104,
	100	97, 100,
	101	};
	102
	103	static unsigned const ncore_pins[BYT_NGPIO_NCORE] = {
	104	19, 18, 17, 20, 21, 22, 24, 25, 23, 16,
	105	14, 15, 12, 26, 27, 1, 4, 8, 11, 0,
	106	3, 6, 10, 13, 2, 5, 9, 7,
	107	};
	108
	109	static unsigned const sus_pins[BYT_NGPIO_SUS] = {
	110	29, 33, 30, 31, 32, 34, 36, 35, 38, 37,
	111	18, 7, 11, 20, 17, 1, 8, 10, 19, 12,
	112	0, 2, 23, 39, 28, 27, 22, 21, 24, 25,
	113	26, 51, 56, 54, 49, 55, 48, 57, 50, 58,
	114	52, 53, 59, 40,
	115	};
	116
	117	static struct pinctrl_gpio_range byt_ranges[] = {
	118	{
42bd0070	119	.name = BYT_SCORE_ACPI_UID, /* match with acpi _UID in probe */
a5d811bb MN	120	.npins = BYT_NGPIO_SCORE,
	121	.pins = score_pins,
	122	},
	123	{
42bd0070	124	.name = BYT_NCORE_ACPI_UID,
a5d811bb MN	125	.npins = BYT_NGPIO_NCORE,
	126	.pins = ncore_pins,
	127	},
	128	{
42bd0070	129	.name = BYT_SUS_ACPI_UID,
a5d811bb MN	130	.npins = BYT_NGPIO_SUS,
	131	.pins = sus_pins,
	132	},
	133	{
	134	},
	135	};
	136
	137	struct byt_gpio {
	138	struct gpio_chip chip;
a5d811bb MN	139	struct platform_device *pdev;
	140	spinlock_t lock;
	141	void __iomem *reg_base;
	142	struct pinctrl_gpio_range *range;
	143	};
	144
17e52464 AS	145	#define to_byt_gpio(c) container_of(c, struct byt_gpio, chip)
17e52464 AS	146
a5d811bb MN	147	static void __iomem byt_gpio_reg(struct gpio_chip chip, unsigned offset,
	148	int reg)
	149	{
17e52464	150	struct byt_gpio *vg = to_byt_gpio(chip);
a5d811bb	151	u32 reg_offset;
a5d811bb MN	152
	153	if (reg == BYT_INT_STAT_REG)
	154	reg_offset = (offset / 32) * 4;
	155	else
	156	reg_offset = vg->range->pins[offset] * 16;
	157
9c5b6557	158	return vg->reg_base + reg_offset + reg;
a5d811bb MN	159	}
a5d811bb MN	160
95f0972c MW	161	static void byt_gpio_clear_triggering(struct byt_gpio *vg, unsigned offset)
	162	{
	163	void __iomem *reg = byt_gpio_reg(&vg->chip, offset, BYT_CONF0_REG);
	164	unsigned long flags;
	165	u32 value;
	166
	167	spin_lock_irqsave(&vg->lock, flags);
	168	value = readl(reg);
	169	value &= ~(BYT_TRIG_POS \| BYT_TRIG_NEG \| BYT_TRIG_LVL);
	170	writel(value, reg);
	171	spin_unlock_irqrestore(&vg->lock, flags);
	172	}
	173
f8323b6b	174	static u32 byt_get_gpio_mux(struct byt_gpio *vg, unsigned offset)
42bd0070 CKH	175	{
	176	/* SCORE pin 92-93 */
	177	if (!strcmp(vg->range->name, BYT_SCORE_ACPI_UID) &&
	178	offset >= 92 && offset <= 93)
f8323b6b	179	return 1;
42bd0070 CKH	180
	181	/* SUS pin 11-21 */
	182	if (!strcmp(vg->range->name, BYT_SUS_ACPI_UID) &&
	183	offset >= 11 && offset <= 21)
f8323b6b	184	return 1;
42bd0070	185
f8323b6b	186	return 0;
42bd0070 CKH	187	}
42bd0070 CKH	188
a5d811bb MN	189	static int byt_gpio_request(struct gpio_chip *chip, unsigned offset)
a5d811bb MN	190	{
17e52464	191	struct byt_gpio *vg = to_byt_gpio(chip);
42bd0070	192	void __iomem *reg = byt_gpio_reg(chip, offset, BYT_CONF0_REG);
f8323b6b	193	u32 value, gpio_mux;
42bd0070 CKH	194
	195	/*
	196	* In most cases, func pin mux 000 means GPIO function.
	197	* But, some pins may have func pin mux 001 represents
f8323b6b MW	198	* GPIO function.
	199	*
	200	* Because there are devices out there where some pins were not
	201	* configured correctly we allow changing the mux value from
	202	* request (but print out warning about that).
42bd0070 CKH	203	*/
42bd0070 CKH	204	value = readl(reg) & BYT_PIN_MUX;
f8323b6b MW	205	gpio_mux = byt_get_gpio_mux(vg, offset);
	206	if (WARN_ON(gpio_mux != value)) {
	207	unsigned long flags;
	208
	209	spin_lock_irqsave(&vg->lock, flags);
	210	value = readl(reg) & ~BYT_PIN_MUX;
	211	value \|= gpio_mux;
	212	writel(value, reg);
	213	spin_unlock_irqrestore(&vg->lock, flags);
	214
	215	dev_warn(&vg->pdev->dev,
	216	"pin %u forcibly re-configured as GPIO\n", offset);
42bd0070	217	}
a5d811bb MN	218
	219	pm_runtime_get(&vg->pdev->dev);
	220
	221	return 0;
	222	}
	223
	224	static void byt_gpio_free(struct gpio_chip *chip, unsigned offset)
	225	{
17e52464	226	struct byt_gpio *vg = to_byt_gpio(chip);
a5d811bb	227
95f0972c	228	byt_gpio_clear_triggering(vg, offset);
a5d811bb MN	229	pm_runtime_put(&vg->pdev->dev);
	230	}
	231
	232	static int byt_irq_type(struct irq_data *d, unsigned type)
	233	{
e1ee5c57	234	struct byt_gpio *vg = to_byt_gpio(irq_data_get_irq_chip_data(d));
a5d811bb MN	235	u32 offset = irqd_to_hwirq(d);
	236	u32 value;
	237	unsigned long flags;
	238	void __iomem *reg = byt_gpio_reg(&vg->chip, offset, BYT_CONF0_REG);
	239
	240	if (offset >= vg->chip.ngpio)
	241	return -EINVAL;
	242
	243	spin_lock_irqsave(&vg->lock, flags);
	244	value = readl(reg);
	245
3a71c05e LP	246	WARN(value & BYT_DIRECT_IRQ_EN,
	247	"Bad pad config for io mode, force direct_irq_en bit clearing");
	248
a5d811bb MN	249	/* For level trigges the BYT_TRIG_POS and BYT_TRIG_NEG bits
	250	* are used to indicate high and low level triggering
	251	*/
3a71c05e LP	252	value &= ~(BYT_DIRECT_IRQ_EN \| BYT_TRIG_POS \| BYT_TRIG_NEG \|
3a71c05e LP	253	BYT_TRIG_LVL);
a5d811bb	254
a5d811bb MN	255	writel(value, reg);
a5d811bb MN	256
31e4329f MW	257	if (type & IRQ_TYPE_EDGE_BOTH)
	258	__irq_set_handler_locked(d->irq, handle_edge_irq);
	259	else if (type & IRQ_TYPE_LEVEL_MASK)
	260	__irq_set_handler_locked(d->irq, handle_level_irq);
	261
a5d811bb MN	262	spin_unlock_irqrestore(&vg->lock, flags);
	263
	264	return 0;
	265	}
	266
	267	static int byt_gpio_get(struct gpio_chip *chip, unsigned offset)
	268	{
	269	void __iomem *reg = byt_gpio_reg(chip, offset, BYT_VAL_REG);
	270	return readl(reg) & BYT_LEVEL;
	271	}
	272
	273	static void byt_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
	274	{
17e52464	275	struct byt_gpio *vg = to_byt_gpio(chip);
a5d811bb MN	276	void __iomem *reg = byt_gpio_reg(chip, offset, BYT_VAL_REG);
	277	unsigned long flags;
	278	u32 old_val;
	279
	280	spin_lock_irqsave(&vg->lock, flags);
	281
	282	old_val = readl(reg);
	283
	284	if (value)
	285	writel(old_val \| BYT_LEVEL, reg);
	286	else
	287	writel(old_val & ~BYT_LEVEL, reg);
	288
	289	spin_unlock_irqrestore(&vg->lock, flags);
	290	}
	291
	292	static int byt_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
	293	{
17e52464	294	struct byt_gpio *vg = to_byt_gpio(chip);
a5d811bb MN	295	void __iomem *reg = byt_gpio_reg(chip, offset, BYT_VAL_REG);
	296	unsigned long flags;
	297	u32 value;
	298
	299	spin_lock_irqsave(&vg->lock, flags);
	300
	301	value = readl(reg) \| BYT_DIR_MASK;
496940c1	302	value &= ~BYT_INPUT_EN; /* active low */
a5d811bb MN	303	writel(value, reg);
	304
	305	spin_unlock_irqrestore(&vg->lock, flags);
	306
	307	return 0;
	308	}
	309
	310	static int byt_gpio_direction_output(struct gpio_chip *chip,
	311	unsigned gpio, int value)
	312	{
17e52464	313	struct byt_gpio *vg = to_byt_gpio(chip);
ff998356	314	void __iomem *conf_reg = byt_gpio_reg(chip, gpio, BYT_CONF0_REG);
a5d811bb MN	315	void __iomem *reg = byt_gpio_reg(chip, gpio, BYT_VAL_REG);
	316	unsigned long flags;
	317	u32 reg_val;
	318
	319	spin_lock_irqsave(&vg->lock, flags);
	320
ff998356 EE	321	/*
	322	* Before making any direction modifications, do a check if gpio
	323	* is set for direct IRQ. On baytrail, setting GPIO to output does
	324	* not make sense, so let's at least warn the caller before they shoot
	325	* themselves in the foot.
	326	*/
	327	WARN(readl(conf_reg) & BYT_DIRECT_IRQ_EN,
	328	"Potential Error: Setting GPIO with direct_irq_en to output");
	329
496940c1	330	reg_val = readl(reg) \| BYT_DIR_MASK;
d90c3381	331	reg_val &= ~(BYT_OUTPUT_EN \| BYT_INPUT_EN);
496940c1 AS	332
	333	if (value)
	334	writel(reg_val \| BYT_LEVEL, reg);
	335	else
	336	writel(reg_val & ~BYT_LEVEL, reg);
a5d811bb MN	337
	338	spin_unlock_irqrestore(&vg->lock, flags);
	339
	340	return 0;
	341	}
	342
	343	static void byt_gpio_dbg_show(struct seq_file s, struct gpio_chip chip)
	344	{
17e52464	345	struct byt_gpio *vg = to_byt_gpio(chip);
a5d811bb MN	346	int i;
	347	unsigned long flags;
	348	u32 conf0, val, offs;
	349
	350	spin_lock_irqsave(&vg->lock, flags);
	351
	352	for (i = 0; i < vg->chip.ngpio; i++) {
3ff95885 MW	353	const char *pull_str = NULL;
3ff95885 MW	354	const char *pull = NULL;
a4d8d6da	355	const char *label;
a5d811bb MN	356	offs = vg->range->pins[i] * 16;
	357	conf0 = readl(vg->reg_base + offs + BYT_CONF0_REG);
	358	val = readl(vg->reg_base + offs + BYT_VAL_REG);
	359
a4d8d6da MN	360	label = gpiochip_is_requested(chip, i);
	361	if (!label)
	362	label = "Unrequested";
	363
3ff95885 MW	364	switch (conf0 & BYT_PULL_ASSIGN_MASK) {
	365	case BYT_PULL_ASSIGN_UP:
	366	pull = "up";
	367	break;
	368	case BYT_PULL_ASSIGN_DOWN:
	369	pull = "down";
	370	break;
	371	}
	372
	373	switch (conf0 & BYT_PULL_STR_MASK) {
	374	case BYT_PULL_STR_2K:
	375	pull_str = "2k";
	376	break;
	377	case BYT_PULL_STR_10K:
	378	pull_str = "10k";
	379	break;
	380	case BYT_PULL_STR_20K:
	381	pull_str = "20k";
	382	break;
	383	case BYT_PULL_STR_40K:
	384	pull_str = "40k";
	385	break;
	386	}
	387
a5d811bb	388	seq_printf(s,
3ff95885	389	" gpio-%-3d (%-20.20s) %s %s %s pad-%-3d offset:0x%03x mux:%d %s%s%s",
a5d811bb	390	i,
a4d8d6da	391	label,
a5d811bb MN	392	val & BYT_INPUT_EN ? " " : "in",
	393	val & BYT_OUTPUT_EN ? " " : "out",
	394	val & BYT_LEVEL ? "hi" : "lo",
	395	vg->range->pins[i], offs,
	396	conf0 & 0x7,
3ff95885 MW	397	conf0 & BYT_TRIG_NEG ? " fall" : " ",
	398	conf0 & BYT_TRIG_POS ? " rise" : " ",
	399	conf0 & BYT_TRIG_LVL ? " level" : " ");
	400
	401	if (pull && pull_str)
	402	seq_printf(s, " %-4s %-3s", pull, pull_str);
	403	else
	404	seq_puts(s, " ");
	405
	406	if (conf0 & BYT_IODEN)
	407	seq_puts(s, " open-drain");
	408
	409	seq_puts(s, "\n");
a5d811bb MN	410	}
	411	spin_unlock_irqrestore(&vg->lock, flags);
	412	}
	413
a5d811bb MN	414	static void byt_gpio_irq_handler(unsigned irq, struct irq_desc *desc)
	415	{
	416	struct irq_data *data = irq_desc_get_irq_data(desc);
e1ee5c57	417	struct byt_gpio *vg = to_byt_gpio(irq_desc_get_handler_data(desc));
a5d811bb	418	struct irq_chip *chip = irq_data_get_irq_chip(data);
31e4329f	419	u32 base, pin;
a5d811bb	420	void __iomem *reg;
31e4329f	421	unsigned long pending;
a5d811bb	422	unsigned virq;
a5d811bb MN	423
	424	/* check from GPIO controller which pin triggered the interrupt */
	425	for (base = 0; base < vg->chip.ngpio; base += 32) {
a5d811bb	426	reg = byt_gpio_reg(&vg->chip, base, BYT_INT_STAT_REG);
31e4329f MW	427	pending = readl(reg);
31e4329f MW	428	for_each_set_bit(pin, &pending, 32) {
e1ee5c57	429	virq = irq_find_mapping(vg->chip.irqdomain, base + pin);
a5d811bb	430	generic_handle_irq(virq);
a5d811bb MN	431	}
	432	}
	433	chip->irq_eoi(data);
	434	}
	435
31e4329f MW	436	static void byt_irq_ack(struct irq_data *d)
	437	{
	438	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	439	struct byt_gpio *vg = to_byt_gpio(gc);
	440	unsigned offset = irqd_to_hwirq(d);
	441	void __iomem *reg;
	442
	443	reg = byt_gpio_reg(&vg->chip, offset, BYT_INT_STAT_REG);
	444	writel(BIT(offset % 32), reg);
	445	}
	446
a5d811bb MN	447	static void byt_irq_unmask(struct irq_data *d)
a5d811bb MN	448	{
31e4329f MW	449	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	450	struct byt_gpio *vg = to_byt_gpio(gc);
	451	unsigned offset = irqd_to_hwirq(d);
	452	unsigned long flags;
	453	void __iomem *reg;
	454	u32 value;
	455
	456	spin_lock_irqsave(&vg->lock, flags);
	457
	458	reg = byt_gpio_reg(&vg->chip, offset, BYT_CONF0_REG);
	459	value = readl(reg);
	460
	461	switch (irqd_get_trigger_type(d)) {
	462	case IRQ_TYPE_LEVEL_HIGH:
	463	value \|= BYT_TRIG_LVL;
	464	case IRQ_TYPE_EDGE_RISING:
	465	value \|= BYT_TRIG_POS;
	466	break;
	467	case IRQ_TYPE_LEVEL_LOW:
	468	value \|= BYT_TRIG_LVL;
	469	case IRQ_TYPE_EDGE_FALLING:
	470	value \|= BYT_TRIG_NEG;
	471	break;
	472	case IRQ_TYPE_EDGE_BOTH:
	473	value \|= (BYT_TRIG_NEG \| BYT_TRIG_POS);
	474	break;
	475	}
	476
	477	writel(value, reg);
	478
	479	spin_unlock_irqrestore(&vg->lock, flags);
a5d811bb MN	480	}
	481
	482	static void byt_irq_mask(struct irq_data *d)
	483	{
31e4329f MW	484	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	485	struct byt_gpio *vg = to_byt_gpio(gc);
	486
	487	byt_gpio_clear_triggering(vg, irqd_to_hwirq(d));
a5d811bb MN	488	}
	489
	490	static struct irq_chip byt_irqchip = {
	491	.name = "BYT-GPIO",
31e4329f	492	.irq_ack = byt_irq_ack,
a5d811bb MN	493	.irq_mask = byt_irq_mask,
	494	.irq_unmask = byt_irq_unmask,
	495	.irq_set_type = byt_irq_type,
41939e69	496	.flags = IRQCHIP_SKIP_SET_WAKE,
a5d811bb MN	497	};
	498
	499	static void byt_gpio_irq_init_hw(struct byt_gpio *vg)
	500	{
	501	void __iomem *reg;
	502	u32 base, value;
95f0972c MW	503	int i;
	504
	505	/*
	506	* Clear interrupt triggers for all pins that are GPIOs and
	507	* do not use direct IRQ mode. This will prevent spurious
	508	* interrupts from misconfigured pins.
	509	*/
	510	for (i = 0; i < vg->chip.ngpio; i++) {
	511	value = readl(byt_gpio_reg(&vg->chip, i, BYT_CONF0_REG));
	512	if ((value & BYT_PIN_MUX) == byt_get_gpio_mux(vg, i) &&
	513	!(value & BYT_DIRECT_IRQ_EN)) {
	514	byt_gpio_clear_triggering(vg, i);
	515	dev_dbg(&vg->pdev->dev, "disabling GPIO %d\n", i);
	516	}
	517	}
a5d811bb MN	518
	519	/* clear interrupt status trigger registers */
	520	for (base = 0; base < vg->chip.ngpio; base += 32) {
	521	reg = byt_gpio_reg(&vg->chip, base, BYT_INT_STAT_REG);
	522	writel(0xffffffff, reg);
	523	/* make sure trigger bits are cleared, if not then a pin
	524	might be misconfigured in bios */
	525	value = readl(reg);
	526	if (value)
	527	dev_err(&vg->pdev->dev,
	528	"GPIO interrupt error, pins misconfigured\n");
	529	}
	530	}
	531
a5d811bb MN	532	static int byt_gpio_probe(struct platform_device *pdev)
	533	{
	534	struct byt_gpio *vg;
	535	struct gpio_chip *gc;
	536	struct resource mem_rc, irq_rc;
	537	struct device *dev = &pdev->dev;
	538	struct acpi_device *acpi_dev;
	539	struct pinctrl_gpio_range *range;
	540	acpi_handle handle = ACPI_HANDLE(dev);
a5d811bb MN	541	int ret;
	542
	543	if (acpi_bus_get_device(handle, &acpi_dev))
	544	return -ENODEV;
	545
	546	vg = devm_kzalloc(dev, sizeof(struct byt_gpio), GFP_KERNEL);
	547	if (!vg) {
	548	dev_err(&pdev->dev, "can't allocate byt_gpio chip data\n");
	549	return -ENOMEM;
	550	}
	551
	552	for (range = byt_ranges; range->name; range++) {
	553	if (!strcmp(acpi_dev->pnp.unique_id, range->name)) {
	554	vg->chip.ngpio = range->npins;
	555	vg->range = range;
	556	break;
	557	}
	558	}
	559
	560	if (!vg->chip.ngpio \|\| !vg->range)
	561	return -ENODEV;
	562
	563	vg->pdev = pdev;
	564	platform_set_drvdata(pdev, vg);
	565
	566	mem_rc = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	567	vg->reg_base = devm_ioremap_resource(dev, mem_rc);
	568	if (IS_ERR(vg->reg_base))
	569	return PTR_ERR(vg->reg_base);
	570
	571	spin_lock_init(&vg->lock);
	572
	573	gc = &vg->chip;
	574	gc->label = dev_name(&pdev->dev);
	575	gc->owner = THIS_MODULE;
	576	gc->request = byt_gpio_request;
	577	gc->free = byt_gpio_free;
	578	gc->direction_input = byt_gpio_direction_input;
	579	gc->direction_output = byt_gpio_direction_output;
	580	gc->get = byt_gpio_get;
	581	gc->set = byt_gpio_set;
	582	gc->dbg_show = byt_gpio_dbg_show;
	583	gc->base = -1;
9fb1f39e	584	gc->can_sleep = false;
a5d811bb MN	585	gc->dev = dev;
a5d811bb MN	586
e1ee5c57 MW	587	ret = gpiochip_add(gc);
	588	if (ret) {
	589	dev_err(&pdev->dev, "failed adding byt-gpio chip\n");
	590	return ret;
	591	}
	592
a5d811bb MN	593	/* set up interrupts */
	594	irq_rc = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
	595	if (irq_rc && irq_rc->start) {
a5d811bb	596	byt_gpio_irq_init_hw(vg);
e1ee5c57 MW	597	ret = gpiochip_irqchip_add(gc, &byt_irqchip, 0,
	598	handle_simple_irq, IRQ_TYPE_NONE);
	599	if (ret) {
	600	dev_err(dev, "failed to add irqchip\n");
	601	gpiochip_remove(gc);
	602	return ret;
	603	}
a5d811bb	604
e1ee5c57 MW	605	gpiochip_set_chained_irqchip(gc, &byt_irqchip,
	606	(unsigned)irq_rc->start,
	607	byt_gpio_irq_handler);
605a7bca JY	608	}
605a7bca JY	609
a5d811bb MN	610	pm_runtime_enable(dev);
	611
	612	return 0;
	613	}
	614
	615	static int byt_gpio_runtime_suspend(struct device *dev)
	616	{
	617	return 0;
	618	}
	619
	620	static int byt_gpio_runtime_resume(struct device *dev)
	621	{
	622	return 0;
	623	}
	624
	625	static const struct dev_pm_ops byt_gpio_pm_ops = {
	626	.runtime_suspend = byt_gpio_runtime_suspend,
	627	.runtime_resume = byt_gpio_runtime_resume,
	628	};
	629
	630	static const struct acpi_device_id byt_gpio_acpi_match[] = {
	631	{ "INT33B2", 0 },
20482d32	632	{ "INT33FC", 0 },
a5d811bb MN	633	{ }
	634	};
	635	MODULE_DEVICE_TABLE(acpi, byt_gpio_acpi_match);
	636
	637	static int byt_gpio_remove(struct platform_device *pdev)
	638	{
	639	struct byt_gpio *vg = platform_get_drvdata(pdev);
ec243320	640
a5d811bb	641	pm_runtime_disable(&pdev->dev);
b4e7c55d	642	gpiochip_remove(&vg->chip);
a5d811bb MN	643
	644	return 0;
	645	}
	646
	647	static struct platform_driver byt_gpio_driver = {
	648	.probe = byt_gpio_probe,
	649	.remove = byt_gpio_remove,
	650	.driver = {
	651	.name = "byt_gpio",
a5d811bb MN	652	.pm = &byt_gpio_pm_ops,
	653	.acpi_match_table = ACPI_PTR(byt_gpio_acpi_match),
	654	},
	655	};
	656
	657	static int __init byt_gpio_init(void)
	658	{
	659	return platform_driver_register(&byt_gpio_driver);
	660	}
a5d811bb	661	subsys_initcall(byt_gpio_init);
9067bbe5 FB	662
	663	static void __exit byt_gpio_exit(void)
	664	{
	665	platform_driver_unregister(&byt_gpio_driver);
	666	}
	667	module_exit(byt_gpio_exit);