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pinctrl: cannonlake: Fix HOSTSW_OWN register offset of H variant
[mirror_ubuntu-bionic-kernel.git] / drivers / pinctrl / intel / pinctrl-cannonlake.c
CommitLineData
19a8a777
MW		 1/*
2 * Intel Cannon Lake PCH pinctrl/GPIO driver
3 *
4 * Copyright (C) 2017, Intel Corporation
a663ccf0
MW		 5 * Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
6 * Mika Westerberg <mika.westerberg@linux.intel.com>
19a8a777
MW		 7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/acpi.h>
14#include <linux/module.h>
15#include <linux/platform_device.h>
16#include <linux/pm.h>
17#include <linux/pinctrl/pinctrl.h>
18
19#include "pinctrl-intel.h"
20
4e1f37c4
MW		 21#define CNL_PAD_OWN 0x020
22#define CNL_PADCFGLOCK 0x080
23#define CNL_LP_HOSTSW_OWN 0x0b0
24#define CNL_H_HOSTSW_OWN 0x0c0
25#define CNL_GPI_IE 0x120
19a8a777 26
afe63b46 27#define CNL_GPP(r, s, e, g) \
19a8a777
MW		 28 { \
29 .reg_num = (r), \
30 .base = (s), \
31 .size = ((e) - (s) + 1), \
afe63b46 32 .gpio_base = (g), \
19a8a777
MW		 33 }
34
afe63b46
MW		 35#define CNL_NO_GPIO -1
36
4e1f37c4 37#define CNL_COMMUNITY(b, s, e, o, g) \
19a8a777
MW		 38 { \
39 .barno = (b), \
40 .padown_offset = CNL_PAD_OWN, \
41 .padcfglock_offset = CNL_PADCFGLOCK, \
4e1f37c4 42 .hostown_offset = (o), \
19a8a777
MW		 43 .ie_offset = CNL_GPI_IE, \
44 .pin_base = (s), \
45 .npins = ((e) - (s) + 1), \
46 .gpps = (g), \
47 .ngpps = ARRAY_SIZE(g), \
48 }
49
4e1f37c4
MW		 50#define CNLLP_COMMUNITY(b, s, e, g) \
51 CNL_COMMUNITY(b, s, e, CNL_LP_HOSTSW_OWN, g)
52
53#define CNLH_COMMUNITY(b, s, e, g) \
54 CNL_COMMUNITY(b, s, e, CNL_H_HOSTSW_OWN, g)
55
a663ccf0
MW		 56/* Cannon Lake-H */
57static const struct pinctrl_pin_desc cnlh_pins[] = {
58 /* GPP_A */
59 PINCTRL_PIN(0, "RCINB"),
60 PINCTRL_PIN(1, "LAD_0"),
61 PINCTRL_PIN(2, "LAD_1"),
62 PINCTRL_PIN(3, "LAD_2"),
63 PINCTRL_PIN(4, "LAD_3"),
64 PINCTRL_PIN(5, "LFRAMEB"),
65 PINCTRL_PIN(6, "SERIRQ"),
66 PINCTRL_PIN(7, "PIRQAB"),
67 PINCTRL_PIN(8, "CLKRUNB"),
68 PINCTRL_PIN(9, "CLKOUT_LPC_0"),
69 PINCTRL_PIN(10, "CLKOUT_LPC_1"),
70 PINCTRL_PIN(11, "PMEB"),
71 PINCTRL_PIN(12, "BM_BUSYB"),
72 PINCTRL_PIN(13, "SUSWARNB_SUSPWRDNACK"),
73 PINCTRL_PIN(14, "SUS_STATB"),
74 PINCTRL_PIN(15, "SUSACKB"),
75 PINCTRL_PIN(16, "CLKOUT_48"),
76 PINCTRL_PIN(17, "SD_VDD1_PWR_EN_B"),
77 PINCTRL_PIN(18, "ISH_GP_0"),
78 PINCTRL_PIN(19, "ISH_GP_1"),
79 PINCTRL_PIN(20, "ISH_GP_2"),
80 PINCTRL_PIN(21, "ISH_GP_3"),
81 PINCTRL_PIN(22, "ISH_GP_4"),
82 PINCTRL_PIN(23, "ISH_GP_5"),
83 PINCTRL_PIN(24, "ESPI_CLK_LOOPBK"),
84 /* GPP_B */
85 PINCTRL_PIN(25, "GSPI0_CS1B"),
86 PINCTRL_PIN(26, "GSPI1_CS1B"),
87 PINCTRL_PIN(27, "VRALERTB"),
88 PINCTRL_PIN(28, "CPU_GP_2"),
89 PINCTRL_PIN(29, "CPU_GP_3"),
90 PINCTRL_PIN(30, "SRCCLKREQB_0"),
91 PINCTRL_PIN(31, "SRCCLKREQB_1"),
92 PINCTRL_PIN(32, "SRCCLKREQB_2"),
93 PINCTRL_PIN(33, "SRCCLKREQB_3"),
94 PINCTRL_PIN(34, "SRCCLKREQB_4"),
95 PINCTRL_PIN(35, "SRCCLKREQB_5"),
96 PINCTRL_PIN(36, "SSP_MCLK"),
97 PINCTRL_PIN(37, "SLP_S0B"),
98 PINCTRL_PIN(38, "PLTRSTB"),
99 PINCTRL_PIN(39, "SPKR"),
100 PINCTRL_PIN(40, "GSPI0_CS0B"),
101 PINCTRL_PIN(41, "GSPI0_CLK"),
102 PINCTRL_PIN(42, "GSPI0_MISO"),
103 PINCTRL_PIN(43, "GSPI0_MOSI"),
104 PINCTRL_PIN(44, "GSPI1_CS0B"),
105 PINCTRL_PIN(45, "GSPI1_CLK"),
106 PINCTRL_PIN(46, "GSPI1_MISO"),
107 PINCTRL_PIN(47, "GSPI1_MOSI"),
108 PINCTRL_PIN(48, "SML1ALERTB"),
109 PINCTRL_PIN(49, "GSPI0_CLK_LOOPBK"),
110 PINCTRL_PIN(50, "GSPI1_CLK_LOOPBK"),
111 /* GPP_C */
112 PINCTRL_PIN(51, "SMBCLK"),
113 PINCTRL_PIN(52, "SMBDATA"),
114 PINCTRL_PIN(53, "SMBALERTB"),
115 PINCTRL_PIN(54, "SML0CLK"),
116 PINCTRL_PIN(55, "SML0DATA"),
117 PINCTRL_PIN(56, "SML0ALERTB"),
118 PINCTRL_PIN(57, "SML1CLK"),
119 PINCTRL_PIN(58, "SML1DATA"),
120 PINCTRL_PIN(59, "UART0_RXD"),
121 PINCTRL_PIN(60, "UART0_TXD"),
122 PINCTRL_PIN(61, "UART0_RTSB"),
123 PINCTRL_PIN(62, "UART0_CTSB"),
124 PINCTRL_PIN(63, "UART1_RXD"),
125 PINCTRL_PIN(64, "UART1_TXD"),
126 PINCTRL_PIN(65, "UART1_RTSB"),
127 PINCTRL_PIN(66, "UART1_CTSB"),
128 PINCTRL_PIN(67, "I2C0_SDA"),
129 PINCTRL_PIN(68, "I2C0_SCL"),
130 PINCTRL_PIN(69, "I2C1_SDA"),
131 PINCTRL_PIN(70, "I2C1_SCL"),
132 PINCTRL_PIN(71, "UART2_RXD"),
133 PINCTRL_PIN(72, "UART2_TXD"),
134 PINCTRL_PIN(73, "UART2_RTSB"),
135 PINCTRL_PIN(74, "UART2_CTSB"),
136 /* GPP_D */
137 PINCTRL_PIN(75, "SPI1_CSB"),
138 PINCTRL_PIN(76, "SPI1_CLK"),
139 PINCTRL_PIN(77, "SPI1_MISO_IO_1"),
140 PINCTRL_PIN(78, "SPI1_MOSI_IO_0"),
141 PINCTRL_PIN(79, "ISH_I2C2_SDA"),
142 PINCTRL_PIN(80, "SSP2_SFRM"),
143 PINCTRL_PIN(81, "SSP2_TXD"),
144 PINCTRL_PIN(82, "SSP2_RXD"),
145 PINCTRL_PIN(83, "SSP2_SCLK"),
146 PINCTRL_PIN(84, "ISH_SPI_CSB"),
147 PINCTRL_PIN(85, "ISH_SPI_CLK"),
148 PINCTRL_PIN(86, "ISH_SPI_MISO"),
149 PINCTRL_PIN(87, "ISH_SPI_MOSI"),
150 PINCTRL_PIN(88, "ISH_UART0_RXD"),
151 PINCTRL_PIN(89, "ISH_UART0_TXD"),
152 PINCTRL_PIN(90, "ISH_UART0_RTSB"),
153 PINCTRL_PIN(91, "ISH_UART0_CTSB"),
154 PINCTRL_PIN(92, "DMIC_CLK_1"),
155 PINCTRL_PIN(93, "DMIC_DATA_1"),
156 PINCTRL_PIN(94, "DMIC_CLK_0"),
157 PINCTRL_PIN(95, "DMIC_DATA_0"),
158 PINCTRL_PIN(96, "SPI1_IO_2"),
159 PINCTRL_PIN(97, "SPI1_IO_3"),
160 PINCTRL_PIN(98, "ISH_I2C2_SCL"),
161 /* GPP_G */
162 PINCTRL_PIN(99, "SD3_CMD"),
163 PINCTRL_PIN(100, "SD3_D0"),
164 PINCTRL_PIN(101, "SD3_D1"),
165 PINCTRL_PIN(102, "SD3_D2"),
166 PINCTRL_PIN(103, "SD3_D3"),
167 PINCTRL_PIN(104, "SD3_CDB"),
168 PINCTRL_PIN(105, "SD3_CLK"),
169 PINCTRL_PIN(106, "SD3_WP"),
170 /* AZA */
171 PINCTRL_PIN(107, "HDA_BCLK"),
172 PINCTRL_PIN(108, "HDA_RSTB"),
173 PINCTRL_PIN(109, "HDA_SYNC"),
174 PINCTRL_PIN(110, "HDA_SDO"),
175 PINCTRL_PIN(111, "HDA_SDI_0"),
176 PINCTRL_PIN(112, "HDA_SDI_1"),
177 PINCTRL_PIN(113, "SSP1_SFRM"),
178 PINCTRL_PIN(114, "SSP1_TXD"),
179 /* vGPIO */
180 PINCTRL_PIN(115, "CNV_BTEN"),
181 PINCTRL_PIN(116, "CNV_GNEN"),
182 PINCTRL_PIN(117, "CNV_WFEN"),
183 PINCTRL_PIN(118, "CNV_WCEN"),
184 PINCTRL_PIN(119, "CNV_BT_HOST_WAKEB"),
185 PINCTRL_PIN(120, "vCNV_GNSS_HOST_WAKEB"),
186 PINCTRL_PIN(121, "vSD3_CD_B"),
187 PINCTRL_PIN(122, "CNV_BT_IF_SELECT"),
188 PINCTRL_PIN(123, "vCNV_BT_UART_TXD"),
189 PINCTRL_PIN(124, "vCNV_BT_UART_RXD"),
190 PINCTRL_PIN(125, "vCNV_BT_UART_CTS_B"),
191 PINCTRL_PIN(126, "vCNV_BT_UART_RTS_B"),
192 PINCTRL_PIN(127, "vCNV_MFUART1_TXD"),
193 PINCTRL_PIN(128, "vCNV_MFUART1_RXD"),
194 PINCTRL_PIN(129, "vCNV_MFUART1_CTS_B"),
195 PINCTRL_PIN(130, "vCNV_MFUART1_RTS_B"),
196 PINCTRL_PIN(131, "vCNV_GNSS_UART_TXD"),
197 PINCTRL_PIN(132, "vCNV_GNSS_UART_RXD"),
198 PINCTRL_PIN(133, "vCNV_GNSS_UART_CTS_B"),
199 PINCTRL_PIN(134, "vCNV_GNSS_UART_RTS_B"),
200 PINCTRL_PIN(135, "vUART0_TXD"),
201 PINCTRL_PIN(136, "vUART0_RXD"),
202 PINCTRL_PIN(137, "vUART0_CTS_B"),
203 PINCTRL_PIN(138, "vUART0_RTSB"),
204 PINCTRL_PIN(139, "vISH_UART0_TXD"),
205 PINCTRL_PIN(140, "vISH_UART0_RXD"),
206 PINCTRL_PIN(141, "vISH_UART0_CTS_B"),
207 PINCTRL_PIN(142, "vISH_UART0_RTSB"),
208 PINCTRL_PIN(143, "vISH_UART1_TXD"),
209 PINCTRL_PIN(144, "vISH_UART1_RXD"),
210 PINCTRL_PIN(145, "vISH_UART1_CTS_B"),
211 PINCTRL_PIN(146, "vISH_UART1_RTS_B"),
212 PINCTRL_PIN(147, "vCNV_BT_I2S_BCLK"),
213 PINCTRL_PIN(148, "vCNV_BT_I2S_WS_SYNC"),
214 PINCTRL_PIN(149, "vCNV_BT_I2S_SDO"),
215 PINCTRL_PIN(150, "vCNV_BT_I2S_SDI"),
216 PINCTRL_PIN(151, "vSSP2_SCLK"),
217 PINCTRL_PIN(152, "vSSP2_SFRM"),
218 PINCTRL_PIN(153, "vSSP2_TXD"),
219 PINCTRL_PIN(154, "vSSP2_RXD"),
220 /* GPP_K */
221 PINCTRL_PIN(155, "FAN_TACH_0"),
222 PINCTRL_PIN(156, "FAN_TACH_1"),
223 PINCTRL_PIN(157, "FAN_TACH_2"),
224 PINCTRL_PIN(158, "FAN_TACH_3"),
225 PINCTRL_PIN(159, "FAN_TACH_4"),
226 PINCTRL_PIN(160, "FAN_TACH_5"),
227 PINCTRL_PIN(161, "FAN_TACH_6"),
228 PINCTRL_PIN(162, "FAN_TACH_7"),
229 PINCTRL_PIN(163, "FAN_PWM_0"),
230 PINCTRL_PIN(164, "FAN_PWM_1"),
231 PINCTRL_PIN(165, "FAN_PWM_2"),
232 PINCTRL_PIN(166, "FAN_PWM_3"),
233 PINCTRL_PIN(167, "GSXDOUT"),
234 PINCTRL_PIN(168, "GSXSLOAD"),
235 PINCTRL_PIN(169, "GSXDIN"),
236 PINCTRL_PIN(170, "GSXSRESETB"),
237 PINCTRL_PIN(171, "GSXCLK"),
238 PINCTRL_PIN(172, "ADR_COMPLETE"),
239 PINCTRL_PIN(173, "NMIB"),
240 PINCTRL_PIN(174, "SMIB"),
241 PINCTRL_PIN(175, "CORE_VID_0"),
242 PINCTRL_PIN(176, "CORE_VID_1"),
243 PINCTRL_PIN(177, "IMGCLKOUT_0"),
244 PINCTRL_PIN(178, "IMGCLKOUT_1"),
245 /* GPP_H */
246 PINCTRL_PIN(179, "SRCCLKREQB_6"),
247 PINCTRL_PIN(180, "SRCCLKREQB_7"),
248 PINCTRL_PIN(181, "SRCCLKREQB_8"),
249 PINCTRL_PIN(182, "SRCCLKREQB_9"),
250 PINCTRL_PIN(183, "SRCCLKREQB_10"),
251 PINCTRL_PIN(184, "SRCCLKREQB_11"),
252 PINCTRL_PIN(185, "SRCCLKREQB_12"),
253 PINCTRL_PIN(186, "SRCCLKREQB_13"),
254 PINCTRL_PIN(187, "SRCCLKREQB_14"),
255 PINCTRL_PIN(188, "SRCCLKREQB_15"),
256 PINCTRL_PIN(189, "SML2CLK"),
257 PINCTRL_PIN(190, "SML2DATA"),
258 PINCTRL_PIN(191, "SML2ALERTB"),
259 PINCTRL_PIN(192, "SML3CLK"),
260 PINCTRL_PIN(193, "SML3DATA"),
261 PINCTRL_PIN(194, "SML3ALERTB"),
262 PINCTRL_PIN(195, "SML4CLK"),
263 PINCTRL_PIN(196, "SML4DATA"),
264 PINCTRL_PIN(197, "SML4ALERTB"),
265 PINCTRL_PIN(198, "ISH_I2C0_SDA"),
266 PINCTRL_PIN(199, "ISH_I2C0_SCL"),
267 PINCTRL_PIN(200, "ISH_I2C1_SDA"),
268 PINCTRL_PIN(201, "ISH_I2C1_SCL"),
269 PINCTRL_PIN(202, "TIME_SYNC_0"),
270 /* GPP_E */
271 PINCTRL_PIN(203, "SATAXPCIE_0"),
272 PINCTRL_PIN(204, "SATAXPCIE_1"),
273 PINCTRL_PIN(205, "SATAXPCIE_2"),
274 PINCTRL_PIN(206, "CPU_GP_0"),
275 PINCTRL_PIN(207, "SATA_DEVSLP_0"),
276 PINCTRL_PIN(208, "SATA_DEVSLP_1"),
277 PINCTRL_PIN(209, "SATA_DEVSLP_2"),
278 PINCTRL_PIN(210, "CPU_GP_1"),
279 PINCTRL_PIN(211, "SATA_LEDB"),
280 PINCTRL_PIN(212, "USB2_OCB_0"),
281 PINCTRL_PIN(213, "USB2_OCB_1"),
282 PINCTRL_PIN(214, "USB2_OCB_2"),
283 PINCTRL_PIN(215, "USB2_OCB_3"),
284 /* GPP_F */
285 PINCTRL_PIN(216, "SATAXPCIE_3"),
286 PINCTRL_PIN(217, "SATAXPCIE_4"),
287 PINCTRL_PIN(218, "SATAXPCIE_5"),
288 PINCTRL_PIN(219, "SATAXPCIE_6"),
289 PINCTRL_PIN(220, "SATAXPCIE_7"),
290 PINCTRL_PIN(221, "SATA_DEVSLP_3"),
291 PINCTRL_PIN(222, "SATA_DEVSLP_4"),
292 PINCTRL_PIN(223, "SATA_DEVSLP_5"),
293 PINCTRL_PIN(224, "SATA_DEVSLP_6"),
294 PINCTRL_PIN(225, "SATA_DEVSLP_7"),
295 PINCTRL_PIN(226, "SATA_SCLOCK"),
296 PINCTRL_PIN(227, "SATA_SLOAD"),
297 PINCTRL_PIN(228, "SATA_SDATAOUT1"),
298 PINCTRL_PIN(229, "SATA_SDATAOUT0"),
299 PINCTRL_PIN(230, "EXT_PWR_GATEB"),
300 PINCTRL_PIN(231, "USB2_OCB_4"),
301 PINCTRL_PIN(232, "USB2_OCB_5"),
302 PINCTRL_PIN(233, "USB2_OCB_6"),
303 PINCTRL_PIN(234, "USB2_OCB_7"),
304 PINCTRL_PIN(235, "L_VDDEN"),
305 PINCTRL_PIN(236, "L_BKLTEN"),
306 PINCTRL_PIN(237, "L_BKLTCTL"),
307 PINCTRL_PIN(238, "DDPF_CTRLCLK"),
308 PINCTRL_PIN(239, "DDPF_CTRLDATA"),
309 /* SPI */
310 PINCTRL_PIN(240, "SPI0_IO_2"),
311 PINCTRL_PIN(241, "SPI0_IO_3"),
312 PINCTRL_PIN(242, "SPI0_MOSI_IO_0"),
313 PINCTRL_PIN(243, "SPI0_MISO_IO_1"),
314 PINCTRL_PIN(244, "SPI0_TPM_CSB"),
315 PINCTRL_PIN(245, "SPI0_FLASH_0_CSB"),
316 PINCTRL_PIN(246, "SPI0_FLASH_1_CSB"),
317 PINCTRL_PIN(247, "SPI0_CLK"),
318 PINCTRL_PIN(248, "SPI0_CLK_LOOPBK"),
319 /* CPU */
320 PINCTRL_PIN(249, "HDACPU_SDI"),
321 PINCTRL_PIN(250, "HDACPU_SDO"),
322 PINCTRL_PIN(251, "HDACPU_SCLK"),
323 PINCTRL_PIN(252, "PM_SYNC"),
324 PINCTRL_PIN(253, "PECI"),
325 PINCTRL_PIN(254, "CPUPWRGD"),
326 PINCTRL_PIN(255, "THRMTRIPB"),
327 PINCTRL_PIN(256, "PLTRST_CPUB"),
328 PINCTRL_PIN(257, "PM_DOWN"),
329 PINCTRL_PIN(258, "TRIGGER_IN"),
330 PINCTRL_PIN(259, "TRIGGER_OUT"),
331 /* JTAG */
332 PINCTRL_PIN(260, "JTAG_TDO"),
333 PINCTRL_PIN(261, "JTAGX"),
334 PINCTRL_PIN(262, "PRDYB"),
335 PINCTRL_PIN(263, "PREQB"),
336 PINCTRL_PIN(264, "CPU_TRSTB"),
337 PINCTRL_PIN(265, "JTAG_TDI"),
338 PINCTRL_PIN(266, "JTAG_TMS"),
339 PINCTRL_PIN(267, "JTAG_TCK"),
340 PINCTRL_PIN(268, "ITP_PMODE"),
341 /* GPP_I */
342 PINCTRL_PIN(269, "DDSP_HPD_0"),
343 PINCTRL_PIN(270, "DDSP_HPD_1"),
344 PINCTRL_PIN(271, "DDSP_HPD_2"),
345 PINCTRL_PIN(272, "DDSP_HPD_3"),
346 PINCTRL_PIN(273, "EDP_HPD"),
347 PINCTRL_PIN(274, "DDPB_CTRLCLK"),
348 PINCTRL_PIN(275, "DDPB_CTRLDATA"),
349 PINCTRL_PIN(276, "DDPC_CTRLCLK"),
350 PINCTRL_PIN(277, "DDPC_CTRLDATA"),
351 PINCTRL_PIN(278, "DDPD_CTRLCLK"),
352 PINCTRL_PIN(279, "DDPD_CTRLDATA"),
353 PINCTRL_PIN(280, "M2_SKT2_CFG_0"),
354 PINCTRL_PIN(281, "M2_SKT2_CFG_1"),
355 PINCTRL_PIN(282, "M2_SKT2_CFG_2"),
356 PINCTRL_PIN(283, "M2_SKT2_CFG_3"),
357 PINCTRL_PIN(284, "SYS_PWROK"),
358 PINCTRL_PIN(285, "SYS_RESETB"),
359 PINCTRL_PIN(286, "MLK_RSTB"),
360 /* GPP_J */
361 PINCTRL_PIN(287, "CNV_PA_BLANKING"),
362 PINCTRL_PIN(288, "CNV_GNSS_FTA"),
363 PINCTRL_PIN(289, "CNV_GNSS_SYSCK"),
364 PINCTRL_PIN(290, "CNV_RF_RESET_B"),
365 PINCTRL_PIN(291, "CNV_BRI_DT"),
366 PINCTRL_PIN(292, "CNV_BRI_RSP"),
367 PINCTRL_PIN(293, "CNV_RGI_DT"),
368 PINCTRL_PIN(294, "CNV_RGI_RSP"),
369 PINCTRL_PIN(295, "CNV_MFUART2_RXD"),
370 PINCTRL_PIN(296, "CNV_MFUART2_TXD"),
371 PINCTRL_PIN(297, "CNV_MODEM_CLKREQ"),
372 PINCTRL_PIN(298, "A4WP_PRESENT"),
373};
374
375static const struct intel_padgroup cnlh_community0_gpps[] = {
afe63b46
MW		 376 CNL_GPP(0, 0, 24, 0), /* GPP_A */
377 CNL_GPP(1, 25, 50, 32), /* GPP_B */
a663ccf0
MW		 378};
379
380static const struct intel_padgroup cnlh_community1_gpps[] = {
afe63b46
MW		 381 CNL_GPP(0, 51, 74, 64), /* GPP_C */
382 CNL_GPP(1, 75, 98, 96), /* GPP_D */
383 CNL_GPP(2, 99, 106, 128), /* GPP_G */
384 CNL_GPP(3, 107, 114, CNL_NO_GPIO), /* AZA */
385 CNL_GPP(4, 115, 146, 160), /* vGPIO_0 */
386 CNL_GPP(5, 147, 154, CNL_NO_GPIO), /* vGPIO_1 */
a663ccf0
MW		 387};
388
389static const struct intel_padgroup cnlh_community3_gpps[] = {
afe63b46
MW		 390 CNL_GPP(0, 155, 178, 192), /* GPP_K */
391 CNL_GPP(1, 179, 202, 224), /* GPP_H */
392 CNL_GPP(2, 203, 215, 258), /* GPP_E */
393 CNL_GPP(3, 216, 239, 288), /* GPP_F */
394 CNL_GPP(4, 240, 248, CNL_NO_GPIO), /* SPI */
a663ccf0
MW		 395};
396
397static const struct intel_padgroup cnlh_community4_gpps[] = {
afe63b46
MW		 398 CNL_GPP(0, 249, 259, CNL_NO_GPIO), /* CPU */
399 CNL_GPP(1, 260, 268, CNL_NO_GPIO), /* JTAG */
400 CNL_GPP(2, 269, 286, 320), /* GPP_I */
401 CNL_GPP(3, 287, 298, 352), /* GPP_J */
a663ccf0
MW		 402};
403
404static const unsigned int cnlh_spi0_pins[] = { 40, 41, 42, 43 };
405static const unsigned int cnlh_spi1_pins[] = { 44, 45, 46, 47 };
406static const unsigned int cnlh_spi2_pins[] = { 84, 85, 86, 87 };
407
408static const unsigned int cnlh_uart0_pins[] = { 59, 60, 61, 62 };
409static const unsigned int cnlh_uart1_pins[] = { 63, 64, 65, 66 };
410static const unsigned int cnlh_uart2_pins[] = { 71, 72, 73, 74 };
411
412static const unsigned int cnlh_i2c0_pins[] = { 67, 68 };
413static const unsigned int cnlh_i2c1_pins[] = { 69, 70 };
414static const unsigned int cnlh_i2c2_pins[] = { 88, 89 };
415static const unsigned int cnlh_i2c3_pins[] = { 79, 98 };
416
417static const struct intel_pingroup cnlh_groups[] = {
418 PIN_GROUP("spi0_grp", cnlh_spi0_pins, 1),
419 PIN_GROUP("spi1_grp", cnlh_spi1_pins, 1),
420 PIN_GROUP("spi2_grp", cnlh_spi2_pins, 3),
421 PIN_GROUP("uart0_grp", cnlh_uart0_pins, 1),
422 PIN_GROUP("uart1_grp", cnlh_uart1_pins, 1),
423 PIN_GROUP("uart2_grp", cnlh_uart2_pins, 1),
424 PIN_GROUP("i2c0_grp", cnlh_i2c0_pins, 1),
425 PIN_GROUP("i2c1_grp", cnlh_i2c1_pins, 1),
426 PIN_GROUP("i2c2_grp", cnlh_i2c2_pins, 3),
427 PIN_GROUP("i2c3_grp", cnlh_i2c3_pins, 2),
428};
429
430static const char * const cnlh_spi0_groups[] = { "spi0_grp" };
431static const char * const cnlh_spi1_groups[] = { "spi1_grp" };
432static const char * const cnlh_spi2_groups[] = { "spi2_grp" };
433static const char * const cnlh_uart0_groups[] = { "uart0_grp" };
434static const char * const cnlh_uart1_groups[] = { "uart1_grp" };
435static const char * const cnlh_uart2_groups[] = { "uart2_grp" };
436static const char * const cnlh_i2c0_groups[] = { "i2c0_grp" };
437static const char * const cnlh_i2c1_groups[] = { "i2c1_grp" };
438static const char * const cnlh_i2c2_groups[] = { "i2c2_grp" };
439static const char * const cnlh_i2c3_groups[] = { "i2c3_grp" };
440
441static const struct intel_function cnlh_functions[] = {
442 FUNCTION("spi0", cnlh_spi0_groups),
443 FUNCTION("spi1", cnlh_spi1_groups),
444 FUNCTION("spi2", cnlh_spi2_groups),
445 FUNCTION("uart0", cnlh_uart0_groups),
446 FUNCTION("uart1", cnlh_uart1_groups),
447 FUNCTION("uart2", cnlh_uart2_groups),
448 FUNCTION("i2c0", cnlh_i2c0_groups),
449 FUNCTION("i2c1", cnlh_i2c1_groups),
450 FUNCTION("i2c2", cnlh_i2c2_groups),
451 FUNCTION("i2c3", cnlh_i2c3_groups),
452};
453
454static const struct intel_community cnlh_communities[] = {
4e1f37c4
MW		 455 CNLH_COMMUNITY(0, 0, 50, cnlh_community0_gpps),
456 CNLH_COMMUNITY(1, 51, 154, cnlh_community1_gpps),
457 CNLH_COMMUNITY(2, 155, 248, cnlh_community3_gpps),
458 CNLH_COMMUNITY(3, 249, 298, cnlh_community4_gpps),
a663ccf0
MW		 459};
460
461static const struct intel_pinctrl_soc_data cnlh_soc_data = {
462 .pins = cnlh_pins,
463 .npins = ARRAY_SIZE(cnlh_pins),
464 .groups = cnlh_groups,
465 .ngroups = ARRAY_SIZE(cnlh_groups),
466 .functions = cnlh_functions,
467 .nfunctions = ARRAY_SIZE(cnlh_functions),
468 .communities = cnlh_communities,
469 .ncommunities = ARRAY_SIZE(cnlh_communities),
470};
471
19a8a777
MW		 472/* Cannon Lake-LP */
473static const struct pinctrl_pin_desc cnllp_pins[] = {
474 /* GPP_A */
475 PINCTRL_PIN(0, "RCINB"),
476 PINCTRL_PIN(1, "LAD_0"),
477 PINCTRL_PIN(2, "LAD_1"),
478 PINCTRL_PIN(3, "LAD_2"),
479 PINCTRL_PIN(4, "LAD_3"),
480 PINCTRL_PIN(5, "LFRAMEB"),
481 PINCTRL_PIN(6, "SERIRQ"),
482 PINCTRL_PIN(7, "PIRQAB"),
483 PINCTRL_PIN(8, "CLKRUNB"),
484 PINCTRL_PIN(9, "CLKOUT_LPC_0"),
485 PINCTRL_PIN(10, "CLKOUT_LPC_1"),
486 PINCTRL_PIN(11, "PMEB"),
487 PINCTRL_PIN(12, "BM_BUSYB"),
488 PINCTRL_PIN(13, "SUSWARNB_SUSPWRDNACK"),
489 PINCTRL_PIN(14, "SUS_STATB"),
490 PINCTRL_PIN(15, "SUSACKB"),
491 PINCTRL_PIN(16, "SD_1P8_SEL"),
492 PINCTRL_PIN(17, "SD_PWR_EN_B"),
493 PINCTRL_PIN(18, "ISH_GP_0"),
494 PINCTRL_PIN(19, "ISH_GP_1"),
495 PINCTRL_PIN(20, "ISH_GP_2"),
496 PINCTRL_PIN(21, "ISH_GP_3"),
497 PINCTRL_PIN(22, "ISH_GP_4"),
498 PINCTRL_PIN(23, "ISH_GP_5"),
499 PINCTRL_PIN(24, "ESPI_CLK_LOOPBK"),
500 /* GPP_B */
501 PINCTRL_PIN(25, "CORE_VID_0"),
502 PINCTRL_PIN(26, "CORE_VID_1"),
503 PINCTRL_PIN(27, "VRALERTB"),
504 PINCTRL_PIN(28, "CPU_GP_2"),
505 PINCTRL_PIN(29, "CPU_GP_3"),
506 PINCTRL_PIN(30, "SRCCLKREQB_0"),
507 PINCTRL_PIN(31, "SRCCLKREQB_1"),
508 PINCTRL_PIN(32, "SRCCLKREQB_2"),
509 PINCTRL_PIN(33, "SRCCLKREQB_3"),
510 PINCTRL_PIN(34, "SRCCLKREQB_4"),
511 PINCTRL_PIN(35, "SRCCLKREQB_5"),
512 PINCTRL_PIN(36, "EXT_PWR_GATEB"),
513 PINCTRL_PIN(37, "SLP_S0B"),
514 PINCTRL_PIN(38, "PLTRSTB"),
515 PINCTRL_PIN(39, "SPKR"),
516 PINCTRL_PIN(40, "GSPI0_CS0B"),
517 PINCTRL_PIN(41, "GSPI0_CLK"),
518 PINCTRL_PIN(42, "GSPI0_MISO"),
519 PINCTRL_PIN(43, "GSPI0_MOSI"),
520 PINCTRL_PIN(44, "GSPI1_CS0B"),
521 PINCTRL_PIN(45, "GSPI1_CLK"),
522 PINCTRL_PIN(46, "GSPI1_MISO"),
523 PINCTRL_PIN(47, "GSPI1_MOSI"),
524 PINCTRL_PIN(48, "SML1ALERTB"),
525 PINCTRL_PIN(49, "GSPI0_CLK_LOOPBK"),
526 PINCTRL_PIN(50, "GSPI1_CLK_LOOPBK"),
527 /* GPP_G */
528 PINCTRL_PIN(51, "SD3_CMD"),
529 PINCTRL_PIN(52, "SD3_D0_SD4_RCLK_P"),
530 PINCTRL_PIN(53, "SD3_D1_SD4_RCLK_N"),
531 PINCTRL_PIN(54, "SD3_D2"),
532 PINCTRL_PIN(55, "SD3_D3"),
533 PINCTRL_PIN(56, "SD3_CDB"),
534 PINCTRL_PIN(57, "SD3_CLK"),
535 PINCTRL_PIN(58, "SD3_WP"),
536 /* SPI */
537 PINCTRL_PIN(59, "SPI0_IO_2"),
538 PINCTRL_PIN(60, "SPI0_IO_3"),
539 PINCTRL_PIN(61, "SPI0_MOSI_IO_0"),
540 PINCTRL_PIN(62, "SPI0_MISO_IO_1"),
541 PINCTRL_PIN(63, "SPI0_TPM_CSB"),
542 PINCTRL_PIN(64, "SPI0_FLASH_0_CSB"),
543 PINCTRL_PIN(65, "SPI0_FLASH_1_CSB"),
544 PINCTRL_PIN(66, "SPI0_CLK"),
545 PINCTRL_PIN(67, "SPI0_CLK_LOOPBK"),
546 /* GPP_D */
547 PINCTRL_PIN(68, "SPI1_CSB"),
548 PINCTRL_PIN(69, "SPI1_CLK"),
549 PINCTRL_PIN(70, "SPI1_MISO_IO_1"),
550 PINCTRL_PIN(71, "SPI1_MOSI_IO_0"),
551 PINCTRL_PIN(72, "IMGCLKOUT_0"),
552 PINCTRL_PIN(73, "ISH_I2C0_SDA"),
553 PINCTRL_PIN(74, "ISH_I2C0_SCL"),
554 PINCTRL_PIN(75, "ISH_I2C1_SDA"),
555 PINCTRL_PIN(76, "ISH_I2C1_SCL"),
556 PINCTRL_PIN(77, "ISH_SPI_CSB"),
557 PINCTRL_PIN(78, "ISH_SPI_CLK"),
558 PINCTRL_PIN(79, "ISH_SPI_MISO"),
559 PINCTRL_PIN(80, "ISH_SPI_MOSI"),
560 PINCTRL_PIN(81, "ISH_UART0_RXD"),
561 PINCTRL_PIN(82, "ISH_UART0_TXD"),
562 PINCTRL_PIN(83, "ISH_UART0_RTSB"),
563 PINCTRL_PIN(84, "ISH_UART0_CTSB"),
564 PINCTRL_PIN(85, "DMIC_CLK_1"),
565 PINCTRL_PIN(86, "DMIC_DATA_1"),
566 PINCTRL_PIN(87, "DMIC_CLK_0"),
567 PINCTRL_PIN(88, "DMIC_DATA_0"),
568 PINCTRL_PIN(89, "SPI1_IO_2"),
569 PINCTRL_PIN(90, "SPI1_IO_3"),
570 PINCTRL_PIN(91, "SSP_MCLK"),
571 PINCTRL_PIN(92, "GSPI2_CLK_LOOPBK"),
572 /* GPP_F */
573 PINCTRL_PIN(93, "CNV_GNSS_PA_BLANKING"),
574 PINCTRL_PIN(94, "CNV_GNSS_FTA"),
575 PINCTRL_PIN(95, "CNV_GNSS_SYSCK"),
576 PINCTRL_PIN(96, "EMMC_HIP_MON"),
577 PINCTRL_PIN(97, "CNV_BRI_DT"),
578 PINCTRL_PIN(98, "CNV_BRI_RSP"),
579 PINCTRL_PIN(99, "CNV_RGI_DT"),
580 PINCTRL_PIN(100, "CNV_RGI_RSP"),
581 PINCTRL_PIN(101, "CNV_MFUART2_RXD"),
582 PINCTRL_PIN(102, "CNV_MFUART2_TXD"),
583 PINCTRL_PIN(103, "GPP_F_10"),
584 PINCTRL_PIN(104, "EMMC_CMD"),
585 PINCTRL_PIN(105, "EMMC_DATA_0"),
586 PINCTRL_PIN(106, "EMMC_DATA_1"),
587 PINCTRL_PIN(107, "EMMC_DATA_2"),
588 PINCTRL_PIN(108, "EMMC_DATA_3"),
589 PINCTRL_PIN(109, "EMMC_DATA_4"),
590 PINCTRL_PIN(110, "EMMC_DATA_5"),
591 PINCTRL_PIN(111, "EMMC_DATA_6"),
592 PINCTRL_PIN(112, "EMMC_DATA_7"),
593 PINCTRL_PIN(113, "EMMC_RCLK"),
594 PINCTRL_PIN(114, "EMMC_CLK"),
595 PINCTRL_PIN(115, "EMMC_RESETB"),
596 PINCTRL_PIN(116, "A4WP_PRESENT"),
597 /* GPP_H */
598 PINCTRL_PIN(117, "SSP2_SCLK"),
599 PINCTRL_PIN(118, "SSP2_SFRM"),
600 PINCTRL_PIN(119, "SSP2_TXD"),
601 PINCTRL_PIN(120, "SSP2_RXD"),
602 PINCTRL_PIN(121, "I2C2_SDA"),
603 PINCTRL_PIN(122, "I2C2_SCL"),
604 PINCTRL_PIN(123, "I2C3_SDA"),
605 PINCTRL_PIN(124, "I2C3_SCL"),
606 PINCTRL_PIN(125, "I2C4_SDA"),
607 PINCTRL_PIN(126, "I2C4_SCL"),
608 PINCTRL_PIN(127, "I2C5_SDA"),
609 PINCTRL_PIN(128, "I2C5_SCL"),
610 PINCTRL_PIN(129, "M2_SKT2_CFG_0"),
611 PINCTRL_PIN(130, "M2_SKT2_CFG_1"),
612 PINCTRL_PIN(131, "M2_SKT2_CFG_2"),
613 PINCTRL_PIN(132, "M2_SKT2_CFG_3"),
614 PINCTRL_PIN(133, "DDPF_CTRLCLK"),
615 PINCTRL_PIN(134, "DDPF_CTRLDATA"),
616 PINCTRL_PIN(135, "CPU_VCCIO_PWR_GATEB"),
617 PINCTRL_PIN(136, "TIMESYNC_0"),
618 PINCTRL_PIN(137, "IMGCLKOUT_1"),
619 PINCTRL_PIN(138, "GPPC_H_21"),
620 PINCTRL_PIN(139, "GPPC_H_22"),
621 PINCTRL_PIN(140, "GPPC_H_23"),
622 /* vGPIO */
623 PINCTRL_PIN(141, "CNV_BTEN"),
624 PINCTRL_PIN(142, "CNV_GNEN"),
625 PINCTRL_PIN(143, "CNV_WFEN"),
626 PINCTRL_PIN(144, "CNV_WCEN"),
627 PINCTRL_PIN(145, "CNV_BT_HOST_WAKEB"),
628 PINCTRL_PIN(146, "CNV_BT_IF_SELECT"),
629 PINCTRL_PIN(147, "vCNV_BT_UART_TXD"),
630 PINCTRL_PIN(148, "vCNV_BT_UART_RXD"),
631 PINCTRL_PIN(149, "vCNV_BT_UART_CTS_B"),
632 PINCTRL_PIN(150, "vCNV_BT_UART_RTS_B"),
633 PINCTRL_PIN(151, "vCNV_MFUART1_TXD"),
634 PINCTRL_PIN(152, "vCNV_MFUART1_RXD"),
635 PINCTRL_PIN(153, "vCNV_MFUART1_CTS_B"),
636 PINCTRL_PIN(154, "vCNV_MFUART1_RTS_B"),
637 PINCTRL_PIN(155, "vCNV_GNSS_UART_TXD"),
638 PINCTRL_PIN(156, "vCNV_GNSS_UART_RXD"),
639 PINCTRL_PIN(157, "vCNV_GNSS_UART_CTS_B"),
640 PINCTRL_PIN(158, "vCNV_GNSS_UART_RTS_B"),
641 PINCTRL_PIN(159, "vUART0_TXD"),
642 PINCTRL_PIN(160, "vUART0_RXD"),
643 PINCTRL_PIN(161, "vUART0_CTS_B"),
644 PINCTRL_PIN(162, "vUART0_RTS_B"),
645 PINCTRL_PIN(163, "vISH_UART0_TXD"),
646 PINCTRL_PIN(164, "vISH_UART0_RXD"),
647 PINCTRL_PIN(165, "vISH_UART0_CTS_B"),
648 PINCTRL_PIN(166, "vISH_UART0_RTS_B"),
649 PINCTRL_PIN(167, "vISH_UART1_TXD"),
650 PINCTRL_PIN(168, "vISH_UART1_RXD"),
651 PINCTRL_PIN(169, "vISH_UART1_CTS_B"),
652 PINCTRL_PIN(170, "vISH_UART1_RTS_B"),
653 PINCTRL_PIN(171, "vCNV_BT_I2S_BCLK"),
654 PINCTRL_PIN(172, "vCNV_BT_I2S_WS_SYNC"),
655 PINCTRL_PIN(173, "vCNV_BT_I2S_SDO"),
656 PINCTRL_PIN(174, "vCNV_BT_I2S_SDI"),
657 PINCTRL_PIN(175, "vSSP2_SCLK"),
658 PINCTRL_PIN(176, "vSSP2_SFRM"),
659 PINCTRL_PIN(177, "vSSP2_TXD"),
660 PINCTRL_PIN(178, "vSSP2_RXD"),
661 PINCTRL_PIN(179, "vCNV_GNSS_HOST_WAKEB"),
662 PINCTRL_PIN(180, "vSD3_CD_B"),
663 /* GPP_C */
664 PINCTRL_PIN(181, "SMBCLK"),
665 PINCTRL_PIN(182, "SMBDATA"),
666 PINCTRL_PIN(183, "SMBALERTB"),
667 PINCTRL_PIN(184, "SML0CLK"),
668 PINCTRL_PIN(185, "SML0DATA"),
669 PINCTRL_PIN(186, "SML0ALERTB"),
670 PINCTRL_PIN(187, "SML1CLK"),
671 PINCTRL_PIN(188, "SML1DATA"),
672 PINCTRL_PIN(189, "UART0_RXD"),
673 PINCTRL_PIN(190, "UART0_TXD"),
674 PINCTRL_PIN(191, "UART0_RTSB"),
675 PINCTRL_PIN(192, "UART0_CTSB"),
676 PINCTRL_PIN(193, "UART1_RXD"),
677 PINCTRL_PIN(194, "UART1_TXD"),
678 PINCTRL_PIN(195, "UART1_RTSB"),
679 PINCTRL_PIN(196, "UART1_CTSB"),
680 PINCTRL_PIN(197, "I2C0_SDA"),
681 PINCTRL_PIN(198, "I2C0_SCL"),
682 PINCTRL_PIN(199, "I2C1_SDA"),
683 PINCTRL_PIN(200, "I2C1_SCL"),
684 PINCTRL_PIN(201, "UART2_RXD"),
685 PINCTRL_PIN(202, "UART2_TXD"),
686 PINCTRL_PIN(203, "UART2_RTSB"),
687 PINCTRL_PIN(204, "UART2_CTSB"),
688 /* GPP_E */
689 PINCTRL_PIN(205, "SATAXPCIE_0"),
690 PINCTRL_PIN(206, "SATAXPCIE_1"),
691 PINCTRL_PIN(207, "SATAXPCIE_2"),
692 PINCTRL_PIN(208, "CPU_GP_0"),
693 PINCTRL_PIN(209, "SATA_DEVSLP_0"),
694 PINCTRL_PIN(210, "SATA_DEVSLP_1"),
695 PINCTRL_PIN(211, "SATA_DEVSLP_2"),
696 PINCTRL_PIN(212, "CPU_GP_1"),
697 PINCTRL_PIN(213, "SATA_LEDB"),
698 PINCTRL_PIN(214, "USB2_OCB_0"),
699 PINCTRL_PIN(215, "USB2_OCB_1"),
700 PINCTRL_PIN(216, "USB2_OCB_2"),
701 PINCTRL_PIN(217, "USB2_OCB_3"),
702 PINCTRL_PIN(218, "DDSP_HPD_0"),
703 PINCTRL_PIN(219, "DDSP_HPD_1"),
704 PINCTRL_PIN(220, "DDSP_HPD_2"),
705 PINCTRL_PIN(221, "DDSP_HPD_3"),
706 PINCTRL_PIN(222, "EDP_HPD"),
707 PINCTRL_PIN(223, "DDPB_CTRLCLK"),
708 PINCTRL_PIN(224, "DDPB_CTRLDATA"),
709 PINCTRL_PIN(225, "DDPC_CTRLCLK"),
710 PINCTRL_PIN(226, "DDPC_CTRLDATA"),
711 PINCTRL_PIN(227, "DDPD_CTRLCLK"),
712 PINCTRL_PIN(228, "DDPD_CTRLDATA"),
713 /* JTAG */
714 PINCTRL_PIN(229, "JTAG_TDO"),
715 PINCTRL_PIN(230, "JTAGX"),
716 PINCTRL_PIN(231, "PRDYB"),
717 PINCTRL_PIN(232, "PREQB"),
718 PINCTRL_PIN(233, "CPU_TRSTB"),
719 PINCTRL_PIN(234, "JTAG_TDI"),
720 PINCTRL_PIN(235, "JTAG_TMS"),
721 PINCTRL_PIN(236, "JTAG_TCK"),
722 PINCTRL_PIN(237, "ITP_PMODE"),
723 /* HVCMOS */
724 PINCTRL_PIN(238, "L_BKLTEN"),
725 PINCTRL_PIN(239, "L_BKLTCTL"),
726 PINCTRL_PIN(240, "L_VDDEN"),
727 PINCTRL_PIN(241, "SYS_PWROK"),
728 PINCTRL_PIN(242, "SYS_RESETB"),
729 PINCTRL_PIN(243, "MLK_RSTB"),
730};
731
732static const unsigned int cnllp_spi0_pins[] = { 40, 41, 42, 43, 7 };
733static const unsigned int cnllp_spi0_modes[] = { 1, 1, 1, 1, 2 };
734static const unsigned int cnllp_spi1_pins[] = { 44, 45, 46, 47, 11 };
735static const unsigned int cnllp_spi1_modes[] = { 1, 1, 1, 1, 2 };
736static const unsigned int cnllp_spi2_pins[] = { 77, 78, 79, 80, 83 };
737static const unsigned int cnllp_spi2_modes[] = { 3, 3, 3, 3, 2 };
738
739static const unsigned int cnllp_i2c0_pins[] = { 197, 198 };
740static const unsigned int cnllp_i2c1_pins[] = { 199, 200 };
741static const unsigned int cnllp_i2c2_pins[] = { 121, 122 };
742static const unsigned int cnllp_i2c3_pins[] = { 123, 124 };
743static const unsigned int cnllp_i2c4_pins[] = { 125, 126 };
744static const unsigned int cnllp_i2c5_pins[] = { 127, 128 };
745
746static const unsigned int cnllp_uart0_pins[] = { 189, 190, 191, 192 };
747static const unsigned int cnllp_uart1_pins[] = { 193, 194, 195, 196 };
748static const unsigned int cnllp_uart2_pins[] = { 201, 202, 203, 204 };
749
750static const struct intel_pingroup cnllp_groups[] = {
751 PIN_GROUP("spi0_grp", cnllp_spi0_pins, cnllp_spi0_modes),
752 PIN_GROUP("spi1_grp", cnllp_spi1_pins, cnllp_spi1_modes),
753 PIN_GROUP("spi2_grp", cnllp_spi2_pins, cnllp_spi2_modes),
754 PIN_GROUP("i2c0_grp", cnllp_i2c0_pins, 1),
755 PIN_GROUP("i2c1_grp", cnllp_i2c1_pins, 1),
756 PIN_GROUP("i2c2_grp", cnllp_i2c2_pins, 1),
757 PIN_GROUP("i2c3_grp", cnllp_i2c3_pins, 1),
758 PIN_GROUP("i2c4_grp", cnllp_i2c4_pins, 1),
759 PIN_GROUP("i2c5_grp", cnllp_i2c5_pins, 1),
760 PIN_GROUP("uart0_grp", cnllp_uart0_pins, 1),
761 PIN_GROUP("uart1_grp", cnllp_uart1_pins, 1),
762 PIN_GROUP("uart2_grp", cnllp_uart2_pins, 1),
763};
764
765static const char * const cnllp_spi0_groups[] = { "spi0_grp" };
766static const char * const cnllp_spi1_groups[] = { "spi1_grp" };
767static const char * const cnllp_spi2_groups[] = { "spi2_grp" };
768static const char * const cnllp_i2c0_groups[] = { "i2c0_grp" };
769static const char * const cnllp_i2c1_groups[] = { "i2c1_grp" };
770static const char * const cnllp_i2c2_groups[] = { "i2c2_grp" };
771static const char * const cnllp_i2c3_groups[] = { "i2c3_grp" };
772static const char * const cnllp_i2c4_groups[] = { "i2c4_grp" };
773static const char * const cnllp_i2c5_groups[] = { "i2c5_grp" };
774static const char * const cnllp_uart0_groups[] = { "uart0_grp" };
775static const char * const cnllp_uart1_groups[] = { "uart1_grp" };
776static const char * const cnllp_uart2_groups[] = { "uart2_grp" };
777
778static const struct intel_function cnllp_functions[] = {
779 FUNCTION("spi0", cnllp_spi0_groups),
780 FUNCTION("spi1", cnllp_spi1_groups),
781 FUNCTION("spi2", cnllp_spi2_groups),
782 FUNCTION("i2c0", cnllp_i2c0_groups),
783 FUNCTION("i2c1", cnllp_i2c1_groups),
784 FUNCTION("i2c2", cnllp_i2c2_groups),
785 FUNCTION("i2c3", cnllp_i2c3_groups),
786 FUNCTION("i2c4", cnllp_i2c4_groups),
787 FUNCTION("i2c5", cnllp_i2c5_groups),
788 FUNCTION("uart0", cnllp_uart0_groups),
789 FUNCTION("uart1", cnllp_uart1_groups),
790 FUNCTION("uart2", cnllp_uart2_groups),
791};
792
793static const struct intel_padgroup cnllp_community0_gpps[] = {
afe63b46
MW		 794 CNL_GPP(0, 0, 24, 0), /* GPP_A */
795 CNL_GPP(1, 25, 50, 32), /* GPP_B */
796 CNL_GPP(2, 51, 58, 64), /* GPP_G */
797 CNL_GPP(3, 59, 67, CNL_NO_GPIO), /* SPI */
19a8a777
MW		 798};
799
800static const struct intel_padgroup cnllp_community1_gpps[] = {
afe63b46
MW		 801 CNL_GPP(0, 68, 92, 96), /* GPP_D */
802 CNL_GPP(1, 93, 116, 128), /* GPP_F */
803 CNL_GPP(2, 117, 140, 160), /* GPP_H */
804 CNL_GPP(3, 141, 172, 192), /* vGPIO */
805 CNL_GPP(4, 173, 180, 224), /* vGPIO */
19a8a777
MW		 806};
807
808static const struct intel_padgroup cnllp_community4_gpps[] = {
afe63b46
MW		 809 CNL_GPP(0, 181, 204, 256), /* GPP_C */
810 CNL_GPP(1, 205, 228, 288), /* GPP_E */
811 CNL_GPP(2, 229, 237, CNL_NO_GPIO), /* JTAG */
812 CNL_GPP(3, 238, 243, CNL_NO_GPIO), /* HVCMOS */
19a8a777
MW		 813};
814
815static const struct intel_community cnllp_communities[] = {
4e1f37c4
MW		 816 CNLLP_COMMUNITY(0, 0, 67, cnllp_community0_gpps),
817 CNLLP_COMMUNITY(1, 68, 180, cnllp_community1_gpps),
818 CNLLP_COMMUNITY(2, 181, 243, cnllp_community4_gpps),
19a8a777
MW		 819};
820
821static const struct intel_pinctrl_soc_data cnllp_soc_data = {
822 .pins = cnllp_pins,
823 .npins = ARRAY_SIZE(cnllp_pins),
824 .groups = cnllp_groups,
825 .ngroups = ARRAY_SIZE(cnllp_groups),
826 .functions = cnllp_functions,
827 .nfunctions = ARRAY_SIZE(cnllp_functions),
828 .communities = cnllp_communities,
829 .ncommunities = ARRAY_SIZE(cnllp_communities),
830};
831
832static const struct acpi_device_id cnl_pinctrl_acpi_match[] = {
a663ccf0 833 { "INT3450", (kernel_ulong_t)&cnlh_soc_data },
19a8a777
MW		 834 { "INT34BB", (kernel_ulong_t)&cnllp_soc_data },
835 { },
836};
837MODULE_DEVICE_TABLE(acpi, cnl_pinctrl_acpi_match);
838
839static int cnl_pinctrl_probe(struct platform_device *pdev)
840{
841 const struct intel_pinctrl_soc_data *soc_data;
842 const struct acpi_device_id *id;
843
844 id = acpi_match_device(cnl_pinctrl_acpi_match, &pdev->dev);
845 if (!id || !id->driver_data)
846 return -ENODEV;
847
848 soc_data = (const struct intel_pinctrl_soc_data *)id->driver_data;
849 return intel_pinctrl_probe(pdev, soc_data);
850}
851
852static const struct dev_pm_ops cnl_pinctrl_pm_ops = {
853 SET_LATE_SYSTEM_SLEEP_PM_OPS(intel_pinctrl_suspend,
854 intel_pinctrl_resume)
855};
856
857static struct platform_driver cnl_pinctrl_driver = {
858 .probe = cnl_pinctrl_probe,
859 .driver = {
860 .name = "cannonlake-pinctrl",
861 .acpi_match_table = cnl_pinctrl_acpi_match,
862 .pm = &cnl_pinctrl_pm_ops,
863 },
864};
865
866module_platform_driver(cnl_pinctrl_driver);
867
868MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
869MODULE_DESCRIPTION("Intel Cannon Lake PCH pinctrl/GPIO driver");
870MODULE_LICENSE("GPL v2");
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