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pinctrl: cherryview: Allocate IRQ chip dynamic
[mirror_ubuntu-bionic-kernel.git] / drivers / pinctrl / intel / pinctrl-cherryview.c
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6e08d6bb
MW		 1/*
2 * Cherryview/Braswell pinctrl driver
3 *
4 * Copyright (C) 2014, Intel Corporation
5 * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
6 *
7 * This driver is based on the original Cherryview GPIO driver by
8 * Ning Li <ning.li@intel.com>
9 * Alan Cox <alan@linux.intel.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
70365027 16#include <linux/dmi.h>
6e08d6bb
MW		 17#include <linux/kernel.h>
18#include <linux/module.h>
19#include <linux/init.h>
20#include <linux/types.h>
21#include <linux/gpio.h>
22#include <linux/gpio/driver.h>
23#include <linux/acpi.h>
24#include <linux/pinctrl/pinctrl.h>
25#include <linux/pinctrl/pinmux.h>
26#include <linux/pinctrl/pinconf.h>
27#include <linux/pinctrl/pinconf-generic.h>
28#include <linux/platform_device.h>
29
30#define CHV_INTSTAT 0x300
31#define CHV_INTMASK 0x380
32
33#define FAMILY_PAD_REGS_OFF 0x4400
34#define FAMILY_PAD_REGS_SIZE 0x400
35#define MAX_FAMILY_PAD_GPIO_NO 15
36#define GPIO_REGS_SIZE 8
37
38#define CHV_PADCTRL0 0x000
39#define CHV_PADCTRL0_INTSEL_SHIFT 28
40#define CHV_PADCTRL0_INTSEL_MASK (0xf << CHV_PADCTRL0_INTSEL_SHIFT)
41#define CHV_PADCTRL0_TERM_UP BIT(23)
42#define CHV_PADCTRL0_TERM_SHIFT 20
43#define CHV_PADCTRL0_TERM_MASK (7 << CHV_PADCTRL0_TERM_SHIFT)
44#define CHV_PADCTRL0_TERM_20K 1
45#define CHV_PADCTRL0_TERM_5K 2
46#define CHV_PADCTRL0_TERM_1K 4
47#define CHV_PADCTRL0_PMODE_SHIFT 16
48#define CHV_PADCTRL0_PMODE_MASK (0xf << CHV_PADCTRL0_PMODE_SHIFT)
49#define CHV_PADCTRL0_GPIOEN BIT(15)
50#define CHV_PADCTRL0_GPIOCFG_SHIFT 8
51#define CHV_PADCTRL0_GPIOCFG_MASK (7 << CHV_PADCTRL0_GPIOCFG_SHIFT)
52#define CHV_PADCTRL0_GPIOCFG_GPIO 0
53#define CHV_PADCTRL0_GPIOCFG_GPO 1
54#define CHV_PADCTRL0_GPIOCFG_GPI 2
55#define CHV_PADCTRL0_GPIOCFG_HIZ 3
56#define CHV_PADCTRL0_GPIOTXSTATE BIT(1)
57#define CHV_PADCTRL0_GPIORXSTATE BIT(0)
58
59#define CHV_PADCTRL1 0x004
60#define CHV_PADCTRL1_CFGLOCK BIT(31)
61#define CHV_PADCTRL1_INVRXTX_SHIFT 4
62#define CHV_PADCTRL1_INVRXTX_MASK (0xf << CHV_PADCTRL1_INVRXTX_SHIFT)
63#define CHV_PADCTRL1_INVRXTX_TXENABLE (2 << CHV_PADCTRL1_INVRXTX_SHIFT)
64#define CHV_PADCTRL1_ODEN BIT(3)
65#define CHV_PADCTRL1_INVRXTX_RXDATA (4 << CHV_PADCTRL1_INVRXTX_SHIFT)
66#define CHV_PADCTRL1_INTWAKECFG_MASK 7
67#define CHV_PADCTRL1_INTWAKECFG_FALLING 1
68#define CHV_PADCTRL1_INTWAKECFG_RISING 2
69#define CHV_PADCTRL1_INTWAKECFG_BOTH 3
70#define CHV_PADCTRL1_INTWAKECFG_LEVEL 4
71
72/**
73 * struct chv_alternate_function - A per group or per pin alternate function
74 * @pin: Pin number (only used in per pin configs)
75 * @mode: Mode the pin should be set in
76 * @invert_oe: Invert OE for this pin
77 */
78struct chv_alternate_function {
79 unsigned pin;
80 u8 mode;
81 bool invert_oe;
82};
83
84/**
85 * struct chv_pincgroup - describes a CHV pin group
86 * @name: Name of the group
87 * @pins: An array of pins in this group
88 * @npins: Number of pins in this group
89 * @altfunc: Alternate function applied to all pins in this group
90 * @overrides: Alternate function override per pin or %NULL if not used
91 * @noverrides: Number of per pin alternate function overrides if
92 * @overrides != NULL.
93 */
94struct chv_pingroup {
95 const char *name;
96 const unsigned *pins;
97 size_t npins;
98 struct chv_alternate_function altfunc;
99 const struct chv_alternate_function *overrides;
100 size_t noverrides;
101};
102
103/**
104 * struct chv_function - A CHV pinmux function
105 * @name: Name of the function
106 * @groups: An array of groups for this function
107 * @ngroups: Number of groups in @groups
108 */
109struct chv_function {
110 const char *name;
111 const char * const *groups;
112 size_t ngroups;
113};
114
115/**
116 * struct chv_gpio_pinrange - A range of pins that can be used as GPIOs
117 * @base: Start pin number
118 * @npins: Number of pins in this range
119 */
120struct chv_gpio_pinrange {
121 unsigned base;
122 unsigned npins;
123};
124
125/**
126 * struct chv_community - A community specific configuration
127 * @uid: ACPI _UID used to match the community
128 * @pins: All pins in this community
129 * @npins: Number of pins
130 * @groups: All groups in this community
131 * @ngroups: Number of groups
132 * @functions: All functions in this community
133 * @nfunctions: Number of functions
6e08d6bb
MW		 134 * @gpio_ranges: An array of GPIO ranges in this community
135 * @ngpio_ranges: Number of GPIO ranges
47c950d1 136 * @nirqs: Total number of IRQs this community can generate
6e08d6bb
MW		 137 */
138struct chv_community {
139 const char *uid;
140 const struct pinctrl_pin_desc *pins;
141 size_t npins;
142 const struct chv_pingroup *groups;
143 size_t ngroups;
144 const struct chv_function *functions;
145 size_t nfunctions;
146 const struct chv_gpio_pinrange *gpio_ranges;
147 size_t ngpio_ranges;
47c950d1 148 size_t nirqs;
a0b02859 149 acpi_adr_space_type acpi_space_id;
6e08d6bb
MW		 150};
151
9eb457b5
MW		 152struct chv_pin_context {
153 u32 padctrl0;
154 u32 padctrl1;
155};
156
6e08d6bb
MW		 157/**
158 * struct chv_pinctrl - CHV pinctrl private structure
159 * @dev: Pointer to the parent device
160 * @pctldesc: Pin controller description
161 * @pctldev: Pointer to the pin controller device
162 * @chip: GPIO chip in this pin controller
05f77e19 163 * @irqchip: IRQ chip in this pin controller
6e08d6bb 164 * @regs: MMIO registers
6e08d6bb
MW		 165 * @intr_lines: Stores mapping between 16 HW interrupt wires and GPIO
166 * offset (in GPIO number space)
167 * @community: Community this pinctrl instance represents
168 *
169 * The first group in @groups is expected to contain all pins that can be
170 * used as GPIOs.
171 */
172struct chv_pinctrl {
173 struct device *dev;
174 struct pinctrl_desc pctldesc;
175 struct pinctrl_dev *pctldev;
176 struct gpio_chip chip;
05f77e19 177 struct irq_chip irqchip;
6e08d6bb 178 void __iomem *regs;
6e08d6bb
MW		 179 unsigned intr_lines[16];
180 const struct chv_community *community;
9eb457b5
MW		 181 u32 saved_intmask;
182 struct chv_pin_context *saved_pin_context;
6e08d6bb
MW		 183};
184
6e08d6bb
MW		 185#define ALTERNATE_FUNCTION(p, m, i) \
186 { \
187 .pin = (p), \
188 .mode = (m), \
189 .invert_oe = (i), \
190 }
191
192#define PIN_GROUP(n, p, m, i) \
193 { \
194 .name = (n), \
195 .pins = (p), \
196 .npins = ARRAY_SIZE((p)), \
197 .altfunc.mode = (m), \
198 .altfunc.invert_oe = (i), \
199 }
200
201#define PIN_GROUP_WITH_OVERRIDE(n, p, m, i, o) \
202 { \
203 .name = (n), \
204 .pins = (p), \
205 .npins = ARRAY_SIZE((p)), \
206 .altfunc.mode = (m), \
207 .altfunc.invert_oe = (i), \
208 .overrides = (o), \
209 .noverrides = ARRAY_SIZE((o)), \
210 }
211
212#define FUNCTION(n, g) \
213 { \
214 .name = (n), \
215 .groups = (g), \
216 .ngroups = ARRAY_SIZE((g)), \
217 }
218
219#define GPIO_PINRANGE(start, end) \
220 { \
221 .base = (start), \
222 .npins = (end) - (start) + 1, \
223 }
224
225static const struct pinctrl_pin_desc southwest_pins[] = {
226 PINCTRL_PIN(0, "FST_SPI_D2"),
227 PINCTRL_PIN(1, "FST_SPI_D0"),
228 PINCTRL_PIN(2, "FST_SPI_CLK"),
229 PINCTRL_PIN(3, "FST_SPI_D3"),
230 PINCTRL_PIN(4, "FST_SPI_CS1_B"),
231 PINCTRL_PIN(5, "FST_SPI_D1"),
232 PINCTRL_PIN(6, "FST_SPI_CS0_B"),
233 PINCTRL_PIN(7, "FST_SPI_CS2_B"),
234
235 PINCTRL_PIN(15, "UART1_RTS_B"),
236 PINCTRL_PIN(16, "UART1_RXD"),
237 PINCTRL_PIN(17, "UART2_RXD"),
238 PINCTRL_PIN(18, "UART1_CTS_B"),
239 PINCTRL_PIN(19, "UART2_RTS_B"),
240 PINCTRL_PIN(20, "UART1_TXD"),
241 PINCTRL_PIN(21, "UART2_TXD"),
242 PINCTRL_PIN(22, "UART2_CTS_B"),
243
244 PINCTRL_PIN(30, "MF_HDA_CLK"),
245 PINCTRL_PIN(31, "MF_HDA_RSTB"),
246 PINCTRL_PIN(32, "MF_HDA_SDIO"),
247 PINCTRL_PIN(33, "MF_HDA_SDO"),
248 PINCTRL_PIN(34, "MF_HDA_DOCKRSTB"),
249 PINCTRL_PIN(35, "MF_HDA_SYNC"),
250 PINCTRL_PIN(36, "MF_HDA_SDI1"),
251 PINCTRL_PIN(37, "MF_HDA_DOCKENB"),
252
253 PINCTRL_PIN(45, "I2C5_SDA"),
254 PINCTRL_PIN(46, "I2C4_SDA"),
255 PINCTRL_PIN(47, "I2C6_SDA"),
256 PINCTRL_PIN(48, "I2C5_SCL"),
257 PINCTRL_PIN(49, "I2C_NFC_SDA"),
258 PINCTRL_PIN(50, "I2C4_SCL"),
259 PINCTRL_PIN(51, "I2C6_SCL"),
260 PINCTRL_PIN(52, "I2C_NFC_SCL"),
261
262 PINCTRL_PIN(60, "I2C1_SDA"),
263 PINCTRL_PIN(61, "I2C0_SDA"),
264 PINCTRL_PIN(62, "I2C2_SDA"),
265 PINCTRL_PIN(63, "I2C1_SCL"),
266 PINCTRL_PIN(64, "I2C3_SDA"),
267 PINCTRL_PIN(65, "I2C0_SCL"),
268 PINCTRL_PIN(66, "I2C2_SCL"),
269 PINCTRL_PIN(67, "I2C3_SCL"),
270
271 PINCTRL_PIN(75, "SATA_GP0"),
272 PINCTRL_PIN(76, "SATA_GP1"),
273 PINCTRL_PIN(77, "SATA_LEDN"),
274 PINCTRL_PIN(78, "SATA_GP2"),
275 PINCTRL_PIN(79, "MF_SMB_ALERTB"),
276 PINCTRL_PIN(80, "SATA_GP3"),
277 PINCTRL_PIN(81, "MF_SMB_CLK"),
278 PINCTRL_PIN(82, "MF_SMB_DATA"),
279
280 PINCTRL_PIN(90, "PCIE_CLKREQ0B"),
281 PINCTRL_PIN(91, "PCIE_CLKREQ1B"),
282 PINCTRL_PIN(92, "GP_SSP_2_CLK"),
283 PINCTRL_PIN(93, "PCIE_CLKREQ2B"),
284 PINCTRL_PIN(94, "GP_SSP_2_RXD"),
285 PINCTRL_PIN(95, "PCIE_CLKREQ3B"),
286 PINCTRL_PIN(96, "GP_SSP_2_FS"),
287 PINCTRL_PIN(97, "GP_SSP_2_TXD"),
288};
289
290static const unsigned southwest_fspi_pins[] = { 0, 1, 2, 3, 4, 5, 6, 7 };
291static const unsigned southwest_uart0_pins[] = { 16, 20 };
292static const unsigned southwest_uart1_pins[] = { 15, 16, 18, 20 };
293static const unsigned southwest_uart2_pins[] = { 17, 19, 21, 22 };
294static const unsigned southwest_i2c0_pins[] = { 61, 65 };
295static const unsigned southwest_hda_pins[] = { 30, 31, 32, 33, 34, 35, 36, 37 };
296static const unsigned southwest_lpe_pins[] = {
297 30, 31, 32, 33, 34, 35, 36, 37, 92, 94, 96, 97,
298};
299static const unsigned southwest_i2c1_pins[] = { 60, 63 };
300static const unsigned southwest_i2c2_pins[] = { 62, 66 };
301static const unsigned southwest_i2c3_pins[] = { 64, 67 };
302static const unsigned southwest_i2c4_pins[] = { 46, 50 };
303static const unsigned southwest_i2c5_pins[] = { 45, 48 };
304static const unsigned southwest_i2c6_pins[] = { 47, 51 };
305static const unsigned southwest_i2c_nfc_pins[] = { 49, 52 };
306static const unsigned southwest_smbus_pins[] = { 79, 81, 82 };
307static const unsigned southwest_spi3_pins[] = { 76, 79, 80, 81, 82 };
308
309/* LPE I2S TXD pins need to have invert_oe set */
310static const struct chv_alternate_function southwest_lpe_altfuncs[] = {
311 ALTERNATE_FUNCTION(30, 1, true),
312 ALTERNATE_FUNCTION(34, 1, true),
313 ALTERNATE_FUNCTION(97, 1, true),
314};
315
316/*
317 * Two spi3 chipselects are available in different mode than the main spi3
318 * functionality, which is using mode 1.
319 */
320static const struct chv_alternate_function southwest_spi3_altfuncs[] = {
321 ALTERNATE_FUNCTION(76, 3, false),
322 ALTERNATE_FUNCTION(80, 3, false),
323};
324
325static const struct chv_pingroup southwest_groups[] = {
326 PIN_GROUP("uart0_grp", southwest_uart0_pins, 2, false),
327 PIN_GROUP("uart1_grp", southwest_uart1_pins, 1, false),
328 PIN_GROUP("uart2_grp", southwest_uart2_pins, 1, false),
329 PIN_GROUP("hda_grp", southwest_hda_pins, 2, false),
330 PIN_GROUP("i2c0_grp", southwest_i2c0_pins, 1, true),
331 PIN_GROUP("i2c1_grp", southwest_i2c1_pins, 1, true),
332 PIN_GROUP("i2c2_grp", southwest_i2c2_pins, 1, true),
333 PIN_GROUP("i2c3_grp", southwest_i2c3_pins, 1, true),
334 PIN_GROUP("i2c4_grp", southwest_i2c4_pins, 1, true),
335 PIN_GROUP("i2c5_grp", southwest_i2c5_pins, 1, true),
336 PIN_GROUP("i2c6_grp", southwest_i2c6_pins, 1, true),
337 PIN_GROUP("i2c_nfc_grp", southwest_i2c_nfc_pins, 2, true),
338
339 PIN_GROUP_WITH_OVERRIDE("lpe_grp", southwest_lpe_pins, 1, false,
340 southwest_lpe_altfuncs),
341 PIN_GROUP_WITH_OVERRIDE("spi3_grp", southwest_spi3_pins, 2, false,
342 southwest_spi3_altfuncs),
343};
344
345static const char * const southwest_uart0_groups[] = { "uart0_grp" };
346static const char * const southwest_uart1_groups[] = { "uart1_grp" };
347static const char * const southwest_uart2_groups[] = { "uart2_grp" };
348static const char * const southwest_hda_groups[] = { "hda_grp" };
349static const char * const southwest_lpe_groups[] = { "lpe_grp" };
350static const char * const southwest_i2c0_groups[] = { "i2c0_grp" };
351static const char * const southwest_i2c1_groups[] = { "i2c1_grp" };
352static const char * const southwest_i2c2_groups[] = { "i2c2_grp" };
353static const char * const southwest_i2c3_groups[] = { "i2c3_grp" };
354static const char * const southwest_i2c4_groups[] = { "i2c4_grp" };
355static const char * const southwest_i2c5_groups[] = { "i2c5_grp" };
356static const char * const southwest_i2c6_groups[] = { "i2c6_grp" };
357static const char * const southwest_i2c_nfc_groups[] = { "i2c_nfc_grp" };
358static const char * const southwest_spi3_groups[] = { "spi3_grp" };
359
360/*
361 * Only do pinmuxing for certain LPSS devices for now. Rest of the pins are
362 * enabled only as GPIOs.
363 */
364static const struct chv_function southwest_functions[] = {
365 FUNCTION("uart0", southwest_uart0_groups),
366 FUNCTION("uart1", southwest_uart1_groups),
367 FUNCTION("uart2", southwest_uart2_groups),
368 FUNCTION("hda", southwest_hda_groups),
369 FUNCTION("lpe", southwest_lpe_groups),
370 FUNCTION("i2c0", southwest_i2c0_groups),
371 FUNCTION("i2c1", southwest_i2c1_groups),
372 FUNCTION("i2c2", southwest_i2c2_groups),
373 FUNCTION("i2c3", southwest_i2c3_groups),
374 FUNCTION("i2c4", southwest_i2c4_groups),
375 FUNCTION("i2c5", southwest_i2c5_groups),
376 FUNCTION("i2c6", southwest_i2c6_groups),
377 FUNCTION("i2c_nfc", southwest_i2c_nfc_groups),
378 FUNCTION("spi3", southwest_spi3_groups),
379};
380
381static const struct chv_gpio_pinrange southwest_gpio_ranges[] = {
382 GPIO_PINRANGE(0, 7),
383 GPIO_PINRANGE(15, 22),
384 GPIO_PINRANGE(30, 37),
385 GPIO_PINRANGE(45, 52),
386 GPIO_PINRANGE(60, 67),
387 GPIO_PINRANGE(75, 82),
388 GPIO_PINRANGE(90, 97),
389};
390
391static const struct chv_community southwest_community = {
392 .uid = "1",
393 .pins = southwest_pins,
394 .npins = ARRAY_SIZE(southwest_pins),
395 .groups = southwest_groups,
396 .ngroups = ARRAY_SIZE(southwest_groups),
397 .functions = southwest_functions,
398 .nfunctions = ARRAY_SIZE(southwest_functions),
399 .gpio_ranges = southwest_gpio_ranges,
400 .ngpio_ranges = ARRAY_SIZE(southwest_gpio_ranges),
47c950d1
MW		 401 /*
402 * Southwest community can benerate GPIO interrupts only for the
403 * first 8 interrupts. The upper half (8-15) can only be used to
404 * trigger GPEs.
405 */
406 .nirqs = 8,
a0b02859 407 .acpi_space_id = 0x91,
6e08d6bb
MW		 408};
409
410static const struct pinctrl_pin_desc north_pins[] = {
411 PINCTRL_PIN(0, "GPIO_DFX_0"),
412 PINCTRL_PIN(1, "GPIO_DFX_3"),
413 PINCTRL_PIN(2, "GPIO_DFX_7"),
414 PINCTRL_PIN(3, "GPIO_DFX_1"),
415 PINCTRL_PIN(4, "GPIO_DFX_5"),
416 PINCTRL_PIN(5, "GPIO_DFX_4"),
417 PINCTRL_PIN(6, "GPIO_DFX_8"),
418 PINCTRL_PIN(7, "GPIO_DFX_2"),
419 PINCTRL_PIN(8, "GPIO_DFX_6"),
420
421 PINCTRL_PIN(15, "GPIO_SUS0"),
422 PINCTRL_PIN(16, "SEC_GPIO_SUS10"),
423 PINCTRL_PIN(17, "GPIO_SUS3"),
424 PINCTRL_PIN(18, "GPIO_SUS7"),
425 PINCTRL_PIN(19, "GPIO_SUS1"),
426 PINCTRL_PIN(20, "GPIO_SUS5"),
427 PINCTRL_PIN(21, "SEC_GPIO_SUS11"),
428 PINCTRL_PIN(22, "GPIO_SUS4"),
429 PINCTRL_PIN(23, "SEC_GPIO_SUS8"),
430 PINCTRL_PIN(24, "GPIO_SUS2"),
431 PINCTRL_PIN(25, "GPIO_SUS6"),
432 PINCTRL_PIN(26, "CX_PREQ_B"),
433 PINCTRL_PIN(27, "SEC_GPIO_SUS9"),
434
435 PINCTRL_PIN(30, "TRST_B"),
436 PINCTRL_PIN(31, "TCK"),
437 PINCTRL_PIN(32, "PROCHOT_B"),
438 PINCTRL_PIN(33, "SVIDO_DATA"),
439 PINCTRL_PIN(34, "TMS"),
440 PINCTRL_PIN(35, "CX_PRDY_B_2"),
441 PINCTRL_PIN(36, "TDO_2"),
442 PINCTRL_PIN(37, "CX_PRDY_B"),
443 PINCTRL_PIN(38, "SVIDO_ALERT_B"),
444 PINCTRL_PIN(39, "TDO"),
445 PINCTRL_PIN(40, "SVIDO_CLK"),
446 PINCTRL_PIN(41, "TDI"),
447
448 PINCTRL_PIN(45, "GP_CAMERASB_05"),
449 PINCTRL_PIN(46, "GP_CAMERASB_02"),
450 PINCTRL_PIN(47, "GP_CAMERASB_08"),
451 PINCTRL_PIN(48, "GP_CAMERASB_00"),
452 PINCTRL_PIN(49, "GP_CAMERASB_06"),
453 PINCTRL_PIN(50, "GP_CAMERASB_10"),
454 PINCTRL_PIN(51, "GP_CAMERASB_03"),
455 PINCTRL_PIN(52, "GP_CAMERASB_09"),
456 PINCTRL_PIN(53, "GP_CAMERASB_01"),
457 PINCTRL_PIN(54, "GP_CAMERASB_07"),
458 PINCTRL_PIN(55, "GP_CAMERASB_11"),
459 PINCTRL_PIN(56, "GP_CAMERASB_04"),
460
461 PINCTRL_PIN(60, "PANEL0_BKLTEN"),
462 PINCTRL_PIN(61, "HV_DDI0_HPD"),
463 PINCTRL_PIN(62, "HV_DDI2_DDC_SDA"),
464 PINCTRL_PIN(63, "PANEL1_BKLTCTL"),
465 PINCTRL_PIN(64, "HV_DDI1_HPD"),
466 PINCTRL_PIN(65, "PANEL0_BKLTCTL"),
467 PINCTRL_PIN(66, "HV_DDI0_DDC_SDA"),
468 PINCTRL_PIN(67, "HV_DDI2_DDC_SCL"),
469 PINCTRL_PIN(68, "HV_DDI2_HPD"),
470 PINCTRL_PIN(69, "PANEL1_VDDEN"),
471 PINCTRL_PIN(70, "PANEL1_BKLTEN"),
472 PINCTRL_PIN(71, "HV_DDI0_DDC_SCL"),
473 PINCTRL_PIN(72, "PANEL0_VDDEN"),
474};
475
476static const struct chv_gpio_pinrange north_gpio_ranges[] = {
477 GPIO_PINRANGE(0, 8),
478 GPIO_PINRANGE(15, 27),
479 GPIO_PINRANGE(30, 41),
480 GPIO_PINRANGE(45, 56),
481 GPIO_PINRANGE(60, 72),
482};
483
484static const struct chv_community north_community = {
485 .uid = "2",
486 .pins = north_pins,
487 .npins = ARRAY_SIZE(north_pins),
488 .gpio_ranges = north_gpio_ranges,
489 .ngpio_ranges = ARRAY_SIZE(north_gpio_ranges),
47c950d1 490 /*
505485a8 491 * North community can generate GPIO interrupts only for the first
47c950d1
MW		 492 * 8 interrupts. The upper half (8-15) can only be used to trigger
493 * GPEs.
494 */
495 .nirqs = 8,
a0b02859 496 .acpi_space_id = 0x92,
6e08d6bb
MW		 497};
498
499static const struct pinctrl_pin_desc east_pins[] = {
500 PINCTRL_PIN(0, "PMU_SLP_S3_B"),
501 PINCTRL_PIN(1, "PMU_BATLOW_B"),
502 PINCTRL_PIN(2, "SUS_STAT_B"),
503 PINCTRL_PIN(3, "PMU_SLP_S0IX_B"),
504 PINCTRL_PIN(4, "PMU_AC_PRESENT"),
505 PINCTRL_PIN(5, "PMU_PLTRST_B"),
506 PINCTRL_PIN(6, "PMU_SUSCLK"),
507 PINCTRL_PIN(7, "PMU_SLP_LAN_B"),
508 PINCTRL_PIN(8, "PMU_PWRBTN_B"),
509 PINCTRL_PIN(9, "PMU_SLP_S4_B"),
510 PINCTRL_PIN(10, "PMU_WAKE_B"),
511 PINCTRL_PIN(11, "PMU_WAKE_LAN_B"),
512
513 PINCTRL_PIN(15, "MF_ISH_GPIO_3"),
514 PINCTRL_PIN(16, "MF_ISH_GPIO_7"),
515 PINCTRL_PIN(17, "MF_ISH_I2C1_SCL"),
516 PINCTRL_PIN(18, "MF_ISH_GPIO_1"),
517 PINCTRL_PIN(19, "MF_ISH_GPIO_5"),
518 PINCTRL_PIN(20, "MF_ISH_GPIO_9"),
519 PINCTRL_PIN(21, "MF_ISH_GPIO_0"),
520 PINCTRL_PIN(22, "MF_ISH_GPIO_4"),
521 PINCTRL_PIN(23, "MF_ISH_GPIO_8"),
522 PINCTRL_PIN(24, "MF_ISH_GPIO_2"),
523 PINCTRL_PIN(25, "MF_ISH_GPIO_6"),
524 PINCTRL_PIN(26, "MF_ISH_I2C1_SDA"),
525};
526
527static const struct chv_gpio_pinrange east_gpio_ranges[] = {
528 GPIO_PINRANGE(0, 11),
529 GPIO_PINRANGE(15, 26),
530};
531
532static const struct chv_community east_community = {
533 .uid = "3",
534 .pins = east_pins,
535 .npins = ARRAY_SIZE(east_pins),
536 .gpio_ranges = east_gpio_ranges,
537 .ngpio_ranges = ARRAY_SIZE(east_gpio_ranges),
47c950d1 538 .nirqs = 16,
a0b02859 539 .acpi_space_id = 0x93,
6e08d6bb
MW		 540};
541
542static const struct pinctrl_pin_desc southeast_pins[] = {
543 PINCTRL_PIN(0, "MF_PLT_CLK0"),
544 PINCTRL_PIN(1, "PWM1"),
545 PINCTRL_PIN(2, "MF_PLT_CLK1"),
546 PINCTRL_PIN(3, "MF_PLT_CLK4"),
547 PINCTRL_PIN(4, "MF_PLT_CLK3"),
548 PINCTRL_PIN(5, "PWM0"),
549 PINCTRL_PIN(6, "MF_PLT_CLK5"),
550 PINCTRL_PIN(7, "MF_PLT_CLK2"),
551
552 PINCTRL_PIN(15, "SDMMC2_D3_CD_B"),
553 PINCTRL_PIN(16, "SDMMC1_CLK"),
554 PINCTRL_PIN(17, "SDMMC1_D0"),
555 PINCTRL_PIN(18, "SDMMC2_D1"),
556 PINCTRL_PIN(19, "SDMMC2_CLK"),
557 PINCTRL_PIN(20, "SDMMC1_D2"),
558 PINCTRL_PIN(21, "SDMMC2_D2"),
559 PINCTRL_PIN(22, "SDMMC2_CMD"),
560 PINCTRL_PIN(23, "SDMMC1_CMD"),
561 PINCTRL_PIN(24, "SDMMC1_D1"),
562 PINCTRL_PIN(25, "SDMMC2_D0"),
563 PINCTRL_PIN(26, "SDMMC1_D3_CD_B"),
564
565 PINCTRL_PIN(30, "SDMMC3_D1"),
566 PINCTRL_PIN(31, "SDMMC3_CLK"),
567 PINCTRL_PIN(32, "SDMMC3_D3"),
568 PINCTRL_PIN(33, "SDMMC3_D2"),
569 PINCTRL_PIN(34, "SDMMC3_CMD"),
570 PINCTRL_PIN(35, "SDMMC3_D0"),
571
572 PINCTRL_PIN(45, "MF_LPC_AD2"),
573 PINCTRL_PIN(46, "LPC_CLKRUNB"),
574 PINCTRL_PIN(47, "MF_LPC_AD0"),
575 PINCTRL_PIN(48, "LPC_FRAMEB"),
576 PINCTRL_PIN(49, "MF_LPC_CLKOUT1"),
577 PINCTRL_PIN(50, "MF_LPC_AD3"),
578 PINCTRL_PIN(51, "MF_LPC_CLKOUT0"),
579 PINCTRL_PIN(52, "MF_LPC_AD1"),
580
581 PINCTRL_PIN(60, "SPI1_MISO"),
582 PINCTRL_PIN(61, "SPI1_CSO_B"),
583 PINCTRL_PIN(62, "SPI1_CLK"),
584 PINCTRL_PIN(63, "MMC1_D6"),
585 PINCTRL_PIN(64, "SPI1_MOSI"),
586 PINCTRL_PIN(65, "MMC1_D5"),
587 PINCTRL_PIN(66, "SPI1_CS1_B"),
588 PINCTRL_PIN(67, "MMC1_D4_SD_WE"),
589 PINCTRL_PIN(68, "MMC1_D7"),
590 PINCTRL_PIN(69, "MMC1_RCLK"),
591
592 PINCTRL_PIN(75, "USB_OC1_B"),
593 PINCTRL_PIN(76, "PMU_RESETBUTTON_B"),
594 PINCTRL_PIN(77, "GPIO_ALERT"),
595 PINCTRL_PIN(78, "SDMMC3_PWR_EN_B"),
596 PINCTRL_PIN(79, "ILB_SERIRQ"),
597 PINCTRL_PIN(80, "USB_OC0_B"),
598 PINCTRL_PIN(81, "SDMMC3_CD_B"),
599 PINCTRL_PIN(82, "SPKR"),
600 PINCTRL_PIN(83, "SUSPWRDNACK"),
601 PINCTRL_PIN(84, "SPARE_PIN"),
602 PINCTRL_PIN(85, "SDMMC3_1P8_EN"),
603};
604
605static const unsigned southeast_pwm0_pins[] = { 5 };
606static const unsigned southeast_pwm1_pins[] = { 1 };
607static const unsigned southeast_sdmmc1_pins[] = {
608 16, 17, 20, 23, 24, 26, 63, 65, 67, 68, 69,
609};
610static const unsigned southeast_sdmmc2_pins[] = { 15, 18, 19, 21, 22, 25 };
611static const unsigned southeast_sdmmc3_pins[] = {
612 30, 31, 32, 33, 34, 35, 78, 81, 85,
613};
614static const unsigned southeast_spi1_pins[] = { 60, 61, 62, 64, 66 };
615static const unsigned southeast_spi2_pins[] = { 2, 3, 4, 6, 7 };
616
617static const struct chv_pingroup southeast_groups[] = {
618 PIN_GROUP("pwm0_grp", southeast_pwm0_pins, 1, false),
619 PIN_GROUP("pwm1_grp", southeast_pwm1_pins, 1, false),
620 PIN_GROUP("sdmmc1_grp", southeast_sdmmc1_pins, 1, false),
621 PIN_GROUP("sdmmc2_grp", southeast_sdmmc2_pins, 1, false),
622 PIN_GROUP("sdmmc3_grp", southeast_sdmmc3_pins, 1, false),
623 PIN_GROUP("spi1_grp", southeast_spi1_pins, 1, false),
624 PIN_GROUP("spi2_grp", southeast_spi2_pins, 4, false),
625};
626
627static const char * const southeast_pwm0_groups[] = { "pwm0_grp" };
628static const char * const southeast_pwm1_groups[] = { "pwm1_grp" };
629static const char * const southeast_sdmmc1_groups[] = { "sdmmc1_grp" };
630static const char * const southeast_sdmmc2_groups[] = { "sdmmc2_grp" };
631static const char * const southeast_sdmmc3_groups[] = { "sdmmc3_grp" };
632static const char * const southeast_spi1_groups[] = { "spi1_grp" };
633static const char * const southeast_spi2_groups[] = { "spi2_grp" };
634
635static const struct chv_function southeast_functions[] = {
636 FUNCTION("pwm0", southeast_pwm0_groups),
637 FUNCTION("pwm1", southeast_pwm1_groups),
638 FUNCTION("sdmmc1", southeast_sdmmc1_groups),
639 FUNCTION("sdmmc2", southeast_sdmmc2_groups),
640 FUNCTION("sdmmc3", southeast_sdmmc3_groups),
641 FUNCTION("spi1", southeast_spi1_groups),
642 FUNCTION("spi2", southeast_spi2_groups),
643};
644
645static const struct chv_gpio_pinrange southeast_gpio_ranges[] = {
646 GPIO_PINRANGE(0, 7),
647 GPIO_PINRANGE(15, 26),
648 GPIO_PINRANGE(30, 35),
649 GPIO_PINRANGE(45, 52),
650 GPIO_PINRANGE(60, 69),
651 GPIO_PINRANGE(75, 85),
652};
653
654static const struct chv_community southeast_community = {
655 .uid = "4",
656 .pins = southeast_pins,
657 .npins = ARRAY_SIZE(southeast_pins),
658 .groups = southeast_groups,
659 .ngroups = ARRAY_SIZE(southeast_groups),
660 .functions = southeast_functions,
661 .nfunctions = ARRAY_SIZE(southeast_functions),
662 .gpio_ranges = southeast_gpio_ranges,
663 .ngpio_ranges = ARRAY_SIZE(southeast_gpio_ranges),
47c950d1 664 .nirqs = 16,
a0b02859 665 .acpi_space_id = 0x94,
6e08d6bb
MW		 666};
667
668static const struct chv_community *chv_communities[] = {
669 &southwest_community,
670 &north_community,
671 &east_community,
672 &southeast_community,
673};
674
0bd50d71
DD		 675/*
676 * Lock to serialize register accesses
677 *
678 * Due to a silicon issue, a shared lock must be used to prevent
679 * concurrent accesses across the 4 GPIO controllers.
680 *
681 * See Intel Atom Z8000 Processor Series Specification Update (Rev. 005),
682 * errata #CHT34, for further information.
683 */
684static DEFINE_RAW_SPINLOCK(chv_lock);
685
6e08d6bb
MW		 686static void __iomem *chv_padreg(struct chv_pinctrl *pctrl, unsigned offset,
687 unsigned reg)
688{
689 unsigned family_no = offset / MAX_FAMILY_PAD_GPIO_NO;
690 unsigned pad_no = offset % MAX_FAMILY_PAD_GPIO_NO;
691
692 offset = FAMILY_PAD_REGS_OFF + FAMILY_PAD_REGS_SIZE * family_no +
693 GPIO_REGS_SIZE * pad_no;
694
695 return pctrl->regs + offset + reg;
696}
697
698static void chv_writel(u32 value, void __iomem *reg)
699{
700 writel(value, reg);
701 /* simple readback to confirm the bus transferring done */
702 readl(reg);
703}
704
705/* When Pad Cfg is locked, driver can only change GPIOTXState or GPIORXState */
706static bool chv_pad_locked(struct chv_pinctrl *pctrl, unsigned offset)
707{
708 void __iomem *reg;
709
710 reg = chv_padreg(pctrl, offset, CHV_PADCTRL1);
711 return readl(reg) & CHV_PADCTRL1_CFGLOCK;
712}
713
714static int chv_get_groups_count(struct pinctrl_dev *pctldev)
715{
716 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
717
718 return pctrl->community->ngroups;
719}
720
721static const char *chv_get_group_name(struct pinctrl_dev *pctldev,
722 unsigned group)
723{
724 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
725
726 return pctrl->community->groups[group].name;
727}
728
729static int chv_get_group_pins(struct pinctrl_dev *pctldev, unsigned group,
730 const unsigned **pins, unsigned *npins)
731{
732 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
733
734 *pins = pctrl->community->groups[group].pins;
735 *npins = pctrl->community->groups[group].npins;
736 return 0;
737}
738
739static void chv_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
740 unsigned offset)
741{
742 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
743 unsigned long flags;
744 u32 ctrl0, ctrl1;
745 bool locked;
746
0bd50d71 747 raw_spin_lock_irqsave(&chv_lock, flags);
6e08d6bb
MW		 748
749 ctrl0 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0));
750 ctrl1 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL1));
751 locked = chv_pad_locked(pctrl, offset);
752
0bd50d71 753 raw_spin_unlock_irqrestore(&chv_lock, flags);
6e08d6bb
MW		 754
755 if (ctrl0 & CHV_PADCTRL0_GPIOEN) {
756 seq_puts(s, "GPIO ");
757 } else {
758 u32 mode;
759
760 mode = ctrl0 & CHV_PADCTRL0_PMODE_MASK;
761 mode >>= CHV_PADCTRL0_PMODE_SHIFT;
762
763 seq_printf(s, "mode %d ", mode);
764 }
765
684373ea 766 seq_printf(s, "0x%08x 0x%08x", ctrl0, ctrl1);
6e08d6bb
MW		 767
768 if (locked)
769 seq_puts(s, " [LOCKED]");
770}
771
772static const struct pinctrl_ops chv_pinctrl_ops = {
773 .get_groups_count = chv_get_groups_count,
774 .get_group_name = chv_get_group_name,
775 .get_group_pins = chv_get_group_pins,
776 .pin_dbg_show = chv_pin_dbg_show,
777};
778
779static int chv_get_functions_count(struct pinctrl_dev *pctldev)
780{
781 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
782
783 return pctrl->community->nfunctions;
784}
785
786static const char *chv_get_function_name(struct pinctrl_dev *pctldev,
787 unsigned function)
788{
789 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
790
791 return pctrl->community->functions[function].name;
792}
793
794static int chv_get_function_groups(struct pinctrl_dev *pctldev,
795 unsigned function,
796 const char * const **groups,
797 unsigned * const ngroups)
798{
799 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
800
801 *groups = pctrl->community->functions[function].groups;
802 *ngroups = pctrl->community->functions[function].ngroups;
803 return 0;
804}
805
806static int chv_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned function,
807 unsigned group)
808{
809 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
810 const struct chv_pingroup *grp;
811 unsigned long flags;
812 int i;
813
814 grp = &pctrl->community->groups[group];
815
0bd50d71 816 raw_spin_lock_irqsave(&chv_lock, flags);
6e08d6bb
MW		 817
818 /* Check first that the pad is not locked */
819 for (i = 0; i < grp->npins; i++) {
820 if (chv_pad_locked(pctrl, grp->pins[i])) {
821 dev_warn(pctrl->dev, "unable to set mode for locked pin %u\n",
822 grp->pins[i]);
0bd50d71 823 raw_spin_unlock_irqrestore(&chv_lock, flags);
6e08d6bb
MW		 824 return -EBUSY;
825 }
826 }
827
828 for (i = 0; i < grp->npins; i++) {
829 const struct chv_alternate_function *altfunc = &grp->altfunc;
830 int pin = grp->pins[i];
831 void __iomem *reg;
832 u32 value;
833
834 /* Check if there is pin-specific config */
835 if (grp->overrides) {
836 int j;
837
838 for (j = 0; j < grp->noverrides; j++) {
839 if (grp->overrides[j].pin == pin) {
840 altfunc = &grp->overrides[j];
841 break;
842 }
843 }
844 }
845
846 reg = chv_padreg(pctrl, pin, CHV_PADCTRL0);
847 value = readl(reg);
848 /* Disable GPIO mode */
849 value &= ~CHV_PADCTRL0_GPIOEN;
850 /* Set to desired mode */
851 value &= ~CHV_PADCTRL0_PMODE_MASK;
852 value |= altfunc->mode << CHV_PADCTRL0_PMODE_SHIFT;
853 chv_writel(value, reg);
854
855 /* Update for invert_oe */
856 reg = chv_padreg(pctrl, pin, CHV_PADCTRL1);
857 value = readl(reg) & ~CHV_PADCTRL1_INVRXTX_MASK;
858 if (altfunc->invert_oe)
859 value |= CHV_PADCTRL1_INVRXTX_TXENABLE;
860 chv_writel(value, reg);
861
862 dev_dbg(pctrl->dev, "configured pin %u mode %u OE %sinverted\n",
863 pin, altfunc->mode, altfunc->invert_oe ? "" : "not ");
864 }
865
0bd50d71 866 raw_spin_unlock_irqrestore(&chv_lock, flags);
6e08d6bb
MW		 867
868 return 0;
869}
870
871static int chv_gpio_request_enable(struct pinctrl_dev *pctldev,
872 struct pinctrl_gpio_range *range,
873 unsigned offset)
874{
875 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
876 unsigned long flags;
877 void __iomem *reg;
878 u32 value;
879
0bd50d71 880 raw_spin_lock_irqsave(&chv_lock, flags);
6e08d6bb
MW		 881
882 if (chv_pad_locked(pctrl, offset)) {
883 value = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0));
884 if (!(value & CHV_PADCTRL0_GPIOEN)) {
885 /* Locked so cannot enable */
0bd50d71 886 raw_spin_unlock_irqrestore(&chv_lock, flags);
6e08d6bb
MW		 887 return -EBUSY;
888 }
889 } else {
890 int i;
891
892 /* Reset the interrupt mapping */
893 for (i = 0; i < ARRAY_SIZE(pctrl->intr_lines); i++) {
894 if (pctrl->intr_lines[i] == offset) {
895 pctrl->intr_lines[i] = 0;
896 break;
897 }
898 }
899
900 /* Disable interrupt generation */
901 reg = chv_padreg(pctrl, offset, CHV_PADCTRL1);
902 value = readl(reg);
903 value &= ~CHV_PADCTRL1_INTWAKECFG_MASK;
904 value &= ~CHV_PADCTRL1_INVRXTX_MASK;
905 chv_writel(value, reg);
906
6e08d6bb 907 reg = chv_padreg(pctrl, offset, CHV_PADCTRL0);
2479c730
MW		 908 value = readl(reg);
909
910 /*
911 * If the pin is in HiZ mode (both TX and RX buffers are
912 * disabled) we turn it to be input now.
913 */
914 if ((value & CHV_PADCTRL0_GPIOCFG_MASK) ==
915 (CHV_PADCTRL0_GPIOCFG_HIZ << CHV_PADCTRL0_GPIOCFG_SHIFT)) {
916 value &= ~CHV_PADCTRL0_GPIOCFG_MASK;
917 value |= CHV_PADCTRL0_GPIOCFG_GPI <<
918 CHV_PADCTRL0_GPIOCFG_SHIFT;
919 }
920
921 /* Switch to a GPIO mode */
922 value |= CHV_PADCTRL0_GPIOEN;
6e08d6bb
MW		 923 chv_writel(value, reg);
924 }
925
0bd50d71 926 raw_spin_unlock_irqrestore(&chv_lock, flags);
6e08d6bb
MW		 927
928 return 0;
929}
930
931static void chv_gpio_disable_free(struct pinctrl_dev *pctldev,
932 struct pinctrl_gpio_range *range,
933 unsigned offset)
934{
935 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
936 unsigned long flags;
937 void __iomem *reg;
938 u32 value;
939
0bd50d71 940 raw_spin_lock_irqsave(&chv_lock, flags);
6e08d6bb
MW		 941
942 reg = chv_padreg(pctrl, offset, CHV_PADCTRL0);
943 value = readl(reg) & ~CHV_PADCTRL0_GPIOEN;
944 chv_writel(value, reg);
945
0bd50d71 946 raw_spin_unlock_irqrestore(&chv_lock, flags);
6e08d6bb
MW		 947}
948
949static int chv_gpio_set_direction(struct pinctrl_dev *pctldev,
950 struct pinctrl_gpio_range *range,
951 unsigned offset, bool input)
952{
953 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
954 void __iomem *reg = chv_padreg(pctrl, offset, CHV_PADCTRL0);
955 unsigned long flags;
956 u32 ctrl0;
957
0bd50d71 958 raw_spin_lock_irqsave(&chv_lock, flags);
6e08d6bb
MW		 959
960 ctrl0 = readl(reg) & ~CHV_PADCTRL0_GPIOCFG_MASK;
961 if (input)
962 ctrl0 |= CHV_PADCTRL0_GPIOCFG_GPI << CHV_PADCTRL0_GPIOCFG_SHIFT;
963 else
964 ctrl0 |= CHV_PADCTRL0_GPIOCFG_GPO << CHV_PADCTRL0_GPIOCFG_SHIFT;
965 chv_writel(ctrl0, reg);
966
0bd50d71 967 raw_spin_unlock_irqrestore(&chv_lock, flags);
6e08d6bb
MW		 968
969 return 0;
970}
971
972static const struct pinmux_ops chv_pinmux_ops = {
973 .get_functions_count = chv_get_functions_count,
974 .get_function_name = chv_get_function_name,
975 .get_function_groups = chv_get_function_groups,
976 .set_mux = chv_pinmux_set_mux,
977 .gpio_request_enable = chv_gpio_request_enable,
978 .gpio_disable_free = chv_gpio_disable_free,
979 .gpio_set_direction = chv_gpio_set_direction,
980};
981
982static int chv_config_get(struct pinctrl_dev *pctldev, unsigned pin,
983 unsigned long *config)
984{
985 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
986 enum pin_config_param param = pinconf_to_config_param(*config);
987 unsigned long flags;
988 u32 ctrl0, ctrl1;
989 u16 arg = 0;
990 u32 term;
991
0bd50d71 992 raw_spin_lock_irqsave(&chv_lock, flags);
6e08d6bb
MW		 993 ctrl0 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
994 ctrl1 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL1));
0bd50d71 995 raw_spin_unlock_irqrestore(&chv_lock, flags);
6e08d6bb
MW		 996
997 term = (ctrl0 & CHV_PADCTRL0_TERM_MASK) >> CHV_PADCTRL0_TERM_SHIFT;
998
999 switch (param) {
1000 case PIN_CONFIG_BIAS_DISABLE:
1001 if (term)
1002 return -EINVAL;
1003 break;
1004
1005 case PIN_CONFIG_BIAS_PULL_UP:
1006 if (!(ctrl0 & CHV_PADCTRL0_TERM_UP))
1007 return -EINVAL;
1008
1009 switch (term) {
1010 case CHV_PADCTRL0_TERM_20K:
1011 arg = 20000;
1012 break;
1013 case CHV_PADCTRL0_TERM_5K:
1014 arg = 5000;
1015 break;
1016 case CHV_PADCTRL0_TERM_1K:
1017 arg = 1000;
1018 break;
1019 }
1020
1021 break;
1022
1023 case PIN_CONFIG_BIAS_PULL_DOWN:
1024 if (!term || (ctrl0 & CHV_PADCTRL0_TERM_UP))
1025 return -EINVAL;
1026
1027 switch (term) {
1028 case CHV_PADCTRL0_TERM_20K:
1029 arg = 20000;
1030 break;
1031 case CHV_PADCTRL0_TERM_5K:
1032 arg = 5000;
1033 break;
1034 }
1035
1036 break;
1037
1038 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
1039 if (!(ctrl1 & CHV_PADCTRL1_ODEN))
1040 return -EINVAL;
1041 break;
1042
1043 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: {
1044 u32 cfg;
1045
1046 cfg = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK;
1047 cfg >>= CHV_PADCTRL0_GPIOCFG_SHIFT;
1048 if (cfg != CHV_PADCTRL0_GPIOCFG_HIZ)
1049 return -EINVAL;
1050
1051 break;
1052 }
1053
1054 default:
1055 return -ENOTSUPP;
1056 }
1057
1058 *config = pinconf_to_config_packed(param, arg);
1059 return 0;
1060}
1061
1062static int chv_config_set_pull(struct chv_pinctrl *pctrl, unsigned pin,
58957d2e 1063 enum pin_config_param param, u32 arg)
6e08d6bb
MW		 1064{
1065 void __iomem *reg = chv_padreg(pctrl, pin, CHV_PADCTRL0);
1066 unsigned long flags;
1067 u32 ctrl0, pull;
1068
0bd50d71 1069 raw_spin_lock_irqsave(&chv_lock, flags);
6e08d6bb
MW		 1070 ctrl0 = readl(reg);
1071
1072 switch (param) {
1073 case PIN_CONFIG_BIAS_DISABLE:
1074 ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP);
1075 break;
1076
1077 case PIN_CONFIG_BIAS_PULL_UP:
1078 ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP);
1079
1080 switch (arg) {
1081 case 1000:
1082 /* For 1k there is only pull up */
1083 pull = CHV_PADCTRL0_TERM_1K << CHV_PADCTRL0_TERM_SHIFT;
1084 break;
1085 case 5000:
1086 pull = CHV_PADCTRL0_TERM_5K << CHV_PADCTRL0_TERM_SHIFT;
1087 break;
1088 case 20000:
1089 pull = CHV_PADCTRL0_TERM_20K << CHV_PADCTRL0_TERM_SHIFT;
1090 break;
1091 default:
0bd50d71 1092 raw_spin_unlock_irqrestore(&chv_lock, flags);
6e08d6bb
MW		 1093 return -EINVAL;
1094 }
1095
1096 ctrl0 |= CHV_PADCTRL0_TERM_UP | pull;
1097 break;
1098
1099 case PIN_CONFIG_BIAS_PULL_DOWN:
1100 ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP);
1101
1102 switch (arg) {
1103 case 5000:
1104 pull = CHV_PADCTRL0_TERM_5K << CHV_PADCTRL0_TERM_SHIFT;
1105 break;
1106 case 20000:
1107 pull = CHV_PADCTRL0_TERM_20K << CHV_PADCTRL0_TERM_SHIFT;
1108 break;
1109 default:
0bd50d71 1110 raw_spin_unlock_irqrestore(&chv_lock, flags);
6e08d6bb
MW		 1111 return -EINVAL;
1112 }
1113
1114 ctrl0 |= pull;
1115 break;
1116
1117 default:
0bd50d71 1118 raw_spin_unlock_irqrestore(&chv_lock, flags);
6e08d6bb
MW		 1119 return -EINVAL;
1120 }
1121
1122 chv_writel(ctrl0, reg);
0bd50d71 1123 raw_spin_unlock_irqrestore(&chv_lock, flags);
6e08d6bb
MW		 1124
1125 return 0;
1126}
1127
ccdf81d0
DD		 1128static int chv_config_set_oden(struct chv_pinctrl *pctrl, unsigned int pin,
1129 bool enable)
1130{
1131 void __iomem *reg = chv_padreg(pctrl, pin, CHV_PADCTRL1);
1132 unsigned long flags;
1133 u32 ctrl1;
1134
1135 raw_spin_lock_irqsave(&chv_lock, flags);
1136 ctrl1 = readl(reg);
1137
1138 if (enable)
1139 ctrl1 |= CHV_PADCTRL1_ODEN;
1140 else
1141 ctrl1 &= ~CHV_PADCTRL1_ODEN;
1142
1143 chv_writel(ctrl1, reg);
1144 raw_spin_unlock_irqrestore(&chv_lock, flags);
1145
1146 return 0;
1147}
1148
6e08d6bb
MW		 1149static int chv_config_set(struct pinctrl_dev *pctldev, unsigned pin,
1150 unsigned long *configs, unsigned nconfigs)
1151{
1152 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
1153 enum pin_config_param param;
1154 int i, ret;
58957d2e 1155 u32 arg;
6e08d6bb
MW		 1156
1157 if (chv_pad_locked(pctrl, pin))
1158 return -EBUSY;
1159
1160 for (i = 0; i < nconfigs; i++) {
1161 param = pinconf_to_config_param(configs[i]);
1162 arg = pinconf_to_config_argument(configs[i]);
1163
1164 switch (param) {
1165 case PIN_CONFIG_BIAS_DISABLE:
1166 case PIN_CONFIG_BIAS_PULL_UP:
1167 case PIN_CONFIG_BIAS_PULL_DOWN:
1168 ret = chv_config_set_pull(pctrl, pin, param, arg);
1169 if (ret)
1170 return ret;
1171 break;
1172
ccdf81d0
DD		 1173 case PIN_CONFIG_DRIVE_PUSH_PULL:
1174 ret = chv_config_set_oden(pctrl, pin, false);
1175 if (ret)
1176 return ret;
1177 break;
1178
1179 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
1180 ret = chv_config_set_oden(pctrl, pin, true);
1181 if (ret)
1182 return ret;
1183 break;
1184
6e08d6bb
MW		 1185 default:
1186 return -ENOTSUPP;
1187 }
1188
1189 dev_dbg(pctrl->dev, "pin %d set config %d arg %u\n", pin,
1190 param, arg);
1191 }
1192
1193 return 0;
1194}
1195
77401d7f
DD		 1196static int chv_config_group_get(struct pinctrl_dev *pctldev,
1197 unsigned int group,
1198 unsigned long *config)
1199{
1200 const unsigned int *pins;
1201 unsigned int npins;
1202 int ret;
1203
1204 ret = chv_get_group_pins(pctldev, group, &pins, &npins);
1205 if (ret)
1206 return ret;
1207
1208 ret = chv_config_get(pctldev, pins[0], config);
1209 if (ret)
1210 return ret;
1211
1212 return 0;
1213}
1214
1215static int chv_config_group_set(struct pinctrl_dev *pctldev,
1216 unsigned int group, unsigned long *configs,
1217 unsigned int num_configs)
1218{
1219 const unsigned int *pins;
1220 unsigned int npins;
1221 int i, ret;
1222
1223 ret = chv_get_group_pins(pctldev, group, &pins, &npins);
1224 if (ret)
1225 return ret;
1226
1227 for (i = 0; i < npins; i++) {
1228 ret = chv_config_set(pctldev, pins[i], configs, num_configs);
1229 if (ret)
1230 return ret;
1231 }
1232
1233 return 0;
1234}
1235
6e08d6bb
MW		 1236static const struct pinconf_ops chv_pinconf_ops = {
1237 .is_generic = true,
1238 .pin_config_set = chv_config_set,
1239 .pin_config_get = chv_config_get,
77401d7f
DD		 1240 .pin_config_group_get = chv_config_group_get,
1241 .pin_config_group_set = chv_config_group_set,
6e08d6bb
MW		 1242};
1243
1244static struct pinctrl_desc chv_pinctrl_desc = {
1245 .pctlops = &chv_pinctrl_ops,
1246 .pmxops = &chv_pinmux_ops,
1247 .confops = &chv_pinconf_ops,
1248 .owner = THIS_MODULE,
1249};
1250
6e08d6bb
MW		 1251static int chv_gpio_get(struct gpio_chip *chip, unsigned offset)
1252{
0587d3db 1253 struct chv_pinctrl *pctrl = gpiochip_get_data(chip);
4585b000 1254 unsigned long flags;
6e08d6bb
MW		 1255 u32 ctrl0, cfg;
1256
0bd50d71 1257 raw_spin_lock_irqsave(&chv_lock, flags);
85ef722e 1258 ctrl0 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0));
0bd50d71 1259 raw_spin_unlock_irqrestore(&chv_lock, flags);
6e08d6bb
MW		 1260
1261 cfg = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK;
1262 cfg >>= CHV_PADCTRL0_GPIOCFG_SHIFT;
1263
1264 if (cfg == CHV_PADCTRL0_GPIOCFG_GPO)
1265 return !!(ctrl0 & CHV_PADCTRL0_GPIOTXSTATE);
1266 return !!(ctrl0 & CHV_PADCTRL0_GPIORXSTATE);
1267}
1268
1269static void chv_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1270{
0587d3db 1271 struct chv_pinctrl *pctrl = gpiochip_get_data(chip);
6e08d6bb
MW		 1272 unsigned long flags;
1273 void __iomem *reg;
1274 u32 ctrl0;
1275
0bd50d71 1276 raw_spin_lock_irqsave(&chv_lock, flags);
6e08d6bb 1277
85ef722e 1278 reg = chv_padreg(pctrl, offset, CHV_PADCTRL0);
6e08d6bb
MW		 1279 ctrl0 = readl(reg);
1280
1281 if (value)
1282 ctrl0 |= CHV_PADCTRL0_GPIOTXSTATE;
1283 else
1284 ctrl0 &= ~CHV_PADCTRL0_GPIOTXSTATE;
1285
1286 chv_writel(ctrl0, reg);
1287
0bd50d71 1288 raw_spin_unlock_irqrestore(&chv_lock, flags);
6e08d6bb
MW		 1289}
1290
1291static int chv_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
1292{
0587d3db 1293 struct chv_pinctrl *pctrl = gpiochip_get_data(chip);
6e08d6bb 1294 u32 ctrl0, direction;
4585b000 1295 unsigned long flags;
6e08d6bb 1296
0bd50d71 1297 raw_spin_lock_irqsave(&chv_lock, flags);
85ef722e 1298 ctrl0 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0));
0bd50d71 1299 raw_spin_unlock_irqrestore(&chv_lock, flags);
6e08d6bb
MW		 1300
1301 direction = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK;
1302 direction >>= CHV_PADCTRL0_GPIOCFG_SHIFT;
1303
1304 return direction != CHV_PADCTRL0_GPIOCFG_GPO;
1305}
1306
1307static int chv_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
1308{
1309 return pinctrl_gpio_direction_input(chip->base + offset);
1310}
1311
1312static int chv_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
1313 int value)
1314{
549e783f 1315 chv_gpio_set(chip, offset, value);
6e08d6bb
MW		 1316 return pinctrl_gpio_direction_output(chip->base + offset);
1317}
1318
1319static const struct gpio_chip chv_gpio_chip = {
1320 .owner = THIS_MODULE,
98c85d58
JG		 1321 .request = gpiochip_generic_request,
1322 .free = gpiochip_generic_free,
6e08d6bb
MW		 1323 .get_direction = chv_gpio_get_direction,
1324 .direction_input = chv_gpio_direction_input,
1325 .direction_output = chv_gpio_direction_output,
1326 .get = chv_gpio_get,
1327 .set = chv_gpio_set,
1328};
1329
1330static void chv_gpio_irq_ack(struct irq_data *d)
1331{
1332 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0587d3db 1333 struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
85ef722e 1334 int pin = irqd_to_hwirq(d);
6e08d6bb
MW		 1335 u32 intr_line;
1336
0bd50d71 1337 raw_spin_lock(&chv_lock);
6e08d6bb
MW		 1338
1339 intr_line = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
1340 intr_line &= CHV_PADCTRL0_INTSEL_MASK;
1341 intr_line >>= CHV_PADCTRL0_INTSEL_SHIFT;
1342 chv_writel(BIT(intr_line), pctrl->regs + CHV_INTSTAT);
1343
0bd50d71 1344 raw_spin_unlock(&chv_lock);
6e08d6bb
MW		 1345}
1346
1347static void chv_gpio_irq_mask_unmask(struct irq_data *d, bool mask)
1348{
1349 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0587d3db 1350 struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
85ef722e 1351 int pin = irqd_to_hwirq(d);
6e08d6bb
MW		 1352 u32 value, intr_line;
1353 unsigned long flags;
1354
0bd50d71 1355 raw_spin_lock_irqsave(&chv_lock, flags);
6e08d6bb
MW		 1356
1357 intr_line = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
1358 intr_line &= CHV_PADCTRL0_INTSEL_MASK;
1359 intr_line >>= CHV_PADCTRL0_INTSEL_SHIFT;
1360
1361 value = readl(pctrl->regs + CHV_INTMASK);
1362 if (mask)
1363 value &= ~BIT(intr_line);
1364 else
1365 value |= BIT(intr_line);
1366 chv_writel(value, pctrl->regs + CHV_INTMASK);
1367
0bd50d71 1368 raw_spin_unlock_irqrestore(&chv_lock, flags);
6e08d6bb
MW		 1369}
1370
1371static void chv_gpio_irq_mask(struct irq_data *d)
1372{
1373 chv_gpio_irq_mask_unmask(d, true);
1374}
1375
1376static void chv_gpio_irq_unmask(struct irq_data *d)
1377{
1378 chv_gpio_irq_mask_unmask(d, false);
1379}
1380
e6c906de
MW		 1381static unsigned chv_gpio_irq_startup(struct irq_data *d)
1382{
1383 /*
1384 * Check if the interrupt has been requested with 0 as triggering
1385 * type. In that case it is assumed that the current values
1386 * programmed to the hardware are used (e.g BIOS configured
1387 * defaults).
1388 *
1389 * In that case ->irq_set_type() will never be called so we need to
1390 * read back the values from hardware now, set correct flow handler
1391 * and update mappings before the interrupt is being used.
1392 */
1393 if (irqd_get_trigger_type(d) == IRQ_TYPE_NONE) {
1394 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0587d3db 1395 struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
85ef722e 1396 unsigned pin = irqd_to_hwirq(d);
e6c906de
MW		 1397 irq_flow_handler_t handler;
1398 unsigned long flags;
1399 u32 intsel, value;
1400
0bd50d71 1401 raw_spin_lock_irqsave(&chv_lock, flags);
e6c906de
MW		 1402 intsel = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
1403 intsel &= CHV_PADCTRL0_INTSEL_MASK;
1404 intsel >>= CHV_PADCTRL0_INTSEL_SHIFT;
1405
1406 value = readl(chv_padreg(pctrl, pin, CHV_PADCTRL1));
1407 if (value & CHV_PADCTRL1_INTWAKECFG_LEVEL)
1408 handler = handle_level_irq;
1409 else
1410 handler = handle_edge_irq;
1411
e6c906de 1412 if (!pctrl->intr_lines[intsel]) {
a4e3f783 1413 irq_set_handler_locked(d, handler);
85ef722e 1414 pctrl->intr_lines[intsel] = pin;
e6c906de 1415 }
0bd50d71 1416 raw_spin_unlock_irqrestore(&chv_lock, flags);
e6c906de
MW		 1417 }
1418
1419 chv_gpio_irq_unmask(d);
1420 return 0;
1421}
1422
6e08d6bb
MW		 1423static int chv_gpio_irq_type(struct irq_data *d, unsigned type)
1424{
1425 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0587d3db 1426 struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
85ef722e 1427 unsigned pin = irqd_to_hwirq(d);
6e08d6bb
MW		 1428 unsigned long flags;
1429 u32 value;
1430
0bd50d71 1431 raw_spin_lock_irqsave(&chv_lock, flags);
6e08d6bb
MW		 1432
1433 /*
1434 * Pins which can be used as shared interrupt are configured in
1435 * BIOS. Driver trusts BIOS configurations and assigns different
1436 * handler according to the irq type.
1437 *
1438 * Driver needs to save the mapping between each pin and
1439 * its interrupt line.
1440 * 1. If the pin cfg is locked in BIOS:
1441 * Trust BIOS has programmed IntWakeCfg bits correctly,
1442 * driver just needs to save the mapping.
1443 * 2. If the pin cfg is not locked in BIOS:
1444 * Driver programs the IntWakeCfg bits and save the mapping.
1445 */
1446 if (!chv_pad_locked(pctrl, pin)) {
1447 void __iomem *reg = chv_padreg(pctrl, pin, CHV_PADCTRL1);
1448
1449 value = readl(reg);
1450 value &= ~CHV_PADCTRL1_INTWAKECFG_MASK;
1451 value &= ~CHV_PADCTRL1_INVRXTX_MASK;
1452
1453 if (type & IRQ_TYPE_EDGE_BOTH) {
1454 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
1455 value |= CHV_PADCTRL1_INTWAKECFG_BOTH;
1456 else if (type & IRQ_TYPE_EDGE_RISING)
1457 value |= CHV_PADCTRL1_INTWAKECFG_RISING;
1458 else if (type & IRQ_TYPE_EDGE_FALLING)
1459 value |= CHV_PADCTRL1_INTWAKECFG_FALLING;
1460 } else if (type & IRQ_TYPE_LEVEL_MASK) {
1461 value |= CHV_PADCTRL1_INTWAKECFG_LEVEL;
1462 if (type & IRQ_TYPE_LEVEL_LOW)
1463 value |= CHV_PADCTRL1_INVRXTX_RXDATA;
1464 }
1465
1466 chv_writel(value, reg);
1467 }
1468
1469 value = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
1470 value &= CHV_PADCTRL0_INTSEL_MASK;
1471 value >>= CHV_PADCTRL0_INTSEL_SHIFT;
1472
85ef722e 1473 pctrl->intr_lines[value] = pin;
6e08d6bb
MW		 1474
1475 if (type & IRQ_TYPE_EDGE_BOTH)
a4e3f783 1476 irq_set_handler_locked(d, handle_edge_irq);
6e08d6bb 1477 else if (type & IRQ_TYPE_LEVEL_MASK)
a4e3f783 1478 irq_set_handler_locked(d, handle_level_irq);
6e08d6bb 1479
0bd50d71 1480 raw_spin_unlock_irqrestore(&chv_lock, flags);
6e08d6bb
MW		 1481
1482 return 0;
1483}
1484
bd0b9ac4 1485static void chv_gpio_irq_handler(struct irq_desc *desc)
6e08d6bb
MW		 1486{
1487 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
0587d3db 1488 struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
5663bb27 1489 struct irq_chip *chip = irq_desc_get_chip(desc);
6e08d6bb
MW		 1490 unsigned long pending;
1491 u32 intr_line;
1492
1493 chained_irq_enter(chip, desc);
1494
1495 pending = readl(pctrl->regs + CHV_INTSTAT);
47c950d1 1496 for_each_set_bit(intr_line, &pending, pctrl->community->nirqs) {
6e08d6bb
MW		 1497 unsigned irq, offset;
1498
1499 offset = pctrl->intr_lines[intr_line];
f0fbe7bc 1500 irq = irq_find_mapping(gc->irq.domain, offset);
6e08d6bb
MW		 1501 generic_handle_irq(irq);
1502 }
1503
1504 chained_irq_exit(chip, desc);
1505}
1506
70365027
MW		 1507/*
1508 * Certain machines seem to hardcode Linux IRQ numbers in their ACPI
1509 * tables. Since we leave GPIOs that are not capable of generating
1510 * interrupts out of the irqdomain the numbering will be different and
1511 * cause devices using the hardcoded IRQ numbers fail. In order not to
1512 * break such machines we will only mask pins from irqdomain if the machine
1513 * is not listed below.
1514 */
1515static const struct dmi_system_id chv_no_valid_mask[] = {
2a8209fa 1516 /* See https://bugzilla.kernel.org/show_bug.cgi?id=194945 */
70365027 1517 {
2a8209fa 1518 .ident = "Intel_Strago based Chromebooks (All models)",
70365027
MW		 1519 .matches = {
1520 DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"),
2a8209fa
MW		 1521 DMI_MATCH(DMI_PRODUCT_FAMILY, "Intel_Strago"),
1522 },
1523 },
2d80bd3f
AS		 1524 {
1525 .ident = "HP Chromebook 11 G5 (Setzer)",
1526 .matches = {
1527 DMI_MATCH(DMI_SYS_VENDOR, "HP"),
1528 DMI_MATCH(DMI_PRODUCT_NAME, "Setzer"),
1529 },
1530 },
2a8209fa
MW		 1531 {
1532 .ident = "Acer Chromebook R11 (Cyan)",
1533 .matches = {
1534 DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"),
1535 DMI_MATCH(DMI_PRODUCT_NAME, "Cyan"),
1536 },
1537 },
1538 {
1539 .ident = "Samsung Chromebook 3 (Celes)",
1540 .matches = {
1541 DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"),
1542 DMI_MATCH(DMI_PRODUCT_NAME, "Celes"),
70365027 1543 },
a9de080b
WY		 1544 },
1545 {}
70365027
MW		 1546};
1547
6e08d6bb
MW		 1548static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq)
1549{
1550 const struct chv_gpio_pinrange *range;
1551 struct gpio_chip *chip = &pctrl->chip;
70365027 1552 bool need_valid_mask = !dmi_check_system(chv_no_valid_mask);
85ef722e
MW		 1553 const struct chv_community *community = pctrl->community;
1554 int ret, i, irq_base;
6e08d6bb
MW		 1555
1556 *chip = chv_gpio_chip;
1557
85ef722e 1558 chip->ngpio = community->pins[community->npins - 1].number + 1;
6e08d6bb 1559 chip->label = dev_name(pctrl->dev);
58383c78 1560 chip->parent = pctrl->dev;
6e08d6bb 1561 chip->base = -1;
dc7b0387 1562 chip->irq.need_valid_mask = need_valid_mask;
6e08d6bb 1563
d1073418 1564 ret = devm_gpiochip_add_data(pctrl->dev, chip, pctrl);
6e08d6bb
MW		 1565 if (ret) {
1566 dev_err(pctrl->dev, "Failed to register gpiochip\n");
1567 return ret;
1568 }
1569
85ef722e
MW		 1570 for (i = 0; i < community->ngpio_ranges; i++) {
1571 range = &community->gpio_ranges[i];
1572 ret = gpiochip_add_pin_range(chip, dev_name(pctrl->dev),
1573 range->base, range->base,
1574 range->npins);
6e08d6bb
MW		 1575 if (ret) {
1576 dev_err(pctrl->dev, "failed to add GPIO pin range\n");
d1073418 1577 return ret;
6e08d6bb 1578 }
6e08d6bb
MW		 1579 }
1580
47c950d1 1581 /* Do not add GPIOs that can only generate GPEs to the IRQ domain */
85ef722e 1582 for (i = 0; i < community->npins; i++) {
47c950d1
MW		 1583 const struct pinctrl_pin_desc *desc;
1584 u32 intsel;
1585
85ef722e 1586 desc = &community->pins[i];
47c950d1
MW		 1587
1588 intsel = readl(chv_padreg(pctrl, desc->number, CHV_PADCTRL0));
1589 intsel &= CHV_PADCTRL0_INTSEL_MASK;
1590 intsel >>= CHV_PADCTRL0_INTSEL_SHIFT;
1591
85ef722e 1592 if (need_valid_mask && intsel >= community->nirqs)
974d08a5 1593 clear_bit(desc->number, chip->irq.valid_mask);
47c950d1
MW		 1594 }
1595
d2b3c353
MW		 1596 /*
1597 * The same set of machines in chv_no_valid_mask[] have incorrectly
1598 * configured GPIOs that generate spurious interrupts so we use
1599 * this same list to apply another quirk for them.
1600 *
1601 * See also https://bugzilla.kernel.org/show_bug.cgi?id=197953.
1602 */
1603 if (!need_valid_mask) {
1604 /*
1605 * Mask all interrupts the community is able to generate
1606 * but leave the ones that can only generate GPEs unmasked.
1607 */
1608 chv_writel(GENMASK(31, pctrl->community->nirqs),
1609 pctrl->regs + CHV_INTMASK);
1610 }
1611
bcb48cca 1612 /* Clear all interrupts */
6e08d6bb
MW		 1613 chv_writel(0xffff, pctrl->regs + CHV_INTSTAT);
1614
845e405e
GS		 1615 if (!need_valid_mask) {
1616 irq_base = devm_irq_alloc_descs(pctrl->dev, -1, 0,
1f6c5883 1617 community->npins, NUMA_NO_NODE);
845e405e
GS		 1618 if (irq_base < 0) {
1619 dev_err(pctrl->dev, "Failed to allocate IRQ numbers\n");
1620 return irq_base;
1621 }
845e405e
GS		 1622 }
1623
05f77e19
AS		 1624 pctrl->irqchip.name = "chv-gpio";
1625 pctrl->irqchip.irq_startup = chv_gpio_irq_startup;
1626 pctrl->irqchip.irq_ack = chv_gpio_irq_ack;
1627 pctrl->irqchip.irq_mask = chv_gpio_irq_mask;
1628 pctrl->irqchip.irq_unmask = chv_gpio_irq_unmask;
1629 pctrl->irqchip.irq_set_type = chv_gpio_irq_type;
1630 pctrl->irqchip.flags = IRQCHIP_SKIP_SET_WAKE;
1631
1632 ret = gpiochip_irqchip_add(chip, &pctrl->irqchip, 0,
bcb48cca 1633 handle_bad_irq, IRQ_TYPE_NONE);
6e08d6bb
MW		 1634 if (ret) {
1635 dev_err(pctrl->dev, "failed to add IRQ chip\n");
d1073418 1636 return ret;
6e08d6bb
MW		 1637 }
1638
1f6c5883
MW		 1639 if (!need_valid_mask) {
1640 for (i = 0; i < community->ngpio_ranges; i++) {
1641 range = &community->gpio_ranges[i];
1642
1643 irq_domain_associate_many(chip->irq.domain, irq_base,
1644 range->base, range->npins);
1645 irq_base += range->npins;
1646 }
1647 }
1648
05f77e19 1649 gpiochip_set_chained_irqchip(chip, &pctrl->irqchip, irq,
6e08d6bb
MW		 1650 chv_gpio_irq_handler);
1651 return 0;
6e08d6bb
MW		 1652}
1653
a0b02859
HG		 1654static acpi_status chv_pinctrl_mmio_access_handler(u32 function,
1655 acpi_physical_address address, u32 bits, u64 *value,
1656 void *handler_context, void *region_context)
1657{
1658 struct chv_pinctrl *pctrl = region_context;
1659 unsigned long flags;
1660 acpi_status ret = AE_OK;
1661
1662 raw_spin_lock_irqsave(&chv_lock, flags);
1663
1664 if (function == ACPI_WRITE)
1665 chv_writel((u32)(*value), pctrl->regs + (u32)address);
1666 else if (function == ACPI_READ)
1667 *value = readl(pctrl->regs + (u32)address);
1668 else
1669 ret = AE_BAD_PARAMETER;
1670
1671 raw_spin_unlock_irqrestore(&chv_lock, flags);
1672
1673 return ret;
1674}
1675
6e08d6bb
MW		 1676static int chv_pinctrl_probe(struct platform_device *pdev)
1677{
1678 struct chv_pinctrl *pctrl;
1679 struct acpi_device *adev;
1680 struct resource *res;
a0b02859 1681 acpi_status status;
6e08d6bb
MW		 1682 int ret, irq, i;
1683
1684 adev = ACPI_COMPANION(&pdev->dev);
1685 if (!adev)
1686 return -ENODEV;
1687
1688 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
1689 if (!pctrl)
1690 return -ENOMEM;
1691
1692 for (i = 0; i < ARRAY_SIZE(chv_communities); i++)
1693 if (!strcmp(adev->pnp.unique_id, chv_communities[i]->uid)) {
1694 pctrl->community = chv_communities[i];
1695 break;
1696 }
1697 if (i == ARRAY_SIZE(chv_communities))
1698 return -ENODEV;
1699
6e08d6bb
MW		 1700 pctrl->dev = &pdev->dev;
1701
9eb457b5
MW		 1702#ifdef CONFIG_PM_SLEEP
1703 pctrl->saved_pin_context = devm_kcalloc(pctrl->dev,
1704 pctrl->community->npins, sizeof(*pctrl->saved_pin_context),
1705 GFP_KERNEL);
1706 if (!pctrl->saved_pin_context)
1707 return -ENOMEM;
1708#endif
1709
6e08d6bb
MW		 1710 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1711 pctrl->regs = devm_ioremap_resource(&pdev->dev, res);
1712 if (IS_ERR(pctrl->regs))
1713 return PTR_ERR(pctrl->regs);
1714
1715 irq = platform_get_irq(pdev, 0);
1716 if (irq < 0) {
1717 dev_err(&pdev->dev, "failed to get interrupt number\n");
1718 return irq;
1719 }
1720
1721 pctrl->pctldesc = chv_pinctrl_desc;
1722 pctrl->pctldesc.name = dev_name(&pdev->dev);
1723 pctrl->pctldesc.pins = pctrl->community->pins;
1724 pctrl->pctldesc.npins = pctrl->community->npins;
1725
7cf061fa
LD		 1726 pctrl->pctldev = devm_pinctrl_register(&pdev->dev, &pctrl->pctldesc,
1727 pctrl);
323de9ef 1728 if (IS_ERR(pctrl->pctldev)) {
6e08d6bb 1729 dev_err(&pdev->dev, "failed to register pinctrl driver\n");
323de9ef 1730 return PTR_ERR(pctrl->pctldev);
6e08d6bb
MW		 1731 }
1732
1733 ret = chv_gpio_probe(pctrl, irq);
7cf061fa 1734 if (ret)
6e08d6bb 1735 return ret;
6e08d6bb 1736
a0b02859
HG		 1737 status = acpi_install_address_space_handler(adev->handle,
1738 pctrl->community->acpi_space_id,
1739 chv_pinctrl_mmio_access_handler,
1740 NULL, pctrl);
1741 if (ACPI_FAILURE(status))
1742 dev_err(&pdev->dev, "failed to install ACPI addr space handler\n");
1743
6e08d6bb
MW		 1744 platform_set_drvdata(pdev, pctrl);
1745
1746 return 0;
1747}
1748
a0b02859
HG		 1749static int chv_pinctrl_remove(struct platform_device *pdev)
1750{
1751 struct chv_pinctrl *pctrl = platform_get_drvdata(pdev);
1752
1753 acpi_remove_address_space_handler(ACPI_COMPANION(&pdev->dev),
1754 pctrl->community->acpi_space_id,
1755 chv_pinctrl_mmio_access_handler);
1756
1757 return 0;
1758}
1759
9eb457b5 1760#ifdef CONFIG_PM_SLEEP
d2cdf5dc 1761static int chv_pinctrl_suspend_noirq(struct device *dev)
9eb457b5
MW		 1762{
1763 struct platform_device *pdev = to_platform_device(dev);
1764 struct chv_pinctrl *pctrl = platform_get_drvdata(pdev);
56211121 1765 unsigned long flags;
9eb457b5
MW		 1766 int i;
1767
56211121
MW		 1768 raw_spin_lock_irqsave(&chv_lock, flags);
1769
9eb457b5
MW		 1770 pctrl->saved_intmask = readl(pctrl->regs + CHV_INTMASK);
1771
1772 for (i = 0; i < pctrl->community->npins; i++) {
1773 const struct pinctrl_pin_desc *desc;
1774 struct chv_pin_context *ctx;
1775 void __iomem *reg;
1776
1777 desc = &pctrl->community->pins[i];
1778 if (chv_pad_locked(pctrl, desc->number))
1779 continue;
1780
1781 ctx = &pctrl->saved_pin_context[i];
1782
1783 reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL0);
1784 ctx->padctrl0 = readl(reg) & ~CHV_PADCTRL0_GPIORXSTATE;
1785
1786 reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL1);
1787 ctx->padctrl1 = readl(reg);
1788 }
1789
56211121
MW		 1790 raw_spin_unlock_irqrestore(&chv_lock, flags);
1791
9eb457b5
MW		 1792 return 0;
1793}
1794
d2cdf5dc 1795static int chv_pinctrl_resume_noirq(struct device *dev)
9eb457b5
MW		 1796{
1797 struct platform_device *pdev = to_platform_device(dev);
1798 struct chv_pinctrl *pctrl = platform_get_drvdata(pdev);
56211121 1799 unsigned long flags;
9eb457b5
MW		 1800 int i;
1801
56211121
MW		 1802 raw_spin_lock_irqsave(&chv_lock, flags);
1803
9eb457b5
MW		 1804 /*
1805 * Mask all interrupts before restoring per-pin configuration
1806 * registers because we don't know in which state BIOS left them
1807 * upon exiting suspend.
1808 */
1809 chv_writel(0, pctrl->regs + CHV_INTMASK);
1810
1811 for (i = 0; i < pctrl->community->npins; i++) {
1812 const struct pinctrl_pin_desc *desc;
1813 const struct chv_pin_context *ctx;
1814 void __iomem *reg;
1815 u32 val;
1816
1817 desc = &pctrl->community->pins[i];
1818 if (chv_pad_locked(pctrl, desc->number))
1819 continue;
1820
1821 ctx = &pctrl->saved_pin_context[i];
1822
1823 /* Only restore if our saved state differs from the current */
1824 reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL0);
1825 val = readl(reg) & ~CHV_PADCTRL0_GPIORXSTATE;
1826 if (ctx->padctrl0 != val) {
1827 chv_writel(ctx->padctrl0, reg);
1828 dev_dbg(pctrl->dev, "restored pin %2u ctrl0 0x%08x\n",
1829 desc->number, readl(reg));
1830 }
1831
1832 reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL1);
1833 val = readl(reg);
1834 if (ctx->padctrl1 != val) {
1835 chv_writel(ctx->padctrl1, reg);
1836 dev_dbg(pctrl->dev, "restored pin %2u ctrl1 0x%08x\n",
1837 desc->number, readl(reg));
1838 }
1839 }
1840
1841 /*
1842 * Now that all pins are restored to known state, we can restore
1843 * the interrupt mask register as well.
1844 */
1845 chv_writel(0xffff, pctrl->regs + CHV_INTSTAT);
1846 chv_writel(pctrl->saved_intmask, pctrl->regs + CHV_INTMASK);
1847
56211121
MW		 1848 raw_spin_unlock_irqrestore(&chv_lock, flags);
1849
9eb457b5
MW		 1850 return 0;
1851}
1852#endif
1853
1854static const struct dev_pm_ops chv_pinctrl_pm_ops = {
d2cdf5dc
MW		 1855 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(chv_pinctrl_suspend_noirq,
1856 chv_pinctrl_resume_noirq)
9eb457b5
MW		 1857};
1858
6e08d6bb
MW		 1859static const struct acpi_device_id chv_pinctrl_acpi_match[] = {
1860 { "INT33FF" },
1861 { }
1862};
1863MODULE_DEVICE_TABLE(acpi, chv_pinctrl_acpi_match);
1864
1865static struct platform_driver chv_pinctrl_driver = {
1866 .probe = chv_pinctrl_probe,
a0b02859 1867 .remove = chv_pinctrl_remove,
6e08d6bb
MW		 1868 .driver = {
1869 .name = "cherryview-pinctrl",
9eb457b5 1870 .pm = &chv_pinctrl_pm_ops,
6e08d6bb
MW		 1871 .acpi_match_table = chv_pinctrl_acpi_match,
1872 },
1873};
1874
1875static int __init chv_pinctrl_init(void)
1876{
1877 return platform_driver_register(&chv_pinctrl_driver);
1878}
1879subsys_initcall(chv_pinctrl_init);
1880
1881static void __exit chv_pinctrl_exit(void)
1882{
1883 platform_driver_unregister(&chv_pinctrl_driver);
1884}
1885module_exit(chv_pinctrl_exit);
1886
1887MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
1888MODULE_DESCRIPTION("Intel Cherryview/Braswell pinctrl driver");
1889MODULE_LICENSE("GPL v2");
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