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Merge tag 'for-linus-20170825' of git://git.infradead.org/linux-mtd
[mirror_ubuntu-artful-kernel.git] / drivers / pinctrl / intel / pinctrl-cherryview.c
CommitLineData
6e08d6bb
MW		 1/*
2 * Cherryview/Braswell pinctrl driver
3 *
4 * Copyright (C) 2014, Intel Corporation
5 * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
6 *
7 * This driver is based on the original Cherryview GPIO driver by
8 * Ning Li <ning.li@intel.com>
9 * Alan Cox <alan@linux.intel.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
70365027 16#include <linux/dmi.h>
6e08d6bb
MW		 17#include <linux/kernel.h>
18#include <linux/module.h>
19#include <linux/init.h>
20#include <linux/types.h>
21#include <linux/gpio.h>
22#include <linux/gpio/driver.h>
23#include <linux/acpi.h>
24#include <linux/pinctrl/pinctrl.h>
25#include <linux/pinctrl/pinmux.h>
26#include <linux/pinctrl/pinconf.h>
27#include <linux/pinctrl/pinconf-generic.h>
28#include <linux/platform_device.h>
29
30#define CHV_INTSTAT 0x300
31#define CHV_INTMASK 0x380
32
33#define FAMILY_PAD_REGS_OFF 0x4400
34#define FAMILY_PAD_REGS_SIZE 0x400
35#define MAX_FAMILY_PAD_GPIO_NO 15
36#define GPIO_REGS_SIZE 8
37
38#define CHV_PADCTRL0 0x000
39#define CHV_PADCTRL0_INTSEL_SHIFT 28
40#define CHV_PADCTRL0_INTSEL_MASK (0xf << CHV_PADCTRL0_INTSEL_SHIFT)
41#define CHV_PADCTRL0_TERM_UP BIT(23)
42#define CHV_PADCTRL0_TERM_SHIFT 20
43#define CHV_PADCTRL0_TERM_MASK (7 << CHV_PADCTRL0_TERM_SHIFT)
44#define CHV_PADCTRL0_TERM_20K 1
45#define CHV_PADCTRL0_TERM_5K 2
46#define CHV_PADCTRL0_TERM_1K 4
47#define CHV_PADCTRL0_PMODE_SHIFT 16
48#define CHV_PADCTRL0_PMODE_MASK (0xf << CHV_PADCTRL0_PMODE_SHIFT)
49#define CHV_PADCTRL0_GPIOEN BIT(15)
50#define CHV_PADCTRL0_GPIOCFG_SHIFT 8
51#define CHV_PADCTRL0_GPIOCFG_MASK (7 << CHV_PADCTRL0_GPIOCFG_SHIFT)
52#define CHV_PADCTRL0_GPIOCFG_GPIO 0
53#define CHV_PADCTRL0_GPIOCFG_GPO 1
54#define CHV_PADCTRL0_GPIOCFG_GPI 2
55#define CHV_PADCTRL0_GPIOCFG_HIZ 3
56#define CHV_PADCTRL0_GPIOTXSTATE BIT(1)
57#define CHV_PADCTRL0_GPIORXSTATE BIT(0)
58
59#define CHV_PADCTRL1 0x004
60#define CHV_PADCTRL1_CFGLOCK BIT(31)
61#define CHV_PADCTRL1_INVRXTX_SHIFT 4
62#define CHV_PADCTRL1_INVRXTX_MASK (0xf << CHV_PADCTRL1_INVRXTX_SHIFT)
63#define CHV_PADCTRL1_INVRXTX_TXENABLE (2 << CHV_PADCTRL1_INVRXTX_SHIFT)
64#define CHV_PADCTRL1_ODEN BIT(3)
65#define CHV_PADCTRL1_INVRXTX_RXDATA (4 << CHV_PADCTRL1_INVRXTX_SHIFT)
66#define CHV_PADCTRL1_INTWAKECFG_MASK 7
67#define CHV_PADCTRL1_INTWAKECFG_FALLING 1
68#define CHV_PADCTRL1_INTWAKECFG_RISING 2
69#define CHV_PADCTRL1_INTWAKECFG_BOTH 3
70#define CHV_PADCTRL1_INTWAKECFG_LEVEL 4
71
72/**
73 * struct chv_alternate_function - A per group or per pin alternate function
74 * @pin: Pin number (only used in per pin configs)
75 * @mode: Mode the pin should be set in
76 * @invert_oe: Invert OE for this pin
77 */
78struct chv_alternate_function {
79 unsigned pin;
80 u8 mode;
81 bool invert_oe;
82};
83
84/**
85 * struct chv_pincgroup - describes a CHV pin group
86 * @name: Name of the group
87 * @pins: An array of pins in this group
88 * @npins: Number of pins in this group
89 * @altfunc: Alternate function applied to all pins in this group
90 * @overrides: Alternate function override per pin or %NULL if not used
91 * @noverrides: Number of per pin alternate function overrides if
92 * @overrides != NULL.
93 */
94struct chv_pingroup {
95 const char *name;
96 const unsigned *pins;
97 size_t npins;
98 struct chv_alternate_function altfunc;
99 const struct chv_alternate_function *overrides;
100 size_t noverrides;
101};
102
103/**
104 * struct chv_function - A CHV pinmux function
105 * @name: Name of the function
106 * @groups: An array of groups for this function
107 * @ngroups: Number of groups in @groups
108 */
109struct chv_function {
110 const char *name;
111 const char * const *groups;
112 size_t ngroups;
113};
114
115/**
116 * struct chv_gpio_pinrange - A range of pins that can be used as GPIOs
117 * @base: Start pin number
118 * @npins: Number of pins in this range
119 */
120struct chv_gpio_pinrange {
121 unsigned base;
122 unsigned npins;
123};
124
125/**
126 * struct chv_community - A community specific configuration
127 * @uid: ACPI _UID used to match the community
128 * @pins: All pins in this community
129 * @npins: Number of pins
130 * @groups: All groups in this community
131 * @ngroups: Number of groups
132 * @functions: All functions in this community
133 * @nfunctions: Number of functions
134 * @ngpios: Number of GPIOs in this community
135 * @gpio_ranges: An array of GPIO ranges in this community
136 * @ngpio_ranges: Number of GPIO ranges
137 * @ngpios: Total number of GPIOs in this community
47c950d1 138 * @nirqs: Total number of IRQs this community can generate
6e08d6bb
MW		 139 */
140struct chv_community {
141 const char *uid;
142 const struct pinctrl_pin_desc *pins;
143 size_t npins;
144 const struct chv_pingroup *groups;
145 size_t ngroups;
146 const struct chv_function *functions;
147 size_t nfunctions;
148 const struct chv_gpio_pinrange *gpio_ranges;
149 size_t ngpio_ranges;
150 size_t ngpios;
47c950d1 151 size_t nirqs;
a0b02859 152 acpi_adr_space_type acpi_space_id;
6e08d6bb
MW		 153};
154
9eb457b5
MW		 155struct chv_pin_context {
156 u32 padctrl0;
157 u32 padctrl1;
158};
159
6e08d6bb
MW		 160/**
161 * struct chv_pinctrl - CHV pinctrl private structure
162 * @dev: Pointer to the parent device
163 * @pctldesc: Pin controller description
164 * @pctldev: Pointer to the pin controller device
165 * @chip: GPIO chip in this pin controller
166 * @regs: MMIO registers
6e08d6bb
MW		 167 * @intr_lines: Stores mapping between 16 HW interrupt wires and GPIO
168 * offset (in GPIO number space)
169 * @community: Community this pinctrl instance represents
170 *
171 * The first group in @groups is expected to contain all pins that can be
172 * used as GPIOs.
173 */
174struct chv_pinctrl {
175 struct device *dev;
176 struct pinctrl_desc pctldesc;
177 struct pinctrl_dev *pctldev;
178 struct gpio_chip chip;
179 void __iomem *regs;
6e08d6bb
MW		 180 unsigned intr_lines[16];
181 const struct chv_community *community;
9eb457b5
MW		 182 u32 saved_intmask;
183 struct chv_pin_context *saved_pin_context;
6e08d6bb
MW		 184};
185
6e08d6bb
MW		 186#define ALTERNATE_FUNCTION(p, m, i) \
187 { \
188 .pin = (p), \
189 .mode = (m), \
190 .invert_oe = (i), \
191 }
192
193#define PIN_GROUP(n, p, m, i) \
194 { \
195 .name = (n), \
196 .pins = (p), \
197 .npins = ARRAY_SIZE((p)), \
198 .altfunc.mode = (m), \
199 .altfunc.invert_oe = (i), \
200 }
201
202#define PIN_GROUP_WITH_OVERRIDE(n, p, m, i, o) \
203 { \
204 .name = (n), \
205 .pins = (p), \
206 .npins = ARRAY_SIZE((p)), \
207 .altfunc.mode = (m), \
208 .altfunc.invert_oe = (i), \
209 .overrides = (o), \
210 .noverrides = ARRAY_SIZE((o)), \
211 }
212
213#define FUNCTION(n, g) \
214 { \
215 .name = (n), \
216 .groups = (g), \
217 .ngroups = ARRAY_SIZE((g)), \
218 }
219
220#define GPIO_PINRANGE(start, end) \
221 { \
222 .base = (start), \
223 .npins = (end) - (start) + 1, \
224 }
225
226static const struct pinctrl_pin_desc southwest_pins[] = {
227 PINCTRL_PIN(0, "FST_SPI_D2"),
228 PINCTRL_PIN(1, "FST_SPI_D0"),
229 PINCTRL_PIN(2, "FST_SPI_CLK"),
230 PINCTRL_PIN(3, "FST_SPI_D3"),
231 PINCTRL_PIN(4, "FST_SPI_CS1_B"),
232 PINCTRL_PIN(5, "FST_SPI_D1"),
233 PINCTRL_PIN(6, "FST_SPI_CS0_B"),
234 PINCTRL_PIN(7, "FST_SPI_CS2_B"),
235
236 PINCTRL_PIN(15, "UART1_RTS_B"),
237 PINCTRL_PIN(16, "UART1_RXD"),
238 PINCTRL_PIN(17, "UART2_RXD"),
239 PINCTRL_PIN(18, "UART1_CTS_B"),
240 PINCTRL_PIN(19, "UART2_RTS_B"),
241 PINCTRL_PIN(20, "UART1_TXD"),
242 PINCTRL_PIN(21, "UART2_TXD"),
243 PINCTRL_PIN(22, "UART2_CTS_B"),
244
245 PINCTRL_PIN(30, "MF_HDA_CLK"),
246 PINCTRL_PIN(31, "MF_HDA_RSTB"),
247 PINCTRL_PIN(32, "MF_HDA_SDIO"),
248 PINCTRL_PIN(33, "MF_HDA_SDO"),
249 PINCTRL_PIN(34, "MF_HDA_DOCKRSTB"),
250 PINCTRL_PIN(35, "MF_HDA_SYNC"),
251 PINCTRL_PIN(36, "MF_HDA_SDI1"),
252 PINCTRL_PIN(37, "MF_HDA_DOCKENB"),
253
254 PINCTRL_PIN(45, "I2C5_SDA"),
255 PINCTRL_PIN(46, "I2C4_SDA"),
256 PINCTRL_PIN(47, "I2C6_SDA"),
257 PINCTRL_PIN(48, "I2C5_SCL"),
258 PINCTRL_PIN(49, "I2C_NFC_SDA"),
259 PINCTRL_PIN(50, "I2C4_SCL"),
260 PINCTRL_PIN(51, "I2C6_SCL"),
261 PINCTRL_PIN(52, "I2C_NFC_SCL"),
262
263 PINCTRL_PIN(60, "I2C1_SDA"),
264 PINCTRL_PIN(61, "I2C0_SDA"),
265 PINCTRL_PIN(62, "I2C2_SDA"),
266 PINCTRL_PIN(63, "I2C1_SCL"),
267 PINCTRL_PIN(64, "I2C3_SDA"),
268 PINCTRL_PIN(65, "I2C0_SCL"),
269 PINCTRL_PIN(66, "I2C2_SCL"),
270 PINCTRL_PIN(67, "I2C3_SCL"),
271
272 PINCTRL_PIN(75, "SATA_GP0"),
273 PINCTRL_PIN(76, "SATA_GP1"),
274 PINCTRL_PIN(77, "SATA_LEDN"),
275 PINCTRL_PIN(78, "SATA_GP2"),
276 PINCTRL_PIN(79, "MF_SMB_ALERTB"),
277 PINCTRL_PIN(80, "SATA_GP3"),
278 PINCTRL_PIN(81, "MF_SMB_CLK"),
279 PINCTRL_PIN(82, "MF_SMB_DATA"),
280
281 PINCTRL_PIN(90, "PCIE_CLKREQ0B"),
282 PINCTRL_PIN(91, "PCIE_CLKREQ1B"),
283 PINCTRL_PIN(92, "GP_SSP_2_CLK"),
284 PINCTRL_PIN(93, "PCIE_CLKREQ2B"),
285 PINCTRL_PIN(94, "GP_SSP_2_RXD"),
286 PINCTRL_PIN(95, "PCIE_CLKREQ3B"),
287 PINCTRL_PIN(96, "GP_SSP_2_FS"),
288 PINCTRL_PIN(97, "GP_SSP_2_TXD"),
289};
290
291static const unsigned southwest_fspi_pins[] = { 0, 1, 2, 3, 4, 5, 6, 7 };
292static const unsigned southwest_uart0_pins[] = { 16, 20 };
293static const unsigned southwest_uart1_pins[] = { 15, 16, 18, 20 };
294static const unsigned southwest_uart2_pins[] = { 17, 19, 21, 22 };
295static const unsigned southwest_i2c0_pins[] = { 61, 65 };
296static const unsigned southwest_hda_pins[] = { 30, 31, 32, 33, 34, 35, 36, 37 };
297static const unsigned southwest_lpe_pins[] = {
298 30, 31, 32, 33, 34, 35, 36, 37, 92, 94, 96, 97,
299};
300static const unsigned southwest_i2c1_pins[] = { 60, 63 };
301static const unsigned southwest_i2c2_pins[] = { 62, 66 };
302static const unsigned southwest_i2c3_pins[] = { 64, 67 };
303static const unsigned southwest_i2c4_pins[] = { 46, 50 };
304static const unsigned southwest_i2c5_pins[] = { 45, 48 };
305static const unsigned southwest_i2c6_pins[] = { 47, 51 };
306static const unsigned southwest_i2c_nfc_pins[] = { 49, 52 };
307static const unsigned southwest_smbus_pins[] = { 79, 81, 82 };
308static const unsigned southwest_spi3_pins[] = { 76, 79, 80, 81, 82 };
309
310/* LPE I2S TXD pins need to have invert_oe set */
311static const struct chv_alternate_function southwest_lpe_altfuncs[] = {
312 ALTERNATE_FUNCTION(30, 1, true),
313 ALTERNATE_FUNCTION(34, 1, true),
314 ALTERNATE_FUNCTION(97, 1, true),
315};
316
317/*
318 * Two spi3 chipselects are available in different mode than the main spi3
319 * functionality, which is using mode 1.
320 */
321static const struct chv_alternate_function southwest_spi3_altfuncs[] = {
322 ALTERNATE_FUNCTION(76, 3, false),
323 ALTERNATE_FUNCTION(80, 3, false),
324};
325
326static const struct chv_pingroup southwest_groups[] = {
327 PIN_GROUP("uart0_grp", southwest_uart0_pins, 2, false),
328 PIN_GROUP("uart1_grp", southwest_uart1_pins, 1, false),
329 PIN_GROUP("uart2_grp", southwest_uart2_pins, 1, false),
330 PIN_GROUP("hda_grp", southwest_hda_pins, 2, false),
331 PIN_GROUP("i2c0_grp", southwest_i2c0_pins, 1, true),
332 PIN_GROUP("i2c1_grp", southwest_i2c1_pins, 1, true),
333 PIN_GROUP("i2c2_grp", southwest_i2c2_pins, 1, true),
334 PIN_GROUP("i2c3_grp", southwest_i2c3_pins, 1, true),
335 PIN_GROUP("i2c4_grp", southwest_i2c4_pins, 1, true),
336 PIN_GROUP("i2c5_grp", southwest_i2c5_pins, 1, true),
337 PIN_GROUP("i2c6_grp", southwest_i2c6_pins, 1, true),
338 PIN_GROUP("i2c_nfc_grp", southwest_i2c_nfc_pins, 2, true),
339
340 PIN_GROUP_WITH_OVERRIDE("lpe_grp", southwest_lpe_pins, 1, false,
341 southwest_lpe_altfuncs),
342 PIN_GROUP_WITH_OVERRIDE("spi3_grp", southwest_spi3_pins, 2, false,
343 southwest_spi3_altfuncs),
344};
345
346static const char * const southwest_uart0_groups[] = { "uart0_grp" };
347static const char * const southwest_uart1_groups[] = { "uart1_grp" };
348static const char * const southwest_uart2_groups[] = { "uart2_grp" };
349static const char * const southwest_hda_groups[] = { "hda_grp" };
350static const char * const southwest_lpe_groups[] = { "lpe_grp" };
351static const char * const southwest_i2c0_groups[] = { "i2c0_grp" };
352static const char * const southwest_i2c1_groups[] = { "i2c1_grp" };
353static const char * const southwest_i2c2_groups[] = { "i2c2_grp" };
354static const char * const southwest_i2c3_groups[] = { "i2c3_grp" };
355static const char * const southwest_i2c4_groups[] = { "i2c4_grp" };
356static const char * const southwest_i2c5_groups[] = { "i2c5_grp" };
357static const char * const southwest_i2c6_groups[] = { "i2c6_grp" };
358static const char * const southwest_i2c_nfc_groups[] = { "i2c_nfc_grp" };
359static const char * const southwest_spi3_groups[] = { "spi3_grp" };
360
361/*
362 * Only do pinmuxing for certain LPSS devices for now. Rest of the pins are
363 * enabled only as GPIOs.
364 */
365static const struct chv_function southwest_functions[] = {
366 FUNCTION("uart0", southwest_uart0_groups),
367 FUNCTION("uart1", southwest_uart1_groups),
368 FUNCTION("uart2", southwest_uart2_groups),
369 FUNCTION("hda", southwest_hda_groups),
370 FUNCTION("lpe", southwest_lpe_groups),
371 FUNCTION("i2c0", southwest_i2c0_groups),
372 FUNCTION("i2c1", southwest_i2c1_groups),
373 FUNCTION("i2c2", southwest_i2c2_groups),
374 FUNCTION("i2c3", southwest_i2c3_groups),
375 FUNCTION("i2c4", southwest_i2c4_groups),
376 FUNCTION("i2c5", southwest_i2c5_groups),
377 FUNCTION("i2c6", southwest_i2c6_groups),
378 FUNCTION("i2c_nfc", southwest_i2c_nfc_groups),
379 FUNCTION("spi3", southwest_spi3_groups),
380};
381
382static const struct chv_gpio_pinrange southwest_gpio_ranges[] = {
383 GPIO_PINRANGE(0, 7),
384 GPIO_PINRANGE(15, 22),
385 GPIO_PINRANGE(30, 37),
386 GPIO_PINRANGE(45, 52),
387 GPIO_PINRANGE(60, 67),
388 GPIO_PINRANGE(75, 82),
389 GPIO_PINRANGE(90, 97),
390};
391
392static const struct chv_community southwest_community = {
393 .uid = "1",
394 .pins = southwest_pins,
395 .npins = ARRAY_SIZE(southwest_pins),
396 .groups = southwest_groups,
397 .ngroups = ARRAY_SIZE(southwest_groups),
398 .functions = southwest_functions,
399 .nfunctions = ARRAY_SIZE(southwest_functions),
400 .gpio_ranges = southwest_gpio_ranges,
401 .ngpio_ranges = ARRAY_SIZE(southwest_gpio_ranges),
402 .ngpios = ARRAY_SIZE(southwest_pins),
47c950d1
MW		 403 /*
404 * Southwest community can benerate GPIO interrupts only for the
405 * first 8 interrupts. The upper half (8-15) can only be used to
406 * trigger GPEs.
407 */
408 .nirqs = 8,
a0b02859 409 .acpi_space_id = 0x91,
6e08d6bb
MW		 410};
411
412static const struct pinctrl_pin_desc north_pins[] = {
413 PINCTRL_PIN(0, "GPIO_DFX_0"),
414 PINCTRL_PIN(1, "GPIO_DFX_3"),
415 PINCTRL_PIN(2, "GPIO_DFX_7"),
416 PINCTRL_PIN(3, "GPIO_DFX_1"),
417 PINCTRL_PIN(4, "GPIO_DFX_5"),
418 PINCTRL_PIN(5, "GPIO_DFX_4"),
419 PINCTRL_PIN(6, "GPIO_DFX_8"),
420 PINCTRL_PIN(7, "GPIO_DFX_2"),
421 PINCTRL_PIN(8, "GPIO_DFX_6"),
422
423 PINCTRL_PIN(15, "GPIO_SUS0"),
424 PINCTRL_PIN(16, "SEC_GPIO_SUS10"),
425 PINCTRL_PIN(17, "GPIO_SUS3"),
426 PINCTRL_PIN(18, "GPIO_SUS7"),
427 PINCTRL_PIN(19, "GPIO_SUS1"),
428 PINCTRL_PIN(20, "GPIO_SUS5"),
429 PINCTRL_PIN(21, "SEC_GPIO_SUS11"),
430 PINCTRL_PIN(22, "GPIO_SUS4"),
431 PINCTRL_PIN(23, "SEC_GPIO_SUS8"),
432 PINCTRL_PIN(24, "GPIO_SUS2"),
433 PINCTRL_PIN(25, "GPIO_SUS6"),
434 PINCTRL_PIN(26, "CX_PREQ_B"),
435 PINCTRL_PIN(27, "SEC_GPIO_SUS9"),
436
437 PINCTRL_PIN(30, "TRST_B"),
438 PINCTRL_PIN(31, "TCK"),
439 PINCTRL_PIN(32, "PROCHOT_B"),
440 PINCTRL_PIN(33, "SVIDO_DATA"),
441 PINCTRL_PIN(34, "TMS"),
442 PINCTRL_PIN(35, "CX_PRDY_B_2"),
443 PINCTRL_PIN(36, "TDO_2"),
444 PINCTRL_PIN(37, "CX_PRDY_B"),
445 PINCTRL_PIN(38, "SVIDO_ALERT_B"),
446 PINCTRL_PIN(39, "TDO"),
447 PINCTRL_PIN(40, "SVIDO_CLK"),
448 PINCTRL_PIN(41, "TDI"),
449
450 PINCTRL_PIN(45, "GP_CAMERASB_05"),
451 PINCTRL_PIN(46, "GP_CAMERASB_02"),
452 PINCTRL_PIN(47, "GP_CAMERASB_08"),
453 PINCTRL_PIN(48, "GP_CAMERASB_00"),
454 PINCTRL_PIN(49, "GP_CAMERASB_06"),
455 PINCTRL_PIN(50, "GP_CAMERASB_10"),
456 PINCTRL_PIN(51, "GP_CAMERASB_03"),
457 PINCTRL_PIN(52, "GP_CAMERASB_09"),
458 PINCTRL_PIN(53, "GP_CAMERASB_01"),
459 PINCTRL_PIN(54, "GP_CAMERASB_07"),
460 PINCTRL_PIN(55, "GP_CAMERASB_11"),
461 PINCTRL_PIN(56, "GP_CAMERASB_04"),
462
463 PINCTRL_PIN(60, "PANEL0_BKLTEN"),
464 PINCTRL_PIN(61, "HV_DDI0_HPD"),
465 PINCTRL_PIN(62, "HV_DDI2_DDC_SDA"),
466 PINCTRL_PIN(63, "PANEL1_BKLTCTL"),
467 PINCTRL_PIN(64, "HV_DDI1_HPD"),
468 PINCTRL_PIN(65, "PANEL0_BKLTCTL"),
469 PINCTRL_PIN(66, "HV_DDI0_DDC_SDA"),
470 PINCTRL_PIN(67, "HV_DDI2_DDC_SCL"),
471 PINCTRL_PIN(68, "HV_DDI2_HPD"),
472 PINCTRL_PIN(69, "PANEL1_VDDEN"),
473 PINCTRL_PIN(70, "PANEL1_BKLTEN"),
474 PINCTRL_PIN(71, "HV_DDI0_DDC_SCL"),
475 PINCTRL_PIN(72, "PANEL0_VDDEN"),
476};
477
478static const struct chv_gpio_pinrange north_gpio_ranges[] = {
479 GPIO_PINRANGE(0, 8),
480 GPIO_PINRANGE(15, 27),
481 GPIO_PINRANGE(30, 41),
482 GPIO_PINRANGE(45, 56),
483 GPIO_PINRANGE(60, 72),
484};
485
486static const struct chv_community north_community = {
487 .uid = "2",
488 .pins = north_pins,
489 .npins = ARRAY_SIZE(north_pins),
490 .gpio_ranges = north_gpio_ranges,
491 .ngpio_ranges = ARRAY_SIZE(north_gpio_ranges),
492 .ngpios = ARRAY_SIZE(north_pins),
47c950d1
MW		 493 /*
494 * North community can benerate GPIO interrupts only for the first
495 * 8 interrupts. The upper half (8-15) can only be used to trigger
496 * GPEs.
497 */
498 .nirqs = 8,
a0b02859 499 .acpi_space_id = 0x92,
6e08d6bb
MW		 500};
501
502static const struct pinctrl_pin_desc east_pins[] = {
503 PINCTRL_PIN(0, "PMU_SLP_S3_B"),
504 PINCTRL_PIN(1, "PMU_BATLOW_B"),
505 PINCTRL_PIN(2, "SUS_STAT_B"),
506 PINCTRL_PIN(3, "PMU_SLP_S0IX_B"),
507 PINCTRL_PIN(4, "PMU_AC_PRESENT"),
508 PINCTRL_PIN(5, "PMU_PLTRST_B"),
509 PINCTRL_PIN(6, "PMU_SUSCLK"),
510 PINCTRL_PIN(7, "PMU_SLP_LAN_B"),
511 PINCTRL_PIN(8, "PMU_PWRBTN_B"),
512 PINCTRL_PIN(9, "PMU_SLP_S4_B"),
513 PINCTRL_PIN(10, "PMU_WAKE_B"),
514 PINCTRL_PIN(11, "PMU_WAKE_LAN_B"),
515
516 PINCTRL_PIN(15, "MF_ISH_GPIO_3"),
517 PINCTRL_PIN(16, "MF_ISH_GPIO_7"),
518 PINCTRL_PIN(17, "MF_ISH_I2C1_SCL"),
519 PINCTRL_PIN(18, "MF_ISH_GPIO_1"),
520 PINCTRL_PIN(19, "MF_ISH_GPIO_5"),
521 PINCTRL_PIN(20, "MF_ISH_GPIO_9"),
522 PINCTRL_PIN(21, "MF_ISH_GPIO_0"),
523 PINCTRL_PIN(22, "MF_ISH_GPIO_4"),
524 PINCTRL_PIN(23, "MF_ISH_GPIO_8"),
525 PINCTRL_PIN(24, "MF_ISH_GPIO_2"),
526 PINCTRL_PIN(25, "MF_ISH_GPIO_6"),
527 PINCTRL_PIN(26, "MF_ISH_I2C1_SDA"),
528};
529
530static const struct chv_gpio_pinrange east_gpio_ranges[] = {
531 GPIO_PINRANGE(0, 11),
532 GPIO_PINRANGE(15, 26),
533};
534
535static const struct chv_community east_community = {
536 .uid = "3",
537 .pins = east_pins,
538 .npins = ARRAY_SIZE(east_pins),
539 .gpio_ranges = east_gpio_ranges,
540 .ngpio_ranges = ARRAY_SIZE(east_gpio_ranges),
541 .ngpios = ARRAY_SIZE(east_pins),
47c950d1 542 .nirqs = 16,
a0b02859 543 .acpi_space_id = 0x93,
6e08d6bb
MW		 544};
545
546static const struct pinctrl_pin_desc southeast_pins[] = {
547 PINCTRL_PIN(0, "MF_PLT_CLK0"),
548 PINCTRL_PIN(1, "PWM1"),
549 PINCTRL_PIN(2, "MF_PLT_CLK1"),
550 PINCTRL_PIN(3, "MF_PLT_CLK4"),
551 PINCTRL_PIN(4, "MF_PLT_CLK3"),
552 PINCTRL_PIN(5, "PWM0"),
553 PINCTRL_PIN(6, "MF_PLT_CLK5"),
554 PINCTRL_PIN(7, "MF_PLT_CLK2"),
555
556 PINCTRL_PIN(15, "SDMMC2_D3_CD_B"),
557 PINCTRL_PIN(16, "SDMMC1_CLK"),
558 PINCTRL_PIN(17, "SDMMC1_D0"),
559 PINCTRL_PIN(18, "SDMMC2_D1"),
560 PINCTRL_PIN(19, "SDMMC2_CLK"),
561 PINCTRL_PIN(20, "SDMMC1_D2"),
562 PINCTRL_PIN(21, "SDMMC2_D2"),
563 PINCTRL_PIN(22, "SDMMC2_CMD"),
564 PINCTRL_PIN(23, "SDMMC1_CMD"),
565 PINCTRL_PIN(24, "SDMMC1_D1"),
566 PINCTRL_PIN(25, "SDMMC2_D0"),
567 PINCTRL_PIN(26, "SDMMC1_D3_CD_B"),
568
569 PINCTRL_PIN(30, "SDMMC3_D1"),
570 PINCTRL_PIN(31, "SDMMC3_CLK"),
571 PINCTRL_PIN(32, "SDMMC3_D3"),
572 PINCTRL_PIN(33, "SDMMC3_D2"),
573 PINCTRL_PIN(34, "SDMMC3_CMD"),
574 PINCTRL_PIN(35, "SDMMC3_D0"),
575
576 PINCTRL_PIN(45, "MF_LPC_AD2"),
577 PINCTRL_PIN(46, "LPC_CLKRUNB"),
578 PINCTRL_PIN(47, "MF_LPC_AD0"),
579 PINCTRL_PIN(48, "LPC_FRAMEB"),
580 PINCTRL_PIN(49, "MF_LPC_CLKOUT1"),
581 PINCTRL_PIN(50, "MF_LPC_AD3"),
582 PINCTRL_PIN(51, "MF_LPC_CLKOUT0"),
583 PINCTRL_PIN(52, "MF_LPC_AD1"),
584
585 PINCTRL_PIN(60, "SPI1_MISO"),
586 PINCTRL_PIN(61, "SPI1_CSO_B"),
587 PINCTRL_PIN(62, "SPI1_CLK"),
588 PINCTRL_PIN(63, "MMC1_D6"),
589 PINCTRL_PIN(64, "SPI1_MOSI"),
590 PINCTRL_PIN(65, "MMC1_D5"),
591 PINCTRL_PIN(66, "SPI1_CS1_B"),
592 PINCTRL_PIN(67, "MMC1_D4_SD_WE"),
593 PINCTRL_PIN(68, "MMC1_D7"),
594 PINCTRL_PIN(69, "MMC1_RCLK"),
595
596 PINCTRL_PIN(75, "USB_OC1_B"),
597 PINCTRL_PIN(76, "PMU_RESETBUTTON_B"),
598 PINCTRL_PIN(77, "GPIO_ALERT"),
599 PINCTRL_PIN(78, "SDMMC3_PWR_EN_B"),
600 PINCTRL_PIN(79, "ILB_SERIRQ"),
601 PINCTRL_PIN(80, "USB_OC0_B"),
602 PINCTRL_PIN(81, "SDMMC3_CD_B"),
603 PINCTRL_PIN(82, "SPKR"),
604 PINCTRL_PIN(83, "SUSPWRDNACK"),
605 PINCTRL_PIN(84, "SPARE_PIN"),
606 PINCTRL_PIN(85, "SDMMC3_1P8_EN"),
607};
608
609static const unsigned southeast_pwm0_pins[] = { 5 };
610static const unsigned southeast_pwm1_pins[] = { 1 };
611static const unsigned southeast_sdmmc1_pins[] = {
612 16, 17, 20, 23, 24, 26, 63, 65, 67, 68, 69,
613};
614static const unsigned southeast_sdmmc2_pins[] = { 15, 18, 19, 21, 22, 25 };
615static const unsigned southeast_sdmmc3_pins[] = {
616 30, 31, 32, 33, 34, 35, 78, 81, 85,
617};
618static const unsigned southeast_spi1_pins[] = { 60, 61, 62, 64, 66 };
619static const unsigned southeast_spi2_pins[] = { 2, 3, 4, 6, 7 };
620
621static const struct chv_pingroup southeast_groups[] = {
622 PIN_GROUP("pwm0_grp", southeast_pwm0_pins, 1, false),
623 PIN_GROUP("pwm1_grp", southeast_pwm1_pins, 1, false),
624 PIN_GROUP("sdmmc1_grp", southeast_sdmmc1_pins, 1, false),
625 PIN_GROUP("sdmmc2_grp", southeast_sdmmc2_pins, 1, false),
626 PIN_GROUP("sdmmc3_grp", southeast_sdmmc3_pins, 1, false),
627 PIN_GROUP("spi1_grp", southeast_spi1_pins, 1, false),
628 PIN_GROUP("spi2_grp", southeast_spi2_pins, 4, false),
629};
630
631static const char * const southeast_pwm0_groups[] = { "pwm0_grp" };
632static const char * const southeast_pwm1_groups[] = { "pwm1_grp" };
633static const char * const southeast_sdmmc1_groups[] = { "sdmmc1_grp" };
634static const char * const southeast_sdmmc2_groups[] = { "sdmmc2_grp" };
635static const char * const southeast_sdmmc3_groups[] = { "sdmmc3_grp" };
636static const char * const southeast_spi1_groups[] = { "spi1_grp" };
637static const char * const southeast_spi2_groups[] = { "spi2_grp" };
638
639static const struct chv_function southeast_functions[] = {
640 FUNCTION("pwm0", southeast_pwm0_groups),
641 FUNCTION("pwm1", southeast_pwm1_groups),
642 FUNCTION("sdmmc1", southeast_sdmmc1_groups),
643 FUNCTION("sdmmc2", southeast_sdmmc2_groups),
644 FUNCTION("sdmmc3", southeast_sdmmc3_groups),
645 FUNCTION("spi1", southeast_spi1_groups),
646 FUNCTION("spi2", southeast_spi2_groups),
647};
648
649static const struct chv_gpio_pinrange southeast_gpio_ranges[] = {
650 GPIO_PINRANGE(0, 7),
651 GPIO_PINRANGE(15, 26),
652 GPIO_PINRANGE(30, 35),
653 GPIO_PINRANGE(45, 52),
654 GPIO_PINRANGE(60, 69),
655 GPIO_PINRANGE(75, 85),
656};
657
658static const struct chv_community southeast_community = {
659 .uid = "4",
660 .pins = southeast_pins,
661 .npins = ARRAY_SIZE(southeast_pins),
662 .groups = southeast_groups,
663 .ngroups = ARRAY_SIZE(southeast_groups),
664 .functions = southeast_functions,
665 .nfunctions = ARRAY_SIZE(southeast_functions),
666 .gpio_ranges = southeast_gpio_ranges,
667 .ngpio_ranges = ARRAY_SIZE(southeast_gpio_ranges),
668 .ngpios = ARRAY_SIZE(southeast_pins),
47c950d1 669 .nirqs = 16,
a0b02859 670 .acpi_space_id = 0x94,
6e08d6bb
MW		 671};
672
673static const struct chv_community *chv_communities[] = {
674 &southwest_community,
675 &north_community,
676 &east_community,
677 &southeast_community,
678};
679
0bd50d71
DD		 680/*
681 * Lock to serialize register accesses
682 *
683 * Due to a silicon issue, a shared lock must be used to prevent
684 * concurrent accesses across the 4 GPIO controllers.
685 *
686 * See Intel Atom Z8000 Processor Series Specification Update (Rev. 005),
687 * errata #CHT34, for further information.
688 */
689static DEFINE_RAW_SPINLOCK(chv_lock);
690
6e08d6bb
MW		 691static void __iomem *chv_padreg(struct chv_pinctrl *pctrl, unsigned offset,
692 unsigned reg)
693{
694 unsigned family_no = offset / MAX_FAMILY_PAD_GPIO_NO;
695 unsigned pad_no = offset % MAX_FAMILY_PAD_GPIO_NO;
696
697 offset = FAMILY_PAD_REGS_OFF + FAMILY_PAD_REGS_SIZE * family_no +
698 GPIO_REGS_SIZE * pad_no;
699
700 return pctrl->regs + offset + reg;
701}
702
703static void chv_writel(u32 value, void __iomem *reg)
704{
705 writel(value, reg);
706 /* simple readback to confirm the bus transferring done */
707 readl(reg);
708}
709
710/* When Pad Cfg is locked, driver can only change GPIOTXState or GPIORXState */
711static bool chv_pad_locked(struct chv_pinctrl *pctrl, unsigned offset)
712{
713 void __iomem *reg;
714
715 reg = chv_padreg(pctrl, offset, CHV_PADCTRL1);
716 return readl(reg) & CHV_PADCTRL1_CFGLOCK;
717}
718
719static int chv_get_groups_count(struct pinctrl_dev *pctldev)
720{
721 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
722
723 return pctrl->community->ngroups;
724}
725
726static const char *chv_get_group_name(struct pinctrl_dev *pctldev,
727 unsigned group)
728{
729 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
730
731 return pctrl->community->groups[group].name;
732}
733
734static int chv_get_group_pins(struct pinctrl_dev *pctldev, unsigned group,
735 const unsigned **pins, unsigned *npins)
736{
737 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
738
739 *pins = pctrl->community->groups[group].pins;
740 *npins = pctrl->community->groups[group].npins;
741 return 0;
742}
743
744static void chv_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
745 unsigned offset)
746{
747 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
748 unsigned long flags;
749 u32 ctrl0, ctrl1;
750 bool locked;
751
0bd50d71 752 raw_spin_lock_irqsave(&chv_lock, flags);
6e08d6bb
MW		 753
754 ctrl0 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0));
755 ctrl1 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL1));
756 locked = chv_pad_locked(pctrl, offset);
757
0bd50d71 758 raw_spin_unlock_irqrestore(&chv_lock, flags);
6e08d6bb
MW		 759
760 if (ctrl0 & CHV_PADCTRL0_GPIOEN) {
761 seq_puts(s, "GPIO ");
762 } else {
763 u32 mode;
764
765 mode = ctrl0 & CHV_PADCTRL0_PMODE_MASK;
766 mode >>= CHV_PADCTRL0_PMODE_SHIFT;
767
768 seq_printf(s, "mode %d ", mode);
769 }
770
684373ea 771 seq_printf(s, "0x%08x 0x%08x", ctrl0, ctrl1);
6e08d6bb
MW		 772
773 if (locked)
774 seq_puts(s, " [LOCKED]");
775}
776
777static const struct pinctrl_ops chv_pinctrl_ops = {
778 .get_groups_count = chv_get_groups_count,
779 .get_group_name = chv_get_group_name,
780 .get_group_pins = chv_get_group_pins,
781 .pin_dbg_show = chv_pin_dbg_show,
782};
783
784static int chv_get_functions_count(struct pinctrl_dev *pctldev)
785{
786 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
787
788 return pctrl->community->nfunctions;
789}
790
791static const char *chv_get_function_name(struct pinctrl_dev *pctldev,
792 unsigned function)
793{
794 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
795
796 return pctrl->community->functions[function].name;
797}
798
799static int chv_get_function_groups(struct pinctrl_dev *pctldev,
800 unsigned function,
801 const char * const **groups,
802 unsigned * const ngroups)
803{
804 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
805
806 *groups = pctrl->community->functions[function].groups;
807 *ngroups = pctrl->community->functions[function].ngroups;
808 return 0;
809}
810
811static int chv_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned function,
812 unsigned group)
813{
814 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
815 const struct chv_pingroup *grp;
816 unsigned long flags;
817 int i;
818
819 grp = &pctrl->community->groups[group];
820
0bd50d71 821 raw_spin_lock_irqsave(&chv_lock, flags);
6e08d6bb
MW		 822
823 /* Check first that the pad is not locked */
824 for (i = 0; i < grp->npins; i++) {
825 if (chv_pad_locked(pctrl, grp->pins[i])) {
826 dev_warn(pctrl->dev, "unable to set mode for locked pin %u\n",
827 grp->pins[i]);
0bd50d71 828 raw_spin_unlock_irqrestore(&chv_lock, flags);
6e08d6bb
MW		 829 return -EBUSY;
830 }
831 }
832
833 for (i = 0; i < grp->npins; i++) {
834 const struct chv_alternate_function *altfunc = &grp->altfunc;
835 int pin = grp->pins[i];
836 void __iomem *reg;
837 u32 value;
838
839 /* Check if there is pin-specific config */
840 if (grp->overrides) {
841 int j;
842
843 for (j = 0; j < grp->noverrides; j++) {
844 if (grp->overrides[j].pin == pin) {
845 altfunc = &grp->overrides[j];
846 break;
847 }
848 }
849 }
850
851 reg = chv_padreg(pctrl, pin, CHV_PADCTRL0);
852 value = readl(reg);
853 /* Disable GPIO mode */
854 value &= ~CHV_PADCTRL0_GPIOEN;
855 /* Set to desired mode */
856 value &= ~CHV_PADCTRL0_PMODE_MASK;
857 value |= altfunc->mode << CHV_PADCTRL0_PMODE_SHIFT;
858 chv_writel(value, reg);
859
860 /* Update for invert_oe */
861 reg = chv_padreg(pctrl, pin, CHV_PADCTRL1);
862 value = readl(reg) & ~CHV_PADCTRL1_INVRXTX_MASK;
863 if (altfunc->invert_oe)
864 value |= CHV_PADCTRL1_INVRXTX_TXENABLE;
865 chv_writel(value, reg);
866
867 dev_dbg(pctrl->dev, "configured pin %u mode %u OE %sinverted\n",
868 pin, altfunc->mode, altfunc->invert_oe ? "" : "not ");
869 }
870
0bd50d71 871 raw_spin_unlock_irqrestore(&chv_lock, flags);
6e08d6bb
MW		 872
873 return 0;
874}
875
876static int chv_gpio_request_enable(struct pinctrl_dev *pctldev,
877 struct pinctrl_gpio_range *range,
878 unsigned offset)
879{
880 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
881 unsigned long flags;
882 void __iomem *reg;
883 u32 value;
884
0bd50d71 885 raw_spin_lock_irqsave(&chv_lock, flags);
6e08d6bb
MW		 886
887 if (chv_pad_locked(pctrl, offset)) {
888 value = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0));
889 if (!(value & CHV_PADCTRL0_GPIOEN)) {
890 /* Locked so cannot enable */
0bd50d71 891 raw_spin_unlock_irqrestore(&chv_lock, flags);
6e08d6bb
MW		 892 return -EBUSY;
893 }
894 } else {
895 int i;
896
897 /* Reset the interrupt mapping */
898 for (i = 0; i < ARRAY_SIZE(pctrl->intr_lines); i++) {
899 if (pctrl->intr_lines[i] == offset) {
900 pctrl->intr_lines[i] = 0;
901 break;
902 }
903 }
904
905 /* Disable interrupt generation */
906 reg = chv_padreg(pctrl, offset, CHV_PADCTRL1);
907 value = readl(reg);
908 value &= ~CHV_PADCTRL1_INTWAKECFG_MASK;
909 value &= ~CHV_PADCTRL1_INVRXTX_MASK;
910 chv_writel(value, reg);
911
6e08d6bb 912 reg = chv_padreg(pctrl, offset, CHV_PADCTRL0);
2479c730
MW		 913 value = readl(reg);
914
915 /*
916 * If the pin is in HiZ mode (both TX and RX buffers are
917 * disabled) we turn it to be input now.
918 */
919 if ((value & CHV_PADCTRL0_GPIOCFG_MASK) ==
920 (CHV_PADCTRL0_GPIOCFG_HIZ << CHV_PADCTRL0_GPIOCFG_SHIFT)) {
921 value &= ~CHV_PADCTRL0_GPIOCFG_MASK;
922 value |= CHV_PADCTRL0_GPIOCFG_GPI <<
923 CHV_PADCTRL0_GPIOCFG_SHIFT;
924 }
925
926 /* Switch to a GPIO mode */
927 value |= CHV_PADCTRL0_GPIOEN;
6e08d6bb
MW		 928 chv_writel(value, reg);
929 }
930
0bd50d71 931 raw_spin_unlock_irqrestore(&chv_lock, flags);
6e08d6bb
MW		 932
933 return 0;
934}
935
936static void chv_gpio_disable_free(struct pinctrl_dev *pctldev,
937 struct pinctrl_gpio_range *range,
938 unsigned offset)
939{
940 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
941 unsigned long flags;
942 void __iomem *reg;
943 u32 value;
944
0bd50d71 945 raw_spin_lock_irqsave(&chv_lock, flags);
6e08d6bb
MW		 946
947 reg = chv_padreg(pctrl, offset, CHV_PADCTRL0);
948 value = readl(reg) & ~CHV_PADCTRL0_GPIOEN;
949 chv_writel(value, reg);
950
0bd50d71 951 raw_spin_unlock_irqrestore(&chv_lock, flags);
6e08d6bb
MW		 952}
953
954static int chv_gpio_set_direction(struct pinctrl_dev *pctldev,
955 struct pinctrl_gpio_range *range,
956 unsigned offset, bool input)
957{
958 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
959 void __iomem *reg = chv_padreg(pctrl, offset, CHV_PADCTRL0);
960 unsigned long flags;
961 u32 ctrl0;
962
0bd50d71 963 raw_spin_lock_irqsave(&chv_lock, flags);
6e08d6bb
MW		 964
965 ctrl0 = readl(reg) & ~CHV_PADCTRL0_GPIOCFG_MASK;
966 if (input)
967 ctrl0 |= CHV_PADCTRL0_GPIOCFG_GPI << CHV_PADCTRL0_GPIOCFG_SHIFT;
968 else
969 ctrl0 |= CHV_PADCTRL0_GPIOCFG_GPO << CHV_PADCTRL0_GPIOCFG_SHIFT;
970 chv_writel(ctrl0, reg);
971
0bd50d71 972 raw_spin_unlock_irqrestore(&chv_lock, flags);
6e08d6bb
MW		 973
974 return 0;
975}
976
977static const struct pinmux_ops chv_pinmux_ops = {
978 .get_functions_count = chv_get_functions_count,
979 .get_function_name = chv_get_function_name,
980 .get_function_groups = chv_get_function_groups,
981 .set_mux = chv_pinmux_set_mux,
982 .gpio_request_enable = chv_gpio_request_enable,
983 .gpio_disable_free = chv_gpio_disable_free,
984 .gpio_set_direction = chv_gpio_set_direction,
985};
986
987static int chv_config_get(struct pinctrl_dev *pctldev, unsigned pin,
988 unsigned long *config)
989{
990 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
991 enum pin_config_param param = pinconf_to_config_param(*config);
992 unsigned long flags;
993 u32 ctrl0, ctrl1;
994 u16 arg = 0;
995 u32 term;
996
0bd50d71 997 raw_spin_lock_irqsave(&chv_lock, flags);
6e08d6bb
MW		 998 ctrl0 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
999 ctrl1 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL1));
0bd50d71 1000 raw_spin_unlock_irqrestore(&chv_lock, flags);
6e08d6bb
MW		 1001
1002 term = (ctrl0 & CHV_PADCTRL0_TERM_MASK) >> CHV_PADCTRL0_TERM_SHIFT;
1003
1004 switch (param) {
1005 case PIN_CONFIG_BIAS_DISABLE:
1006 if (term)
1007 return -EINVAL;
1008 break;
1009
1010 case PIN_CONFIG_BIAS_PULL_UP:
1011 if (!(ctrl0 & CHV_PADCTRL0_TERM_UP))
1012 return -EINVAL;
1013
1014 switch (term) {
1015 case CHV_PADCTRL0_TERM_20K:
1016 arg = 20000;
1017 break;
1018 case CHV_PADCTRL0_TERM_5K:
1019 arg = 5000;
1020 break;
1021 case CHV_PADCTRL0_TERM_1K:
1022 arg = 1000;
1023 break;
1024 }
1025
1026 break;
1027
1028 case PIN_CONFIG_BIAS_PULL_DOWN:
1029 if (!term || (ctrl0 & CHV_PADCTRL0_TERM_UP))
1030 return -EINVAL;
1031
1032 switch (term) {
1033 case CHV_PADCTRL0_TERM_20K:
1034 arg = 20000;
1035 break;
1036 case CHV_PADCTRL0_TERM_5K:
1037 arg = 5000;
1038 break;
1039 }
1040
1041 break;
1042
1043 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
1044 if (!(ctrl1 & CHV_PADCTRL1_ODEN))
1045 return -EINVAL;
1046 break;
1047
1048 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: {
1049 u32 cfg;
1050
1051 cfg = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK;
1052 cfg >>= CHV_PADCTRL0_GPIOCFG_SHIFT;
1053 if (cfg != CHV_PADCTRL0_GPIOCFG_HIZ)
1054 return -EINVAL;
1055
1056 break;
1057 }
1058
1059 default:
1060 return -ENOTSUPP;
1061 }
1062
1063 *config = pinconf_to_config_packed(param, arg);
1064 return 0;
1065}
1066
1067static int chv_config_set_pull(struct chv_pinctrl *pctrl, unsigned pin,
58957d2e 1068 enum pin_config_param param, u32 arg)
6e08d6bb
MW		 1069{
1070 void __iomem *reg = chv_padreg(pctrl, pin, CHV_PADCTRL0);
1071 unsigned long flags;
1072 u32 ctrl0, pull;
1073
0bd50d71 1074 raw_spin_lock_irqsave(&chv_lock, flags);
6e08d6bb
MW		 1075 ctrl0 = readl(reg);
1076
1077 switch (param) {
1078 case PIN_CONFIG_BIAS_DISABLE:
1079 ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP);
1080 break;
1081
1082 case PIN_CONFIG_BIAS_PULL_UP:
1083 ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP);
1084
1085 switch (arg) {
1086 case 1000:
1087 /* For 1k there is only pull up */
1088 pull = CHV_PADCTRL0_TERM_1K << CHV_PADCTRL0_TERM_SHIFT;
1089 break;
1090 case 5000:
1091 pull = CHV_PADCTRL0_TERM_5K << CHV_PADCTRL0_TERM_SHIFT;
1092 break;
1093 case 20000:
1094 pull = CHV_PADCTRL0_TERM_20K << CHV_PADCTRL0_TERM_SHIFT;
1095 break;
1096 default:
0bd50d71 1097 raw_spin_unlock_irqrestore(&chv_lock, flags);
6e08d6bb
MW		 1098 return -EINVAL;
1099 }
1100
1101 ctrl0 |= CHV_PADCTRL0_TERM_UP | pull;
1102 break;
1103
1104 case PIN_CONFIG_BIAS_PULL_DOWN:
1105 ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP);
1106
1107 switch (arg) {
1108 case 5000:
1109 pull = CHV_PADCTRL0_TERM_5K << CHV_PADCTRL0_TERM_SHIFT;
1110 break;
1111 case 20000:
1112 pull = CHV_PADCTRL0_TERM_20K << CHV_PADCTRL0_TERM_SHIFT;
1113 break;
1114 default:
0bd50d71 1115 raw_spin_unlock_irqrestore(&chv_lock, flags);
6e08d6bb
MW		 1116 return -EINVAL;
1117 }
1118
1119 ctrl0 |= pull;
1120 break;
1121
1122 default:
0bd50d71 1123 raw_spin_unlock_irqrestore(&chv_lock, flags);
6e08d6bb
MW		 1124 return -EINVAL;
1125 }
1126
1127 chv_writel(ctrl0, reg);
0bd50d71 1128 raw_spin_unlock_irqrestore(&chv_lock, flags);
6e08d6bb
MW		 1129
1130 return 0;
1131}
1132
ccdf81d0
DD		 1133static int chv_config_set_oden(struct chv_pinctrl *pctrl, unsigned int pin,
1134 bool enable)
1135{
1136 void __iomem *reg = chv_padreg(pctrl, pin, CHV_PADCTRL1);
1137 unsigned long flags;
1138 u32 ctrl1;
1139
1140 raw_spin_lock_irqsave(&chv_lock, flags);
1141 ctrl1 = readl(reg);
1142
1143 if (enable)
1144 ctrl1 |= CHV_PADCTRL1_ODEN;
1145 else
1146 ctrl1 &= ~CHV_PADCTRL1_ODEN;
1147
1148 chv_writel(ctrl1, reg);
1149 raw_spin_unlock_irqrestore(&chv_lock, flags);
1150
1151 return 0;
1152}
1153
6e08d6bb
MW		 1154static int chv_config_set(struct pinctrl_dev *pctldev, unsigned pin,
1155 unsigned long *configs, unsigned nconfigs)
1156{
1157 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
1158 enum pin_config_param param;
1159 int i, ret;
58957d2e 1160 u32 arg;
6e08d6bb
MW		 1161
1162 if (chv_pad_locked(pctrl, pin))
1163 return -EBUSY;
1164
1165 for (i = 0; i < nconfigs; i++) {
1166 param = pinconf_to_config_param(configs[i]);
1167 arg = pinconf_to_config_argument(configs[i]);
1168
1169 switch (param) {
1170 case PIN_CONFIG_BIAS_DISABLE:
1171 case PIN_CONFIG_BIAS_PULL_UP:
1172 case PIN_CONFIG_BIAS_PULL_DOWN:
1173 ret = chv_config_set_pull(pctrl, pin, param, arg);
1174 if (ret)
1175 return ret;
1176 break;
1177
ccdf81d0
DD		 1178 case PIN_CONFIG_DRIVE_PUSH_PULL:
1179 ret = chv_config_set_oden(pctrl, pin, false);
1180 if (ret)
1181 return ret;
1182 break;
1183
1184 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
1185 ret = chv_config_set_oden(pctrl, pin, true);
1186 if (ret)
1187 return ret;
1188 break;
1189
6e08d6bb
MW		 1190 default:
1191 return -ENOTSUPP;
1192 }
1193
1194 dev_dbg(pctrl->dev, "pin %d set config %d arg %u\n", pin,
1195 param, arg);
1196 }
1197
1198 return 0;
1199}
1200
77401d7f
DD		 1201static int chv_config_group_get(struct pinctrl_dev *pctldev,
1202 unsigned int group,
1203 unsigned long *config)
1204{
1205 const unsigned int *pins;
1206 unsigned int npins;
1207 int ret;
1208
1209 ret = chv_get_group_pins(pctldev, group, &pins, &npins);
1210 if (ret)
1211 return ret;
1212
1213 ret = chv_config_get(pctldev, pins[0], config);
1214 if (ret)
1215 return ret;
1216
1217 return 0;
1218}
1219
1220static int chv_config_group_set(struct pinctrl_dev *pctldev,
1221 unsigned int group, unsigned long *configs,
1222 unsigned int num_configs)
1223{
1224 const unsigned int *pins;
1225 unsigned int npins;
1226 int i, ret;
1227
1228 ret = chv_get_group_pins(pctldev, group, &pins, &npins);
1229 if (ret)
1230 return ret;
1231
1232 for (i = 0; i < npins; i++) {
1233 ret = chv_config_set(pctldev, pins[i], configs, num_configs);
1234 if (ret)
1235 return ret;
1236 }
1237
1238 return 0;
1239}
1240
6e08d6bb
MW		 1241static const struct pinconf_ops chv_pinconf_ops = {
1242 .is_generic = true,
1243 .pin_config_set = chv_config_set,
1244 .pin_config_get = chv_config_get,
77401d7f
DD		 1245 .pin_config_group_get = chv_config_group_get,
1246 .pin_config_group_set = chv_config_group_set,
6e08d6bb
MW		 1247};
1248
1249static struct pinctrl_desc chv_pinctrl_desc = {
1250 .pctlops = &chv_pinctrl_ops,
1251 .pmxops = &chv_pinmux_ops,
1252 .confops = &chv_pinconf_ops,
1253 .owner = THIS_MODULE,
1254};
1255
6e08d6bb
MW		 1256static unsigned chv_gpio_offset_to_pin(struct chv_pinctrl *pctrl,
1257 unsigned offset)
1258{
1259 return pctrl->community->pins[offset].number;
1260}
1261
1262static int chv_gpio_get(struct gpio_chip *chip, unsigned offset)
1263{
0587d3db 1264 struct chv_pinctrl *pctrl = gpiochip_get_data(chip);
6e08d6bb 1265 int pin = chv_gpio_offset_to_pin(pctrl, offset);
4585b000 1266 unsigned long flags;
6e08d6bb
MW		 1267 u32 ctrl0, cfg;
1268
0bd50d71 1269 raw_spin_lock_irqsave(&chv_lock, flags);
6e08d6bb 1270 ctrl0 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
0bd50d71 1271 raw_spin_unlock_irqrestore(&chv_lock, flags);
6e08d6bb
MW		 1272
1273 cfg = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK;
1274 cfg >>= CHV_PADCTRL0_GPIOCFG_SHIFT;
1275
1276 if (cfg == CHV_PADCTRL0_GPIOCFG_GPO)
1277 return !!(ctrl0 & CHV_PADCTRL0_GPIOTXSTATE);
1278 return !!(ctrl0 & CHV_PADCTRL0_GPIORXSTATE);
1279}
1280
1281static void chv_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1282{
0587d3db 1283 struct chv_pinctrl *pctrl = gpiochip_get_data(chip);
6e08d6bb
MW		 1284 unsigned pin = chv_gpio_offset_to_pin(pctrl, offset);
1285 unsigned long flags;
1286 void __iomem *reg;
1287 u32 ctrl0;
1288
0bd50d71 1289 raw_spin_lock_irqsave(&chv_lock, flags);
6e08d6bb
MW		 1290
1291 reg = chv_padreg(pctrl, pin, CHV_PADCTRL0);
1292 ctrl0 = readl(reg);
1293
1294 if (value)
1295 ctrl0 |= CHV_PADCTRL0_GPIOTXSTATE;
1296 else
1297 ctrl0 &= ~CHV_PADCTRL0_GPIOTXSTATE;
1298
1299 chv_writel(ctrl0, reg);
1300
0bd50d71 1301 raw_spin_unlock_irqrestore(&chv_lock, flags);
6e08d6bb
MW		 1302}
1303
1304static int chv_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
1305{
0587d3db 1306 struct chv_pinctrl *pctrl = gpiochip_get_data(chip);
6e08d6bb
MW		 1307 unsigned pin = chv_gpio_offset_to_pin(pctrl, offset);
1308 u32 ctrl0, direction;
4585b000 1309 unsigned long flags;
6e08d6bb 1310
0bd50d71 1311 raw_spin_lock_irqsave(&chv_lock, flags);
6e08d6bb 1312 ctrl0 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
0bd50d71 1313 raw_spin_unlock_irqrestore(&chv_lock, flags);
6e08d6bb
MW		 1314
1315 direction = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK;
1316 direction >>= CHV_PADCTRL0_GPIOCFG_SHIFT;
1317
1318 return direction != CHV_PADCTRL0_GPIOCFG_GPO;
1319}
1320
1321static int chv_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
1322{
1323 return pinctrl_gpio_direction_input(chip->base + offset);
1324}
1325
1326static int chv_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
1327 int value)
1328{
549e783f 1329 chv_gpio_set(chip, offset, value);
6e08d6bb
MW		 1330 return pinctrl_gpio_direction_output(chip->base + offset);
1331}
1332
1333static const struct gpio_chip chv_gpio_chip = {
1334 .owner = THIS_MODULE,
98c85d58
JG		 1335 .request = gpiochip_generic_request,
1336 .free = gpiochip_generic_free,
6e08d6bb
MW		 1337 .get_direction = chv_gpio_get_direction,
1338 .direction_input = chv_gpio_direction_input,
1339 .direction_output = chv_gpio_direction_output,
1340 .get = chv_gpio_get,
1341 .set = chv_gpio_set,
1342};
1343
1344static void chv_gpio_irq_ack(struct irq_data *d)
1345{
1346 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0587d3db 1347 struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
6e08d6bb
MW		 1348 int pin = chv_gpio_offset_to_pin(pctrl, irqd_to_hwirq(d));
1349 u32 intr_line;
1350
0bd50d71 1351 raw_spin_lock(&chv_lock);
6e08d6bb
MW		 1352
1353 intr_line = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
1354 intr_line &= CHV_PADCTRL0_INTSEL_MASK;
1355 intr_line >>= CHV_PADCTRL0_INTSEL_SHIFT;
1356 chv_writel(BIT(intr_line), pctrl->regs + CHV_INTSTAT);
1357
0bd50d71 1358 raw_spin_unlock(&chv_lock);
6e08d6bb
MW		 1359}
1360
1361static void chv_gpio_irq_mask_unmask(struct irq_data *d, bool mask)
1362{
1363 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0587d3db 1364 struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
6e08d6bb
MW		 1365 int pin = chv_gpio_offset_to_pin(pctrl, irqd_to_hwirq(d));
1366 u32 value, intr_line;
1367 unsigned long flags;
1368
0bd50d71 1369 raw_spin_lock_irqsave(&chv_lock, flags);
6e08d6bb
MW		 1370
1371 intr_line = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
1372 intr_line &= CHV_PADCTRL0_INTSEL_MASK;
1373 intr_line >>= CHV_PADCTRL0_INTSEL_SHIFT;
1374
1375 value = readl(pctrl->regs + CHV_INTMASK);
1376 if (mask)
1377 value &= ~BIT(intr_line);
1378 else
1379 value |= BIT(intr_line);
1380 chv_writel(value, pctrl->regs + CHV_INTMASK);
1381
0bd50d71 1382 raw_spin_unlock_irqrestore(&chv_lock, flags);
6e08d6bb
MW		 1383}
1384
1385static void chv_gpio_irq_mask(struct irq_data *d)
1386{
1387 chv_gpio_irq_mask_unmask(d, true);
1388}
1389
1390static void chv_gpio_irq_unmask(struct irq_data *d)
1391{
1392 chv_gpio_irq_mask_unmask(d, false);
1393}
1394
e6c906de
MW		 1395static unsigned chv_gpio_irq_startup(struct irq_data *d)
1396{
1397 /*
1398 * Check if the interrupt has been requested with 0 as triggering
1399 * type. In that case it is assumed that the current values
1400 * programmed to the hardware are used (e.g BIOS configured
1401 * defaults).
1402 *
1403 * In that case ->irq_set_type() will never be called so we need to
1404 * read back the values from hardware now, set correct flow handler
1405 * and update mappings before the interrupt is being used.
1406 */
1407 if (irqd_get_trigger_type(d) == IRQ_TYPE_NONE) {
1408 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0587d3db 1409 struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
e6c906de
MW		 1410 unsigned offset = irqd_to_hwirq(d);
1411 int pin = chv_gpio_offset_to_pin(pctrl, offset);
1412 irq_flow_handler_t handler;
1413 unsigned long flags;
1414 u32 intsel, value;
1415
0bd50d71 1416 raw_spin_lock_irqsave(&chv_lock, flags);
e6c906de
MW		 1417 intsel = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
1418 intsel &= CHV_PADCTRL0_INTSEL_MASK;
1419 intsel >>= CHV_PADCTRL0_INTSEL_SHIFT;
1420
1421 value = readl(chv_padreg(pctrl, pin, CHV_PADCTRL1));
1422 if (value & CHV_PADCTRL1_INTWAKECFG_LEVEL)
1423 handler = handle_level_irq;
1424 else
1425 handler = handle_edge_irq;
1426
e6c906de 1427 if (!pctrl->intr_lines[intsel]) {
a4e3f783 1428 irq_set_handler_locked(d, handler);
e6c906de
MW		 1429 pctrl->intr_lines[intsel] = offset;
1430 }
0bd50d71 1431 raw_spin_unlock_irqrestore(&chv_lock, flags);
e6c906de
MW		 1432 }
1433
1434 chv_gpio_irq_unmask(d);
1435 return 0;
1436}
1437
6e08d6bb
MW		 1438static int chv_gpio_irq_type(struct irq_data *d, unsigned type)
1439{
1440 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0587d3db 1441 struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
6e08d6bb
MW		 1442 unsigned offset = irqd_to_hwirq(d);
1443 int pin = chv_gpio_offset_to_pin(pctrl, offset);
1444 unsigned long flags;
1445 u32 value;
1446
0bd50d71 1447 raw_spin_lock_irqsave(&chv_lock, flags);
6e08d6bb
MW		 1448
1449 /*
1450 * Pins which can be used as shared interrupt are configured in
1451 * BIOS. Driver trusts BIOS configurations and assigns different
1452 * handler according to the irq type.
1453 *
1454 * Driver needs to save the mapping between each pin and
1455 * its interrupt line.
1456 * 1. If the pin cfg is locked in BIOS:
1457 * Trust BIOS has programmed IntWakeCfg bits correctly,
1458 * driver just needs to save the mapping.
1459 * 2. If the pin cfg is not locked in BIOS:
1460 * Driver programs the IntWakeCfg bits and save the mapping.
1461 */
1462 if (!chv_pad_locked(pctrl, pin)) {
1463 void __iomem *reg = chv_padreg(pctrl, pin, CHV_PADCTRL1);
1464
1465 value = readl(reg);
1466 value &= ~CHV_PADCTRL1_INTWAKECFG_MASK;
1467 value &= ~CHV_PADCTRL1_INVRXTX_MASK;
1468
1469 if (type & IRQ_TYPE_EDGE_BOTH) {
1470 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
1471 value |= CHV_PADCTRL1_INTWAKECFG_BOTH;
1472 else if (type & IRQ_TYPE_EDGE_RISING)
1473 value |= CHV_PADCTRL1_INTWAKECFG_RISING;
1474 else if (type & IRQ_TYPE_EDGE_FALLING)
1475 value |= CHV_PADCTRL1_INTWAKECFG_FALLING;
1476 } else if (type & IRQ_TYPE_LEVEL_MASK) {
1477 value |= CHV_PADCTRL1_INTWAKECFG_LEVEL;
1478 if (type & IRQ_TYPE_LEVEL_LOW)
1479 value |= CHV_PADCTRL1_INVRXTX_RXDATA;
1480 }
1481
1482 chv_writel(value, reg);
1483 }
1484
1485 value = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
1486 value &= CHV_PADCTRL0_INTSEL_MASK;
1487 value >>= CHV_PADCTRL0_INTSEL_SHIFT;
1488
1489 pctrl->intr_lines[value] = offset;
1490
1491 if (type & IRQ_TYPE_EDGE_BOTH)
a4e3f783 1492 irq_set_handler_locked(d, handle_edge_irq);
6e08d6bb 1493 else if (type & IRQ_TYPE_LEVEL_MASK)
a4e3f783 1494 irq_set_handler_locked(d, handle_level_irq);
6e08d6bb 1495
0bd50d71 1496 raw_spin_unlock_irqrestore(&chv_lock, flags);
6e08d6bb
MW		 1497
1498 return 0;
1499}
1500
1501static struct irq_chip chv_gpio_irqchip = {
1502 .name = "chv-gpio",
e6c906de 1503 .irq_startup = chv_gpio_irq_startup,
6e08d6bb
MW		 1504 .irq_ack = chv_gpio_irq_ack,
1505 .irq_mask = chv_gpio_irq_mask,
1506 .irq_unmask = chv_gpio_irq_unmask,
1507 .irq_set_type = chv_gpio_irq_type,
1508 .flags = IRQCHIP_SKIP_SET_WAKE,
1509};
1510
bd0b9ac4 1511static void chv_gpio_irq_handler(struct irq_desc *desc)
6e08d6bb
MW		 1512{
1513 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
0587d3db 1514 struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
5663bb27 1515 struct irq_chip *chip = irq_desc_get_chip(desc);
6e08d6bb
MW		 1516 unsigned long pending;
1517 u32 intr_line;
1518
1519 chained_irq_enter(chip, desc);
1520
1521 pending = readl(pctrl->regs + CHV_INTSTAT);
47c950d1 1522 for_each_set_bit(intr_line, &pending, pctrl->community->nirqs) {
6e08d6bb
MW		 1523 unsigned irq, offset;
1524
1525 offset = pctrl->intr_lines[intr_line];
1526 irq = irq_find_mapping(gc->irqdomain, offset);
1527 generic_handle_irq(irq);
1528 }
1529
1530 chained_irq_exit(chip, desc);
1531}
1532
70365027
MW		 1533/*
1534 * Certain machines seem to hardcode Linux IRQ numbers in their ACPI
1535 * tables. Since we leave GPIOs that are not capable of generating
1536 * interrupts out of the irqdomain the numbering will be different and
1537 * cause devices using the hardcoded IRQ numbers fail. In order not to
1538 * break such machines we will only mask pins from irqdomain if the machine
1539 * is not listed below.
1540 */
1541static const struct dmi_system_id chv_no_valid_mask[] = {
2a8209fa 1542 /* See https://bugzilla.kernel.org/show_bug.cgi?id=194945 */
70365027 1543 {
2a8209fa 1544 .ident = "Intel_Strago based Chromebooks (All models)",
70365027
MW		 1545 .matches = {
1546 DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"),
2a8209fa
MW		 1547 DMI_MATCH(DMI_PRODUCT_FAMILY, "Intel_Strago"),
1548 },
1549 },
2d80bd3f
AS		 1550 {
1551 .ident = "HP Chromebook 11 G5 (Setzer)",
1552 .matches = {
1553 DMI_MATCH(DMI_SYS_VENDOR, "HP"),
1554 DMI_MATCH(DMI_PRODUCT_NAME, "Setzer"),
1555 },
1556 },
2a8209fa
MW		 1557 {
1558 .ident = "Acer Chromebook R11 (Cyan)",
1559 .matches = {
1560 DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"),
1561 DMI_MATCH(DMI_PRODUCT_NAME, "Cyan"),
1562 },
1563 },
1564 {
1565 .ident = "Samsung Chromebook 3 (Celes)",
1566 .matches = {
1567 DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"),
1568 DMI_MATCH(DMI_PRODUCT_NAME, "Celes"),
70365027 1569 },
a9de080b
WY		 1570 },
1571 {}
70365027
MW		 1572};
1573
6e08d6bb
MW		 1574static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq)
1575{
1576 const struct chv_gpio_pinrange *range;
1577 struct gpio_chip *chip = &pctrl->chip;
70365027 1578 bool need_valid_mask = !dmi_check_system(chv_no_valid_mask);
6e08d6bb
MW		 1579 int ret, i, offset;
1580
1581 *chip = chv_gpio_chip;
1582
1583 chip->ngpio = pctrl->community->ngpios;
1584 chip->label = dev_name(pctrl->dev);
58383c78 1585 chip->parent = pctrl->dev;
6e08d6bb 1586 chip->base = -1;
70365027 1587 chip->irq_need_valid_mask = need_valid_mask;
6e08d6bb 1588
d1073418 1589 ret = devm_gpiochip_add_data(pctrl->dev, chip, pctrl);
6e08d6bb
MW		 1590 if (ret) {
1591 dev_err(pctrl->dev, "Failed to register gpiochip\n");
1592 return ret;
1593 }
1594
1595 for (i = 0, offset = 0; i < pctrl->community->ngpio_ranges; i++) {
1596 range = &pctrl->community->gpio_ranges[i];
1597 ret = gpiochip_add_pin_range(chip, dev_name(pctrl->dev), offset,
1598 range->base, range->npins);
1599 if (ret) {
1600 dev_err(pctrl->dev, "failed to add GPIO pin range\n");
d1073418 1601 return ret;
6e08d6bb
MW		 1602 }
1603
1604 offset += range->npins;
1605 }
1606
47c950d1
MW		 1607 /* Do not add GPIOs that can only generate GPEs to the IRQ domain */
1608 for (i = 0; i < pctrl->community->npins; i++) {
1609 const struct pinctrl_pin_desc *desc;
1610 u32 intsel;
1611
1612 desc = &pctrl->community->pins[i];
1613
1614 intsel = readl(chv_padreg(pctrl, desc->number, CHV_PADCTRL0));
1615 intsel &= CHV_PADCTRL0_INTSEL_MASK;
1616 intsel >>= CHV_PADCTRL0_INTSEL_SHIFT;
1617
70365027 1618 if (need_valid_mask && intsel >= pctrl->community->nirqs)
47c950d1
MW		 1619 clear_bit(i, chip->irq_valid_mask);
1620 }
1621
bcb48cca 1622 /* Clear all interrupts */
6e08d6bb
MW		 1623 chv_writel(0xffff, pctrl->regs + CHV_INTSTAT);
1624
1625 ret = gpiochip_irqchip_add(chip, &chv_gpio_irqchip, 0,
bcb48cca 1626 handle_bad_irq, IRQ_TYPE_NONE);
6e08d6bb
MW		 1627 if (ret) {
1628 dev_err(pctrl->dev, "failed to add IRQ chip\n");
d1073418 1629 return ret;
6e08d6bb
MW		 1630 }
1631
1632 gpiochip_set_chained_irqchip(chip, &chv_gpio_irqchip, irq,
1633 chv_gpio_irq_handler);
1634 return 0;
6e08d6bb
MW		 1635}
1636
a0b02859
HG		 1637static acpi_status chv_pinctrl_mmio_access_handler(u32 function,
1638 acpi_physical_address address, u32 bits, u64 *value,
1639 void *handler_context, void *region_context)
1640{
1641 struct chv_pinctrl *pctrl = region_context;
1642 unsigned long flags;
1643 acpi_status ret = AE_OK;
1644
1645 raw_spin_lock_irqsave(&chv_lock, flags);
1646
1647 if (function == ACPI_WRITE)
1648 chv_writel((u32)(*value), pctrl->regs + (u32)address);
1649 else if (function == ACPI_READ)
1650 *value = readl(pctrl->regs + (u32)address);
1651 else
1652 ret = AE_BAD_PARAMETER;
1653
1654 raw_spin_unlock_irqrestore(&chv_lock, flags);
1655
1656 return ret;
1657}
1658
6e08d6bb
MW		 1659static int chv_pinctrl_probe(struct platform_device *pdev)
1660{
1661 struct chv_pinctrl *pctrl;
1662 struct acpi_device *adev;
1663 struct resource *res;
a0b02859 1664 acpi_status status;
6e08d6bb
MW		 1665 int ret, irq, i;
1666
1667 adev = ACPI_COMPANION(&pdev->dev);
1668 if (!adev)
1669 return -ENODEV;
1670
1671 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
1672 if (!pctrl)
1673 return -ENOMEM;
1674
1675 for (i = 0; i < ARRAY_SIZE(chv_communities); i++)
1676 if (!strcmp(adev->pnp.unique_id, chv_communities[i]->uid)) {
1677 pctrl->community = chv_communities[i];
1678 break;
1679 }
1680 if (i == ARRAY_SIZE(chv_communities))
1681 return -ENODEV;
1682
6e08d6bb
MW		 1683 pctrl->dev = &pdev->dev;
1684
9eb457b5
MW		 1685#ifdef CONFIG_PM_SLEEP
1686 pctrl->saved_pin_context = devm_kcalloc(pctrl->dev,
1687 pctrl->community->npins, sizeof(*pctrl->saved_pin_context),
1688 GFP_KERNEL);
1689 if (!pctrl->saved_pin_context)
1690 return -ENOMEM;
1691#endif
1692
6e08d6bb
MW		 1693 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1694 pctrl->regs = devm_ioremap_resource(&pdev->dev, res);
1695 if (IS_ERR(pctrl->regs))
1696 return PTR_ERR(pctrl->regs);
1697
1698 irq = platform_get_irq(pdev, 0);
1699 if (irq < 0) {
1700 dev_err(&pdev->dev, "failed to get interrupt number\n");
1701 return irq;
1702 }
1703
1704 pctrl->pctldesc = chv_pinctrl_desc;
1705 pctrl->pctldesc.name = dev_name(&pdev->dev);
1706 pctrl->pctldesc.pins = pctrl->community->pins;
1707 pctrl->pctldesc.npins = pctrl->community->npins;
1708
7cf061fa
LD		 1709 pctrl->pctldev = devm_pinctrl_register(&pdev->dev, &pctrl->pctldesc,
1710 pctrl);
323de9ef 1711 if (IS_ERR(pctrl->pctldev)) {
6e08d6bb 1712 dev_err(&pdev->dev, "failed to register pinctrl driver\n");
323de9ef 1713 return PTR_ERR(pctrl->pctldev);
6e08d6bb
MW		 1714 }
1715
1716 ret = chv_gpio_probe(pctrl, irq);
7cf061fa 1717 if (ret)
6e08d6bb 1718 return ret;
6e08d6bb 1719
a0b02859
HG		 1720 status = acpi_install_address_space_handler(adev->handle,
1721 pctrl->community->acpi_space_id,
1722 chv_pinctrl_mmio_access_handler,
1723 NULL, pctrl);
1724 if (ACPI_FAILURE(status))
1725 dev_err(&pdev->dev, "failed to install ACPI addr space handler\n");
1726
6e08d6bb
MW		 1727 platform_set_drvdata(pdev, pctrl);
1728
1729 return 0;
1730}
1731
a0b02859
HG		 1732static int chv_pinctrl_remove(struct platform_device *pdev)
1733{
1734 struct chv_pinctrl *pctrl = platform_get_drvdata(pdev);
1735
1736 acpi_remove_address_space_handler(ACPI_COMPANION(&pdev->dev),
1737 pctrl->community->acpi_space_id,
1738 chv_pinctrl_mmio_access_handler);
1739
1740 return 0;
1741}
1742
9eb457b5 1743#ifdef CONFIG_PM_SLEEP
d2cdf5dc 1744static int chv_pinctrl_suspend_noirq(struct device *dev)
9eb457b5
MW		 1745{
1746 struct platform_device *pdev = to_platform_device(dev);
1747 struct chv_pinctrl *pctrl = platform_get_drvdata(pdev);
56211121 1748 unsigned long flags;
9eb457b5
MW		 1749 int i;
1750
56211121
MW		 1751 raw_spin_lock_irqsave(&chv_lock, flags);
1752
9eb457b5
MW		 1753 pctrl->saved_intmask = readl(pctrl->regs + CHV_INTMASK);
1754
1755 for (i = 0; i < pctrl->community->npins; i++) {
1756 const struct pinctrl_pin_desc *desc;
1757 struct chv_pin_context *ctx;
1758 void __iomem *reg;
1759
1760 desc = &pctrl->community->pins[i];
1761 if (chv_pad_locked(pctrl, desc->number))
1762 continue;
1763
1764 ctx = &pctrl->saved_pin_context[i];
1765
1766 reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL0);
1767 ctx->padctrl0 = readl(reg) & ~CHV_PADCTRL0_GPIORXSTATE;
1768
1769 reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL1);
1770 ctx->padctrl1 = readl(reg);
1771 }
1772
56211121
MW		 1773 raw_spin_unlock_irqrestore(&chv_lock, flags);
1774
9eb457b5
MW		 1775 return 0;
1776}
1777
d2cdf5dc 1778static int chv_pinctrl_resume_noirq(struct device *dev)
9eb457b5
MW		 1779{
1780 struct platform_device *pdev = to_platform_device(dev);
1781 struct chv_pinctrl *pctrl = platform_get_drvdata(pdev);
56211121 1782 unsigned long flags;
9eb457b5
MW		 1783 int i;
1784
56211121
MW		 1785 raw_spin_lock_irqsave(&chv_lock, flags);
1786
9eb457b5
MW		 1787 /*
1788 * Mask all interrupts before restoring per-pin configuration
1789 * registers because we don't know in which state BIOS left them
1790 * upon exiting suspend.
1791 */
1792 chv_writel(0, pctrl->regs + CHV_INTMASK);
1793
1794 for (i = 0; i < pctrl->community->npins; i++) {
1795 const struct pinctrl_pin_desc *desc;
1796 const struct chv_pin_context *ctx;
1797 void __iomem *reg;
1798 u32 val;
1799
1800 desc = &pctrl->community->pins[i];
1801 if (chv_pad_locked(pctrl, desc->number))
1802 continue;
1803
1804 ctx = &pctrl->saved_pin_context[i];
1805
1806 /* Only restore if our saved state differs from the current */
1807 reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL0);
1808 val = readl(reg) & ~CHV_PADCTRL0_GPIORXSTATE;
1809 if (ctx->padctrl0 != val) {
1810 chv_writel(ctx->padctrl0, reg);
1811 dev_dbg(pctrl->dev, "restored pin %2u ctrl0 0x%08x\n",
1812 desc->number, readl(reg));
1813 }
1814
1815 reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL1);
1816 val = readl(reg);
1817 if (ctx->padctrl1 != val) {
1818 chv_writel(ctx->padctrl1, reg);
1819 dev_dbg(pctrl->dev, "restored pin %2u ctrl1 0x%08x\n",
1820 desc->number, readl(reg));
1821 }
1822 }
1823
1824 /*
1825 * Now that all pins are restored to known state, we can restore
1826 * the interrupt mask register as well.
1827 */
1828 chv_writel(0xffff, pctrl->regs + CHV_INTSTAT);
1829 chv_writel(pctrl->saved_intmask, pctrl->regs + CHV_INTMASK);
1830
56211121
MW		 1831 raw_spin_unlock_irqrestore(&chv_lock, flags);
1832
9eb457b5
MW		 1833 return 0;
1834}
1835#endif
1836
1837static const struct dev_pm_ops chv_pinctrl_pm_ops = {
d2cdf5dc
MW		 1838 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(chv_pinctrl_suspend_noirq,
1839 chv_pinctrl_resume_noirq)
9eb457b5
MW		 1840};
1841
6e08d6bb
MW		 1842static const struct acpi_device_id chv_pinctrl_acpi_match[] = {
1843 { "INT33FF" },
1844 { }
1845};
1846MODULE_DEVICE_TABLE(acpi, chv_pinctrl_acpi_match);
1847
1848static struct platform_driver chv_pinctrl_driver = {
1849 .probe = chv_pinctrl_probe,
a0b02859 1850 .remove = chv_pinctrl_remove,
6e08d6bb
MW		 1851 .driver = {
1852 .name = "cherryview-pinctrl",
9eb457b5 1853 .pm = &chv_pinctrl_pm_ops,
6e08d6bb
MW		 1854 .acpi_match_table = chv_pinctrl_acpi_match,
1855 },
1856};
1857
1858static int __init chv_pinctrl_init(void)
1859{
1860 return platform_driver_register(&chv_pinctrl_driver);
1861}
1862subsys_initcall(chv_pinctrl_init);
1863
1864static void __exit chv_pinctrl_exit(void)
1865{
1866 platform_driver_unregister(&chv_pinctrl_driver);
1867}
1868module_exit(chv_pinctrl_exit);
1869
1870MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
1871MODULE_DESCRIPTION("Intel Cherryview/Braswell pinctrl driver");
1872MODULE_LICENSE("GPL v2");
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