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7981c001 MW |
1 | /* |
2 | * Intel pinctrl/GPIO core driver. | |
3 | * | |
4 | * Copyright (C) 2015, Intel Corporation | |
5 | * Authors: Mathias Nyman <mathias.nyman@linux.intel.com> | |
6 | * Mika Westerberg <mika.westerberg@linux.intel.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #include <linux/module.h> | |
193b40c8 | 14 | #include <linux/interrupt.h> |
7981c001 | 15 | #include <linux/gpio/driver.h> |
e57725ea | 16 | #include <linux/log2.h> |
7981c001 | 17 | #include <linux/platform_device.h> |
7981c001 MW |
18 | #include <linux/pinctrl/pinctrl.h> |
19 | #include <linux/pinctrl/pinmux.h> | |
20 | #include <linux/pinctrl/pinconf.h> | |
21 | #include <linux/pinctrl/pinconf-generic.h> | |
22 | ||
c538b943 | 23 | #include "../core.h" |
7981c001 MW |
24 | #include "pinctrl-intel.h" |
25 | ||
7981c001 | 26 | /* Offset from regs */ |
e57725ea MW |
27 | #define REVID 0x000 |
28 | #define REVID_SHIFT 16 | |
29 | #define REVID_MASK GENMASK(31, 16) | |
30 | ||
7981c001 MW |
31 | #define PADBAR 0x00c |
32 | #define GPI_IS 0x100 | |
33 | #define GPI_GPE_STS 0x140 | |
34 | #define GPI_GPE_EN 0x160 | |
35 | ||
36 | #define PADOWN_BITS 4 | |
37 | #define PADOWN_SHIFT(p) ((p) % 8 * PADOWN_BITS) | |
38 | #define PADOWN_MASK(p) (0xf << PADOWN_SHIFT(p)) | |
99a735b3 | 39 | #define PADOWN_GPP(p) ((p) / 8) |
7981c001 MW |
40 | |
41 | /* Offset from pad_regs */ | |
42 | #define PADCFG0 0x000 | |
43 | #define PADCFG0_RXEVCFG_SHIFT 25 | |
44 | #define PADCFG0_RXEVCFG_MASK (3 << PADCFG0_RXEVCFG_SHIFT) | |
45 | #define PADCFG0_RXEVCFG_LEVEL 0 | |
46 | #define PADCFG0_RXEVCFG_EDGE 1 | |
47 | #define PADCFG0_RXEVCFG_DISABLED 2 | |
48 | #define PADCFG0_RXEVCFG_EDGE_BOTH 3 | |
e57725ea | 49 | #define PADCFG0_PREGFRXSEL BIT(24) |
7981c001 MW |
50 | #define PADCFG0_RXINV BIT(23) |
51 | #define PADCFG0_GPIROUTIOXAPIC BIT(20) | |
52 | #define PADCFG0_GPIROUTSCI BIT(19) | |
53 | #define PADCFG0_GPIROUTSMI BIT(18) | |
54 | #define PADCFG0_GPIROUTNMI BIT(17) | |
55 | #define PADCFG0_PMODE_SHIFT 10 | |
56 | #define PADCFG0_PMODE_MASK (0xf << PADCFG0_PMODE_SHIFT) | |
57 | #define PADCFG0_GPIORXDIS BIT(9) | |
58 | #define PADCFG0_GPIOTXDIS BIT(8) | |
59 | #define PADCFG0_GPIORXSTATE BIT(1) | |
60 | #define PADCFG0_GPIOTXSTATE BIT(0) | |
61 | ||
62 | #define PADCFG1 0x004 | |
63 | #define PADCFG1_TERM_UP BIT(13) | |
64 | #define PADCFG1_TERM_SHIFT 10 | |
65 | #define PADCFG1_TERM_MASK (7 << PADCFG1_TERM_SHIFT) | |
66 | #define PADCFG1_TERM_20K 4 | |
67 | #define PADCFG1_TERM_2K 3 | |
68 | #define PADCFG1_TERM_5K 2 | |
69 | #define PADCFG1_TERM_1K 1 | |
70 | ||
e57725ea MW |
71 | #define PADCFG2 0x008 |
72 | #define PADCFG2_DEBEN BIT(0) | |
73 | #define PADCFG2_DEBOUNCE_SHIFT 1 | |
74 | #define PADCFG2_DEBOUNCE_MASK GENMASK(4, 1) | |
75 | ||
76 | #define DEBOUNCE_PERIOD 31250 /* ns */ | |
77 | ||
7981c001 MW |
78 | struct intel_pad_context { |
79 | u32 padcfg0; | |
80 | u32 padcfg1; | |
e57725ea | 81 | u32 padcfg2; |
7981c001 MW |
82 | }; |
83 | ||
84 | struct intel_community_context { | |
85 | u32 *intmask; | |
86 | }; | |
87 | ||
88 | struct intel_pinctrl_context { | |
89 | struct intel_pad_context *pads; | |
90 | struct intel_community_context *communities; | |
91 | }; | |
92 | ||
93 | /** | |
94 | * struct intel_pinctrl - Intel pinctrl private structure | |
95 | * @dev: Pointer to the device structure | |
96 | * @lock: Lock to serialize register access | |
97 | * @pctldesc: Pin controller description | |
98 | * @pctldev: Pointer to the pin controller device | |
99 | * @chip: GPIO chip in this pin controller | |
100 | * @soc: SoC/PCH specific pin configuration data | |
101 | * @communities: All communities in this pin controller | |
102 | * @ncommunities: Number of communities in this pin controller | |
103 | * @context: Configuration saved over system sleep | |
01dabe91 | 104 | * @irq: pinctrl/GPIO chip irq number |
7981c001 MW |
105 | */ |
106 | struct intel_pinctrl { | |
107 | struct device *dev; | |
27d9098c | 108 | raw_spinlock_t lock; |
7981c001 MW |
109 | struct pinctrl_desc pctldesc; |
110 | struct pinctrl_dev *pctldev; | |
111 | struct gpio_chip chip; | |
112 | const struct intel_pinctrl_soc_data *soc; | |
113 | struct intel_community *communities; | |
114 | size_t ncommunities; | |
115 | struct intel_pinctrl_context context; | |
01dabe91 | 116 | int irq; |
7981c001 MW |
117 | }; |
118 | ||
7981c001 | 119 | #define pin_to_padno(c, p) ((p) - (c)->pin_base) |
919eb475 | 120 | #define padgroup_offset(g, p) ((p) - (g)->base) |
7981c001 MW |
121 | |
122 | static struct intel_community *intel_get_community(struct intel_pinctrl *pctrl, | |
123 | unsigned pin) | |
124 | { | |
125 | struct intel_community *community; | |
126 | int i; | |
127 | ||
128 | for (i = 0; i < pctrl->ncommunities; i++) { | |
129 | community = &pctrl->communities[i]; | |
130 | if (pin >= community->pin_base && | |
131 | pin < community->pin_base + community->npins) | |
132 | return community; | |
133 | } | |
134 | ||
135 | dev_warn(pctrl->dev, "failed to find community for pin %u\n", pin); | |
136 | return NULL; | |
137 | } | |
138 | ||
919eb475 MW |
139 | static const struct intel_padgroup * |
140 | intel_community_get_padgroup(const struct intel_community *community, | |
141 | unsigned pin) | |
142 | { | |
143 | int i; | |
144 | ||
145 | for (i = 0; i < community->ngpps; i++) { | |
146 | const struct intel_padgroup *padgrp = &community->gpps[i]; | |
147 | ||
148 | if (pin >= padgrp->base && pin < padgrp->base + padgrp->size) | |
149 | return padgrp; | |
150 | } | |
151 | ||
152 | return NULL; | |
153 | } | |
154 | ||
7981c001 MW |
155 | static void __iomem *intel_get_padcfg(struct intel_pinctrl *pctrl, unsigned pin, |
156 | unsigned reg) | |
157 | { | |
158 | const struct intel_community *community; | |
159 | unsigned padno; | |
e57725ea | 160 | size_t nregs; |
7981c001 MW |
161 | |
162 | community = intel_get_community(pctrl, pin); | |
163 | if (!community) | |
164 | return NULL; | |
165 | ||
166 | padno = pin_to_padno(community, pin); | |
e57725ea MW |
167 | nregs = (community->features & PINCTRL_FEATURE_DEBOUNCE) ? 4 : 2; |
168 | ||
169 | if (reg == PADCFG2 && !(community->features & PINCTRL_FEATURE_DEBOUNCE)) | |
170 | return NULL; | |
171 | ||
172 | return community->pad_regs + reg + padno * nregs * 4; | |
7981c001 MW |
173 | } |
174 | ||
175 | static bool intel_pad_owned_by_host(struct intel_pinctrl *pctrl, unsigned pin) | |
176 | { | |
177 | const struct intel_community *community; | |
919eb475 MW |
178 | const struct intel_padgroup *padgrp; |
179 | unsigned gpp, offset, gpp_offset; | |
7981c001 MW |
180 | void __iomem *padown; |
181 | ||
182 | community = intel_get_community(pctrl, pin); | |
183 | if (!community) | |
184 | return false; | |
185 | if (!community->padown_offset) | |
186 | return true; | |
187 | ||
919eb475 MW |
188 | padgrp = intel_community_get_padgroup(community, pin); |
189 | if (!padgrp) | |
190 | return false; | |
191 | ||
192 | gpp_offset = padgroup_offset(padgrp, pin); | |
193 | gpp = PADOWN_GPP(gpp_offset); | |
194 | offset = community->padown_offset + padgrp->padown_num * 4 + gpp * 4; | |
7981c001 MW |
195 | padown = community->regs + offset; |
196 | ||
919eb475 | 197 | return !(readl(padown) & PADOWN_MASK(gpp_offset)); |
7981c001 MW |
198 | } |
199 | ||
4341e8a5 | 200 | static bool intel_pad_acpi_mode(struct intel_pinctrl *pctrl, unsigned pin) |
7981c001 MW |
201 | { |
202 | const struct intel_community *community; | |
919eb475 MW |
203 | const struct intel_padgroup *padgrp; |
204 | unsigned offset, gpp_offset; | |
7981c001 MW |
205 | void __iomem *hostown; |
206 | ||
207 | community = intel_get_community(pctrl, pin); | |
208 | if (!community) | |
209 | return true; | |
210 | if (!community->hostown_offset) | |
211 | return false; | |
212 | ||
919eb475 MW |
213 | padgrp = intel_community_get_padgroup(community, pin); |
214 | if (!padgrp) | |
215 | return true; | |
216 | ||
217 | gpp_offset = padgroup_offset(padgrp, pin); | |
218 | offset = community->hostown_offset + padgrp->reg_num * 4; | |
7981c001 MW |
219 | hostown = community->regs + offset; |
220 | ||
919eb475 | 221 | return !(readl(hostown) & BIT(gpp_offset)); |
7981c001 MW |
222 | } |
223 | ||
224 | static bool intel_pad_locked(struct intel_pinctrl *pctrl, unsigned pin) | |
225 | { | |
226 | struct intel_community *community; | |
919eb475 MW |
227 | const struct intel_padgroup *padgrp; |
228 | unsigned offset, gpp_offset; | |
7981c001 MW |
229 | u32 value; |
230 | ||
231 | community = intel_get_community(pctrl, pin); | |
232 | if (!community) | |
233 | return true; | |
234 | if (!community->padcfglock_offset) | |
235 | return false; | |
236 | ||
919eb475 MW |
237 | padgrp = intel_community_get_padgroup(community, pin); |
238 | if (!padgrp) | |
239 | return true; | |
240 | ||
241 | gpp_offset = padgroup_offset(padgrp, pin); | |
7981c001 MW |
242 | |
243 | /* | |
244 | * If PADCFGLOCK and PADCFGLOCKTX bits are both clear for this pad, | |
245 | * the pad is considered unlocked. Any other case means that it is | |
246 | * either fully or partially locked and we don't touch it. | |
247 | */ | |
919eb475 | 248 | offset = community->padcfglock_offset + padgrp->reg_num * 8; |
7981c001 | 249 | value = readl(community->regs + offset); |
919eb475 | 250 | if (value & BIT(gpp_offset)) |
7981c001 MW |
251 | return true; |
252 | ||
919eb475 | 253 | offset = community->padcfglock_offset + 4 + padgrp->reg_num * 8; |
7981c001 | 254 | value = readl(community->regs + offset); |
919eb475 | 255 | if (value & BIT(gpp_offset)) |
7981c001 MW |
256 | return true; |
257 | ||
258 | return false; | |
259 | } | |
260 | ||
261 | static bool intel_pad_usable(struct intel_pinctrl *pctrl, unsigned pin) | |
262 | { | |
263 | return intel_pad_owned_by_host(pctrl, pin) && | |
7981c001 MW |
264 | !intel_pad_locked(pctrl, pin); |
265 | } | |
266 | ||
267 | static int intel_get_groups_count(struct pinctrl_dev *pctldev) | |
268 | { | |
269 | struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
270 | ||
271 | return pctrl->soc->ngroups; | |
272 | } | |
273 | ||
274 | static const char *intel_get_group_name(struct pinctrl_dev *pctldev, | |
275 | unsigned group) | |
276 | { | |
277 | struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
278 | ||
279 | return pctrl->soc->groups[group].name; | |
280 | } | |
281 | ||
282 | static int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned group, | |
283 | const unsigned **pins, unsigned *npins) | |
284 | { | |
285 | struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
286 | ||
287 | *pins = pctrl->soc->groups[group].pins; | |
288 | *npins = pctrl->soc->groups[group].npins; | |
289 | return 0; | |
290 | } | |
291 | ||
292 | static void intel_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, | |
293 | unsigned pin) | |
294 | { | |
295 | struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
e57725ea | 296 | void __iomem *padcfg; |
7981c001 MW |
297 | u32 cfg0, cfg1, mode; |
298 | bool locked, acpi; | |
299 | ||
300 | if (!intel_pad_owned_by_host(pctrl, pin)) { | |
301 | seq_puts(s, "not available"); | |
302 | return; | |
303 | } | |
304 | ||
305 | cfg0 = readl(intel_get_padcfg(pctrl, pin, PADCFG0)); | |
306 | cfg1 = readl(intel_get_padcfg(pctrl, pin, PADCFG1)); | |
307 | ||
308 | mode = (cfg0 & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT; | |
309 | if (!mode) | |
310 | seq_puts(s, "GPIO "); | |
311 | else | |
312 | seq_printf(s, "mode %d ", mode); | |
313 | ||
314 | seq_printf(s, "0x%08x 0x%08x", cfg0, cfg1); | |
315 | ||
e57725ea MW |
316 | /* Dump the additional PADCFG registers if available */ |
317 | padcfg = intel_get_padcfg(pctrl, pin, PADCFG2); | |
318 | if (padcfg) | |
319 | seq_printf(s, " 0x%08x", readl(padcfg)); | |
320 | ||
7981c001 | 321 | locked = intel_pad_locked(pctrl, pin); |
4341e8a5 | 322 | acpi = intel_pad_acpi_mode(pctrl, pin); |
7981c001 MW |
323 | |
324 | if (locked || acpi) { | |
325 | seq_puts(s, " ["); | |
326 | if (locked) { | |
327 | seq_puts(s, "LOCKED"); | |
328 | if (acpi) | |
329 | seq_puts(s, ", "); | |
330 | } | |
331 | if (acpi) | |
332 | seq_puts(s, "ACPI"); | |
333 | seq_puts(s, "]"); | |
334 | } | |
335 | } | |
336 | ||
337 | static const struct pinctrl_ops intel_pinctrl_ops = { | |
338 | .get_groups_count = intel_get_groups_count, | |
339 | .get_group_name = intel_get_group_name, | |
340 | .get_group_pins = intel_get_group_pins, | |
341 | .pin_dbg_show = intel_pin_dbg_show, | |
342 | }; | |
343 | ||
344 | static int intel_get_functions_count(struct pinctrl_dev *pctldev) | |
345 | { | |
346 | struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
347 | ||
348 | return pctrl->soc->nfunctions; | |
349 | } | |
350 | ||
351 | static const char *intel_get_function_name(struct pinctrl_dev *pctldev, | |
352 | unsigned function) | |
353 | { | |
354 | struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
355 | ||
356 | return pctrl->soc->functions[function].name; | |
357 | } | |
358 | ||
359 | static int intel_get_function_groups(struct pinctrl_dev *pctldev, | |
360 | unsigned function, | |
361 | const char * const **groups, | |
362 | unsigned * const ngroups) | |
363 | { | |
364 | struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
365 | ||
366 | *groups = pctrl->soc->functions[function].groups; | |
367 | *ngroups = pctrl->soc->functions[function].ngroups; | |
368 | return 0; | |
369 | } | |
370 | ||
371 | static int intel_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned function, | |
372 | unsigned group) | |
373 | { | |
374 | struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
375 | const struct intel_pingroup *grp = &pctrl->soc->groups[group]; | |
376 | unsigned long flags; | |
377 | int i; | |
378 | ||
27d9098c | 379 | raw_spin_lock_irqsave(&pctrl->lock, flags); |
7981c001 MW |
380 | |
381 | /* | |
382 | * All pins in the groups needs to be accessible and writable | |
383 | * before we can enable the mux for this group. | |
384 | */ | |
385 | for (i = 0; i < grp->npins; i++) { | |
386 | if (!intel_pad_usable(pctrl, grp->pins[i])) { | |
27d9098c | 387 | raw_spin_unlock_irqrestore(&pctrl->lock, flags); |
7981c001 MW |
388 | return -EBUSY; |
389 | } | |
390 | } | |
391 | ||
392 | /* Now enable the mux setting for each pin in the group */ | |
393 | for (i = 0; i < grp->npins; i++) { | |
394 | void __iomem *padcfg0; | |
395 | u32 value; | |
396 | ||
397 | padcfg0 = intel_get_padcfg(pctrl, grp->pins[i], PADCFG0); | |
398 | value = readl(padcfg0); | |
399 | ||
400 | value &= ~PADCFG0_PMODE_MASK; | |
401 | value |= grp->mode << PADCFG0_PMODE_SHIFT; | |
402 | ||
403 | writel(value, padcfg0); | |
404 | } | |
405 | ||
27d9098c | 406 | raw_spin_unlock_irqrestore(&pctrl->lock, flags); |
7981c001 MW |
407 | |
408 | return 0; | |
409 | } | |
410 | ||
17fab473 AS |
411 | static void __intel_gpio_set_direction(void __iomem *padcfg0, bool input) |
412 | { | |
413 | u32 value; | |
414 | ||
415 | value = readl(padcfg0); | |
416 | if (input) { | |
417 | value &= ~PADCFG0_GPIORXDIS; | |
418 | value |= PADCFG0_GPIOTXDIS; | |
419 | } else { | |
420 | value &= ~PADCFG0_GPIOTXDIS; | |
421 | value |= PADCFG0_GPIORXDIS; | |
422 | } | |
423 | writel(value, padcfg0); | |
424 | } | |
425 | ||
7981c001 MW |
426 | static int intel_gpio_request_enable(struct pinctrl_dev *pctldev, |
427 | struct pinctrl_gpio_range *range, | |
428 | unsigned pin) | |
429 | { | |
430 | struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
431 | void __iomem *padcfg0; | |
432 | unsigned long flags; | |
433 | u32 value; | |
434 | ||
27d9098c | 435 | raw_spin_lock_irqsave(&pctrl->lock, flags); |
7981c001 MW |
436 | |
437 | if (!intel_pad_usable(pctrl, pin)) { | |
27d9098c | 438 | raw_spin_unlock_irqrestore(&pctrl->lock, flags); |
7981c001 MW |
439 | return -EBUSY; |
440 | } | |
441 | ||
442 | padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0); | |
443 | /* Put the pad into GPIO mode */ | |
444 | value = readl(padcfg0) & ~PADCFG0_PMODE_MASK; | |
445 | /* Disable SCI/SMI/NMI generation */ | |
446 | value &= ~(PADCFG0_GPIROUTIOXAPIC | PADCFG0_GPIROUTSCI); | |
447 | value &= ~(PADCFG0_GPIROUTSMI | PADCFG0_GPIROUTNMI); | |
7981c001 MW |
448 | writel(value, padcfg0); |
449 | ||
17fab473 AS |
450 | /* Disable TX buffer and enable RX (this will be input) */ |
451 | __intel_gpio_set_direction(padcfg0, true); | |
452 | ||
27d9098c | 453 | raw_spin_unlock_irqrestore(&pctrl->lock, flags); |
7981c001 MW |
454 | |
455 | return 0; | |
456 | } | |
457 | ||
458 | static int intel_gpio_set_direction(struct pinctrl_dev *pctldev, | |
459 | struct pinctrl_gpio_range *range, | |
460 | unsigned pin, bool input) | |
461 | { | |
462 | struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
463 | void __iomem *padcfg0; | |
464 | unsigned long flags; | |
7981c001 | 465 | |
27d9098c | 466 | raw_spin_lock_irqsave(&pctrl->lock, flags); |
7981c001 MW |
467 | |
468 | padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0); | |
17fab473 | 469 | __intel_gpio_set_direction(padcfg0, input); |
7981c001 | 470 | |
27d9098c | 471 | raw_spin_unlock_irqrestore(&pctrl->lock, flags); |
7981c001 MW |
472 | |
473 | return 0; | |
474 | } | |
475 | ||
476 | static const struct pinmux_ops intel_pinmux_ops = { | |
477 | .get_functions_count = intel_get_functions_count, | |
478 | .get_function_name = intel_get_function_name, | |
479 | .get_function_groups = intel_get_function_groups, | |
480 | .set_mux = intel_pinmux_set_mux, | |
481 | .gpio_request_enable = intel_gpio_request_enable, | |
482 | .gpio_set_direction = intel_gpio_set_direction, | |
483 | }; | |
484 | ||
485 | static int intel_config_get(struct pinctrl_dev *pctldev, unsigned pin, | |
486 | unsigned long *config) | |
487 | { | |
488 | struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
489 | enum pin_config_param param = pinconf_to_config_param(*config); | |
04cc058f | 490 | const struct intel_community *community; |
7981c001 | 491 | u32 value, term; |
e57725ea | 492 | u32 arg = 0; |
7981c001 MW |
493 | |
494 | if (!intel_pad_owned_by_host(pctrl, pin)) | |
495 | return -ENOTSUPP; | |
496 | ||
04cc058f | 497 | community = intel_get_community(pctrl, pin); |
7981c001 MW |
498 | value = readl(intel_get_padcfg(pctrl, pin, PADCFG1)); |
499 | term = (value & PADCFG1_TERM_MASK) >> PADCFG1_TERM_SHIFT; | |
500 | ||
501 | switch (param) { | |
502 | case PIN_CONFIG_BIAS_DISABLE: | |
503 | if (term) | |
504 | return -EINVAL; | |
505 | break; | |
506 | ||
507 | case PIN_CONFIG_BIAS_PULL_UP: | |
508 | if (!term || !(value & PADCFG1_TERM_UP)) | |
509 | return -EINVAL; | |
510 | ||
511 | switch (term) { | |
512 | case PADCFG1_TERM_1K: | |
513 | arg = 1000; | |
514 | break; | |
515 | case PADCFG1_TERM_2K: | |
516 | arg = 2000; | |
517 | break; | |
518 | case PADCFG1_TERM_5K: | |
519 | arg = 5000; | |
520 | break; | |
521 | case PADCFG1_TERM_20K: | |
522 | arg = 20000; | |
523 | break; | |
524 | } | |
525 | ||
526 | break; | |
527 | ||
528 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
529 | if (!term || value & PADCFG1_TERM_UP) | |
530 | return -EINVAL; | |
531 | ||
532 | switch (term) { | |
04cc058f MW |
533 | case PADCFG1_TERM_1K: |
534 | if (!(community->features & PINCTRL_FEATURE_1K_PD)) | |
535 | return -EINVAL; | |
536 | arg = 1000; | |
537 | break; | |
7981c001 MW |
538 | case PADCFG1_TERM_5K: |
539 | arg = 5000; | |
540 | break; | |
541 | case PADCFG1_TERM_20K: | |
542 | arg = 20000; | |
543 | break; | |
544 | } | |
545 | ||
546 | break; | |
547 | ||
e57725ea MW |
548 | case PIN_CONFIG_INPUT_DEBOUNCE: { |
549 | void __iomem *padcfg2; | |
550 | u32 v; | |
551 | ||
552 | padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2); | |
553 | if (!padcfg2) | |
554 | return -ENOTSUPP; | |
555 | ||
556 | v = readl(padcfg2); | |
557 | if (!(v & PADCFG2_DEBEN)) | |
558 | return -EINVAL; | |
559 | ||
560 | v = (v & PADCFG2_DEBOUNCE_MASK) >> PADCFG2_DEBOUNCE_SHIFT; | |
561 | arg = BIT(v) * DEBOUNCE_PERIOD / 1000; | |
562 | ||
563 | break; | |
564 | } | |
565 | ||
7981c001 MW |
566 | default: |
567 | return -ENOTSUPP; | |
568 | } | |
569 | ||
570 | *config = pinconf_to_config_packed(param, arg); | |
571 | return 0; | |
572 | } | |
573 | ||
574 | static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned pin, | |
575 | unsigned long config) | |
576 | { | |
577 | unsigned param = pinconf_to_config_param(config); | |
578 | unsigned arg = pinconf_to_config_argument(config); | |
04cc058f | 579 | const struct intel_community *community; |
7981c001 MW |
580 | void __iomem *padcfg1; |
581 | unsigned long flags; | |
582 | int ret = 0; | |
583 | u32 value; | |
584 | ||
27d9098c | 585 | raw_spin_lock_irqsave(&pctrl->lock, flags); |
7981c001 | 586 | |
04cc058f | 587 | community = intel_get_community(pctrl, pin); |
7981c001 MW |
588 | padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1); |
589 | value = readl(padcfg1); | |
590 | ||
591 | switch (param) { | |
592 | case PIN_CONFIG_BIAS_DISABLE: | |
593 | value &= ~(PADCFG1_TERM_MASK | PADCFG1_TERM_UP); | |
594 | break; | |
595 | ||
596 | case PIN_CONFIG_BIAS_PULL_UP: | |
597 | value &= ~PADCFG1_TERM_MASK; | |
598 | ||
599 | value |= PADCFG1_TERM_UP; | |
600 | ||
601 | switch (arg) { | |
602 | case 20000: | |
603 | value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT; | |
604 | break; | |
605 | case 5000: | |
606 | value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT; | |
607 | break; | |
608 | case 2000: | |
609 | value |= PADCFG1_TERM_2K << PADCFG1_TERM_SHIFT; | |
610 | break; | |
611 | case 1000: | |
612 | value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT; | |
613 | break; | |
614 | default: | |
615 | ret = -EINVAL; | |
616 | } | |
617 | ||
618 | break; | |
619 | ||
620 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
621 | value &= ~(PADCFG1_TERM_UP | PADCFG1_TERM_MASK); | |
622 | ||
623 | switch (arg) { | |
624 | case 20000: | |
625 | value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT; | |
626 | break; | |
627 | case 5000: | |
628 | value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT; | |
629 | break; | |
04cc058f | 630 | case 1000: |
aa1dd80f DC |
631 | if (!(community->features & PINCTRL_FEATURE_1K_PD)) { |
632 | ret = -EINVAL; | |
633 | break; | |
634 | } | |
04cc058f MW |
635 | value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT; |
636 | break; | |
7981c001 MW |
637 | default: |
638 | ret = -EINVAL; | |
639 | } | |
640 | ||
641 | break; | |
642 | } | |
643 | ||
644 | if (!ret) | |
645 | writel(value, padcfg1); | |
646 | ||
27d9098c | 647 | raw_spin_unlock_irqrestore(&pctrl->lock, flags); |
7981c001 MW |
648 | |
649 | return ret; | |
650 | } | |
651 | ||
e57725ea MW |
652 | static int intel_config_set_debounce(struct intel_pinctrl *pctrl, unsigned pin, |
653 | unsigned debounce) | |
654 | { | |
655 | void __iomem *padcfg0, *padcfg2; | |
656 | unsigned long flags; | |
657 | u32 value0, value2; | |
658 | int ret = 0; | |
659 | ||
660 | padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2); | |
661 | if (!padcfg2) | |
662 | return -ENOTSUPP; | |
663 | ||
664 | padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0); | |
665 | ||
666 | raw_spin_lock_irqsave(&pctrl->lock, flags); | |
667 | ||
668 | value0 = readl(padcfg0); | |
669 | value2 = readl(padcfg2); | |
670 | ||
671 | /* Disable glitch filter and debouncer */ | |
672 | value0 &= ~PADCFG0_PREGFRXSEL; | |
673 | value2 &= ~(PADCFG2_DEBEN | PADCFG2_DEBOUNCE_MASK); | |
674 | ||
675 | if (debounce) { | |
676 | unsigned long v; | |
677 | ||
678 | v = order_base_2(debounce * 1000 / DEBOUNCE_PERIOD); | |
679 | if (v < 3 || v > 15) { | |
680 | ret = -EINVAL; | |
681 | goto exit_unlock; | |
682 | } else { | |
683 | /* Enable glitch filter and debouncer */ | |
684 | value0 |= PADCFG0_PREGFRXSEL; | |
685 | value2 |= v << PADCFG2_DEBOUNCE_SHIFT; | |
686 | value2 |= PADCFG2_DEBEN; | |
687 | } | |
688 | } | |
689 | ||
690 | writel(value0, padcfg0); | |
691 | writel(value2, padcfg2); | |
692 | ||
693 | exit_unlock: | |
694 | raw_spin_unlock_irqrestore(&pctrl->lock, flags); | |
695 | ||
696 | return ret; | |
697 | } | |
698 | ||
7981c001 MW |
699 | static int intel_config_set(struct pinctrl_dev *pctldev, unsigned pin, |
700 | unsigned long *configs, unsigned nconfigs) | |
701 | { | |
702 | struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
703 | int i, ret; | |
704 | ||
705 | if (!intel_pad_usable(pctrl, pin)) | |
706 | return -ENOTSUPP; | |
707 | ||
708 | for (i = 0; i < nconfigs; i++) { | |
709 | switch (pinconf_to_config_param(configs[i])) { | |
710 | case PIN_CONFIG_BIAS_DISABLE: | |
711 | case PIN_CONFIG_BIAS_PULL_UP: | |
712 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
713 | ret = intel_config_set_pull(pctrl, pin, configs[i]); | |
714 | if (ret) | |
715 | return ret; | |
716 | break; | |
717 | ||
e57725ea MW |
718 | case PIN_CONFIG_INPUT_DEBOUNCE: |
719 | ret = intel_config_set_debounce(pctrl, pin, | |
720 | pinconf_to_config_argument(configs[i])); | |
721 | if (ret) | |
722 | return ret; | |
723 | break; | |
724 | ||
7981c001 MW |
725 | default: |
726 | return -ENOTSUPP; | |
727 | } | |
728 | } | |
729 | ||
730 | return 0; | |
731 | } | |
732 | ||
733 | static const struct pinconf_ops intel_pinconf_ops = { | |
734 | .is_generic = true, | |
735 | .pin_config_get = intel_config_get, | |
736 | .pin_config_set = intel_config_set, | |
737 | }; | |
738 | ||
739 | static const struct pinctrl_desc intel_pinctrl_desc = { | |
740 | .pctlops = &intel_pinctrl_ops, | |
741 | .pmxops = &intel_pinmux_ops, | |
742 | .confops = &intel_pinconf_ops, | |
743 | .owner = THIS_MODULE, | |
744 | }; | |
745 | ||
7981c001 MW |
746 | static int intel_gpio_get(struct gpio_chip *chip, unsigned offset) |
747 | { | |
acfd4c63 | 748 | struct intel_pinctrl *pctrl = gpiochip_get_data(chip); |
7981c001 MW |
749 | void __iomem *reg; |
750 | ||
751 | reg = intel_get_padcfg(pctrl, offset, PADCFG0); | |
752 | if (!reg) | |
753 | return -EINVAL; | |
754 | ||
755 | return !!(readl(reg) & PADCFG0_GPIORXSTATE); | |
756 | } | |
757 | ||
758 | static void intel_gpio_set(struct gpio_chip *chip, unsigned offset, int value) | |
759 | { | |
acfd4c63 | 760 | struct intel_pinctrl *pctrl = gpiochip_get_data(chip); |
7981c001 MW |
761 | void __iomem *reg; |
762 | ||
763 | reg = intel_get_padcfg(pctrl, offset, PADCFG0); | |
764 | if (reg) { | |
765 | unsigned long flags; | |
766 | u32 padcfg0; | |
767 | ||
27d9098c | 768 | raw_spin_lock_irqsave(&pctrl->lock, flags); |
7981c001 MW |
769 | padcfg0 = readl(reg); |
770 | if (value) | |
771 | padcfg0 |= PADCFG0_GPIOTXSTATE; | |
772 | else | |
773 | padcfg0 &= ~PADCFG0_GPIOTXSTATE; | |
774 | writel(padcfg0, reg); | |
27d9098c | 775 | raw_spin_unlock_irqrestore(&pctrl->lock, flags); |
7981c001 MW |
776 | } |
777 | } | |
778 | ||
779 | static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned offset) | |
780 | { | |
781 | return pinctrl_gpio_direction_input(chip->base + offset); | |
782 | } | |
783 | ||
784 | static int intel_gpio_direction_output(struct gpio_chip *chip, unsigned offset, | |
785 | int value) | |
786 | { | |
787 | intel_gpio_set(chip, offset, value); | |
788 | return pinctrl_gpio_direction_output(chip->base + offset); | |
789 | } | |
790 | ||
791 | static const struct gpio_chip intel_gpio_chip = { | |
792 | .owner = THIS_MODULE, | |
98c85d58 JG |
793 | .request = gpiochip_generic_request, |
794 | .free = gpiochip_generic_free, | |
7981c001 MW |
795 | .direction_input = intel_gpio_direction_input, |
796 | .direction_output = intel_gpio_direction_output, | |
797 | .get = intel_gpio_get, | |
798 | .set = intel_gpio_set, | |
e57725ea | 799 | .set_config = gpiochip_generic_config, |
7981c001 MW |
800 | }; |
801 | ||
802 | static void intel_gpio_irq_ack(struct irq_data *d) | |
803 | { | |
804 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); | |
acfd4c63 | 805 | struct intel_pinctrl *pctrl = gpiochip_get_data(gc); |
7981c001 MW |
806 | const struct intel_community *community; |
807 | unsigned pin = irqd_to_hwirq(d); | |
808 | ||
7981c001 MW |
809 | community = intel_get_community(pctrl, pin); |
810 | if (community) { | |
919eb475 MW |
811 | const struct intel_padgroup *padgrp; |
812 | unsigned gpp, gpp_offset; | |
813 | ||
814 | padgrp = intel_community_get_padgroup(community, pin); | |
815 | if (!padgrp) | |
816 | return; | |
817 | ||
818 | gpp = padgrp->reg_num; | |
819 | gpp_offset = padgroup_offset(padgrp, pin); | |
7981c001 | 820 | |
919eb475 | 821 | raw_spin_lock(&pctrl->lock); |
7981c001 | 822 | writel(BIT(gpp_offset), community->regs + GPI_IS + gpp * 4); |
919eb475 | 823 | raw_spin_unlock(&pctrl->lock); |
7981c001 | 824 | } |
7981c001 MW |
825 | } |
826 | ||
a939bb57 QZ |
827 | static void intel_gpio_irq_enable(struct irq_data *d) |
828 | { | |
829 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); | |
830 | struct intel_pinctrl *pctrl = gpiochip_get_data(gc); | |
831 | const struct intel_community *community; | |
832 | unsigned pin = irqd_to_hwirq(d); | |
a939bb57 QZ |
833 | |
834 | community = intel_get_community(pctrl, pin); | |
835 | if (community) { | |
919eb475 MW |
836 | const struct intel_padgroup *padgrp; |
837 | unsigned gpp, gpp_offset; | |
838 | unsigned long flags; | |
a939bb57 QZ |
839 | u32 value; |
840 | ||
919eb475 MW |
841 | padgrp = intel_community_get_padgroup(community, pin); |
842 | if (!padgrp) | |
843 | return; | |
844 | ||
845 | gpp = padgrp->reg_num; | |
846 | gpp_offset = padgroup_offset(padgrp, pin); | |
847 | ||
848 | raw_spin_lock_irqsave(&pctrl->lock, flags); | |
a939bb57 QZ |
849 | /* Clear interrupt status first to avoid unexpected interrupt */ |
850 | writel(BIT(gpp_offset), community->regs + GPI_IS + gpp * 4); | |
851 | ||
852 | value = readl(community->regs + community->ie_offset + gpp * 4); | |
853 | value |= BIT(gpp_offset); | |
854 | writel(value, community->regs + community->ie_offset + gpp * 4); | |
919eb475 | 855 | raw_spin_unlock_irqrestore(&pctrl->lock, flags); |
a939bb57 | 856 | } |
a939bb57 QZ |
857 | } |
858 | ||
7981c001 MW |
859 | static void intel_gpio_irq_mask_unmask(struct irq_data *d, bool mask) |
860 | { | |
861 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); | |
acfd4c63 | 862 | struct intel_pinctrl *pctrl = gpiochip_get_data(gc); |
7981c001 MW |
863 | const struct intel_community *community; |
864 | unsigned pin = irqd_to_hwirq(d); | |
7981c001 MW |
865 | |
866 | community = intel_get_community(pctrl, pin); | |
867 | if (community) { | |
919eb475 MW |
868 | const struct intel_padgroup *padgrp; |
869 | unsigned gpp, gpp_offset; | |
870 | unsigned long flags; | |
7981c001 MW |
871 | void __iomem *reg; |
872 | u32 value; | |
873 | ||
919eb475 MW |
874 | padgrp = intel_community_get_padgroup(community, pin); |
875 | if (!padgrp) | |
876 | return; | |
877 | ||
878 | gpp = padgrp->reg_num; | |
879 | gpp_offset = padgroup_offset(padgrp, pin); | |
880 | ||
7981c001 | 881 | reg = community->regs + community->ie_offset + gpp * 4; |
919eb475 MW |
882 | |
883 | raw_spin_lock_irqsave(&pctrl->lock, flags); | |
7981c001 MW |
884 | value = readl(reg); |
885 | if (mask) | |
886 | value &= ~BIT(gpp_offset); | |
887 | else | |
888 | value |= BIT(gpp_offset); | |
889 | writel(value, reg); | |
919eb475 | 890 | raw_spin_unlock_irqrestore(&pctrl->lock, flags); |
7981c001 | 891 | } |
7981c001 MW |
892 | } |
893 | ||
894 | static void intel_gpio_irq_mask(struct irq_data *d) | |
895 | { | |
896 | intel_gpio_irq_mask_unmask(d, true); | |
897 | } | |
898 | ||
899 | static void intel_gpio_irq_unmask(struct irq_data *d) | |
900 | { | |
901 | intel_gpio_irq_mask_unmask(d, false); | |
902 | } | |
903 | ||
904 | static int intel_gpio_irq_type(struct irq_data *d, unsigned type) | |
905 | { | |
906 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); | |
acfd4c63 | 907 | struct intel_pinctrl *pctrl = gpiochip_get_data(gc); |
7981c001 MW |
908 | unsigned pin = irqd_to_hwirq(d); |
909 | unsigned long flags; | |
910 | void __iomem *reg; | |
911 | u32 value; | |
912 | ||
913 | reg = intel_get_padcfg(pctrl, pin, PADCFG0); | |
914 | if (!reg) | |
915 | return -EINVAL; | |
916 | ||
4341e8a5 MW |
917 | /* |
918 | * If the pin is in ACPI mode it is still usable as a GPIO but it | |
919 | * cannot be used as IRQ because GPI_IS status bit will not be | |
920 | * updated by the host controller hardware. | |
921 | */ | |
922 | if (intel_pad_acpi_mode(pctrl, pin)) { | |
923 | dev_warn(pctrl->dev, "pin %u cannot be used as IRQ\n", pin); | |
924 | return -EPERM; | |
925 | } | |
926 | ||
27d9098c | 927 | raw_spin_lock_irqsave(&pctrl->lock, flags); |
7981c001 MW |
928 | |
929 | value = readl(reg); | |
930 | ||
931 | value &= ~(PADCFG0_RXEVCFG_MASK | PADCFG0_RXINV); | |
932 | ||
933 | if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) { | |
934 | value |= PADCFG0_RXEVCFG_EDGE_BOTH << PADCFG0_RXEVCFG_SHIFT; | |
935 | } else if (type & IRQ_TYPE_EDGE_FALLING) { | |
936 | value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT; | |
937 | value |= PADCFG0_RXINV; | |
938 | } else if (type & IRQ_TYPE_EDGE_RISING) { | |
939 | value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT; | |
bf380cfa QZ |
940 | } else if (type & IRQ_TYPE_LEVEL_MASK) { |
941 | if (type & IRQ_TYPE_LEVEL_LOW) | |
942 | value |= PADCFG0_RXINV; | |
7981c001 MW |
943 | } else { |
944 | value |= PADCFG0_RXEVCFG_DISABLED << PADCFG0_RXEVCFG_SHIFT; | |
945 | } | |
946 | ||
947 | writel(value, reg); | |
948 | ||
949 | if (type & IRQ_TYPE_EDGE_BOTH) | |
fc756bcd | 950 | irq_set_handler_locked(d, handle_edge_irq); |
7981c001 | 951 | else if (type & IRQ_TYPE_LEVEL_MASK) |
fc756bcd | 952 | irq_set_handler_locked(d, handle_level_irq); |
7981c001 | 953 | |
27d9098c | 954 | raw_spin_unlock_irqrestore(&pctrl->lock, flags); |
7981c001 MW |
955 | |
956 | return 0; | |
957 | } | |
958 | ||
959 | static int intel_gpio_irq_wake(struct irq_data *d, unsigned int on) | |
960 | { | |
961 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); | |
acfd4c63 | 962 | struct intel_pinctrl *pctrl = gpiochip_get_data(gc); |
7981c001 | 963 | unsigned pin = irqd_to_hwirq(d); |
9a520fd9 | 964 | |
7981c001 | 965 | if (on) |
01dabe91 | 966 | enable_irq_wake(pctrl->irq); |
7981c001 | 967 | else |
01dabe91 | 968 | disable_irq_wake(pctrl->irq); |
9a520fd9 | 969 | |
7981c001 MW |
970 | dev_dbg(pctrl->dev, "%sable wake for pin %u\n", on ? "en" : "dis", pin); |
971 | return 0; | |
972 | } | |
973 | ||
193b40c8 | 974 | static irqreturn_t intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl, |
7981c001 MW |
975 | const struct intel_community *community) |
976 | { | |
193b40c8 MW |
977 | struct gpio_chip *gc = &pctrl->chip; |
978 | irqreturn_t ret = IRQ_NONE; | |
7981c001 MW |
979 | int gpp; |
980 | ||
981 | for (gpp = 0; gpp < community->ngpps; gpp++) { | |
919eb475 | 982 | const struct intel_padgroup *padgrp = &community->gpps[gpp]; |
7981c001 MW |
983 | unsigned long pending, enabled, gpp_offset; |
984 | ||
919eb475 | 985 | pending = readl(community->regs + GPI_IS + padgrp->reg_num * 4); |
7981c001 | 986 | enabled = readl(community->regs + community->ie_offset + |
919eb475 | 987 | padgrp->reg_num * 4); |
7981c001 MW |
988 | |
989 | /* Only interrupts that are enabled */ | |
990 | pending &= enabled; | |
991 | ||
919eb475 | 992 | for_each_set_bit(gpp_offset, &pending, padgrp->size) { |
7981c001 MW |
993 | unsigned padno, irq; |
994 | ||
919eb475 | 995 | padno = padgrp->base - community->pin_base + gpp_offset; |
7981c001 MW |
996 | if (padno >= community->npins) |
997 | break; | |
998 | ||
999 | irq = irq_find_mapping(gc->irqdomain, | |
1000 | community->pin_base + padno); | |
1001 | generic_handle_irq(irq); | |
193b40c8 MW |
1002 | |
1003 | ret |= IRQ_HANDLED; | |
7981c001 MW |
1004 | } |
1005 | } | |
193b40c8 MW |
1006 | |
1007 | return ret; | |
7981c001 MW |
1008 | } |
1009 | ||
193b40c8 | 1010 | static irqreturn_t intel_gpio_irq(int irq, void *data) |
7981c001 | 1011 | { |
193b40c8 MW |
1012 | const struct intel_community *community; |
1013 | struct intel_pinctrl *pctrl = data; | |
1014 | irqreturn_t ret = IRQ_NONE; | |
7981c001 MW |
1015 | int i; |
1016 | ||
7981c001 | 1017 | /* Need to check all communities for pending interrupts */ |
193b40c8 MW |
1018 | for (i = 0; i < pctrl->ncommunities; i++) { |
1019 | community = &pctrl->communities[i]; | |
1020 | ret |= intel_gpio_community_irq_handler(pctrl, community); | |
1021 | } | |
7981c001 | 1022 | |
193b40c8 | 1023 | return ret; |
7981c001 MW |
1024 | } |
1025 | ||
1026 | static struct irq_chip intel_gpio_irqchip = { | |
1027 | .name = "intel-gpio", | |
a939bb57 | 1028 | .irq_enable = intel_gpio_irq_enable, |
7981c001 MW |
1029 | .irq_ack = intel_gpio_irq_ack, |
1030 | .irq_mask = intel_gpio_irq_mask, | |
1031 | .irq_unmask = intel_gpio_irq_unmask, | |
1032 | .irq_set_type = intel_gpio_irq_type, | |
1033 | .irq_set_wake = intel_gpio_irq_wake, | |
1034 | }; | |
1035 | ||
7981c001 MW |
1036 | static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq) |
1037 | { | |
1038 | int ret; | |
1039 | ||
1040 | pctrl->chip = intel_gpio_chip; | |
1041 | ||
1042 | pctrl->chip.ngpio = pctrl->soc->npins; | |
1043 | pctrl->chip.label = dev_name(pctrl->dev); | |
58383c78 | 1044 | pctrl->chip.parent = pctrl->dev; |
7981c001 | 1045 | pctrl->chip.base = -1; |
01dabe91 | 1046 | pctrl->irq = irq; |
7981c001 | 1047 | |
f25c3aa9 | 1048 | ret = devm_gpiochip_add_data(pctrl->dev, &pctrl->chip, pctrl); |
7981c001 MW |
1049 | if (ret) { |
1050 | dev_err(pctrl->dev, "failed to register gpiochip\n"); | |
1051 | return ret; | |
1052 | } | |
1053 | ||
1054 | ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), | |
1055 | 0, 0, pctrl->soc->npins); | |
1056 | if (ret) { | |
1057 | dev_err(pctrl->dev, "failed to add GPIO pin range\n"); | |
f25c3aa9 | 1058 | return ret; |
193b40c8 MW |
1059 | } |
1060 | ||
1061 | /* | |
1062 | * We need to request the interrupt here (instead of providing chip | |
1063 | * to the irq directly) because on some platforms several GPIO | |
1064 | * controllers share the same interrupt line. | |
1065 | */ | |
1a7d1cb8 MW |
1066 | ret = devm_request_irq(pctrl->dev, irq, intel_gpio_irq, |
1067 | IRQF_SHARED | IRQF_NO_THREAD, | |
193b40c8 MW |
1068 | dev_name(pctrl->dev), pctrl); |
1069 | if (ret) { | |
1070 | dev_err(pctrl->dev, "failed to request interrupt\n"); | |
f25c3aa9 | 1071 | return ret; |
7981c001 MW |
1072 | } |
1073 | ||
1074 | ret = gpiochip_irqchip_add(&pctrl->chip, &intel_gpio_irqchip, 0, | |
3ae02c14 | 1075 | handle_bad_irq, IRQ_TYPE_NONE); |
7981c001 MW |
1076 | if (ret) { |
1077 | dev_err(pctrl->dev, "failed to add irqchip\n"); | |
f25c3aa9 | 1078 | return ret; |
7981c001 MW |
1079 | } |
1080 | ||
1081 | gpiochip_set_chained_irqchip(&pctrl->chip, &intel_gpio_irqchip, irq, | |
193b40c8 | 1082 | NULL); |
7981c001 MW |
1083 | return 0; |
1084 | } | |
1085 | ||
919eb475 MW |
1086 | static int intel_pinctrl_add_padgroups(struct intel_pinctrl *pctrl, |
1087 | struct intel_community *community) | |
1088 | { | |
1089 | struct intel_padgroup *gpps; | |
1090 | unsigned npins = community->npins; | |
1091 | unsigned padown_num = 0; | |
1092 | size_t ngpps, i; | |
1093 | ||
1094 | if (community->gpps) | |
1095 | ngpps = community->ngpps; | |
1096 | else | |
1097 | ngpps = DIV_ROUND_UP(community->npins, community->gpp_size); | |
1098 | ||
1099 | gpps = devm_kcalloc(pctrl->dev, ngpps, sizeof(*gpps), GFP_KERNEL); | |
1100 | if (!gpps) | |
1101 | return -ENOMEM; | |
1102 | ||
1103 | for (i = 0; i < ngpps; i++) { | |
1104 | if (community->gpps) { | |
1105 | gpps[i] = community->gpps[i]; | |
1106 | } else { | |
1107 | unsigned gpp_size = community->gpp_size; | |
1108 | ||
1109 | gpps[i].reg_num = i; | |
1110 | gpps[i].base = community->pin_base + i * gpp_size; | |
1111 | gpps[i].size = min(gpp_size, npins); | |
1112 | npins -= gpps[i].size; | |
1113 | } | |
1114 | ||
1115 | if (gpps[i].size > 32) | |
1116 | return -EINVAL; | |
1117 | ||
1118 | gpps[i].padown_num = padown_num; | |
1119 | ||
1120 | /* | |
1121 | * In older hardware the number of padown registers per | |
1122 | * group is fixed regardless of the group size. | |
1123 | */ | |
1124 | if (community->gpp_num_padown_regs) | |
1125 | padown_num += community->gpp_num_padown_regs; | |
1126 | else | |
1127 | padown_num += DIV_ROUND_UP(gpps[i].size * 4, 32); | |
1128 | } | |
1129 | ||
1130 | community->ngpps = ngpps; | |
1131 | community->gpps = gpps; | |
1132 | ||
1133 | return 0; | |
1134 | } | |
1135 | ||
7981c001 MW |
1136 | static int intel_pinctrl_pm_init(struct intel_pinctrl *pctrl) |
1137 | { | |
1138 | #ifdef CONFIG_PM_SLEEP | |
1139 | const struct intel_pinctrl_soc_data *soc = pctrl->soc; | |
1140 | struct intel_community_context *communities; | |
1141 | struct intel_pad_context *pads; | |
1142 | int i; | |
1143 | ||
1144 | pads = devm_kcalloc(pctrl->dev, soc->npins, sizeof(*pads), GFP_KERNEL); | |
1145 | if (!pads) | |
1146 | return -ENOMEM; | |
1147 | ||
1148 | communities = devm_kcalloc(pctrl->dev, pctrl->ncommunities, | |
1149 | sizeof(*communities), GFP_KERNEL); | |
1150 | if (!communities) | |
1151 | return -ENOMEM; | |
1152 | ||
1153 | ||
1154 | for (i = 0; i < pctrl->ncommunities; i++) { | |
1155 | struct intel_community *community = &pctrl->communities[i]; | |
1156 | u32 *intmask; | |
1157 | ||
1158 | intmask = devm_kcalloc(pctrl->dev, community->ngpps, | |
1159 | sizeof(*intmask), GFP_KERNEL); | |
1160 | if (!intmask) | |
1161 | return -ENOMEM; | |
1162 | ||
1163 | communities[i].intmask = intmask; | |
1164 | } | |
1165 | ||
1166 | pctrl->context.pads = pads; | |
1167 | pctrl->context.communities = communities; | |
1168 | #endif | |
1169 | ||
1170 | return 0; | |
1171 | } | |
1172 | ||
1173 | int intel_pinctrl_probe(struct platform_device *pdev, | |
1174 | const struct intel_pinctrl_soc_data *soc_data) | |
1175 | { | |
1176 | struct intel_pinctrl *pctrl; | |
1177 | int i, ret, irq; | |
1178 | ||
1179 | if (!soc_data) | |
1180 | return -EINVAL; | |
1181 | ||
1182 | pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); | |
1183 | if (!pctrl) | |
1184 | return -ENOMEM; | |
1185 | ||
1186 | pctrl->dev = &pdev->dev; | |
1187 | pctrl->soc = soc_data; | |
27d9098c | 1188 | raw_spin_lock_init(&pctrl->lock); |
7981c001 MW |
1189 | |
1190 | /* | |
1191 | * Make a copy of the communities which we can use to hold pointers | |
1192 | * to the registers. | |
1193 | */ | |
1194 | pctrl->ncommunities = pctrl->soc->ncommunities; | |
1195 | pctrl->communities = devm_kcalloc(&pdev->dev, pctrl->ncommunities, | |
1196 | sizeof(*pctrl->communities), GFP_KERNEL); | |
1197 | if (!pctrl->communities) | |
1198 | return -ENOMEM; | |
1199 | ||
1200 | for (i = 0; i < pctrl->ncommunities; i++) { | |
1201 | struct intel_community *community = &pctrl->communities[i]; | |
1202 | struct resource *res; | |
1203 | void __iomem *regs; | |
1204 | u32 padbar; | |
1205 | ||
1206 | *community = pctrl->soc->communities[i]; | |
1207 | ||
1208 | res = platform_get_resource(pdev, IORESOURCE_MEM, | |
1209 | community->barno); | |
1210 | regs = devm_ioremap_resource(&pdev->dev, res); | |
1211 | if (IS_ERR(regs)) | |
1212 | return PTR_ERR(regs); | |
1213 | ||
e57725ea MW |
1214 | /* |
1215 | * Determine community features based on the revision if | |
1216 | * not specified already. | |
1217 | */ | |
1218 | if (!community->features) { | |
1219 | u32 rev; | |
1220 | ||
1221 | rev = (readl(regs + REVID) & REVID_MASK) >> REVID_SHIFT; | |
04cc058f | 1222 | if (rev >= 0x94) { |
e57725ea | 1223 | community->features |= PINCTRL_FEATURE_DEBOUNCE; |
04cc058f MW |
1224 | community->features |= PINCTRL_FEATURE_1K_PD; |
1225 | } | |
e57725ea MW |
1226 | } |
1227 | ||
7981c001 MW |
1228 | /* Read offset of the pad configuration registers */ |
1229 | padbar = readl(regs + PADBAR); | |
1230 | ||
1231 | community->regs = regs; | |
1232 | community->pad_regs = regs + padbar; | |
919eb475 MW |
1233 | |
1234 | ret = intel_pinctrl_add_padgroups(pctrl, community); | |
1235 | if (ret) | |
1236 | return ret; | |
7981c001 MW |
1237 | } |
1238 | ||
1239 | irq = platform_get_irq(pdev, 0); | |
1240 | if (irq < 0) { | |
1241 | dev_err(&pdev->dev, "failed to get interrupt number\n"); | |
1242 | return irq; | |
1243 | } | |
1244 | ||
1245 | ret = intel_pinctrl_pm_init(pctrl); | |
1246 | if (ret) | |
1247 | return ret; | |
1248 | ||
1249 | pctrl->pctldesc = intel_pinctrl_desc; | |
1250 | pctrl->pctldesc.name = dev_name(&pdev->dev); | |
1251 | pctrl->pctldesc.pins = pctrl->soc->pins; | |
1252 | pctrl->pctldesc.npins = pctrl->soc->npins; | |
1253 | ||
54d46cd7 LD |
1254 | pctrl->pctldev = devm_pinctrl_register(&pdev->dev, &pctrl->pctldesc, |
1255 | pctrl); | |
323de9ef | 1256 | if (IS_ERR(pctrl->pctldev)) { |
7981c001 | 1257 | dev_err(&pdev->dev, "failed to register pinctrl driver\n"); |
323de9ef | 1258 | return PTR_ERR(pctrl->pctldev); |
7981c001 MW |
1259 | } |
1260 | ||
1261 | ret = intel_gpio_probe(pctrl, irq); | |
54d46cd7 | 1262 | if (ret) |
7981c001 | 1263 | return ret; |
7981c001 MW |
1264 | |
1265 | platform_set_drvdata(pdev, pctrl); | |
1266 | ||
1267 | return 0; | |
1268 | } | |
1269 | EXPORT_SYMBOL_GPL(intel_pinctrl_probe); | |
1270 | ||
7981c001 | 1271 | #ifdef CONFIG_PM_SLEEP |
c538b943 MW |
1272 | static bool intel_pinctrl_should_save(struct intel_pinctrl *pctrl, unsigned pin) |
1273 | { | |
1274 | const struct pin_desc *pd = pin_desc_get(pctrl->pctldev, pin); | |
1275 | ||
1276 | if (!pd || !intel_pad_usable(pctrl, pin)) | |
1277 | return false; | |
1278 | ||
1279 | /* | |
1280 | * Only restore the pin if it is actually in use by the kernel (or | |
1281 | * by userspace). It is possible that some pins are used by the | |
1282 | * BIOS during resume and those are not always locked down so leave | |
1283 | * them alone. | |
1284 | */ | |
1285 | if (pd->mux_owner || pd->gpio_owner || | |
1286 | gpiochip_line_is_irq(&pctrl->chip, pin)) | |
1287 | return true; | |
1288 | ||
1289 | return false; | |
1290 | } | |
1291 | ||
7981c001 MW |
1292 | int intel_pinctrl_suspend(struct device *dev) |
1293 | { | |
1294 | struct platform_device *pdev = to_platform_device(dev); | |
1295 | struct intel_pinctrl *pctrl = platform_get_drvdata(pdev); | |
1296 | struct intel_community_context *communities; | |
1297 | struct intel_pad_context *pads; | |
1298 | int i; | |
1299 | ||
1300 | pads = pctrl->context.pads; | |
1301 | for (i = 0; i < pctrl->soc->npins; i++) { | |
1302 | const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i]; | |
e57725ea | 1303 | void __iomem *padcfg; |
7981c001 MW |
1304 | u32 val; |
1305 | ||
c538b943 | 1306 | if (!intel_pinctrl_should_save(pctrl, desc->number)) |
7981c001 MW |
1307 | continue; |
1308 | ||
1309 | val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG0)); | |
1310 | pads[i].padcfg0 = val & ~PADCFG0_GPIORXSTATE; | |
1311 | val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG1)); | |
1312 | pads[i].padcfg1 = val; | |
e57725ea MW |
1313 | |
1314 | padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG2); | |
1315 | if (padcfg) | |
1316 | pads[i].padcfg2 = readl(padcfg); | |
7981c001 MW |
1317 | } |
1318 | ||
1319 | communities = pctrl->context.communities; | |
1320 | for (i = 0; i < pctrl->ncommunities; i++) { | |
1321 | struct intel_community *community = &pctrl->communities[i]; | |
1322 | void __iomem *base; | |
1323 | unsigned gpp; | |
1324 | ||
1325 | base = community->regs + community->ie_offset; | |
1326 | for (gpp = 0; gpp < community->ngpps; gpp++) | |
1327 | communities[i].intmask[gpp] = readl(base + gpp * 4); | |
1328 | } | |
1329 | ||
1330 | return 0; | |
1331 | } | |
1332 | EXPORT_SYMBOL_GPL(intel_pinctrl_suspend); | |
1333 | ||
f487bbf3 MW |
1334 | static void intel_gpio_irq_init(struct intel_pinctrl *pctrl) |
1335 | { | |
1336 | size_t i; | |
1337 | ||
1338 | for (i = 0; i < pctrl->ncommunities; i++) { | |
1339 | const struct intel_community *community; | |
1340 | void __iomem *base; | |
1341 | unsigned gpp; | |
1342 | ||
1343 | community = &pctrl->communities[i]; | |
1344 | base = community->regs; | |
1345 | ||
1346 | for (gpp = 0; gpp < community->ngpps; gpp++) { | |
1347 | /* Mask and clear all interrupts */ | |
1348 | writel(0, base + community->ie_offset + gpp * 4); | |
1349 | writel(0xffff, base + GPI_IS + gpp * 4); | |
1350 | } | |
1351 | } | |
1352 | } | |
1353 | ||
7981c001 MW |
1354 | int intel_pinctrl_resume(struct device *dev) |
1355 | { | |
1356 | struct platform_device *pdev = to_platform_device(dev); | |
1357 | struct intel_pinctrl *pctrl = platform_get_drvdata(pdev); | |
1358 | const struct intel_community_context *communities; | |
1359 | const struct intel_pad_context *pads; | |
1360 | int i; | |
1361 | ||
1362 | /* Mask all interrupts */ | |
1363 | intel_gpio_irq_init(pctrl); | |
1364 | ||
1365 | pads = pctrl->context.pads; | |
1366 | for (i = 0; i < pctrl->soc->npins; i++) { | |
1367 | const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i]; | |
1368 | void __iomem *padcfg; | |
1369 | u32 val; | |
1370 | ||
c538b943 | 1371 | if (!intel_pinctrl_should_save(pctrl, desc->number)) |
7981c001 MW |
1372 | continue; |
1373 | ||
1374 | padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG0); | |
1375 | val = readl(padcfg) & ~PADCFG0_GPIORXSTATE; | |
1376 | if (val != pads[i].padcfg0) { | |
1377 | writel(pads[i].padcfg0, padcfg); | |
1378 | dev_dbg(dev, "restored pin %u padcfg0 %#08x\n", | |
1379 | desc->number, readl(padcfg)); | |
1380 | } | |
1381 | ||
1382 | padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG1); | |
1383 | val = readl(padcfg); | |
1384 | if (val != pads[i].padcfg1) { | |
1385 | writel(pads[i].padcfg1, padcfg); | |
1386 | dev_dbg(dev, "restored pin %u padcfg1 %#08x\n", | |
1387 | desc->number, readl(padcfg)); | |
1388 | } | |
e57725ea MW |
1389 | |
1390 | padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG2); | |
1391 | if (padcfg) { | |
1392 | val = readl(padcfg); | |
1393 | if (val != pads[i].padcfg2) { | |
1394 | writel(pads[i].padcfg2, padcfg); | |
1395 | dev_dbg(dev, "restored pin %u padcfg2 %#08x\n", | |
1396 | desc->number, readl(padcfg)); | |
1397 | } | |
1398 | } | |
7981c001 MW |
1399 | } |
1400 | ||
1401 | communities = pctrl->context.communities; | |
1402 | for (i = 0; i < pctrl->ncommunities; i++) { | |
1403 | struct intel_community *community = &pctrl->communities[i]; | |
1404 | void __iomem *base; | |
1405 | unsigned gpp; | |
1406 | ||
1407 | base = community->regs + community->ie_offset; | |
1408 | for (gpp = 0; gpp < community->ngpps; gpp++) { | |
1409 | writel(communities[i].intmask[gpp], base + gpp * 4); | |
1410 | dev_dbg(dev, "restored mask %d/%u %#08x\n", i, gpp, | |
1411 | readl(base + gpp * 4)); | |
1412 | } | |
1413 | } | |
1414 | ||
1415 | return 0; | |
1416 | } | |
1417 | EXPORT_SYMBOL_GPL(intel_pinctrl_resume); | |
1418 | #endif | |
1419 | ||
1420 | MODULE_AUTHOR("Mathias Nyman <mathias.nyman@linux.intel.com>"); | |
1421 | MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>"); | |
1422 | MODULE_DESCRIPTION("Intel pinctrl/GPIO core driver"); | |
1423 | MODULE_LICENSE("GPL v2"); |