]>
Commit | Line | Data |
---|---|---|
7981c001 MW |
1 | /* |
2 | * Intel pinctrl/GPIO core driver. | |
3 | * | |
4 | * Copyright (C) 2015, Intel Corporation | |
5 | * Authors: Mathias Nyman <mathias.nyman@linux.intel.com> | |
6 | * Mika Westerberg <mika.westerberg@linux.intel.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #include <linux/module.h> | |
193b40c8 | 14 | #include <linux/interrupt.h> |
7981c001 | 15 | #include <linux/gpio/driver.h> |
e57725ea | 16 | #include <linux/log2.h> |
7981c001 | 17 | #include <linux/platform_device.h> |
7981c001 MW |
18 | #include <linux/pinctrl/pinctrl.h> |
19 | #include <linux/pinctrl/pinmux.h> | |
20 | #include <linux/pinctrl/pinconf.h> | |
21 | #include <linux/pinctrl/pinconf-generic.h> | |
22 | ||
c538b943 | 23 | #include "../core.h" |
7981c001 MW |
24 | #include "pinctrl-intel.h" |
25 | ||
7981c001 | 26 | /* Offset from regs */ |
e57725ea MW |
27 | #define REVID 0x000 |
28 | #define REVID_SHIFT 16 | |
29 | #define REVID_MASK GENMASK(31, 16) | |
30 | ||
7981c001 MW |
31 | #define PADBAR 0x00c |
32 | #define GPI_IS 0x100 | |
33 | #define GPI_GPE_STS 0x140 | |
34 | #define GPI_GPE_EN 0x160 | |
35 | ||
36 | #define PADOWN_BITS 4 | |
37 | #define PADOWN_SHIFT(p) ((p) % 8 * PADOWN_BITS) | |
38 | #define PADOWN_MASK(p) (0xf << PADOWN_SHIFT(p)) | |
99a735b3 | 39 | #define PADOWN_GPP(p) ((p) / 8) |
7981c001 MW |
40 | |
41 | /* Offset from pad_regs */ | |
42 | #define PADCFG0 0x000 | |
43 | #define PADCFG0_RXEVCFG_SHIFT 25 | |
44 | #define PADCFG0_RXEVCFG_MASK (3 << PADCFG0_RXEVCFG_SHIFT) | |
45 | #define PADCFG0_RXEVCFG_LEVEL 0 | |
46 | #define PADCFG0_RXEVCFG_EDGE 1 | |
47 | #define PADCFG0_RXEVCFG_DISABLED 2 | |
48 | #define PADCFG0_RXEVCFG_EDGE_BOTH 3 | |
e57725ea | 49 | #define PADCFG0_PREGFRXSEL BIT(24) |
7981c001 MW |
50 | #define PADCFG0_RXINV BIT(23) |
51 | #define PADCFG0_GPIROUTIOXAPIC BIT(20) | |
52 | #define PADCFG0_GPIROUTSCI BIT(19) | |
53 | #define PADCFG0_GPIROUTSMI BIT(18) | |
54 | #define PADCFG0_GPIROUTNMI BIT(17) | |
55 | #define PADCFG0_PMODE_SHIFT 10 | |
56 | #define PADCFG0_PMODE_MASK (0xf << PADCFG0_PMODE_SHIFT) | |
57 | #define PADCFG0_GPIORXDIS BIT(9) | |
58 | #define PADCFG0_GPIOTXDIS BIT(8) | |
59 | #define PADCFG0_GPIORXSTATE BIT(1) | |
60 | #define PADCFG0_GPIOTXSTATE BIT(0) | |
61 | ||
62 | #define PADCFG1 0x004 | |
63 | #define PADCFG1_TERM_UP BIT(13) | |
64 | #define PADCFG1_TERM_SHIFT 10 | |
65 | #define PADCFG1_TERM_MASK (7 << PADCFG1_TERM_SHIFT) | |
66 | #define PADCFG1_TERM_20K 4 | |
67 | #define PADCFG1_TERM_2K 3 | |
68 | #define PADCFG1_TERM_5K 2 | |
69 | #define PADCFG1_TERM_1K 1 | |
70 | ||
e57725ea MW |
71 | #define PADCFG2 0x008 |
72 | #define PADCFG2_DEBEN BIT(0) | |
73 | #define PADCFG2_DEBOUNCE_SHIFT 1 | |
74 | #define PADCFG2_DEBOUNCE_MASK GENMASK(4, 1) | |
75 | ||
76 | #define DEBOUNCE_PERIOD 31250 /* ns */ | |
77 | ||
7981c001 MW |
78 | struct intel_pad_context { |
79 | u32 padcfg0; | |
80 | u32 padcfg1; | |
e57725ea | 81 | u32 padcfg2; |
7981c001 MW |
82 | }; |
83 | ||
84 | struct intel_community_context { | |
85 | u32 *intmask; | |
86 | }; | |
87 | ||
88 | struct intel_pinctrl_context { | |
89 | struct intel_pad_context *pads; | |
90 | struct intel_community_context *communities; | |
91 | }; | |
92 | ||
93 | /** | |
94 | * struct intel_pinctrl - Intel pinctrl private structure | |
95 | * @dev: Pointer to the device structure | |
96 | * @lock: Lock to serialize register access | |
97 | * @pctldesc: Pin controller description | |
98 | * @pctldev: Pointer to the pin controller device | |
99 | * @chip: GPIO chip in this pin controller | |
100 | * @soc: SoC/PCH specific pin configuration data | |
101 | * @communities: All communities in this pin controller | |
102 | * @ncommunities: Number of communities in this pin controller | |
103 | * @context: Configuration saved over system sleep | |
01dabe91 | 104 | * @irq: pinctrl/GPIO chip irq number |
7981c001 MW |
105 | */ |
106 | struct intel_pinctrl { | |
107 | struct device *dev; | |
27d9098c | 108 | raw_spinlock_t lock; |
7981c001 MW |
109 | struct pinctrl_desc pctldesc; |
110 | struct pinctrl_dev *pctldev; | |
111 | struct gpio_chip chip; | |
112 | const struct intel_pinctrl_soc_data *soc; | |
113 | struct intel_community *communities; | |
114 | size_t ncommunities; | |
115 | struct intel_pinctrl_context context; | |
01dabe91 | 116 | int irq; |
7981c001 MW |
117 | }; |
118 | ||
7981c001 MW |
119 | #define pin_to_padno(c, p) ((p) - (c)->pin_base) |
120 | ||
121 | static struct intel_community *intel_get_community(struct intel_pinctrl *pctrl, | |
122 | unsigned pin) | |
123 | { | |
124 | struct intel_community *community; | |
125 | int i; | |
126 | ||
127 | for (i = 0; i < pctrl->ncommunities; i++) { | |
128 | community = &pctrl->communities[i]; | |
129 | if (pin >= community->pin_base && | |
130 | pin < community->pin_base + community->npins) | |
131 | return community; | |
132 | } | |
133 | ||
134 | dev_warn(pctrl->dev, "failed to find community for pin %u\n", pin); | |
135 | return NULL; | |
136 | } | |
137 | ||
138 | static void __iomem *intel_get_padcfg(struct intel_pinctrl *pctrl, unsigned pin, | |
139 | unsigned reg) | |
140 | { | |
141 | const struct intel_community *community; | |
142 | unsigned padno; | |
e57725ea | 143 | size_t nregs; |
7981c001 MW |
144 | |
145 | community = intel_get_community(pctrl, pin); | |
146 | if (!community) | |
147 | return NULL; | |
148 | ||
149 | padno = pin_to_padno(community, pin); | |
e57725ea MW |
150 | nregs = (community->features & PINCTRL_FEATURE_DEBOUNCE) ? 4 : 2; |
151 | ||
152 | if (reg == PADCFG2 && !(community->features & PINCTRL_FEATURE_DEBOUNCE)) | |
153 | return NULL; | |
154 | ||
155 | return community->pad_regs + reg + padno * nregs * 4; | |
7981c001 MW |
156 | } |
157 | ||
158 | static bool intel_pad_owned_by_host(struct intel_pinctrl *pctrl, unsigned pin) | |
159 | { | |
160 | const struct intel_community *community; | |
99a735b3 | 161 | unsigned padno, gpp, offset, group; |
7981c001 MW |
162 | void __iomem *padown; |
163 | ||
164 | community = intel_get_community(pctrl, pin); | |
165 | if (!community) | |
166 | return false; | |
167 | if (!community->padown_offset) | |
168 | return true; | |
169 | ||
170 | padno = pin_to_padno(community, pin); | |
99a735b3 QZ |
171 | group = padno / community->gpp_size; |
172 | gpp = PADOWN_GPP(padno % community->gpp_size); | |
173 | offset = community->padown_offset + 0x10 * group + gpp * 4; | |
7981c001 MW |
174 | padown = community->regs + offset; |
175 | ||
176 | return !(readl(padown) & PADOWN_MASK(padno)); | |
177 | } | |
178 | ||
4341e8a5 | 179 | static bool intel_pad_acpi_mode(struct intel_pinctrl *pctrl, unsigned pin) |
7981c001 MW |
180 | { |
181 | const struct intel_community *community; | |
182 | unsigned padno, gpp, offset; | |
183 | void __iomem *hostown; | |
184 | ||
185 | community = intel_get_community(pctrl, pin); | |
186 | if (!community) | |
187 | return true; | |
188 | if (!community->hostown_offset) | |
189 | return false; | |
190 | ||
191 | padno = pin_to_padno(community, pin); | |
618a919b | 192 | gpp = padno / community->gpp_size; |
7981c001 MW |
193 | offset = community->hostown_offset + gpp * 4; |
194 | hostown = community->regs + offset; | |
195 | ||
618a919b | 196 | return !(readl(hostown) & BIT(padno % community->gpp_size)); |
7981c001 MW |
197 | } |
198 | ||
199 | static bool intel_pad_locked(struct intel_pinctrl *pctrl, unsigned pin) | |
200 | { | |
201 | struct intel_community *community; | |
202 | unsigned padno, gpp, offset; | |
203 | u32 value; | |
204 | ||
205 | community = intel_get_community(pctrl, pin); | |
206 | if (!community) | |
207 | return true; | |
208 | if (!community->padcfglock_offset) | |
209 | return false; | |
210 | ||
211 | padno = pin_to_padno(community, pin); | |
618a919b | 212 | gpp = padno / community->gpp_size; |
7981c001 MW |
213 | |
214 | /* | |
215 | * If PADCFGLOCK and PADCFGLOCKTX bits are both clear for this pad, | |
216 | * the pad is considered unlocked. Any other case means that it is | |
217 | * either fully or partially locked and we don't touch it. | |
218 | */ | |
219 | offset = community->padcfglock_offset + gpp * 8; | |
220 | value = readl(community->regs + offset); | |
618a919b | 221 | if (value & BIT(pin % community->gpp_size)) |
7981c001 MW |
222 | return true; |
223 | ||
224 | offset = community->padcfglock_offset + 4 + gpp * 8; | |
225 | value = readl(community->regs + offset); | |
618a919b | 226 | if (value & BIT(pin % community->gpp_size)) |
7981c001 MW |
227 | return true; |
228 | ||
229 | return false; | |
230 | } | |
231 | ||
232 | static bool intel_pad_usable(struct intel_pinctrl *pctrl, unsigned pin) | |
233 | { | |
234 | return intel_pad_owned_by_host(pctrl, pin) && | |
7981c001 MW |
235 | !intel_pad_locked(pctrl, pin); |
236 | } | |
237 | ||
238 | static int intel_get_groups_count(struct pinctrl_dev *pctldev) | |
239 | { | |
240 | struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
241 | ||
242 | return pctrl->soc->ngroups; | |
243 | } | |
244 | ||
245 | static const char *intel_get_group_name(struct pinctrl_dev *pctldev, | |
246 | unsigned group) | |
247 | { | |
248 | struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
249 | ||
250 | return pctrl->soc->groups[group].name; | |
251 | } | |
252 | ||
253 | static int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned group, | |
254 | const unsigned **pins, unsigned *npins) | |
255 | { | |
256 | struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
257 | ||
258 | *pins = pctrl->soc->groups[group].pins; | |
259 | *npins = pctrl->soc->groups[group].npins; | |
260 | return 0; | |
261 | } | |
262 | ||
263 | static void intel_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, | |
264 | unsigned pin) | |
265 | { | |
266 | struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
e57725ea | 267 | void __iomem *padcfg; |
7981c001 MW |
268 | u32 cfg0, cfg1, mode; |
269 | bool locked, acpi; | |
270 | ||
271 | if (!intel_pad_owned_by_host(pctrl, pin)) { | |
272 | seq_puts(s, "not available"); | |
273 | return; | |
274 | } | |
275 | ||
276 | cfg0 = readl(intel_get_padcfg(pctrl, pin, PADCFG0)); | |
277 | cfg1 = readl(intel_get_padcfg(pctrl, pin, PADCFG1)); | |
278 | ||
279 | mode = (cfg0 & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT; | |
280 | if (!mode) | |
281 | seq_puts(s, "GPIO "); | |
282 | else | |
283 | seq_printf(s, "mode %d ", mode); | |
284 | ||
285 | seq_printf(s, "0x%08x 0x%08x", cfg0, cfg1); | |
286 | ||
e57725ea MW |
287 | /* Dump the additional PADCFG registers if available */ |
288 | padcfg = intel_get_padcfg(pctrl, pin, PADCFG2); | |
289 | if (padcfg) | |
290 | seq_printf(s, " 0x%08x", readl(padcfg)); | |
291 | ||
7981c001 | 292 | locked = intel_pad_locked(pctrl, pin); |
4341e8a5 | 293 | acpi = intel_pad_acpi_mode(pctrl, pin); |
7981c001 MW |
294 | |
295 | if (locked || acpi) { | |
296 | seq_puts(s, " ["); | |
297 | if (locked) { | |
298 | seq_puts(s, "LOCKED"); | |
299 | if (acpi) | |
300 | seq_puts(s, ", "); | |
301 | } | |
302 | if (acpi) | |
303 | seq_puts(s, "ACPI"); | |
304 | seq_puts(s, "]"); | |
305 | } | |
306 | } | |
307 | ||
308 | static const struct pinctrl_ops intel_pinctrl_ops = { | |
309 | .get_groups_count = intel_get_groups_count, | |
310 | .get_group_name = intel_get_group_name, | |
311 | .get_group_pins = intel_get_group_pins, | |
312 | .pin_dbg_show = intel_pin_dbg_show, | |
313 | }; | |
314 | ||
315 | static int intel_get_functions_count(struct pinctrl_dev *pctldev) | |
316 | { | |
317 | struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
318 | ||
319 | return pctrl->soc->nfunctions; | |
320 | } | |
321 | ||
322 | static const char *intel_get_function_name(struct pinctrl_dev *pctldev, | |
323 | unsigned function) | |
324 | { | |
325 | struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
326 | ||
327 | return pctrl->soc->functions[function].name; | |
328 | } | |
329 | ||
330 | static int intel_get_function_groups(struct pinctrl_dev *pctldev, | |
331 | unsigned function, | |
332 | const char * const **groups, | |
333 | unsigned * const ngroups) | |
334 | { | |
335 | struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
336 | ||
337 | *groups = pctrl->soc->functions[function].groups; | |
338 | *ngroups = pctrl->soc->functions[function].ngroups; | |
339 | return 0; | |
340 | } | |
341 | ||
342 | static int intel_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned function, | |
343 | unsigned group) | |
344 | { | |
345 | struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
346 | const struct intel_pingroup *grp = &pctrl->soc->groups[group]; | |
347 | unsigned long flags; | |
348 | int i; | |
349 | ||
27d9098c | 350 | raw_spin_lock_irqsave(&pctrl->lock, flags); |
7981c001 MW |
351 | |
352 | /* | |
353 | * All pins in the groups needs to be accessible and writable | |
354 | * before we can enable the mux for this group. | |
355 | */ | |
356 | for (i = 0; i < grp->npins; i++) { | |
357 | if (!intel_pad_usable(pctrl, grp->pins[i])) { | |
27d9098c | 358 | raw_spin_unlock_irqrestore(&pctrl->lock, flags); |
7981c001 MW |
359 | return -EBUSY; |
360 | } | |
361 | } | |
362 | ||
363 | /* Now enable the mux setting for each pin in the group */ | |
364 | for (i = 0; i < grp->npins; i++) { | |
365 | void __iomem *padcfg0; | |
366 | u32 value; | |
367 | ||
368 | padcfg0 = intel_get_padcfg(pctrl, grp->pins[i], PADCFG0); | |
369 | value = readl(padcfg0); | |
370 | ||
371 | value &= ~PADCFG0_PMODE_MASK; | |
372 | value |= grp->mode << PADCFG0_PMODE_SHIFT; | |
373 | ||
374 | writel(value, padcfg0); | |
375 | } | |
376 | ||
27d9098c | 377 | raw_spin_unlock_irqrestore(&pctrl->lock, flags); |
7981c001 MW |
378 | |
379 | return 0; | |
380 | } | |
381 | ||
17fab473 AS |
382 | static void __intel_gpio_set_direction(void __iomem *padcfg0, bool input) |
383 | { | |
384 | u32 value; | |
385 | ||
386 | value = readl(padcfg0); | |
387 | if (input) { | |
388 | value &= ~PADCFG0_GPIORXDIS; | |
389 | value |= PADCFG0_GPIOTXDIS; | |
390 | } else { | |
391 | value &= ~PADCFG0_GPIOTXDIS; | |
392 | value |= PADCFG0_GPIORXDIS; | |
393 | } | |
394 | writel(value, padcfg0); | |
395 | } | |
396 | ||
7981c001 MW |
397 | static int intel_gpio_request_enable(struct pinctrl_dev *pctldev, |
398 | struct pinctrl_gpio_range *range, | |
399 | unsigned pin) | |
400 | { | |
401 | struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
402 | void __iomem *padcfg0; | |
403 | unsigned long flags; | |
404 | u32 value; | |
405 | ||
27d9098c | 406 | raw_spin_lock_irqsave(&pctrl->lock, flags); |
7981c001 MW |
407 | |
408 | if (!intel_pad_usable(pctrl, pin)) { | |
27d9098c | 409 | raw_spin_unlock_irqrestore(&pctrl->lock, flags); |
7981c001 MW |
410 | return -EBUSY; |
411 | } | |
412 | ||
413 | padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0); | |
414 | /* Put the pad into GPIO mode */ | |
415 | value = readl(padcfg0) & ~PADCFG0_PMODE_MASK; | |
416 | /* Disable SCI/SMI/NMI generation */ | |
417 | value &= ~(PADCFG0_GPIROUTIOXAPIC | PADCFG0_GPIROUTSCI); | |
418 | value &= ~(PADCFG0_GPIROUTSMI | PADCFG0_GPIROUTNMI); | |
7981c001 MW |
419 | writel(value, padcfg0); |
420 | ||
17fab473 AS |
421 | /* Disable TX buffer and enable RX (this will be input) */ |
422 | __intel_gpio_set_direction(padcfg0, true); | |
423 | ||
27d9098c | 424 | raw_spin_unlock_irqrestore(&pctrl->lock, flags); |
7981c001 MW |
425 | |
426 | return 0; | |
427 | } | |
428 | ||
429 | static int intel_gpio_set_direction(struct pinctrl_dev *pctldev, | |
430 | struct pinctrl_gpio_range *range, | |
431 | unsigned pin, bool input) | |
432 | { | |
433 | struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
434 | void __iomem *padcfg0; | |
435 | unsigned long flags; | |
7981c001 | 436 | |
27d9098c | 437 | raw_spin_lock_irqsave(&pctrl->lock, flags); |
7981c001 MW |
438 | |
439 | padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0); | |
17fab473 | 440 | __intel_gpio_set_direction(padcfg0, input); |
7981c001 | 441 | |
27d9098c | 442 | raw_spin_unlock_irqrestore(&pctrl->lock, flags); |
7981c001 MW |
443 | |
444 | return 0; | |
445 | } | |
446 | ||
447 | static const struct pinmux_ops intel_pinmux_ops = { | |
448 | .get_functions_count = intel_get_functions_count, | |
449 | .get_function_name = intel_get_function_name, | |
450 | .get_function_groups = intel_get_function_groups, | |
451 | .set_mux = intel_pinmux_set_mux, | |
452 | .gpio_request_enable = intel_gpio_request_enable, | |
453 | .gpio_set_direction = intel_gpio_set_direction, | |
454 | }; | |
455 | ||
456 | static int intel_config_get(struct pinctrl_dev *pctldev, unsigned pin, | |
457 | unsigned long *config) | |
458 | { | |
459 | struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
460 | enum pin_config_param param = pinconf_to_config_param(*config); | |
461 | u32 value, term; | |
e57725ea | 462 | u32 arg = 0; |
7981c001 MW |
463 | |
464 | if (!intel_pad_owned_by_host(pctrl, pin)) | |
465 | return -ENOTSUPP; | |
466 | ||
467 | value = readl(intel_get_padcfg(pctrl, pin, PADCFG1)); | |
468 | term = (value & PADCFG1_TERM_MASK) >> PADCFG1_TERM_SHIFT; | |
469 | ||
470 | switch (param) { | |
471 | case PIN_CONFIG_BIAS_DISABLE: | |
472 | if (term) | |
473 | return -EINVAL; | |
474 | break; | |
475 | ||
476 | case PIN_CONFIG_BIAS_PULL_UP: | |
477 | if (!term || !(value & PADCFG1_TERM_UP)) | |
478 | return -EINVAL; | |
479 | ||
480 | switch (term) { | |
481 | case PADCFG1_TERM_1K: | |
482 | arg = 1000; | |
483 | break; | |
484 | case PADCFG1_TERM_2K: | |
485 | arg = 2000; | |
486 | break; | |
487 | case PADCFG1_TERM_5K: | |
488 | arg = 5000; | |
489 | break; | |
490 | case PADCFG1_TERM_20K: | |
491 | arg = 20000; | |
492 | break; | |
493 | } | |
494 | ||
495 | break; | |
496 | ||
497 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
498 | if (!term || value & PADCFG1_TERM_UP) | |
499 | return -EINVAL; | |
500 | ||
501 | switch (term) { | |
502 | case PADCFG1_TERM_5K: | |
503 | arg = 5000; | |
504 | break; | |
505 | case PADCFG1_TERM_20K: | |
506 | arg = 20000; | |
507 | break; | |
508 | } | |
509 | ||
510 | break; | |
511 | ||
e57725ea MW |
512 | case PIN_CONFIG_INPUT_DEBOUNCE: { |
513 | void __iomem *padcfg2; | |
514 | u32 v; | |
515 | ||
516 | padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2); | |
517 | if (!padcfg2) | |
518 | return -ENOTSUPP; | |
519 | ||
520 | v = readl(padcfg2); | |
521 | if (!(v & PADCFG2_DEBEN)) | |
522 | return -EINVAL; | |
523 | ||
524 | v = (v & PADCFG2_DEBOUNCE_MASK) >> PADCFG2_DEBOUNCE_SHIFT; | |
525 | arg = BIT(v) * DEBOUNCE_PERIOD / 1000; | |
526 | ||
527 | break; | |
528 | } | |
529 | ||
7981c001 MW |
530 | default: |
531 | return -ENOTSUPP; | |
532 | } | |
533 | ||
534 | *config = pinconf_to_config_packed(param, arg); | |
535 | return 0; | |
536 | } | |
537 | ||
538 | static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned pin, | |
539 | unsigned long config) | |
540 | { | |
541 | unsigned param = pinconf_to_config_param(config); | |
542 | unsigned arg = pinconf_to_config_argument(config); | |
543 | void __iomem *padcfg1; | |
544 | unsigned long flags; | |
545 | int ret = 0; | |
546 | u32 value; | |
547 | ||
27d9098c | 548 | raw_spin_lock_irqsave(&pctrl->lock, flags); |
7981c001 MW |
549 | |
550 | padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1); | |
551 | value = readl(padcfg1); | |
552 | ||
553 | switch (param) { | |
554 | case PIN_CONFIG_BIAS_DISABLE: | |
555 | value &= ~(PADCFG1_TERM_MASK | PADCFG1_TERM_UP); | |
556 | break; | |
557 | ||
558 | case PIN_CONFIG_BIAS_PULL_UP: | |
559 | value &= ~PADCFG1_TERM_MASK; | |
560 | ||
561 | value |= PADCFG1_TERM_UP; | |
562 | ||
563 | switch (arg) { | |
564 | case 20000: | |
565 | value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT; | |
566 | break; | |
567 | case 5000: | |
568 | value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT; | |
569 | break; | |
570 | case 2000: | |
571 | value |= PADCFG1_TERM_2K << PADCFG1_TERM_SHIFT; | |
572 | break; | |
573 | case 1000: | |
574 | value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT; | |
575 | break; | |
576 | default: | |
577 | ret = -EINVAL; | |
578 | } | |
579 | ||
580 | break; | |
581 | ||
582 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
583 | value &= ~(PADCFG1_TERM_UP | PADCFG1_TERM_MASK); | |
584 | ||
585 | switch (arg) { | |
586 | case 20000: | |
587 | value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT; | |
588 | break; | |
589 | case 5000: | |
590 | value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT; | |
591 | break; | |
592 | default: | |
593 | ret = -EINVAL; | |
594 | } | |
595 | ||
596 | break; | |
597 | } | |
598 | ||
599 | if (!ret) | |
600 | writel(value, padcfg1); | |
601 | ||
27d9098c | 602 | raw_spin_unlock_irqrestore(&pctrl->lock, flags); |
7981c001 MW |
603 | |
604 | return ret; | |
605 | } | |
606 | ||
e57725ea MW |
607 | static int intel_config_set_debounce(struct intel_pinctrl *pctrl, unsigned pin, |
608 | unsigned debounce) | |
609 | { | |
610 | void __iomem *padcfg0, *padcfg2; | |
611 | unsigned long flags; | |
612 | u32 value0, value2; | |
613 | int ret = 0; | |
614 | ||
615 | padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2); | |
616 | if (!padcfg2) | |
617 | return -ENOTSUPP; | |
618 | ||
619 | padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0); | |
620 | ||
621 | raw_spin_lock_irqsave(&pctrl->lock, flags); | |
622 | ||
623 | value0 = readl(padcfg0); | |
624 | value2 = readl(padcfg2); | |
625 | ||
626 | /* Disable glitch filter and debouncer */ | |
627 | value0 &= ~PADCFG0_PREGFRXSEL; | |
628 | value2 &= ~(PADCFG2_DEBEN | PADCFG2_DEBOUNCE_MASK); | |
629 | ||
630 | if (debounce) { | |
631 | unsigned long v; | |
632 | ||
633 | v = order_base_2(debounce * 1000 / DEBOUNCE_PERIOD); | |
634 | if (v < 3 || v > 15) { | |
635 | ret = -EINVAL; | |
636 | goto exit_unlock; | |
637 | } else { | |
638 | /* Enable glitch filter and debouncer */ | |
639 | value0 |= PADCFG0_PREGFRXSEL; | |
640 | value2 |= v << PADCFG2_DEBOUNCE_SHIFT; | |
641 | value2 |= PADCFG2_DEBEN; | |
642 | } | |
643 | } | |
644 | ||
645 | writel(value0, padcfg0); | |
646 | writel(value2, padcfg2); | |
647 | ||
648 | exit_unlock: | |
649 | raw_spin_unlock_irqrestore(&pctrl->lock, flags); | |
650 | ||
651 | return ret; | |
652 | } | |
653 | ||
7981c001 MW |
654 | static int intel_config_set(struct pinctrl_dev *pctldev, unsigned pin, |
655 | unsigned long *configs, unsigned nconfigs) | |
656 | { | |
657 | struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
658 | int i, ret; | |
659 | ||
660 | if (!intel_pad_usable(pctrl, pin)) | |
661 | return -ENOTSUPP; | |
662 | ||
663 | for (i = 0; i < nconfigs; i++) { | |
664 | switch (pinconf_to_config_param(configs[i])) { | |
665 | case PIN_CONFIG_BIAS_DISABLE: | |
666 | case PIN_CONFIG_BIAS_PULL_UP: | |
667 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
668 | ret = intel_config_set_pull(pctrl, pin, configs[i]); | |
669 | if (ret) | |
670 | return ret; | |
671 | break; | |
672 | ||
e57725ea MW |
673 | case PIN_CONFIG_INPUT_DEBOUNCE: |
674 | ret = intel_config_set_debounce(pctrl, pin, | |
675 | pinconf_to_config_argument(configs[i])); | |
676 | if (ret) | |
677 | return ret; | |
678 | break; | |
679 | ||
7981c001 MW |
680 | default: |
681 | return -ENOTSUPP; | |
682 | } | |
683 | } | |
684 | ||
685 | return 0; | |
686 | } | |
687 | ||
688 | static const struct pinconf_ops intel_pinconf_ops = { | |
689 | .is_generic = true, | |
690 | .pin_config_get = intel_config_get, | |
691 | .pin_config_set = intel_config_set, | |
692 | }; | |
693 | ||
694 | static const struct pinctrl_desc intel_pinctrl_desc = { | |
695 | .pctlops = &intel_pinctrl_ops, | |
696 | .pmxops = &intel_pinmux_ops, | |
697 | .confops = &intel_pinconf_ops, | |
698 | .owner = THIS_MODULE, | |
699 | }; | |
700 | ||
7981c001 MW |
701 | static int intel_gpio_get(struct gpio_chip *chip, unsigned offset) |
702 | { | |
acfd4c63 | 703 | struct intel_pinctrl *pctrl = gpiochip_get_data(chip); |
7981c001 MW |
704 | void __iomem *reg; |
705 | ||
706 | reg = intel_get_padcfg(pctrl, offset, PADCFG0); | |
707 | if (!reg) | |
708 | return -EINVAL; | |
709 | ||
710 | return !!(readl(reg) & PADCFG0_GPIORXSTATE); | |
711 | } | |
712 | ||
713 | static void intel_gpio_set(struct gpio_chip *chip, unsigned offset, int value) | |
714 | { | |
acfd4c63 | 715 | struct intel_pinctrl *pctrl = gpiochip_get_data(chip); |
7981c001 MW |
716 | void __iomem *reg; |
717 | ||
718 | reg = intel_get_padcfg(pctrl, offset, PADCFG0); | |
719 | if (reg) { | |
720 | unsigned long flags; | |
721 | u32 padcfg0; | |
722 | ||
27d9098c | 723 | raw_spin_lock_irqsave(&pctrl->lock, flags); |
7981c001 MW |
724 | padcfg0 = readl(reg); |
725 | if (value) | |
726 | padcfg0 |= PADCFG0_GPIOTXSTATE; | |
727 | else | |
728 | padcfg0 &= ~PADCFG0_GPIOTXSTATE; | |
729 | writel(padcfg0, reg); | |
27d9098c | 730 | raw_spin_unlock_irqrestore(&pctrl->lock, flags); |
7981c001 MW |
731 | } |
732 | } | |
733 | ||
734 | static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned offset) | |
735 | { | |
736 | return pinctrl_gpio_direction_input(chip->base + offset); | |
737 | } | |
738 | ||
739 | static int intel_gpio_direction_output(struct gpio_chip *chip, unsigned offset, | |
740 | int value) | |
741 | { | |
742 | intel_gpio_set(chip, offset, value); | |
743 | return pinctrl_gpio_direction_output(chip->base + offset); | |
744 | } | |
745 | ||
746 | static const struct gpio_chip intel_gpio_chip = { | |
747 | .owner = THIS_MODULE, | |
98c85d58 JG |
748 | .request = gpiochip_generic_request, |
749 | .free = gpiochip_generic_free, | |
7981c001 MW |
750 | .direction_input = intel_gpio_direction_input, |
751 | .direction_output = intel_gpio_direction_output, | |
752 | .get = intel_gpio_get, | |
753 | .set = intel_gpio_set, | |
e57725ea | 754 | .set_config = gpiochip_generic_config, |
7981c001 MW |
755 | }; |
756 | ||
757 | static void intel_gpio_irq_ack(struct irq_data *d) | |
758 | { | |
759 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); | |
acfd4c63 | 760 | struct intel_pinctrl *pctrl = gpiochip_get_data(gc); |
7981c001 MW |
761 | const struct intel_community *community; |
762 | unsigned pin = irqd_to_hwirq(d); | |
763 | ||
27d9098c | 764 | raw_spin_lock(&pctrl->lock); |
7981c001 MW |
765 | |
766 | community = intel_get_community(pctrl, pin); | |
767 | if (community) { | |
768 | unsigned padno = pin_to_padno(community, pin); | |
618a919b QZ |
769 | unsigned gpp_offset = padno % community->gpp_size; |
770 | unsigned gpp = padno / community->gpp_size; | |
7981c001 MW |
771 | |
772 | writel(BIT(gpp_offset), community->regs + GPI_IS + gpp * 4); | |
773 | } | |
774 | ||
27d9098c | 775 | raw_spin_unlock(&pctrl->lock); |
7981c001 MW |
776 | } |
777 | ||
a939bb57 QZ |
778 | static void intel_gpio_irq_enable(struct irq_data *d) |
779 | { | |
780 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); | |
781 | struct intel_pinctrl *pctrl = gpiochip_get_data(gc); | |
782 | const struct intel_community *community; | |
783 | unsigned pin = irqd_to_hwirq(d); | |
784 | unsigned long flags; | |
785 | ||
27d9098c | 786 | raw_spin_lock_irqsave(&pctrl->lock, flags); |
a939bb57 QZ |
787 | |
788 | community = intel_get_community(pctrl, pin); | |
789 | if (community) { | |
790 | unsigned padno = pin_to_padno(community, pin); | |
791 | unsigned gpp_size = community->gpp_size; | |
792 | unsigned gpp_offset = padno % gpp_size; | |
793 | unsigned gpp = padno / gpp_size; | |
794 | u32 value; | |
795 | ||
796 | /* Clear interrupt status first to avoid unexpected interrupt */ | |
797 | writel(BIT(gpp_offset), community->regs + GPI_IS + gpp * 4); | |
798 | ||
799 | value = readl(community->regs + community->ie_offset + gpp * 4); | |
800 | value |= BIT(gpp_offset); | |
801 | writel(value, community->regs + community->ie_offset + gpp * 4); | |
802 | } | |
803 | ||
27d9098c | 804 | raw_spin_unlock_irqrestore(&pctrl->lock, flags); |
a939bb57 QZ |
805 | } |
806 | ||
7981c001 MW |
807 | static void intel_gpio_irq_mask_unmask(struct irq_data *d, bool mask) |
808 | { | |
809 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); | |
acfd4c63 | 810 | struct intel_pinctrl *pctrl = gpiochip_get_data(gc); |
7981c001 MW |
811 | const struct intel_community *community; |
812 | unsigned pin = irqd_to_hwirq(d); | |
813 | unsigned long flags; | |
814 | ||
27d9098c | 815 | raw_spin_lock_irqsave(&pctrl->lock, flags); |
7981c001 MW |
816 | |
817 | community = intel_get_community(pctrl, pin); | |
818 | if (community) { | |
819 | unsigned padno = pin_to_padno(community, pin); | |
618a919b QZ |
820 | unsigned gpp_offset = padno % community->gpp_size; |
821 | unsigned gpp = padno / community->gpp_size; | |
7981c001 MW |
822 | void __iomem *reg; |
823 | u32 value; | |
824 | ||
825 | reg = community->regs + community->ie_offset + gpp * 4; | |
826 | value = readl(reg); | |
827 | if (mask) | |
828 | value &= ~BIT(gpp_offset); | |
829 | else | |
830 | value |= BIT(gpp_offset); | |
831 | writel(value, reg); | |
832 | } | |
833 | ||
27d9098c | 834 | raw_spin_unlock_irqrestore(&pctrl->lock, flags); |
7981c001 MW |
835 | } |
836 | ||
837 | static void intel_gpio_irq_mask(struct irq_data *d) | |
838 | { | |
839 | intel_gpio_irq_mask_unmask(d, true); | |
840 | } | |
841 | ||
842 | static void intel_gpio_irq_unmask(struct irq_data *d) | |
843 | { | |
844 | intel_gpio_irq_mask_unmask(d, false); | |
845 | } | |
846 | ||
847 | static int intel_gpio_irq_type(struct irq_data *d, unsigned type) | |
848 | { | |
849 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); | |
acfd4c63 | 850 | struct intel_pinctrl *pctrl = gpiochip_get_data(gc); |
7981c001 MW |
851 | unsigned pin = irqd_to_hwirq(d); |
852 | unsigned long flags; | |
853 | void __iomem *reg; | |
854 | u32 value; | |
855 | ||
856 | reg = intel_get_padcfg(pctrl, pin, PADCFG0); | |
857 | if (!reg) | |
858 | return -EINVAL; | |
859 | ||
4341e8a5 MW |
860 | /* |
861 | * If the pin is in ACPI mode it is still usable as a GPIO but it | |
862 | * cannot be used as IRQ because GPI_IS status bit will not be | |
863 | * updated by the host controller hardware. | |
864 | */ | |
865 | if (intel_pad_acpi_mode(pctrl, pin)) { | |
866 | dev_warn(pctrl->dev, "pin %u cannot be used as IRQ\n", pin); | |
867 | return -EPERM; | |
868 | } | |
869 | ||
27d9098c | 870 | raw_spin_lock_irqsave(&pctrl->lock, flags); |
7981c001 MW |
871 | |
872 | value = readl(reg); | |
873 | ||
874 | value &= ~(PADCFG0_RXEVCFG_MASK | PADCFG0_RXINV); | |
875 | ||
876 | if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) { | |
877 | value |= PADCFG0_RXEVCFG_EDGE_BOTH << PADCFG0_RXEVCFG_SHIFT; | |
878 | } else if (type & IRQ_TYPE_EDGE_FALLING) { | |
879 | value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT; | |
880 | value |= PADCFG0_RXINV; | |
881 | } else if (type & IRQ_TYPE_EDGE_RISING) { | |
882 | value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT; | |
bf380cfa QZ |
883 | } else if (type & IRQ_TYPE_LEVEL_MASK) { |
884 | if (type & IRQ_TYPE_LEVEL_LOW) | |
885 | value |= PADCFG0_RXINV; | |
7981c001 MW |
886 | } else { |
887 | value |= PADCFG0_RXEVCFG_DISABLED << PADCFG0_RXEVCFG_SHIFT; | |
888 | } | |
889 | ||
890 | writel(value, reg); | |
891 | ||
892 | if (type & IRQ_TYPE_EDGE_BOTH) | |
fc756bcd | 893 | irq_set_handler_locked(d, handle_edge_irq); |
7981c001 | 894 | else if (type & IRQ_TYPE_LEVEL_MASK) |
fc756bcd | 895 | irq_set_handler_locked(d, handle_level_irq); |
7981c001 | 896 | |
27d9098c | 897 | raw_spin_unlock_irqrestore(&pctrl->lock, flags); |
7981c001 MW |
898 | |
899 | return 0; | |
900 | } | |
901 | ||
902 | static int intel_gpio_irq_wake(struct irq_data *d, unsigned int on) | |
903 | { | |
904 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); | |
acfd4c63 | 905 | struct intel_pinctrl *pctrl = gpiochip_get_data(gc); |
7981c001 | 906 | unsigned pin = irqd_to_hwirq(d); |
9a520fd9 | 907 | |
7981c001 | 908 | if (on) |
01dabe91 | 909 | enable_irq_wake(pctrl->irq); |
7981c001 | 910 | else |
01dabe91 | 911 | disable_irq_wake(pctrl->irq); |
9a520fd9 | 912 | |
7981c001 MW |
913 | dev_dbg(pctrl->dev, "%sable wake for pin %u\n", on ? "en" : "dis", pin); |
914 | return 0; | |
915 | } | |
916 | ||
193b40c8 | 917 | static irqreturn_t intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl, |
7981c001 MW |
918 | const struct intel_community *community) |
919 | { | |
193b40c8 MW |
920 | struct gpio_chip *gc = &pctrl->chip; |
921 | irqreturn_t ret = IRQ_NONE; | |
7981c001 MW |
922 | int gpp; |
923 | ||
924 | for (gpp = 0; gpp < community->ngpps; gpp++) { | |
925 | unsigned long pending, enabled, gpp_offset; | |
926 | ||
927 | pending = readl(community->regs + GPI_IS + gpp * 4); | |
928 | enabled = readl(community->regs + community->ie_offset + | |
929 | gpp * 4); | |
930 | ||
931 | /* Only interrupts that are enabled */ | |
932 | pending &= enabled; | |
933 | ||
618a919b | 934 | for_each_set_bit(gpp_offset, &pending, community->gpp_size) { |
7981c001 MW |
935 | unsigned padno, irq; |
936 | ||
937 | /* | |
938 | * The last group in community can have less pins | |
939 | * than NPADS_IN_GPP. | |
940 | */ | |
618a919b | 941 | padno = gpp_offset + gpp * community->gpp_size; |
7981c001 MW |
942 | if (padno >= community->npins) |
943 | break; | |
944 | ||
945 | irq = irq_find_mapping(gc->irqdomain, | |
946 | community->pin_base + padno); | |
947 | generic_handle_irq(irq); | |
193b40c8 MW |
948 | |
949 | ret |= IRQ_HANDLED; | |
7981c001 MW |
950 | } |
951 | } | |
193b40c8 MW |
952 | |
953 | return ret; | |
7981c001 MW |
954 | } |
955 | ||
193b40c8 | 956 | static irqreturn_t intel_gpio_irq(int irq, void *data) |
7981c001 | 957 | { |
193b40c8 MW |
958 | const struct intel_community *community; |
959 | struct intel_pinctrl *pctrl = data; | |
960 | irqreturn_t ret = IRQ_NONE; | |
7981c001 MW |
961 | int i; |
962 | ||
7981c001 | 963 | /* Need to check all communities for pending interrupts */ |
193b40c8 MW |
964 | for (i = 0; i < pctrl->ncommunities; i++) { |
965 | community = &pctrl->communities[i]; | |
966 | ret |= intel_gpio_community_irq_handler(pctrl, community); | |
967 | } | |
7981c001 | 968 | |
193b40c8 | 969 | return ret; |
7981c001 MW |
970 | } |
971 | ||
972 | static struct irq_chip intel_gpio_irqchip = { | |
973 | .name = "intel-gpio", | |
a939bb57 | 974 | .irq_enable = intel_gpio_irq_enable, |
7981c001 MW |
975 | .irq_ack = intel_gpio_irq_ack, |
976 | .irq_mask = intel_gpio_irq_mask, | |
977 | .irq_unmask = intel_gpio_irq_unmask, | |
978 | .irq_set_type = intel_gpio_irq_type, | |
979 | .irq_set_wake = intel_gpio_irq_wake, | |
980 | }; | |
981 | ||
7981c001 MW |
982 | static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq) |
983 | { | |
984 | int ret; | |
985 | ||
986 | pctrl->chip = intel_gpio_chip; | |
987 | ||
988 | pctrl->chip.ngpio = pctrl->soc->npins; | |
989 | pctrl->chip.label = dev_name(pctrl->dev); | |
58383c78 | 990 | pctrl->chip.parent = pctrl->dev; |
7981c001 | 991 | pctrl->chip.base = -1; |
01dabe91 | 992 | pctrl->irq = irq; |
7981c001 | 993 | |
f25c3aa9 | 994 | ret = devm_gpiochip_add_data(pctrl->dev, &pctrl->chip, pctrl); |
7981c001 MW |
995 | if (ret) { |
996 | dev_err(pctrl->dev, "failed to register gpiochip\n"); | |
997 | return ret; | |
998 | } | |
999 | ||
1000 | ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), | |
1001 | 0, 0, pctrl->soc->npins); | |
1002 | if (ret) { | |
1003 | dev_err(pctrl->dev, "failed to add GPIO pin range\n"); | |
f25c3aa9 | 1004 | return ret; |
193b40c8 MW |
1005 | } |
1006 | ||
1007 | /* | |
1008 | * We need to request the interrupt here (instead of providing chip | |
1009 | * to the irq directly) because on some platforms several GPIO | |
1010 | * controllers share the same interrupt line. | |
1011 | */ | |
1a7d1cb8 MW |
1012 | ret = devm_request_irq(pctrl->dev, irq, intel_gpio_irq, |
1013 | IRQF_SHARED | IRQF_NO_THREAD, | |
193b40c8 MW |
1014 | dev_name(pctrl->dev), pctrl); |
1015 | if (ret) { | |
1016 | dev_err(pctrl->dev, "failed to request interrupt\n"); | |
f25c3aa9 | 1017 | return ret; |
7981c001 MW |
1018 | } |
1019 | ||
1020 | ret = gpiochip_irqchip_add(&pctrl->chip, &intel_gpio_irqchip, 0, | |
3ae02c14 | 1021 | handle_bad_irq, IRQ_TYPE_NONE); |
7981c001 MW |
1022 | if (ret) { |
1023 | dev_err(pctrl->dev, "failed to add irqchip\n"); | |
f25c3aa9 | 1024 | return ret; |
7981c001 MW |
1025 | } |
1026 | ||
1027 | gpiochip_set_chained_irqchip(&pctrl->chip, &intel_gpio_irqchip, irq, | |
193b40c8 | 1028 | NULL); |
7981c001 MW |
1029 | return 0; |
1030 | } | |
1031 | ||
1032 | static int intel_pinctrl_pm_init(struct intel_pinctrl *pctrl) | |
1033 | { | |
1034 | #ifdef CONFIG_PM_SLEEP | |
1035 | const struct intel_pinctrl_soc_data *soc = pctrl->soc; | |
1036 | struct intel_community_context *communities; | |
1037 | struct intel_pad_context *pads; | |
1038 | int i; | |
1039 | ||
1040 | pads = devm_kcalloc(pctrl->dev, soc->npins, sizeof(*pads), GFP_KERNEL); | |
1041 | if (!pads) | |
1042 | return -ENOMEM; | |
1043 | ||
1044 | communities = devm_kcalloc(pctrl->dev, pctrl->ncommunities, | |
1045 | sizeof(*communities), GFP_KERNEL); | |
1046 | if (!communities) | |
1047 | return -ENOMEM; | |
1048 | ||
1049 | ||
1050 | for (i = 0; i < pctrl->ncommunities; i++) { | |
1051 | struct intel_community *community = &pctrl->communities[i]; | |
1052 | u32 *intmask; | |
1053 | ||
1054 | intmask = devm_kcalloc(pctrl->dev, community->ngpps, | |
1055 | sizeof(*intmask), GFP_KERNEL); | |
1056 | if (!intmask) | |
1057 | return -ENOMEM; | |
1058 | ||
1059 | communities[i].intmask = intmask; | |
1060 | } | |
1061 | ||
1062 | pctrl->context.pads = pads; | |
1063 | pctrl->context.communities = communities; | |
1064 | #endif | |
1065 | ||
1066 | return 0; | |
1067 | } | |
1068 | ||
1069 | int intel_pinctrl_probe(struct platform_device *pdev, | |
1070 | const struct intel_pinctrl_soc_data *soc_data) | |
1071 | { | |
1072 | struct intel_pinctrl *pctrl; | |
1073 | int i, ret, irq; | |
1074 | ||
1075 | if (!soc_data) | |
1076 | return -EINVAL; | |
1077 | ||
1078 | pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); | |
1079 | if (!pctrl) | |
1080 | return -ENOMEM; | |
1081 | ||
1082 | pctrl->dev = &pdev->dev; | |
1083 | pctrl->soc = soc_data; | |
27d9098c | 1084 | raw_spin_lock_init(&pctrl->lock); |
7981c001 MW |
1085 | |
1086 | /* | |
1087 | * Make a copy of the communities which we can use to hold pointers | |
1088 | * to the registers. | |
1089 | */ | |
1090 | pctrl->ncommunities = pctrl->soc->ncommunities; | |
1091 | pctrl->communities = devm_kcalloc(&pdev->dev, pctrl->ncommunities, | |
1092 | sizeof(*pctrl->communities), GFP_KERNEL); | |
1093 | if (!pctrl->communities) | |
1094 | return -ENOMEM; | |
1095 | ||
1096 | for (i = 0; i < pctrl->ncommunities; i++) { | |
1097 | struct intel_community *community = &pctrl->communities[i]; | |
1098 | struct resource *res; | |
1099 | void __iomem *regs; | |
1100 | u32 padbar; | |
1101 | ||
1102 | *community = pctrl->soc->communities[i]; | |
1103 | ||
1104 | res = platform_get_resource(pdev, IORESOURCE_MEM, | |
1105 | community->barno); | |
1106 | regs = devm_ioremap_resource(&pdev->dev, res); | |
1107 | if (IS_ERR(regs)) | |
1108 | return PTR_ERR(regs); | |
1109 | ||
e57725ea MW |
1110 | /* |
1111 | * Determine community features based on the revision if | |
1112 | * not specified already. | |
1113 | */ | |
1114 | if (!community->features) { | |
1115 | u32 rev; | |
1116 | ||
1117 | rev = (readl(regs + REVID) & REVID_MASK) >> REVID_SHIFT; | |
1118 | if (rev >= 0x94) | |
1119 | community->features |= PINCTRL_FEATURE_DEBOUNCE; | |
1120 | } | |
1121 | ||
7981c001 MW |
1122 | /* Read offset of the pad configuration registers */ |
1123 | padbar = readl(regs + PADBAR); | |
1124 | ||
1125 | community->regs = regs; | |
1126 | community->pad_regs = regs + padbar; | |
618a919b QZ |
1127 | community->ngpps = DIV_ROUND_UP(community->npins, |
1128 | community->gpp_size); | |
7981c001 MW |
1129 | } |
1130 | ||
1131 | irq = platform_get_irq(pdev, 0); | |
1132 | if (irq < 0) { | |
1133 | dev_err(&pdev->dev, "failed to get interrupt number\n"); | |
1134 | return irq; | |
1135 | } | |
1136 | ||
1137 | ret = intel_pinctrl_pm_init(pctrl); | |
1138 | if (ret) | |
1139 | return ret; | |
1140 | ||
1141 | pctrl->pctldesc = intel_pinctrl_desc; | |
1142 | pctrl->pctldesc.name = dev_name(&pdev->dev); | |
1143 | pctrl->pctldesc.pins = pctrl->soc->pins; | |
1144 | pctrl->pctldesc.npins = pctrl->soc->npins; | |
1145 | ||
54d46cd7 LD |
1146 | pctrl->pctldev = devm_pinctrl_register(&pdev->dev, &pctrl->pctldesc, |
1147 | pctrl); | |
323de9ef | 1148 | if (IS_ERR(pctrl->pctldev)) { |
7981c001 | 1149 | dev_err(&pdev->dev, "failed to register pinctrl driver\n"); |
323de9ef | 1150 | return PTR_ERR(pctrl->pctldev); |
7981c001 MW |
1151 | } |
1152 | ||
1153 | ret = intel_gpio_probe(pctrl, irq); | |
54d46cd7 | 1154 | if (ret) |
7981c001 | 1155 | return ret; |
7981c001 MW |
1156 | |
1157 | platform_set_drvdata(pdev, pctrl); | |
1158 | ||
1159 | return 0; | |
1160 | } | |
1161 | EXPORT_SYMBOL_GPL(intel_pinctrl_probe); | |
1162 | ||
7981c001 | 1163 | #ifdef CONFIG_PM_SLEEP |
c538b943 MW |
1164 | static bool intel_pinctrl_should_save(struct intel_pinctrl *pctrl, unsigned pin) |
1165 | { | |
1166 | const struct pin_desc *pd = pin_desc_get(pctrl->pctldev, pin); | |
1167 | ||
1168 | if (!pd || !intel_pad_usable(pctrl, pin)) | |
1169 | return false; | |
1170 | ||
1171 | /* | |
1172 | * Only restore the pin if it is actually in use by the kernel (or | |
1173 | * by userspace). It is possible that some pins are used by the | |
1174 | * BIOS during resume and those are not always locked down so leave | |
1175 | * them alone. | |
1176 | */ | |
1177 | if (pd->mux_owner || pd->gpio_owner || | |
1178 | gpiochip_line_is_irq(&pctrl->chip, pin)) | |
1179 | return true; | |
1180 | ||
1181 | return false; | |
1182 | } | |
1183 | ||
7981c001 MW |
1184 | int intel_pinctrl_suspend(struct device *dev) |
1185 | { | |
1186 | struct platform_device *pdev = to_platform_device(dev); | |
1187 | struct intel_pinctrl *pctrl = platform_get_drvdata(pdev); | |
1188 | struct intel_community_context *communities; | |
1189 | struct intel_pad_context *pads; | |
1190 | int i; | |
1191 | ||
1192 | pads = pctrl->context.pads; | |
1193 | for (i = 0; i < pctrl->soc->npins; i++) { | |
1194 | const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i]; | |
e57725ea | 1195 | void __iomem *padcfg; |
7981c001 MW |
1196 | u32 val; |
1197 | ||
c538b943 | 1198 | if (!intel_pinctrl_should_save(pctrl, desc->number)) |
7981c001 MW |
1199 | continue; |
1200 | ||
1201 | val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG0)); | |
1202 | pads[i].padcfg0 = val & ~PADCFG0_GPIORXSTATE; | |
1203 | val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG1)); | |
1204 | pads[i].padcfg1 = val; | |
e57725ea MW |
1205 | |
1206 | padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG2); | |
1207 | if (padcfg) | |
1208 | pads[i].padcfg2 = readl(padcfg); | |
7981c001 MW |
1209 | } |
1210 | ||
1211 | communities = pctrl->context.communities; | |
1212 | for (i = 0; i < pctrl->ncommunities; i++) { | |
1213 | struct intel_community *community = &pctrl->communities[i]; | |
1214 | void __iomem *base; | |
1215 | unsigned gpp; | |
1216 | ||
1217 | base = community->regs + community->ie_offset; | |
1218 | for (gpp = 0; gpp < community->ngpps; gpp++) | |
1219 | communities[i].intmask[gpp] = readl(base + gpp * 4); | |
1220 | } | |
1221 | ||
1222 | return 0; | |
1223 | } | |
1224 | EXPORT_SYMBOL_GPL(intel_pinctrl_suspend); | |
1225 | ||
f487bbf3 MW |
1226 | static void intel_gpio_irq_init(struct intel_pinctrl *pctrl) |
1227 | { | |
1228 | size_t i; | |
1229 | ||
1230 | for (i = 0; i < pctrl->ncommunities; i++) { | |
1231 | const struct intel_community *community; | |
1232 | void __iomem *base; | |
1233 | unsigned gpp; | |
1234 | ||
1235 | community = &pctrl->communities[i]; | |
1236 | base = community->regs; | |
1237 | ||
1238 | for (gpp = 0; gpp < community->ngpps; gpp++) { | |
1239 | /* Mask and clear all interrupts */ | |
1240 | writel(0, base + community->ie_offset + gpp * 4); | |
1241 | writel(0xffff, base + GPI_IS + gpp * 4); | |
1242 | } | |
1243 | } | |
1244 | } | |
1245 | ||
7981c001 MW |
1246 | int intel_pinctrl_resume(struct device *dev) |
1247 | { | |
1248 | struct platform_device *pdev = to_platform_device(dev); | |
1249 | struct intel_pinctrl *pctrl = platform_get_drvdata(pdev); | |
1250 | const struct intel_community_context *communities; | |
1251 | const struct intel_pad_context *pads; | |
1252 | int i; | |
1253 | ||
1254 | /* Mask all interrupts */ | |
1255 | intel_gpio_irq_init(pctrl); | |
1256 | ||
1257 | pads = pctrl->context.pads; | |
1258 | for (i = 0; i < pctrl->soc->npins; i++) { | |
1259 | const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i]; | |
1260 | void __iomem *padcfg; | |
1261 | u32 val; | |
1262 | ||
c538b943 | 1263 | if (!intel_pinctrl_should_save(pctrl, desc->number)) |
7981c001 MW |
1264 | continue; |
1265 | ||
1266 | padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG0); | |
1267 | val = readl(padcfg) & ~PADCFG0_GPIORXSTATE; | |
1268 | if (val != pads[i].padcfg0) { | |
1269 | writel(pads[i].padcfg0, padcfg); | |
1270 | dev_dbg(dev, "restored pin %u padcfg0 %#08x\n", | |
1271 | desc->number, readl(padcfg)); | |
1272 | } | |
1273 | ||
1274 | padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG1); | |
1275 | val = readl(padcfg); | |
1276 | if (val != pads[i].padcfg1) { | |
1277 | writel(pads[i].padcfg1, padcfg); | |
1278 | dev_dbg(dev, "restored pin %u padcfg1 %#08x\n", | |
1279 | desc->number, readl(padcfg)); | |
1280 | } | |
e57725ea MW |
1281 | |
1282 | padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG2); | |
1283 | if (padcfg) { | |
1284 | val = readl(padcfg); | |
1285 | if (val != pads[i].padcfg2) { | |
1286 | writel(pads[i].padcfg2, padcfg); | |
1287 | dev_dbg(dev, "restored pin %u padcfg2 %#08x\n", | |
1288 | desc->number, readl(padcfg)); | |
1289 | } | |
1290 | } | |
7981c001 MW |
1291 | } |
1292 | ||
1293 | communities = pctrl->context.communities; | |
1294 | for (i = 0; i < pctrl->ncommunities; i++) { | |
1295 | struct intel_community *community = &pctrl->communities[i]; | |
1296 | void __iomem *base; | |
1297 | unsigned gpp; | |
1298 | ||
1299 | base = community->regs + community->ie_offset; | |
1300 | for (gpp = 0; gpp < community->ngpps; gpp++) { | |
1301 | writel(communities[i].intmask[gpp], base + gpp * 4); | |
1302 | dev_dbg(dev, "restored mask %d/%u %#08x\n", i, gpp, | |
1303 | readl(base + gpp * 4)); | |
1304 | } | |
1305 | } | |
1306 | ||
1307 | return 0; | |
1308 | } | |
1309 | EXPORT_SYMBOL_GPL(intel_pinctrl_resume); | |
1310 | #endif | |
1311 | ||
1312 | MODULE_AUTHOR("Mathias Nyman <mathias.nyman@linux.intel.com>"); | |
1313 | MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>"); | |
1314 | MODULE_DESCRIPTION("Intel pinctrl/GPIO core driver"); | |
1315 | MODULE_LICENSE("GPL v2"); |