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875a92b3 | 1 | // SPDX-License-Identifier: GPL-2.0 |
7981c001 MW |
2 | /* |
3 | * Intel pinctrl/GPIO core driver. | |
4 | * | |
5 | * Copyright (C) 2015, Intel Corporation | |
6 | * Authors: Mathias Nyman <mathias.nyman@linux.intel.com> | |
7 | * Mika Westerberg <mika.westerberg@linux.intel.com> | |
7981c001 MW |
8 | */ |
9 | ||
924cf800 | 10 | #include <linux/acpi.h> |
7981c001 | 11 | #include <linux/module.h> |
193b40c8 | 12 | #include <linux/interrupt.h> |
7981c001 | 13 | #include <linux/gpio/driver.h> |
e57725ea | 14 | #include <linux/log2.h> |
7981c001 | 15 | #include <linux/platform_device.h> |
924cf800 AS |
16 | #include <linux/property.h> |
17 | ||
7981c001 MW |
18 | #include <linux/pinctrl/pinctrl.h> |
19 | #include <linux/pinctrl/pinmux.h> | |
20 | #include <linux/pinctrl/pinconf.h> | |
21 | #include <linux/pinctrl/pinconf-generic.h> | |
22 | ||
c538b943 | 23 | #include "../core.h" |
7981c001 MW |
24 | #include "pinctrl-intel.h" |
25 | ||
7981c001 | 26 | /* Offset from regs */ |
e57725ea MW |
27 | #define REVID 0x000 |
28 | #define REVID_SHIFT 16 | |
29 | #define REVID_MASK GENMASK(31, 16) | |
30 | ||
7981c001 MW |
31 | #define PADBAR 0x00c |
32 | #define GPI_IS 0x100 | |
7981c001 MW |
33 | |
34 | #define PADOWN_BITS 4 | |
35 | #define PADOWN_SHIFT(p) ((p) % 8 * PADOWN_BITS) | |
e58926e7 | 36 | #define PADOWN_MASK(p) (GENMASK(3, 0) << PADOWN_SHIFT(p)) |
99a735b3 | 37 | #define PADOWN_GPP(p) ((p) / 8) |
7981c001 MW |
38 | |
39 | /* Offset from pad_regs */ | |
40 | #define PADCFG0 0x000 | |
41 | #define PADCFG0_RXEVCFG_SHIFT 25 | |
e58926e7 | 42 | #define PADCFG0_RXEVCFG_MASK GENMASK(26, 25) |
7981c001 MW |
43 | #define PADCFG0_RXEVCFG_LEVEL 0 |
44 | #define PADCFG0_RXEVCFG_EDGE 1 | |
45 | #define PADCFG0_RXEVCFG_DISABLED 2 | |
46 | #define PADCFG0_RXEVCFG_EDGE_BOTH 3 | |
e57725ea | 47 | #define PADCFG0_PREGFRXSEL BIT(24) |
7981c001 MW |
48 | #define PADCFG0_RXINV BIT(23) |
49 | #define PADCFG0_GPIROUTIOXAPIC BIT(20) | |
50 | #define PADCFG0_GPIROUTSCI BIT(19) | |
51 | #define PADCFG0_GPIROUTSMI BIT(18) | |
52 | #define PADCFG0_GPIROUTNMI BIT(17) | |
53 | #define PADCFG0_PMODE_SHIFT 10 | |
e58926e7 | 54 | #define PADCFG0_PMODE_MASK GENMASK(13, 10) |
7981c001 MW |
55 | #define PADCFG0_GPIORXDIS BIT(9) |
56 | #define PADCFG0_GPIOTXDIS BIT(8) | |
57 | #define PADCFG0_GPIORXSTATE BIT(1) | |
58 | #define PADCFG0_GPIOTXSTATE BIT(0) | |
59 | ||
60 | #define PADCFG1 0x004 | |
61 | #define PADCFG1_TERM_UP BIT(13) | |
62 | #define PADCFG1_TERM_SHIFT 10 | |
e58926e7 | 63 | #define PADCFG1_TERM_MASK GENMASK(12, 10) |
7981c001 MW |
64 | #define PADCFG1_TERM_20K 4 |
65 | #define PADCFG1_TERM_2K 3 | |
66 | #define PADCFG1_TERM_5K 2 | |
67 | #define PADCFG1_TERM_1K 1 | |
68 | ||
e57725ea MW |
69 | #define PADCFG2 0x008 |
70 | #define PADCFG2_DEBEN BIT(0) | |
71 | #define PADCFG2_DEBOUNCE_SHIFT 1 | |
72 | #define PADCFG2_DEBOUNCE_MASK GENMASK(4, 1) | |
73 | ||
74 | #define DEBOUNCE_PERIOD 31250 /* ns */ | |
75 | ||
7981c001 MW |
76 | struct intel_pad_context { |
77 | u32 padcfg0; | |
78 | u32 padcfg1; | |
e57725ea | 79 | u32 padcfg2; |
7981c001 MW |
80 | }; |
81 | ||
82 | struct intel_community_context { | |
83 | u32 *intmask; | |
a0a5f766 | 84 | u32 *hostown; |
7981c001 MW |
85 | }; |
86 | ||
87 | struct intel_pinctrl_context { | |
88 | struct intel_pad_context *pads; | |
89 | struct intel_community_context *communities; | |
90 | }; | |
91 | ||
92 | /** | |
93 | * struct intel_pinctrl - Intel pinctrl private structure | |
94 | * @dev: Pointer to the device structure | |
95 | * @lock: Lock to serialize register access | |
96 | * @pctldesc: Pin controller description | |
97 | * @pctldev: Pointer to the pin controller device | |
98 | * @chip: GPIO chip in this pin controller | |
99 | * @soc: SoC/PCH specific pin configuration data | |
100 | * @communities: All communities in this pin controller | |
101 | * @ncommunities: Number of communities in this pin controller | |
102 | * @context: Configuration saved over system sleep | |
01dabe91 | 103 | * @irq: pinctrl/GPIO chip irq number |
7981c001 MW |
104 | */ |
105 | struct intel_pinctrl { | |
106 | struct device *dev; | |
27d9098c | 107 | raw_spinlock_t lock; |
7981c001 MW |
108 | struct pinctrl_desc pctldesc; |
109 | struct pinctrl_dev *pctldev; | |
110 | struct gpio_chip chip; | |
111 | const struct intel_pinctrl_soc_data *soc; | |
112 | struct intel_community *communities; | |
113 | size_t ncommunities; | |
114 | struct intel_pinctrl_context context; | |
01dabe91 | 115 | int irq; |
7981c001 MW |
116 | }; |
117 | ||
7981c001 | 118 | #define pin_to_padno(c, p) ((p) - (c)->pin_base) |
919eb475 | 119 | #define padgroup_offset(g, p) ((p) - (g)->base) |
7981c001 MW |
120 | |
121 | static struct intel_community *intel_get_community(struct intel_pinctrl *pctrl, | |
04035f7f | 122 | unsigned int pin) |
7981c001 MW |
123 | { |
124 | struct intel_community *community; | |
125 | int i; | |
126 | ||
127 | for (i = 0; i < pctrl->ncommunities; i++) { | |
128 | community = &pctrl->communities[i]; | |
129 | if (pin >= community->pin_base && | |
130 | pin < community->pin_base + community->npins) | |
131 | return community; | |
132 | } | |
133 | ||
134 | dev_warn(pctrl->dev, "failed to find community for pin %u\n", pin); | |
135 | return NULL; | |
136 | } | |
137 | ||
919eb475 MW |
138 | static const struct intel_padgroup * |
139 | intel_community_get_padgroup(const struct intel_community *community, | |
04035f7f | 140 | unsigned int pin) |
919eb475 MW |
141 | { |
142 | int i; | |
143 | ||
144 | for (i = 0; i < community->ngpps; i++) { | |
145 | const struct intel_padgroup *padgrp = &community->gpps[i]; | |
146 | ||
147 | if (pin >= padgrp->base && pin < padgrp->base + padgrp->size) | |
148 | return padgrp; | |
149 | } | |
150 | ||
151 | return NULL; | |
152 | } | |
153 | ||
04035f7f AS |
154 | static void __iomem *intel_get_padcfg(struct intel_pinctrl *pctrl, |
155 | unsigned int pin, unsigned int reg) | |
7981c001 MW |
156 | { |
157 | const struct intel_community *community; | |
04035f7f | 158 | unsigned int padno; |
e57725ea | 159 | size_t nregs; |
7981c001 MW |
160 | |
161 | community = intel_get_community(pctrl, pin); | |
162 | if (!community) | |
163 | return NULL; | |
164 | ||
165 | padno = pin_to_padno(community, pin); | |
e57725ea MW |
166 | nregs = (community->features & PINCTRL_FEATURE_DEBOUNCE) ? 4 : 2; |
167 | ||
168 | if (reg == PADCFG2 && !(community->features & PINCTRL_FEATURE_DEBOUNCE)) | |
169 | return NULL; | |
170 | ||
171 | return community->pad_regs + reg + padno * nregs * 4; | |
7981c001 MW |
172 | } |
173 | ||
04035f7f | 174 | static bool intel_pad_owned_by_host(struct intel_pinctrl *pctrl, unsigned int pin) |
7981c001 MW |
175 | { |
176 | const struct intel_community *community; | |
919eb475 | 177 | const struct intel_padgroup *padgrp; |
04035f7f | 178 | unsigned int gpp, offset, gpp_offset; |
7981c001 MW |
179 | void __iomem *padown; |
180 | ||
181 | community = intel_get_community(pctrl, pin); | |
182 | if (!community) | |
183 | return false; | |
184 | if (!community->padown_offset) | |
185 | return true; | |
186 | ||
919eb475 MW |
187 | padgrp = intel_community_get_padgroup(community, pin); |
188 | if (!padgrp) | |
189 | return false; | |
190 | ||
191 | gpp_offset = padgroup_offset(padgrp, pin); | |
192 | gpp = PADOWN_GPP(gpp_offset); | |
193 | offset = community->padown_offset + padgrp->padown_num * 4 + gpp * 4; | |
7981c001 MW |
194 | padown = community->regs + offset; |
195 | ||
919eb475 | 196 | return !(readl(padown) & PADOWN_MASK(gpp_offset)); |
7981c001 MW |
197 | } |
198 | ||
04035f7f | 199 | static bool intel_pad_acpi_mode(struct intel_pinctrl *pctrl, unsigned int pin) |
7981c001 MW |
200 | { |
201 | const struct intel_community *community; | |
919eb475 | 202 | const struct intel_padgroup *padgrp; |
04035f7f | 203 | unsigned int offset, gpp_offset; |
7981c001 MW |
204 | void __iomem *hostown; |
205 | ||
206 | community = intel_get_community(pctrl, pin); | |
207 | if (!community) | |
208 | return true; | |
209 | if (!community->hostown_offset) | |
210 | return false; | |
211 | ||
919eb475 MW |
212 | padgrp = intel_community_get_padgroup(community, pin); |
213 | if (!padgrp) | |
214 | return true; | |
215 | ||
216 | gpp_offset = padgroup_offset(padgrp, pin); | |
217 | offset = community->hostown_offset + padgrp->reg_num * 4; | |
7981c001 MW |
218 | hostown = community->regs + offset; |
219 | ||
919eb475 | 220 | return !(readl(hostown) & BIT(gpp_offset)); |
7981c001 MW |
221 | } |
222 | ||
04035f7f | 223 | static bool intel_pad_locked(struct intel_pinctrl *pctrl, unsigned int pin) |
7981c001 MW |
224 | { |
225 | struct intel_community *community; | |
919eb475 | 226 | const struct intel_padgroup *padgrp; |
04035f7f | 227 | unsigned int offset, gpp_offset; |
7981c001 MW |
228 | u32 value; |
229 | ||
230 | community = intel_get_community(pctrl, pin); | |
231 | if (!community) | |
232 | return true; | |
233 | if (!community->padcfglock_offset) | |
234 | return false; | |
235 | ||
919eb475 MW |
236 | padgrp = intel_community_get_padgroup(community, pin); |
237 | if (!padgrp) | |
238 | return true; | |
239 | ||
240 | gpp_offset = padgroup_offset(padgrp, pin); | |
7981c001 MW |
241 | |
242 | /* | |
243 | * If PADCFGLOCK and PADCFGLOCKTX bits are both clear for this pad, | |
244 | * the pad is considered unlocked. Any other case means that it is | |
245 | * either fully or partially locked and we don't touch it. | |
246 | */ | |
919eb475 | 247 | offset = community->padcfglock_offset + padgrp->reg_num * 8; |
7981c001 | 248 | value = readl(community->regs + offset); |
919eb475 | 249 | if (value & BIT(gpp_offset)) |
7981c001 MW |
250 | return true; |
251 | ||
919eb475 | 252 | offset = community->padcfglock_offset + 4 + padgrp->reg_num * 8; |
7981c001 | 253 | value = readl(community->regs + offset); |
919eb475 | 254 | if (value & BIT(gpp_offset)) |
7981c001 MW |
255 | return true; |
256 | ||
257 | return false; | |
258 | } | |
259 | ||
04035f7f | 260 | static bool intel_pad_usable(struct intel_pinctrl *pctrl, unsigned int pin) |
7981c001 MW |
261 | { |
262 | return intel_pad_owned_by_host(pctrl, pin) && | |
7981c001 MW |
263 | !intel_pad_locked(pctrl, pin); |
264 | } | |
265 | ||
266 | static int intel_get_groups_count(struct pinctrl_dev *pctldev) | |
267 | { | |
268 | struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
269 | ||
270 | return pctrl->soc->ngroups; | |
271 | } | |
272 | ||
273 | static const char *intel_get_group_name(struct pinctrl_dev *pctldev, | |
04035f7f | 274 | unsigned int group) |
7981c001 MW |
275 | { |
276 | struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
277 | ||
278 | return pctrl->soc->groups[group].name; | |
279 | } | |
280 | ||
04035f7f AS |
281 | static int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group, |
282 | const unsigned int **pins, unsigned int *npins) | |
7981c001 MW |
283 | { |
284 | struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
285 | ||
286 | *pins = pctrl->soc->groups[group].pins; | |
287 | *npins = pctrl->soc->groups[group].npins; | |
288 | return 0; | |
289 | } | |
290 | ||
291 | static void intel_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, | |
04035f7f | 292 | unsigned int pin) |
7981c001 MW |
293 | { |
294 | struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
e57725ea | 295 | void __iomem *padcfg; |
7981c001 MW |
296 | u32 cfg0, cfg1, mode; |
297 | bool locked, acpi; | |
298 | ||
299 | if (!intel_pad_owned_by_host(pctrl, pin)) { | |
300 | seq_puts(s, "not available"); | |
301 | return; | |
302 | } | |
303 | ||
304 | cfg0 = readl(intel_get_padcfg(pctrl, pin, PADCFG0)); | |
305 | cfg1 = readl(intel_get_padcfg(pctrl, pin, PADCFG1)); | |
306 | ||
307 | mode = (cfg0 & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT; | |
308 | if (!mode) | |
309 | seq_puts(s, "GPIO "); | |
310 | else | |
311 | seq_printf(s, "mode %d ", mode); | |
312 | ||
313 | seq_printf(s, "0x%08x 0x%08x", cfg0, cfg1); | |
314 | ||
e57725ea MW |
315 | /* Dump the additional PADCFG registers if available */ |
316 | padcfg = intel_get_padcfg(pctrl, pin, PADCFG2); | |
317 | if (padcfg) | |
318 | seq_printf(s, " 0x%08x", readl(padcfg)); | |
319 | ||
7981c001 | 320 | locked = intel_pad_locked(pctrl, pin); |
4341e8a5 | 321 | acpi = intel_pad_acpi_mode(pctrl, pin); |
7981c001 MW |
322 | |
323 | if (locked || acpi) { | |
324 | seq_puts(s, " ["); | |
325 | if (locked) { | |
326 | seq_puts(s, "LOCKED"); | |
327 | if (acpi) | |
328 | seq_puts(s, ", "); | |
329 | } | |
330 | if (acpi) | |
331 | seq_puts(s, "ACPI"); | |
332 | seq_puts(s, "]"); | |
333 | } | |
334 | } | |
335 | ||
336 | static const struct pinctrl_ops intel_pinctrl_ops = { | |
337 | .get_groups_count = intel_get_groups_count, | |
338 | .get_group_name = intel_get_group_name, | |
339 | .get_group_pins = intel_get_group_pins, | |
340 | .pin_dbg_show = intel_pin_dbg_show, | |
341 | }; | |
342 | ||
343 | static int intel_get_functions_count(struct pinctrl_dev *pctldev) | |
344 | { | |
345 | struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
346 | ||
347 | return pctrl->soc->nfunctions; | |
348 | } | |
349 | ||
350 | static const char *intel_get_function_name(struct pinctrl_dev *pctldev, | |
04035f7f | 351 | unsigned int function) |
7981c001 MW |
352 | { |
353 | struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
354 | ||
355 | return pctrl->soc->functions[function].name; | |
356 | } | |
357 | ||
358 | static int intel_get_function_groups(struct pinctrl_dev *pctldev, | |
04035f7f | 359 | unsigned int function, |
7981c001 | 360 | const char * const **groups, |
04035f7f | 361 | unsigned int * const ngroups) |
7981c001 MW |
362 | { |
363 | struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
364 | ||
365 | *groups = pctrl->soc->functions[function].groups; | |
366 | *ngroups = pctrl->soc->functions[function].ngroups; | |
367 | return 0; | |
368 | } | |
369 | ||
04035f7f AS |
370 | static int intel_pinmux_set_mux(struct pinctrl_dev *pctldev, |
371 | unsigned int function, unsigned int group) | |
7981c001 MW |
372 | { |
373 | struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
374 | const struct intel_pingroup *grp = &pctrl->soc->groups[group]; | |
375 | unsigned long flags; | |
376 | int i; | |
377 | ||
27d9098c | 378 | raw_spin_lock_irqsave(&pctrl->lock, flags); |
7981c001 MW |
379 | |
380 | /* | |
381 | * All pins in the groups needs to be accessible and writable | |
382 | * before we can enable the mux for this group. | |
383 | */ | |
384 | for (i = 0; i < grp->npins; i++) { | |
385 | if (!intel_pad_usable(pctrl, grp->pins[i])) { | |
27d9098c | 386 | raw_spin_unlock_irqrestore(&pctrl->lock, flags); |
7981c001 MW |
387 | return -EBUSY; |
388 | } | |
389 | } | |
390 | ||
391 | /* Now enable the mux setting for each pin in the group */ | |
392 | for (i = 0; i < grp->npins; i++) { | |
393 | void __iomem *padcfg0; | |
394 | u32 value; | |
395 | ||
396 | padcfg0 = intel_get_padcfg(pctrl, grp->pins[i], PADCFG0); | |
397 | value = readl(padcfg0); | |
398 | ||
399 | value &= ~PADCFG0_PMODE_MASK; | |
1f6b419b MW |
400 | |
401 | if (grp->modes) | |
402 | value |= grp->modes[i] << PADCFG0_PMODE_SHIFT; | |
403 | else | |
404 | value |= grp->mode << PADCFG0_PMODE_SHIFT; | |
7981c001 MW |
405 | |
406 | writel(value, padcfg0); | |
407 | } | |
408 | ||
27d9098c | 409 | raw_spin_unlock_irqrestore(&pctrl->lock, flags); |
7981c001 MW |
410 | |
411 | return 0; | |
412 | } | |
413 | ||
17fab473 AS |
414 | static void __intel_gpio_set_direction(void __iomem *padcfg0, bool input) |
415 | { | |
416 | u32 value; | |
417 | ||
418 | value = readl(padcfg0); | |
419 | if (input) { | |
420 | value &= ~PADCFG0_GPIORXDIS; | |
421 | value |= PADCFG0_GPIOTXDIS; | |
422 | } else { | |
423 | value &= ~PADCFG0_GPIOTXDIS; | |
424 | value |= PADCFG0_GPIORXDIS; | |
425 | } | |
426 | writel(value, padcfg0); | |
427 | } | |
428 | ||
f5a26acf MW |
429 | static void intel_gpio_set_gpio_mode(void __iomem *padcfg0) |
430 | { | |
431 | u32 value; | |
432 | ||
433 | /* Put the pad into GPIO mode */ | |
434 | value = readl(padcfg0) & ~PADCFG0_PMODE_MASK; | |
435 | /* Disable SCI/SMI/NMI generation */ | |
436 | value &= ~(PADCFG0_GPIROUTIOXAPIC | PADCFG0_GPIROUTSCI); | |
437 | value &= ~(PADCFG0_GPIROUTSMI | PADCFG0_GPIROUTNMI); | |
438 | writel(value, padcfg0); | |
439 | } | |
440 | ||
7981c001 MW |
441 | static int intel_gpio_request_enable(struct pinctrl_dev *pctldev, |
442 | struct pinctrl_gpio_range *range, | |
04035f7f | 443 | unsigned int pin) |
7981c001 MW |
444 | { |
445 | struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
446 | void __iomem *padcfg0; | |
447 | unsigned long flags; | |
7981c001 | 448 | |
27d9098c | 449 | raw_spin_lock_irqsave(&pctrl->lock, flags); |
7981c001 MW |
450 | |
451 | if (!intel_pad_usable(pctrl, pin)) { | |
27d9098c | 452 | raw_spin_unlock_irqrestore(&pctrl->lock, flags); |
7981c001 MW |
453 | return -EBUSY; |
454 | } | |
455 | ||
456 | padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0); | |
f5a26acf | 457 | intel_gpio_set_gpio_mode(padcfg0); |
17fab473 AS |
458 | /* Disable TX buffer and enable RX (this will be input) */ |
459 | __intel_gpio_set_direction(padcfg0, true); | |
460 | ||
27d9098c | 461 | raw_spin_unlock_irqrestore(&pctrl->lock, flags); |
7981c001 MW |
462 | |
463 | return 0; | |
464 | } | |
465 | ||
466 | static int intel_gpio_set_direction(struct pinctrl_dev *pctldev, | |
467 | struct pinctrl_gpio_range *range, | |
04035f7f | 468 | unsigned int pin, bool input) |
7981c001 MW |
469 | { |
470 | struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
471 | void __iomem *padcfg0; | |
472 | unsigned long flags; | |
7981c001 | 473 | |
27d9098c | 474 | raw_spin_lock_irqsave(&pctrl->lock, flags); |
7981c001 MW |
475 | |
476 | padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0); | |
17fab473 | 477 | __intel_gpio_set_direction(padcfg0, input); |
7981c001 | 478 | |
27d9098c | 479 | raw_spin_unlock_irqrestore(&pctrl->lock, flags); |
7981c001 MW |
480 | |
481 | return 0; | |
482 | } | |
483 | ||
484 | static const struct pinmux_ops intel_pinmux_ops = { | |
485 | .get_functions_count = intel_get_functions_count, | |
486 | .get_function_name = intel_get_function_name, | |
487 | .get_function_groups = intel_get_function_groups, | |
488 | .set_mux = intel_pinmux_set_mux, | |
489 | .gpio_request_enable = intel_gpio_request_enable, | |
490 | .gpio_set_direction = intel_gpio_set_direction, | |
491 | }; | |
492 | ||
04035f7f | 493 | static int intel_config_get(struct pinctrl_dev *pctldev, unsigned int pin, |
7981c001 MW |
494 | unsigned long *config) |
495 | { | |
496 | struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
497 | enum pin_config_param param = pinconf_to_config_param(*config); | |
04cc058f | 498 | const struct intel_community *community; |
7981c001 | 499 | u32 value, term; |
e57725ea | 500 | u32 arg = 0; |
7981c001 MW |
501 | |
502 | if (!intel_pad_owned_by_host(pctrl, pin)) | |
503 | return -ENOTSUPP; | |
504 | ||
04cc058f | 505 | community = intel_get_community(pctrl, pin); |
7981c001 MW |
506 | value = readl(intel_get_padcfg(pctrl, pin, PADCFG1)); |
507 | term = (value & PADCFG1_TERM_MASK) >> PADCFG1_TERM_SHIFT; | |
508 | ||
509 | switch (param) { | |
510 | case PIN_CONFIG_BIAS_DISABLE: | |
511 | if (term) | |
512 | return -EINVAL; | |
513 | break; | |
514 | ||
515 | case PIN_CONFIG_BIAS_PULL_UP: | |
516 | if (!term || !(value & PADCFG1_TERM_UP)) | |
517 | return -EINVAL; | |
518 | ||
519 | switch (term) { | |
520 | case PADCFG1_TERM_1K: | |
521 | arg = 1000; | |
522 | break; | |
523 | case PADCFG1_TERM_2K: | |
524 | arg = 2000; | |
525 | break; | |
526 | case PADCFG1_TERM_5K: | |
527 | arg = 5000; | |
528 | break; | |
529 | case PADCFG1_TERM_20K: | |
530 | arg = 20000; | |
531 | break; | |
532 | } | |
533 | ||
534 | break; | |
535 | ||
536 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
537 | if (!term || value & PADCFG1_TERM_UP) | |
538 | return -EINVAL; | |
539 | ||
540 | switch (term) { | |
04cc058f MW |
541 | case PADCFG1_TERM_1K: |
542 | if (!(community->features & PINCTRL_FEATURE_1K_PD)) | |
543 | return -EINVAL; | |
544 | arg = 1000; | |
545 | break; | |
7981c001 MW |
546 | case PADCFG1_TERM_5K: |
547 | arg = 5000; | |
548 | break; | |
549 | case PADCFG1_TERM_20K: | |
550 | arg = 20000; | |
551 | break; | |
552 | } | |
553 | ||
554 | break; | |
555 | ||
e57725ea MW |
556 | case PIN_CONFIG_INPUT_DEBOUNCE: { |
557 | void __iomem *padcfg2; | |
558 | u32 v; | |
559 | ||
560 | padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2); | |
561 | if (!padcfg2) | |
562 | return -ENOTSUPP; | |
563 | ||
564 | v = readl(padcfg2); | |
565 | if (!(v & PADCFG2_DEBEN)) | |
566 | return -EINVAL; | |
567 | ||
568 | v = (v & PADCFG2_DEBOUNCE_MASK) >> PADCFG2_DEBOUNCE_SHIFT; | |
569 | arg = BIT(v) * DEBOUNCE_PERIOD / 1000; | |
570 | ||
571 | break; | |
572 | } | |
573 | ||
7981c001 MW |
574 | default: |
575 | return -ENOTSUPP; | |
576 | } | |
577 | ||
578 | *config = pinconf_to_config_packed(param, arg); | |
579 | return 0; | |
580 | } | |
581 | ||
04035f7f | 582 | static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned int pin, |
7981c001 MW |
583 | unsigned long config) |
584 | { | |
04035f7f AS |
585 | unsigned int param = pinconf_to_config_param(config); |
586 | unsigned int arg = pinconf_to_config_argument(config); | |
04cc058f | 587 | const struct intel_community *community; |
7981c001 MW |
588 | void __iomem *padcfg1; |
589 | unsigned long flags; | |
590 | int ret = 0; | |
591 | u32 value; | |
592 | ||
27d9098c | 593 | raw_spin_lock_irqsave(&pctrl->lock, flags); |
7981c001 | 594 | |
04cc058f | 595 | community = intel_get_community(pctrl, pin); |
7981c001 MW |
596 | padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1); |
597 | value = readl(padcfg1); | |
598 | ||
599 | switch (param) { | |
600 | case PIN_CONFIG_BIAS_DISABLE: | |
601 | value &= ~(PADCFG1_TERM_MASK | PADCFG1_TERM_UP); | |
602 | break; | |
603 | ||
604 | case PIN_CONFIG_BIAS_PULL_UP: | |
605 | value &= ~PADCFG1_TERM_MASK; | |
606 | ||
607 | value |= PADCFG1_TERM_UP; | |
608 | ||
609 | switch (arg) { | |
610 | case 20000: | |
611 | value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT; | |
612 | break; | |
613 | case 5000: | |
614 | value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT; | |
615 | break; | |
616 | case 2000: | |
617 | value |= PADCFG1_TERM_2K << PADCFG1_TERM_SHIFT; | |
618 | break; | |
619 | case 1000: | |
620 | value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT; | |
621 | break; | |
622 | default: | |
623 | ret = -EINVAL; | |
624 | } | |
625 | ||
626 | break; | |
627 | ||
628 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
629 | value &= ~(PADCFG1_TERM_UP | PADCFG1_TERM_MASK); | |
630 | ||
631 | switch (arg) { | |
632 | case 20000: | |
633 | value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT; | |
634 | break; | |
635 | case 5000: | |
636 | value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT; | |
637 | break; | |
04cc058f | 638 | case 1000: |
aa1dd80f DC |
639 | if (!(community->features & PINCTRL_FEATURE_1K_PD)) { |
640 | ret = -EINVAL; | |
641 | break; | |
642 | } | |
04cc058f MW |
643 | value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT; |
644 | break; | |
7981c001 MW |
645 | default: |
646 | ret = -EINVAL; | |
647 | } | |
648 | ||
649 | break; | |
650 | } | |
651 | ||
652 | if (!ret) | |
653 | writel(value, padcfg1); | |
654 | ||
27d9098c | 655 | raw_spin_unlock_irqrestore(&pctrl->lock, flags); |
7981c001 MW |
656 | |
657 | return ret; | |
658 | } | |
659 | ||
04035f7f AS |
660 | static int intel_config_set_debounce(struct intel_pinctrl *pctrl, |
661 | unsigned int pin, unsigned int debounce) | |
e57725ea MW |
662 | { |
663 | void __iomem *padcfg0, *padcfg2; | |
664 | unsigned long flags; | |
665 | u32 value0, value2; | |
666 | int ret = 0; | |
667 | ||
668 | padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2); | |
669 | if (!padcfg2) | |
670 | return -ENOTSUPP; | |
671 | ||
672 | padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0); | |
673 | ||
674 | raw_spin_lock_irqsave(&pctrl->lock, flags); | |
675 | ||
676 | value0 = readl(padcfg0); | |
677 | value2 = readl(padcfg2); | |
678 | ||
679 | /* Disable glitch filter and debouncer */ | |
680 | value0 &= ~PADCFG0_PREGFRXSEL; | |
681 | value2 &= ~(PADCFG2_DEBEN | PADCFG2_DEBOUNCE_MASK); | |
682 | ||
683 | if (debounce) { | |
684 | unsigned long v; | |
685 | ||
686 | v = order_base_2(debounce * 1000 / DEBOUNCE_PERIOD); | |
687 | if (v < 3 || v > 15) { | |
688 | ret = -EINVAL; | |
689 | goto exit_unlock; | |
690 | } else { | |
691 | /* Enable glitch filter and debouncer */ | |
692 | value0 |= PADCFG0_PREGFRXSEL; | |
693 | value2 |= v << PADCFG2_DEBOUNCE_SHIFT; | |
694 | value2 |= PADCFG2_DEBEN; | |
695 | } | |
696 | } | |
697 | ||
698 | writel(value0, padcfg0); | |
699 | writel(value2, padcfg2); | |
700 | ||
701 | exit_unlock: | |
702 | raw_spin_unlock_irqrestore(&pctrl->lock, flags); | |
703 | ||
704 | return ret; | |
705 | } | |
706 | ||
04035f7f AS |
707 | static int intel_config_set(struct pinctrl_dev *pctldev, unsigned int pin, |
708 | unsigned long *configs, unsigned int nconfigs) | |
7981c001 MW |
709 | { |
710 | struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
711 | int i, ret; | |
712 | ||
713 | if (!intel_pad_usable(pctrl, pin)) | |
714 | return -ENOTSUPP; | |
715 | ||
716 | for (i = 0; i < nconfigs; i++) { | |
717 | switch (pinconf_to_config_param(configs[i])) { | |
718 | case PIN_CONFIG_BIAS_DISABLE: | |
719 | case PIN_CONFIG_BIAS_PULL_UP: | |
720 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
721 | ret = intel_config_set_pull(pctrl, pin, configs[i]); | |
722 | if (ret) | |
723 | return ret; | |
724 | break; | |
725 | ||
e57725ea MW |
726 | case PIN_CONFIG_INPUT_DEBOUNCE: |
727 | ret = intel_config_set_debounce(pctrl, pin, | |
728 | pinconf_to_config_argument(configs[i])); | |
729 | if (ret) | |
730 | return ret; | |
731 | break; | |
732 | ||
7981c001 MW |
733 | default: |
734 | return -ENOTSUPP; | |
735 | } | |
736 | } | |
737 | ||
738 | return 0; | |
739 | } | |
740 | ||
741 | static const struct pinconf_ops intel_pinconf_ops = { | |
742 | .is_generic = true, | |
743 | .pin_config_get = intel_config_get, | |
744 | .pin_config_set = intel_config_set, | |
745 | }; | |
746 | ||
747 | static const struct pinctrl_desc intel_pinctrl_desc = { | |
748 | .pctlops = &intel_pinctrl_ops, | |
749 | .pmxops = &intel_pinmux_ops, | |
750 | .confops = &intel_pinconf_ops, | |
751 | .owner = THIS_MODULE, | |
752 | }; | |
753 | ||
96147db1 MW |
754 | /** |
755 | * intel_gpio_to_pin() - Translate from GPIO offset to pin number | |
756 | * @pctrl: Pinctrl structure | |
757 | * @offset: GPIO offset from gpiolib | |
946ffefc | 758 | * @community: Community is filled here if not %NULL |
96147db1 MW |
759 | * @padgrp: Pad group is filled here if not %NULL |
760 | * | |
761 | * When coming through gpiolib irqchip, the GPIO offset is not | |
762 | * automatically translated to pinctrl pin number. This function can be | |
763 | * used to find out the corresponding pinctrl pin. | |
764 | */ | |
04035f7f | 765 | static int intel_gpio_to_pin(struct intel_pinctrl *pctrl, unsigned int offset, |
96147db1 MW |
766 | const struct intel_community **community, |
767 | const struct intel_padgroup **padgrp) | |
768 | { | |
769 | int i; | |
770 | ||
771 | for (i = 0; i < pctrl->ncommunities; i++) { | |
772 | const struct intel_community *comm = &pctrl->communities[i]; | |
773 | int j; | |
774 | ||
775 | for (j = 0; j < comm->ngpps; j++) { | |
776 | const struct intel_padgroup *pgrp = &comm->gpps[j]; | |
777 | ||
778 | if (pgrp->gpio_base < 0) | |
779 | continue; | |
780 | ||
781 | if (offset >= pgrp->gpio_base && | |
782 | offset < pgrp->gpio_base + pgrp->size) { | |
783 | int pin; | |
784 | ||
785 | pin = pgrp->base + offset - pgrp->gpio_base; | |
786 | if (community) | |
787 | *community = comm; | |
788 | if (padgrp) | |
789 | *padgrp = pgrp; | |
790 | ||
791 | return pin; | |
792 | } | |
793 | } | |
794 | } | |
795 | ||
796 | return -EINVAL; | |
797 | } | |
798 | ||
eeb126fe CC |
799 | /** |
800 | * intel_pin_to_gpio() - Translate from pin number to GPIO offset | |
801 | * @pctrl: Pinctrl structure | |
802 | * @pin: pin number | |
803 | * | |
804 | * Translate the pin number of pinctrl to GPIO offset | |
805 | */ | |
806 | static int intel_pin_to_gpio(struct intel_pinctrl *pctrl, int pin) | |
807 | { | |
808 | const struct intel_community *community; | |
809 | const struct intel_padgroup *padgrp; | |
810 | ||
811 | community = intel_get_community(pctrl, pin); | |
812 | if (!community) | |
813 | return -EINVAL; | |
814 | ||
815 | padgrp = intel_community_get_padgroup(community, pin); | |
816 | if (!padgrp) | |
817 | return -EINVAL; | |
818 | ||
819 | return pin - padgrp->base + padgrp->gpio_base; | |
820 | } | |
821 | ||
04035f7f | 822 | static int intel_gpio_get(struct gpio_chip *chip, unsigned int offset) |
7981c001 | 823 | { |
acfd4c63 | 824 | struct intel_pinctrl *pctrl = gpiochip_get_data(chip); |
7981c001 | 825 | void __iomem *reg; |
d68b42e3 | 826 | u32 padcfg0; |
96147db1 | 827 | int pin; |
7981c001 | 828 | |
96147db1 MW |
829 | pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL); |
830 | if (pin < 0) | |
831 | return -EINVAL; | |
7981c001 | 832 | |
96147db1 | 833 | reg = intel_get_padcfg(pctrl, pin, PADCFG0); |
7981c001 MW |
834 | if (!reg) |
835 | return -EINVAL; | |
836 | ||
d68b42e3 AS |
837 | padcfg0 = readl(reg); |
838 | if (!(padcfg0 & PADCFG0_GPIOTXDIS)) | |
839 | return !!(padcfg0 & PADCFG0_GPIOTXSTATE); | |
840 | ||
841 | return !!(padcfg0 & PADCFG0_GPIORXSTATE); | |
7981c001 MW |
842 | } |
843 | ||
04035f7f AS |
844 | static void intel_gpio_set(struct gpio_chip *chip, unsigned int offset, |
845 | int value) | |
7981c001 | 846 | { |
acfd4c63 | 847 | struct intel_pinctrl *pctrl = gpiochip_get_data(chip); |
85461377 | 848 | unsigned long flags; |
7981c001 | 849 | void __iomem *reg; |
85461377 | 850 | u32 padcfg0; |
96147db1 | 851 | int pin; |
7981c001 | 852 | |
96147db1 MW |
853 | pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL); |
854 | if (pin < 0) | |
855 | return; | |
856 | ||
857 | reg = intel_get_padcfg(pctrl, pin, PADCFG0); | |
85461377 AS |
858 | if (!reg) |
859 | return; | |
860 | ||
861 | raw_spin_lock_irqsave(&pctrl->lock, flags); | |
862 | padcfg0 = readl(reg); | |
863 | if (value) | |
864 | padcfg0 |= PADCFG0_GPIOTXSTATE; | |
865 | else | |
866 | padcfg0 &= ~PADCFG0_GPIOTXSTATE; | |
867 | writel(padcfg0, reg); | |
868 | raw_spin_unlock_irqrestore(&pctrl->lock, flags); | |
7981c001 MW |
869 | } |
870 | ||
67e6d3e8 JA |
871 | static int intel_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) |
872 | { | |
873 | struct intel_pinctrl *pctrl = gpiochip_get_data(chip); | |
874 | void __iomem *reg; | |
875 | u32 padcfg0; | |
96147db1 MW |
876 | int pin; |
877 | ||
878 | pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL); | |
879 | if (pin < 0) | |
880 | return -EINVAL; | |
67e6d3e8 | 881 | |
96147db1 | 882 | reg = intel_get_padcfg(pctrl, pin, PADCFG0); |
67e6d3e8 JA |
883 | if (!reg) |
884 | return -EINVAL; | |
885 | ||
886 | padcfg0 = readl(reg); | |
887 | ||
888 | if (padcfg0 & PADCFG0_PMODE_MASK) | |
889 | return -EINVAL; | |
890 | ||
891 | return !!(padcfg0 & PADCFG0_GPIOTXDIS); | |
892 | } | |
893 | ||
04035f7f | 894 | static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) |
7981c001 MW |
895 | { |
896 | return pinctrl_gpio_direction_input(chip->base + offset); | |
897 | } | |
898 | ||
04035f7f | 899 | static int intel_gpio_direction_output(struct gpio_chip *chip, unsigned int offset, |
7981c001 MW |
900 | int value) |
901 | { | |
902 | intel_gpio_set(chip, offset, value); | |
903 | return pinctrl_gpio_direction_output(chip->base + offset); | |
904 | } | |
905 | ||
906 | static const struct gpio_chip intel_gpio_chip = { | |
907 | .owner = THIS_MODULE, | |
98c85d58 JG |
908 | .request = gpiochip_generic_request, |
909 | .free = gpiochip_generic_free, | |
67e6d3e8 | 910 | .get_direction = intel_gpio_get_direction, |
7981c001 MW |
911 | .direction_input = intel_gpio_direction_input, |
912 | .direction_output = intel_gpio_direction_output, | |
913 | .get = intel_gpio_get, | |
914 | .set = intel_gpio_set, | |
e57725ea | 915 | .set_config = gpiochip_generic_config, |
7981c001 MW |
916 | }; |
917 | ||
918 | static void intel_gpio_irq_ack(struct irq_data *d) | |
919 | { | |
920 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); | |
acfd4c63 | 921 | struct intel_pinctrl *pctrl = gpiochip_get_data(gc); |
7981c001 | 922 | const struct intel_community *community; |
a60eac32 MW |
923 | const struct intel_padgroup *padgrp; |
924 | int pin; | |
7981c001 | 925 | |
a60eac32 MW |
926 | pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp); |
927 | if (pin >= 0) { | |
04035f7f | 928 | unsigned int gpp, gpp_offset, is_offset; |
919eb475 | 929 | |
919eb475 MW |
930 | gpp = padgrp->reg_num; |
931 | gpp_offset = padgroup_offset(padgrp, pin); | |
cf769bd8 | 932 | is_offset = community->is_offset + gpp * 4; |
7981c001 | 933 | |
919eb475 | 934 | raw_spin_lock(&pctrl->lock); |
cf769bd8 | 935 | writel(BIT(gpp_offset), community->regs + is_offset); |
919eb475 | 936 | raw_spin_unlock(&pctrl->lock); |
7981c001 | 937 | } |
7981c001 MW |
938 | } |
939 | ||
940 | static void intel_gpio_irq_mask_unmask(struct irq_data *d, bool mask) | |
941 | { | |
942 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); | |
acfd4c63 | 943 | struct intel_pinctrl *pctrl = gpiochip_get_data(gc); |
7981c001 | 944 | const struct intel_community *community; |
a60eac32 MW |
945 | const struct intel_padgroup *padgrp; |
946 | int pin; | |
7981c001 | 947 | |
a60eac32 MW |
948 | pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp); |
949 | if (pin >= 0) { | |
04035f7f | 950 | unsigned int gpp, gpp_offset; |
919eb475 | 951 | unsigned long flags; |
670784fb | 952 | void __iomem *reg, *is; |
7981c001 MW |
953 | u32 value; |
954 | ||
919eb475 MW |
955 | gpp = padgrp->reg_num; |
956 | gpp_offset = padgroup_offset(padgrp, pin); | |
957 | ||
7981c001 | 958 | reg = community->regs + community->ie_offset + gpp * 4; |
670784fb | 959 | is = community->regs + community->is_offset + gpp * 4; |
919eb475 MW |
960 | |
961 | raw_spin_lock_irqsave(&pctrl->lock, flags); | |
670784fb KHF |
962 | |
963 | /* Clear interrupt status first to avoid unexpected interrupt */ | |
964 | writel(BIT(gpp_offset), is); | |
965 | ||
7981c001 MW |
966 | value = readl(reg); |
967 | if (mask) | |
968 | value &= ~BIT(gpp_offset); | |
969 | else | |
970 | value |= BIT(gpp_offset); | |
971 | writel(value, reg); | |
919eb475 | 972 | raw_spin_unlock_irqrestore(&pctrl->lock, flags); |
7981c001 | 973 | } |
7981c001 MW |
974 | } |
975 | ||
976 | static void intel_gpio_irq_mask(struct irq_data *d) | |
977 | { | |
978 | intel_gpio_irq_mask_unmask(d, true); | |
979 | } | |
980 | ||
981 | static void intel_gpio_irq_unmask(struct irq_data *d) | |
982 | { | |
983 | intel_gpio_irq_mask_unmask(d, false); | |
984 | } | |
985 | ||
04035f7f | 986 | static int intel_gpio_irq_type(struct irq_data *d, unsigned int type) |
7981c001 MW |
987 | { |
988 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); | |
acfd4c63 | 989 | struct intel_pinctrl *pctrl = gpiochip_get_data(gc); |
04035f7f | 990 | unsigned int pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL); |
7981c001 MW |
991 | unsigned long flags; |
992 | void __iomem *reg; | |
993 | u32 value; | |
994 | ||
995 | reg = intel_get_padcfg(pctrl, pin, PADCFG0); | |
996 | if (!reg) | |
997 | return -EINVAL; | |
998 | ||
4341e8a5 MW |
999 | /* |
1000 | * If the pin is in ACPI mode it is still usable as a GPIO but it | |
1001 | * cannot be used as IRQ because GPI_IS status bit will not be | |
1002 | * updated by the host controller hardware. | |
1003 | */ | |
1004 | if (intel_pad_acpi_mode(pctrl, pin)) { | |
1005 | dev_warn(pctrl->dev, "pin %u cannot be used as IRQ\n", pin); | |
1006 | return -EPERM; | |
1007 | } | |
1008 | ||
27d9098c | 1009 | raw_spin_lock_irqsave(&pctrl->lock, flags); |
7981c001 | 1010 | |
f5a26acf MW |
1011 | intel_gpio_set_gpio_mode(reg); |
1012 | ||
7981c001 MW |
1013 | value = readl(reg); |
1014 | ||
1015 | value &= ~(PADCFG0_RXEVCFG_MASK | PADCFG0_RXINV); | |
1016 | ||
1017 | if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) { | |
1018 | value |= PADCFG0_RXEVCFG_EDGE_BOTH << PADCFG0_RXEVCFG_SHIFT; | |
1019 | } else if (type & IRQ_TYPE_EDGE_FALLING) { | |
1020 | value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT; | |
1021 | value |= PADCFG0_RXINV; | |
1022 | } else if (type & IRQ_TYPE_EDGE_RISING) { | |
1023 | value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT; | |
bf380cfa QZ |
1024 | } else if (type & IRQ_TYPE_LEVEL_MASK) { |
1025 | if (type & IRQ_TYPE_LEVEL_LOW) | |
1026 | value |= PADCFG0_RXINV; | |
7981c001 MW |
1027 | } else { |
1028 | value |= PADCFG0_RXEVCFG_DISABLED << PADCFG0_RXEVCFG_SHIFT; | |
1029 | } | |
1030 | ||
1031 | writel(value, reg); | |
1032 | ||
1033 | if (type & IRQ_TYPE_EDGE_BOTH) | |
fc756bcd | 1034 | irq_set_handler_locked(d, handle_edge_irq); |
7981c001 | 1035 | else if (type & IRQ_TYPE_LEVEL_MASK) |
fc756bcd | 1036 | irq_set_handler_locked(d, handle_level_irq); |
7981c001 | 1037 | |
27d9098c | 1038 | raw_spin_unlock_irqrestore(&pctrl->lock, flags); |
7981c001 MW |
1039 | |
1040 | return 0; | |
1041 | } | |
1042 | ||
1043 | static int intel_gpio_irq_wake(struct irq_data *d, unsigned int on) | |
1044 | { | |
1045 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); | |
acfd4c63 | 1046 | struct intel_pinctrl *pctrl = gpiochip_get_data(gc); |
04035f7f | 1047 | unsigned int pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL); |
9a520fd9 | 1048 | |
7981c001 | 1049 | if (on) |
01dabe91 | 1050 | enable_irq_wake(pctrl->irq); |
7981c001 | 1051 | else |
01dabe91 | 1052 | disable_irq_wake(pctrl->irq); |
9a520fd9 | 1053 | |
7981c001 MW |
1054 | dev_dbg(pctrl->dev, "%sable wake for pin %u\n", on ? "en" : "dis", pin); |
1055 | return 0; | |
1056 | } | |
1057 | ||
193b40c8 | 1058 | static irqreturn_t intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl, |
7981c001 MW |
1059 | const struct intel_community *community) |
1060 | { | |
193b40c8 MW |
1061 | struct gpio_chip *gc = &pctrl->chip; |
1062 | irqreturn_t ret = IRQ_NONE; | |
7981c001 MW |
1063 | int gpp; |
1064 | ||
1065 | for (gpp = 0; gpp < community->ngpps; gpp++) { | |
919eb475 | 1066 | const struct intel_padgroup *padgrp = &community->gpps[gpp]; |
7981c001 MW |
1067 | unsigned long pending, enabled, gpp_offset; |
1068 | ||
cf769bd8 MW |
1069 | pending = readl(community->regs + community->is_offset + |
1070 | padgrp->reg_num * 4); | |
7981c001 | 1071 | enabled = readl(community->regs + community->ie_offset + |
919eb475 | 1072 | padgrp->reg_num * 4); |
7981c001 MW |
1073 | |
1074 | /* Only interrupts that are enabled */ | |
1075 | pending &= enabled; | |
1076 | ||
919eb475 | 1077 | for_each_set_bit(gpp_offset, &pending, padgrp->size) { |
a60eac32 | 1078 | unsigned irq; |
7981c001 | 1079 | |
f0fbe7bc | 1080 | irq = irq_find_mapping(gc->irq.domain, |
a60eac32 | 1081 | padgrp->gpio_base + gpp_offset); |
7981c001 | 1082 | generic_handle_irq(irq); |
193b40c8 MW |
1083 | |
1084 | ret |= IRQ_HANDLED; | |
7981c001 MW |
1085 | } |
1086 | } | |
193b40c8 MW |
1087 | |
1088 | return ret; | |
7981c001 MW |
1089 | } |
1090 | ||
193b40c8 | 1091 | static irqreturn_t intel_gpio_irq(int irq, void *data) |
7981c001 | 1092 | { |
193b40c8 MW |
1093 | const struct intel_community *community; |
1094 | struct intel_pinctrl *pctrl = data; | |
1095 | irqreturn_t ret = IRQ_NONE; | |
7981c001 MW |
1096 | int i; |
1097 | ||
7981c001 | 1098 | /* Need to check all communities for pending interrupts */ |
193b40c8 MW |
1099 | for (i = 0; i < pctrl->ncommunities; i++) { |
1100 | community = &pctrl->communities[i]; | |
1101 | ret |= intel_gpio_community_irq_handler(pctrl, community); | |
1102 | } | |
7981c001 | 1103 | |
193b40c8 | 1104 | return ret; |
7981c001 MW |
1105 | } |
1106 | ||
1107 | static struct irq_chip intel_gpio_irqchip = { | |
1108 | .name = "intel-gpio", | |
1109 | .irq_ack = intel_gpio_irq_ack, | |
1110 | .irq_mask = intel_gpio_irq_mask, | |
1111 | .irq_unmask = intel_gpio_irq_unmask, | |
1112 | .irq_set_type = intel_gpio_irq_type, | |
1113 | .irq_set_wake = intel_gpio_irq_wake, | |
5ff56b01 | 1114 | .flags = IRQCHIP_MASK_ON_SUSPEND, |
7981c001 MW |
1115 | }; |
1116 | ||
a60eac32 MW |
1117 | static int intel_gpio_add_pin_ranges(struct intel_pinctrl *pctrl, |
1118 | const struct intel_community *community) | |
1119 | { | |
33b6cb58 | 1120 | int ret = 0, i; |
a60eac32 MW |
1121 | |
1122 | for (i = 0; i < community->ngpps; i++) { | |
1123 | const struct intel_padgroup *gpp = &community->gpps[i]; | |
1124 | ||
1125 | if (gpp->gpio_base < 0) | |
1126 | continue; | |
1127 | ||
1128 | ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), | |
1129 | gpp->gpio_base, gpp->base, | |
1130 | gpp->size); | |
1131 | if (ret) | |
1132 | return ret; | |
1133 | } | |
1134 | ||
1135 | return ret; | |
1136 | } | |
1137 | ||
1138 | static unsigned intel_gpio_ngpio(const struct intel_pinctrl *pctrl) | |
1139 | { | |
1140 | const struct intel_community *community; | |
04035f7f | 1141 | unsigned int ngpio = 0; |
a60eac32 MW |
1142 | int i, j; |
1143 | ||
1144 | for (i = 0; i < pctrl->ncommunities; i++) { | |
1145 | community = &pctrl->communities[i]; | |
1146 | for (j = 0; j < community->ngpps; j++) { | |
1147 | const struct intel_padgroup *gpp = &community->gpps[j]; | |
1148 | ||
1149 | if (gpp->gpio_base < 0) | |
1150 | continue; | |
1151 | ||
1152 | if (gpp->gpio_base + gpp->size > ngpio) | |
1153 | ngpio = gpp->gpio_base + gpp->size; | |
1154 | } | |
1155 | } | |
1156 | ||
1157 | return ngpio; | |
1158 | } | |
1159 | ||
7981c001 MW |
1160 | static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq) |
1161 | { | |
a60eac32 | 1162 | int ret, i; |
7981c001 MW |
1163 | |
1164 | pctrl->chip = intel_gpio_chip; | |
1165 | ||
a60eac32 | 1166 | pctrl->chip.ngpio = intel_gpio_ngpio(pctrl); |
7981c001 | 1167 | pctrl->chip.label = dev_name(pctrl->dev); |
58383c78 | 1168 | pctrl->chip.parent = pctrl->dev; |
7981c001 | 1169 | pctrl->chip.base = -1; |
01dabe91 | 1170 | pctrl->irq = irq; |
7981c001 | 1171 | |
f25c3aa9 | 1172 | ret = devm_gpiochip_add_data(pctrl->dev, &pctrl->chip, pctrl); |
7981c001 MW |
1173 | if (ret) { |
1174 | dev_err(pctrl->dev, "failed to register gpiochip\n"); | |
1175 | return ret; | |
1176 | } | |
1177 | ||
a60eac32 MW |
1178 | for (i = 0; i < pctrl->ncommunities; i++) { |
1179 | struct intel_community *community = &pctrl->communities[i]; | |
1180 | ||
1181 | ret = intel_gpio_add_pin_ranges(pctrl, community); | |
1182 | if (ret) { | |
1183 | dev_err(pctrl->dev, "failed to add GPIO pin range\n"); | |
1184 | return ret; | |
1185 | } | |
193b40c8 MW |
1186 | } |
1187 | ||
1188 | /* | |
1189 | * We need to request the interrupt here (instead of providing chip | |
1190 | * to the irq directly) because on some platforms several GPIO | |
1191 | * controllers share the same interrupt line. | |
1192 | */ | |
1a7d1cb8 MW |
1193 | ret = devm_request_irq(pctrl->dev, irq, intel_gpio_irq, |
1194 | IRQF_SHARED | IRQF_NO_THREAD, | |
193b40c8 MW |
1195 | dev_name(pctrl->dev), pctrl); |
1196 | if (ret) { | |
1197 | dev_err(pctrl->dev, "failed to request interrupt\n"); | |
f25c3aa9 | 1198 | return ret; |
7981c001 MW |
1199 | } |
1200 | ||
1201 | ret = gpiochip_irqchip_add(&pctrl->chip, &intel_gpio_irqchip, 0, | |
3ae02c14 | 1202 | handle_bad_irq, IRQ_TYPE_NONE); |
7981c001 MW |
1203 | if (ret) { |
1204 | dev_err(pctrl->dev, "failed to add irqchip\n"); | |
f25c3aa9 | 1205 | return ret; |
7981c001 MW |
1206 | } |
1207 | ||
1208 | gpiochip_set_chained_irqchip(&pctrl->chip, &intel_gpio_irqchip, irq, | |
193b40c8 | 1209 | NULL); |
7981c001 MW |
1210 | return 0; |
1211 | } | |
1212 | ||
919eb475 MW |
1213 | static int intel_pinctrl_add_padgroups(struct intel_pinctrl *pctrl, |
1214 | struct intel_community *community) | |
1215 | { | |
1216 | struct intel_padgroup *gpps; | |
04035f7f AS |
1217 | unsigned int npins = community->npins; |
1218 | unsigned int padown_num = 0; | |
919eb475 MW |
1219 | size_t ngpps, i; |
1220 | ||
1221 | if (community->gpps) | |
1222 | ngpps = community->ngpps; | |
1223 | else | |
1224 | ngpps = DIV_ROUND_UP(community->npins, community->gpp_size); | |
1225 | ||
1226 | gpps = devm_kcalloc(pctrl->dev, ngpps, sizeof(*gpps), GFP_KERNEL); | |
1227 | if (!gpps) | |
1228 | return -ENOMEM; | |
1229 | ||
1230 | for (i = 0; i < ngpps; i++) { | |
1231 | if (community->gpps) { | |
1232 | gpps[i] = community->gpps[i]; | |
1233 | } else { | |
04035f7f | 1234 | unsigned int gpp_size = community->gpp_size; |
919eb475 MW |
1235 | |
1236 | gpps[i].reg_num = i; | |
1237 | gpps[i].base = community->pin_base + i * gpp_size; | |
1238 | gpps[i].size = min(gpp_size, npins); | |
1239 | npins -= gpps[i].size; | |
1240 | } | |
1241 | ||
1242 | if (gpps[i].size > 32) | |
1243 | return -EINVAL; | |
1244 | ||
a60eac32 MW |
1245 | if (!gpps[i].gpio_base) |
1246 | gpps[i].gpio_base = gpps[i].base; | |
1247 | ||
919eb475 MW |
1248 | gpps[i].padown_num = padown_num; |
1249 | ||
1250 | /* | |
1251 | * In older hardware the number of padown registers per | |
1252 | * group is fixed regardless of the group size. | |
1253 | */ | |
1254 | if (community->gpp_num_padown_regs) | |
1255 | padown_num += community->gpp_num_padown_regs; | |
1256 | else | |
1257 | padown_num += DIV_ROUND_UP(gpps[i].size * 4, 32); | |
1258 | } | |
1259 | ||
1260 | community->ngpps = ngpps; | |
1261 | community->gpps = gpps; | |
1262 | ||
1263 | return 0; | |
1264 | } | |
1265 | ||
7981c001 MW |
1266 | static int intel_pinctrl_pm_init(struct intel_pinctrl *pctrl) |
1267 | { | |
1268 | #ifdef CONFIG_PM_SLEEP | |
1269 | const struct intel_pinctrl_soc_data *soc = pctrl->soc; | |
1270 | struct intel_community_context *communities; | |
1271 | struct intel_pad_context *pads; | |
1272 | int i; | |
1273 | ||
1274 | pads = devm_kcalloc(pctrl->dev, soc->npins, sizeof(*pads), GFP_KERNEL); | |
1275 | if (!pads) | |
1276 | return -ENOMEM; | |
1277 | ||
1278 | communities = devm_kcalloc(pctrl->dev, pctrl->ncommunities, | |
1279 | sizeof(*communities), GFP_KERNEL); | |
1280 | if (!communities) | |
1281 | return -ENOMEM; | |
1282 | ||
1283 | ||
1284 | for (i = 0; i < pctrl->ncommunities; i++) { | |
1285 | struct intel_community *community = &pctrl->communities[i]; | |
a0a5f766 | 1286 | u32 *intmask, *hostown; |
7981c001 MW |
1287 | |
1288 | intmask = devm_kcalloc(pctrl->dev, community->ngpps, | |
1289 | sizeof(*intmask), GFP_KERNEL); | |
1290 | if (!intmask) | |
1291 | return -ENOMEM; | |
1292 | ||
1293 | communities[i].intmask = intmask; | |
a0a5f766 CC |
1294 | |
1295 | hostown = devm_kcalloc(pctrl->dev, community->ngpps, | |
1296 | sizeof(*hostown), GFP_KERNEL); | |
1297 | if (!hostown) | |
1298 | return -ENOMEM; | |
1299 | ||
1300 | communities[i].hostown = hostown; | |
7981c001 MW |
1301 | } |
1302 | ||
1303 | pctrl->context.pads = pads; | |
1304 | pctrl->context.communities = communities; | |
1305 | #endif | |
1306 | ||
1307 | return 0; | |
1308 | } | |
1309 | ||
0dd519e3 AS |
1310 | static int intel_pinctrl_probe(struct platform_device *pdev, |
1311 | const struct intel_pinctrl_soc_data *soc_data) | |
7981c001 MW |
1312 | { |
1313 | struct intel_pinctrl *pctrl; | |
1314 | int i, ret, irq; | |
1315 | ||
1316 | if (!soc_data) | |
1317 | return -EINVAL; | |
1318 | ||
1319 | pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); | |
1320 | if (!pctrl) | |
1321 | return -ENOMEM; | |
1322 | ||
1323 | pctrl->dev = &pdev->dev; | |
1324 | pctrl->soc = soc_data; | |
27d9098c | 1325 | raw_spin_lock_init(&pctrl->lock); |
7981c001 MW |
1326 | |
1327 | /* | |
1328 | * Make a copy of the communities which we can use to hold pointers | |
1329 | * to the registers. | |
1330 | */ | |
1331 | pctrl->ncommunities = pctrl->soc->ncommunities; | |
1332 | pctrl->communities = devm_kcalloc(&pdev->dev, pctrl->ncommunities, | |
1333 | sizeof(*pctrl->communities), GFP_KERNEL); | |
1334 | if (!pctrl->communities) | |
1335 | return -ENOMEM; | |
1336 | ||
1337 | for (i = 0; i < pctrl->ncommunities; i++) { | |
1338 | struct intel_community *community = &pctrl->communities[i]; | |
1339 | struct resource *res; | |
1340 | void __iomem *regs; | |
1341 | u32 padbar; | |
1342 | ||
1343 | *community = pctrl->soc->communities[i]; | |
1344 | ||
1345 | res = platform_get_resource(pdev, IORESOURCE_MEM, | |
1346 | community->barno); | |
1347 | regs = devm_ioremap_resource(&pdev->dev, res); | |
1348 | if (IS_ERR(regs)) | |
1349 | return PTR_ERR(regs); | |
1350 | ||
e57725ea MW |
1351 | /* |
1352 | * Determine community features based on the revision if | |
1353 | * not specified already. | |
1354 | */ | |
1355 | if (!community->features) { | |
1356 | u32 rev; | |
1357 | ||
1358 | rev = (readl(regs + REVID) & REVID_MASK) >> REVID_SHIFT; | |
04cc058f | 1359 | if (rev >= 0x94) { |
e57725ea | 1360 | community->features |= PINCTRL_FEATURE_DEBOUNCE; |
04cc058f MW |
1361 | community->features |= PINCTRL_FEATURE_1K_PD; |
1362 | } | |
e57725ea MW |
1363 | } |
1364 | ||
7981c001 MW |
1365 | /* Read offset of the pad configuration registers */ |
1366 | padbar = readl(regs + PADBAR); | |
1367 | ||
1368 | community->regs = regs; | |
1369 | community->pad_regs = regs + padbar; | |
919eb475 | 1370 | |
cf769bd8 MW |
1371 | if (!community->is_offset) |
1372 | community->is_offset = GPI_IS; | |
1373 | ||
919eb475 MW |
1374 | ret = intel_pinctrl_add_padgroups(pctrl, community); |
1375 | if (ret) | |
1376 | return ret; | |
7981c001 MW |
1377 | } |
1378 | ||
1379 | irq = platform_get_irq(pdev, 0); | |
1380 | if (irq < 0) { | |
1381 | dev_err(&pdev->dev, "failed to get interrupt number\n"); | |
1382 | return irq; | |
1383 | } | |
1384 | ||
1385 | ret = intel_pinctrl_pm_init(pctrl); | |
1386 | if (ret) | |
1387 | return ret; | |
1388 | ||
1389 | pctrl->pctldesc = intel_pinctrl_desc; | |
1390 | pctrl->pctldesc.name = dev_name(&pdev->dev); | |
1391 | pctrl->pctldesc.pins = pctrl->soc->pins; | |
1392 | pctrl->pctldesc.npins = pctrl->soc->npins; | |
1393 | ||
54d46cd7 LD |
1394 | pctrl->pctldev = devm_pinctrl_register(&pdev->dev, &pctrl->pctldesc, |
1395 | pctrl); | |
323de9ef | 1396 | if (IS_ERR(pctrl->pctldev)) { |
7981c001 | 1397 | dev_err(&pdev->dev, "failed to register pinctrl driver\n"); |
323de9ef | 1398 | return PTR_ERR(pctrl->pctldev); |
7981c001 MW |
1399 | } |
1400 | ||
1401 | ret = intel_gpio_probe(pctrl, irq); | |
54d46cd7 | 1402 | if (ret) |
7981c001 | 1403 | return ret; |
7981c001 MW |
1404 | |
1405 | platform_set_drvdata(pdev, pctrl); | |
1406 | ||
1407 | return 0; | |
1408 | } | |
7981c001 | 1409 | |
70c263c4 AS |
1410 | int intel_pinctrl_probe_by_hid(struct platform_device *pdev) |
1411 | { | |
1412 | const struct intel_pinctrl_soc_data *data; | |
1413 | ||
1414 | data = device_get_match_data(&pdev->dev); | |
1415 | return intel_pinctrl_probe(pdev, data); | |
1416 | } | |
1417 | EXPORT_SYMBOL_GPL(intel_pinctrl_probe_by_hid); | |
1418 | ||
924cf800 AS |
1419 | int intel_pinctrl_probe_by_uid(struct platform_device *pdev) |
1420 | { | |
1421 | const struct intel_pinctrl_soc_data *data = NULL; | |
1422 | const struct intel_pinctrl_soc_data **table; | |
1423 | struct acpi_device *adev; | |
1424 | unsigned int i; | |
1425 | ||
1426 | adev = ACPI_COMPANION(&pdev->dev); | |
1427 | if (adev) { | |
1428 | const void *match = device_get_match_data(&pdev->dev); | |
1429 | ||
1430 | table = (const struct intel_pinctrl_soc_data **)match; | |
1431 | for (i = 0; table[i]; i++) { | |
1432 | if (!strcmp(adev->pnp.unique_id, table[i]->uid)) { | |
1433 | data = table[i]; | |
1434 | break; | |
1435 | } | |
1436 | } | |
1437 | } else { | |
1438 | const struct platform_device_id *id; | |
1439 | ||
1440 | id = platform_get_device_id(pdev); | |
1441 | if (!id) | |
1442 | return -ENODEV; | |
1443 | ||
1444 | table = (const struct intel_pinctrl_soc_data **)id->driver_data; | |
1445 | data = table[pdev->id]; | |
1446 | } | |
1447 | if (!data) | |
1448 | return -ENODEV; | |
1449 | ||
1450 | return intel_pinctrl_probe(pdev, data); | |
1451 | } | |
1452 | EXPORT_SYMBOL_GPL(intel_pinctrl_probe_by_uid); | |
1453 | ||
7981c001 | 1454 | #ifdef CONFIG_PM_SLEEP |
04035f7f | 1455 | static bool intel_pinctrl_should_save(struct intel_pinctrl *pctrl, unsigned int pin) |
c538b943 MW |
1456 | { |
1457 | const struct pin_desc *pd = pin_desc_get(pctrl->pctldev, pin); | |
1458 | ||
1459 | if (!pd || !intel_pad_usable(pctrl, pin)) | |
1460 | return false; | |
1461 | ||
1462 | /* | |
1463 | * Only restore the pin if it is actually in use by the kernel (or | |
1464 | * by userspace). It is possible that some pins are used by the | |
1465 | * BIOS during resume and those are not always locked down so leave | |
1466 | * them alone. | |
1467 | */ | |
1468 | if (pd->mux_owner || pd->gpio_owner || | |
eeb126fe | 1469 | gpiochip_line_is_irq(&pctrl->chip, intel_pin_to_gpio(pctrl, pin))) |
c538b943 MW |
1470 | return true; |
1471 | ||
1472 | return false; | |
1473 | } | |
1474 | ||
2fef3276 | 1475 | int intel_pinctrl_suspend_noirq(struct device *dev) |
7981c001 | 1476 | { |
cb035d74 | 1477 | struct intel_pinctrl *pctrl = dev_get_drvdata(dev); |
7981c001 MW |
1478 | struct intel_community_context *communities; |
1479 | struct intel_pad_context *pads; | |
1480 | int i; | |
1481 | ||
1482 | pads = pctrl->context.pads; | |
1483 | for (i = 0; i < pctrl->soc->npins; i++) { | |
1484 | const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i]; | |
e57725ea | 1485 | void __iomem *padcfg; |
7981c001 MW |
1486 | u32 val; |
1487 | ||
c538b943 | 1488 | if (!intel_pinctrl_should_save(pctrl, desc->number)) |
7981c001 MW |
1489 | continue; |
1490 | ||
1491 | val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG0)); | |
1492 | pads[i].padcfg0 = val & ~PADCFG0_GPIORXSTATE; | |
1493 | val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG1)); | |
1494 | pads[i].padcfg1 = val; | |
e57725ea MW |
1495 | |
1496 | padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG2); | |
1497 | if (padcfg) | |
1498 | pads[i].padcfg2 = readl(padcfg); | |
7981c001 MW |
1499 | } |
1500 | ||
1501 | communities = pctrl->context.communities; | |
1502 | for (i = 0; i < pctrl->ncommunities; i++) { | |
1503 | struct intel_community *community = &pctrl->communities[i]; | |
1504 | void __iomem *base; | |
04035f7f | 1505 | unsigned int gpp; |
7981c001 MW |
1506 | |
1507 | base = community->regs + community->ie_offset; | |
1508 | for (gpp = 0; gpp < community->ngpps; gpp++) | |
1509 | communities[i].intmask[gpp] = readl(base + gpp * 4); | |
a0a5f766 CC |
1510 | |
1511 | base = community->regs + community->hostown_offset; | |
1512 | for (gpp = 0; gpp < community->ngpps; gpp++) | |
1513 | communities[i].hostown[gpp] = readl(base + gpp * 4); | |
7981c001 MW |
1514 | } |
1515 | ||
1516 | return 0; | |
1517 | } | |
2fef3276 | 1518 | EXPORT_SYMBOL_GPL(intel_pinctrl_suspend_noirq); |
7981c001 | 1519 | |
f487bbf3 MW |
1520 | static void intel_gpio_irq_init(struct intel_pinctrl *pctrl) |
1521 | { | |
1522 | size_t i; | |
1523 | ||
1524 | for (i = 0; i < pctrl->ncommunities; i++) { | |
1525 | const struct intel_community *community; | |
1526 | void __iomem *base; | |
04035f7f | 1527 | unsigned int gpp; |
f487bbf3 MW |
1528 | |
1529 | community = &pctrl->communities[i]; | |
1530 | base = community->regs; | |
1531 | ||
1532 | for (gpp = 0; gpp < community->ngpps; gpp++) { | |
1533 | /* Mask and clear all interrupts */ | |
1534 | writel(0, base + community->ie_offset + gpp * 4); | |
cf769bd8 | 1535 | writel(0xffff, base + community->is_offset + gpp * 4); |
f487bbf3 MW |
1536 | } |
1537 | } | |
1538 | } | |
1539 | ||
a0a5f766 CC |
1540 | static u32 |
1541 | intel_gpio_is_requested(struct gpio_chip *chip, int base, unsigned int size) | |
1542 | { | |
1543 | u32 requested = 0; | |
1544 | unsigned int i; | |
1545 | ||
1546 | for (i = 0; i < size; i++) | |
1547 | if (gpiochip_is_requested(chip, base + i)) | |
1548 | requested |= BIT(i); | |
1549 | ||
1550 | return requested; | |
1551 | } | |
1552 | ||
1553 | static u32 | |
1554 | intel_gpio_update_pad_mode(void __iomem *hostown, u32 mask, u32 value) | |
1555 | { | |
5f61d951 | 1556 | u32 curr, updated; |
a0a5f766 | 1557 | |
5f61d951 AS |
1558 | curr = readl(hostown); |
1559 | updated = (curr & ~mask) | (value & mask); | |
a0a5f766 | 1560 | writel(updated, hostown); |
5f61d951 | 1561 | |
a0a5f766 CC |
1562 | return curr; |
1563 | } | |
1564 | ||
2fef3276 | 1565 | int intel_pinctrl_resume_noirq(struct device *dev) |
7981c001 | 1566 | { |
cb035d74 | 1567 | struct intel_pinctrl *pctrl = dev_get_drvdata(dev); |
7981c001 MW |
1568 | const struct intel_community_context *communities; |
1569 | const struct intel_pad_context *pads; | |
1570 | int i; | |
1571 | ||
1572 | /* Mask all interrupts */ | |
1573 | intel_gpio_irq_init(pctrl); | |
1574 | ||
1575 | pads = pctrl->context.pads; | |
1576 | for (i = 0; i < pctrl->soc->npins; i++) { | |
1577 | const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i]; | |
1578 | void __iomem *padcfg; | |
1579 | u32 val; | |
1580 | ||
c538b943 | 1581 | if (!intel_pinctrl_should_save(pctrl, desc->number)) |
7981c001 MW |
1582 | continue; |
1583 | ||
1584 | padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG0); | |
1585 | val = readl(padcfg) & ~PADCFG0_GPIORXSTATE; | |
1586 | if (val != pads[i].padcfg0) { | |
1587 | writel(pads[i].padcfg0, padcfg); | |
1588 | dev_dbg(dev, "restored pin %u padcfg0 %#08x\n", | |
1589 | desc->number, readl(padcfg)); | |
1590 | } | |
1591 | ||
1592 | padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG1); | |
1593 | val = readl(padcfg); | |
1594 | if (val != pads[i].padcfg1) { | |
1595 | writel(pads[i].padcfg1, padcfg); | |
1596 | dev_dbg(dev, "restored pin %u padcfg1 %#08x\n", | |
1597 | desc->number, readl(padcfg)); | |
1598 | } | |
e57725ea MW |
1599 | |
1600 | padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG2); | |
1601 | if (padcfg) { | |
1602 | val = readl(padcfg); | |
1603 | if (val != pads[i].padcfg2) { | |
1604 | writel(pads[i].padcfg2, padcfg); | |
1605 | dev_dbg(dev, "restored pin %u padcfg2 %#08x\n", | |
1606 | desc->number, readl(padcfg)); | |
1607 | } | |
1608 | } | |
7981c001 MW |
1609 | } |
1610 | ||
1611 | communities = pctrl->context.communities; | |
1612 | for (i = 0; i < pctrl->ncommunities; i++) { | |
1613 | struct intel_community *community = &pctrl->communities[i]; | |
1614 | void __iomem *base; | |
04035f7f | 1615 | unsigned int gpp; |
7981c001 MW |
1616 | |
1617 | base = community->regs + community->ie_offset; | |
1618 | for (gpp = 0; gpp < community->ngpps; gpp++) { | |
1619 | writel(communities[i].intmask[gpp], base + gpp * 4); | |
1620 | dev_dbg(dev, "restored mask %d/%u %#08x\n", i, gpp, | |
1621 | readl(base + gpp * 4)); | |
1622 | } | |
a0a5f766 CC |
1623 | |
1624 | base = community->regs + community->hostown_offset; | |
1625 | for (gpp = 0; gpp < community->ngpps; gpp++) { | |
1626 | const struct intel_padgroup *padgrp = &community->gpps[gpp]; | |
1627 | u32 requested = 0, value = 0; | |
1628 | u32 saved = communities[i].hostown[gpp]; | |
1629 | ||
1630 | if (padgrp->gpio_base < 0) | |
1631 | continue; | |
1632 | ||
1633 | requested = intel_gpio_is_requested(&pctrl->chip, | |
1634 | padgrp->gpio_base, padgrp->size); | |
1635 | value = intel_gpio_update_pad_mode(base + gpp * 4, | |
1636 | requested, saved); | |
1637 | if ((value ^ saved) & requested) { | |
1638 | dev_warn(dev, "restore hostown %d/%u %#8x->%#8x\n", | |
1639 | i, gpp, value, saved); | |
1640 | } | |
1641 | } | |
7981c001 MW |
1642 | } |
1643 | ||
1644 | return 0; | |
1645 | } | |
2fef3276 | 1646 | EXPORT_SYMBOL_GPL(intel_pinctrl_resume_noirq); |
7981c001 MW |
1647 | #endif |
1648 | ||
1649 | MODULE_AUTHOR("Mathias Nyman <mathias.nyman@linux.intel.com>"); | |
1650 | MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>"); | |
1651 | MODULE_DESCRIPTION("Intel pinctrl/GPIO core driver"); | |
1652 | MODULE_LICENSE("GPL v2"); |