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[mirror_ubuntu-artful-kernel.git] / drivers / pinctrl / mediatek / pinctrl-mtk-common.c
CommitLineData
a6df410d
HY		 1/*
2 * mt65xx pinctrl driver based on Allwinner A1X pinctrl driver.
3 * Copyright (c) 2014 MediaTek Inc.
4 * Author: Hongzhou.Yang <hongzhou.yang@mediatek.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/io.h>
11aa679a 17#include <linux/gpio/driver.h>
a6df410d
HY		 18#include <linux/module.h>
19#include <linux/of.h>
20#include <linux/of_address.h>
21#include <linux/of_device.h>
22#include <linux/of_irq.h>
23#include <linux/pinctrl/consumer.h>
24#include <linux/pinctrl/machine.h>
25#include <linux/pinctrl/pinconf.h>
26#include <linux/pinctrl/pinconf-generic.h>
27#include <linux/pinctrl/pinctrl.h>
28#include <linux/pinctrl/pinmux.h>
29#include <linux/platform_device.h>
30#include <linux/slab.h>
31#include <linux/bitops.h>
32#include <linux/regmap.h>
33#include <linux/mfd/syscon.h>
d9819eb9 34#include <linux/delay.h>
30f010f5 35#include <linux/interrupt.h>
58a5e1b6 36#include <linux/pm.h>
a6df410d
HY		 37#include <dt-bindings/pinctrl/mt65xx.h>
38
39#include "../core.h"
40#include "../pinconf.h"
41#include "../pinctrl-utils.h"
42#include "pinctrl-mtk-common.h"
43
44#define MAX_GPIO_MODE_PER_REG 5
45#define GPIO_MODE_BITS 3
59ee9c96 46#define GPIO_MODE_PREFIX "GPIO"
a6df410d
HY		 47
48static const char * const mtk_gpio_functions[] = {
49 "func0", "func1", "func2", "func3",
50 "func4", "func5", "func6", "func7",
148b95ee
BH		 51 "func8", "func9", "func10", "func11",
52 "func12", "func13", "func14", "func15",
a6df410d
HY		 53};
54
55/*
56 * There are two base address for pull related configuration
57 * in mt8135, and different GPIO pins use different base address.
58 * When pin number greater than type1_start and less than type1_end,
59 * should use the second base address.
60 */
61static struct regmap *mtk_get_regmap(struct mtk_pinctrl *pctl,
62 unsigned long pin)
63{
64 if (pin >= pctl->devdata->type1_start && pin < pctl->devdata->type1_end)
65 return pctl->regmap2;
66 return pctl->regmap1;
67}
68
69static unsigned int mtk_get_port(struct mtk_pinctrl *pctl, unsigned long pin)
70{
71 /* Different SoC has different mask and port shift. */
72 return ((pin >> 4) & pctl->devdata->port_mask)
73 << pctl->devdata->port_shf;
74}
75
76static int mtk_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
77 struct pinctrl_gpio_range *range, unsigned offset,
78 bool input)
79{
80 unsigned int reg_addr;
81 unsigned int bit;
82 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
83
84 reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dir_offset;
85 bit = BIT(offset & 0xf);
86
148b95ee
BH		 87 if (pctl->devdata->spec_dir_set)
88 pctl->devdata->spec_dir_set(&reg_addr, offset);
89
a6df410d
HY		 90 if (input)
91 /* Different SoC has different alignment offset. */
92 reg_addr = CLR_ADDR(reg_addr, pctl);
93 else
94 reg_addr = SET_ADDR(reg_addr, pctl);
95
96 regmap_write(mtk_get_regmap(pctl, offset), reg_addr, bit);
97 return 0;
98}
99
100static void mtk_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
101{
102 unsigned int reg_addr;
103 unsigned int bit;
11aa679a 104 struct mtk_pinctrl *pctl = gpiochip_get_data(chip);
a6df410d
HY		 105
106 reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dout_offset;
107 bit = BIT(offset & 0xf);
108
109 if (value)
110 reg_addr = SET_ADDR(reg_addr, pctl);
111 else
112 reg_addr = CLR_ADDR(reg_addr, pctl);
113
114 regmap_write(mtk_get_regmap(pctl, offset), reg_addr, bit);
115}
116
25d76b21
HY		 117static int mtk_pconf_set_ies_smt(struct mtk_pinctrl *pctl, unsigned pin,
118 int value, enum pin_config_param arg)
a6df410d
HY		 119{
120 unsigned int reg_addr, offset;
121 unsigned int bit;
25d76b21
HY		 122
123 /**
124 * Due to some soc are not support ies/smt config, add this special
125 * control to handle it.
126 */
127 if (!pctl->devdata->spec_ies_smt_set &&
128 pctl->devdata->ies_offset == MTK_PINCTRL_NOT_SUPPORT &&
129 arg == PIN_CONFIG_INPUT_ENABLE)
130 return -EINVAL;
131
132 if (!pctl->devdata->spec_ies_smt_set &&
133 pctl->devdata->smt_offset == MTK_PINCTRL_NOT_SUPPORT &&
134 arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE)
135 return -EINVAL;
30f010f5
HY		 136
137 /*
138 * Due to some pins are irregular, their input enable and smt
25d76b21 139 * control register are discontinuous, so we need this special handle.
30f010f5
HY		 140 */
141 if (pctl->devdata->spec_ies_smt_set) {
25d76b21
HY		 142 return pctl->devdata->spec_ies_smt_set(mtk_get_regmap(pctl, pin),
143 pin, pctl->devdata->port_align, value, arg);
30f010f5 144 }
a6df410d
HY		 145
146 bit = BIT(pin & 0xf);
147
25d76b21 148 if (arg == PIN_CONFIG_INPUT_ENABLE)
a6df410d
HY		 149 offset = pctl->devdata->ies_offset;
150 else
151 offset = pctl->devdata->smt_offset;
152
153 if (value)
154 reg_addr = SET_ADDR(mtk_get_port(pctl, pin) + offset, pctl);
155 else
156 reg_addr = CLR_ADDR(mtk_get_port(pctl, pin) + offset, pctl);
157
158 regmap_write(mtk_get_regmap(pctl, pin), reg_addr, bit);
25d76b21
HY		 159 return 0;
160}
161
162int mtk_pconf_spec_set_ies_smt_range(struct regmap *regmap,
163 const struct mtk_pin_ies_smt_set *ies_smt_infos, unsigned int info_num,
164 unsigned int pin, unsigned char align, int value)
165{
166 unsigned int i, reg_addr, bit;
167
168 for (i = 0; i < info_num; i++) {
169 if (pin >= ies_smt_infos[i].start &&
170 pin <= ies_smt_infos[i].end) {
171 break;
172 }
173 }
174
175 if (i == info_num)
176 return -EINVAL;
177
178 if (value)
179 reg_addr = ies_smt_infos[i].offset + align;
180 else
181 reg_addr = ies_smt_infos[i].offset + (align << 1);
182
183 bit = BIT(ies_smt_infos[i].bit);
184 regmap_write(regmap, reg_addr, bit);
185 return 0;
a6df410d
HY		 186}
187
188static const struct mtk_pin_drv_grp *mtk_find_pin_drv_grp_by_pin(
189 struct mtk_pinctrl *pctl, unsigned long pin) {
190 int i;
191
192 for (i = 0; i < pctl->devdata->n_pin_drv_grps; i++) {
193 const struct mtk_pin_drv_grp *pin_drv =
194 pctl->devdata->pin_drv_grp + i;
195 if (pin == pin_drv->pin)
196 return pin_drv;
197 }
198
199 return NULL;
200}
201
202static int mtk_pconf_set_driving(struct mtk_pinctrl *pctl,
203 unsigned int pin, unsigned char driving)
204{
205 const struct mtk_pin_drv_grp *pin_drv;
206 unsigned int val;
207 unsigned int bits, mask, shift;
208 const struct mtk_drv_group_desc *drv_grp;
209
210 if (pin >= pctl->devdata->npins)
211 return -EINVAL;
212
213 pin_drv = mtk_find_pin_drv_grp_by_pin(pctl, pin);
214 if (!pin_drv || pin_drv->grp > pctl->devdata->n_grp_cls)
215 return -EINVAL;
216
217 drv_grp = pctl->devdata->grp_desc + pin_drv->grp;
218 if (driving >= drv_grp->min_drv && driving <= drv_grp->max_drv
219 && !(driving % drv_grp->step)) {
220 val = driving / drv_grp->step - 1;
221 bits = drv_grp->high_bit - drv_grp->low_bit + 1;
222 mask = BIT(bits) - 1;
223 shift = pin_drv->bit + drv_grp->low_bit;
224 mask <<= shift;
225 val <<= shift;
226 return regmap_update_bits(mtk_get_regmap(pctl, pin),
227 pin_drv->offset, mask, val);
228 }
229
230 return -EINVAL;
231}
232
e73fe271
YC		 233int mtk_pctrl_spec_pull_set_samereg(struct regmap *regmap,
234 const struct mtk_pin_spec_pupd_set_samereg *pupd_infos,
235 unsigned int info_num, unsigned int pin,
236 unsigned char align, bool isup, unsigned int r1r0)
237{
238 unsigned int i;
239 unsigned int reg_pupd, reg_set, reg_rst;
240 unsigned int bit_pupd, bit_r0, bit_r1;
241 const struct mtk_pin_spec_pupd_set_samereg *spec_pupd_pin;
242 bool find = false;
243
244 for (i = 0; i < info_num; i++) {
245 if (pin == pupd_infos[i].pin) {
246 find = true;
247 break;
248 }
249 }
250
251 if (!find)
252 return -EINVAL;
253
254 spec_pupd_pin = pupd_infos + i;
255 reg_set = spec_pupd_pin->offset + align;
256 reg_rst = spec_pupd_pin->offset + (align << 1);
257
258 if (isup)
259 reg_pupd = reg_rst;
260 else
261 reg_pupd = reg_set;
262
263 bit_pupd = BIT(spec_pupd_pin->pupd_bit);
264 regmap_write(regmap, reg_pupd, bit_pupd);
265
266 bit_r0 = BIT(spec_pupd_pin->r0_bit);
267 bit_r1 = BIT(spec_pupd_pin->r1_bit);
268
269 switch (r1r0) {
270 case MTK_PUPD_SET_R1R0_00:
271 regmap_write(regmap, reg_rst, bit_r0);
272 regmap_write(regmap, reg_rst, bit_r1);
273 break;
274 case MTK_PUPD_SET_R1R0_01:
275 regmap_write(regmap, reg_set, bit_r0);
276 regmap_write(regmap, reg_rst, bit_r1);
277 break;
278 case MTK_PUPD_SET_R1R0_10:
279 regmap_write(regmap, reg_rst, bit_r0);
280 regmap_write(regmap, reg_set, bit_r1);
281 break;
282 case MTK_PUPD_SET_R1R0_11:
283 regmap_write(regmap, reg_set, bit_r0);
284 regmap_write(regmap, reg_set, bit_r1);
285 break;
286 default:
287 return -EINVAL;
288 }
289
290 return 0;
291}
292
a6df410d
HY		 293static int mtk_pconf_set_pull_select(struct mtk_pinctrl *pctl,
294 unsigned int pin, bool enable, bool isup, unsigned int arg)
295{
296 unsigned int bit;
297 unsigned int reg_pullen, reg_pullsel;
298 int ret;
299
300 /* Some pins' pull setting are very different,
301 * they have separate pull up/down bit, R0 and R1
302 * resistor bit, so we need this special handle.
303 */
304 if (pctl->devdata->spec_pull_set) {
305 ret = pctl->devdata->spec_pull_set(mtk_get_regmap(pctl, pin),
306 pin, pctl->devdata->port_align, isup, arg);
307 if (!ret)
308 return 0;
309 }
310
311 /* For generic pull config, default arg value should be 0 or 1. */
312 if (arg != 0 && arg != 1) {
313 dev_err(pctl->dev, "invalid pull-up argument %d on pin %d .\n",
314 arg, pin);
315 return -EINVAL;
316 }
317
318 bit = BIT(pin & 0xf);
319 if (enable)
320 reg_pullen = SET_ADDR(mtk_get_port(pctl, pin) +
321 pctl->devdata->pullen_offset, pctl);
322 else
323 reg_pullen = CLR_ADDR(mtk_get_port(pctl, pin) +
324 pctl->devdata->pullen_offset, pctl);
325
326 if (isup)
327 reg_pullsel = SET_ADDR(mtk_get_port(pctl, pin) +
328 pctl->devdata->pullsel_offset, pctl);
329 else
330 reg_pullsel = CLR_ADDR(mtk_get_port(pctl, pin) +
331 pctl->devdata->pullsel_offset, pctl);
332
333 regmap_write(mtk_get_regmap(pctl, pin), reg_pullen, bit);
334 regmap_write(mtk_get_regmap(pctl, pin), reg_pullsel, bit);
335 return 0;
336}
337
338static int mtk_pconf_parse_conf(struct pinctrl_dev *pctldev,
339 unsigned int pin, enum pin_config_param param,
340 enum pin_config_param arg)
341{
25d76b21 342 int ret = 0;
a6df410d
HY		 343 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
344
345 switch (param) {
346 case PIN_CONFIG_BIAS_DISABLE:
25d76b21 347 ret = mtk_pconf_set_pull_select(pctl, pin, false, false, arg);
a6df410d
HY		 348 break;
349 case PIN_CONFIG_BIAS_PULL_UP:
25d76b21 350 ret = mtk_pconf_set_pull_select(pctl, pin, true, true, arg);
a6df410d
HY		 351 break;
352 case PIN_CONFIG_BIAS_PULL_DOWN:
25d76b21 353 ret = mtk_pconf_set_pull_select(pctl, pin, true, false, arg);
a6df410d
HY		 354 break;
355 case PIN_CONFIG_INPUT_ENABLE:
25d76b21 356 ret = mtk_pconf_set_ies_smt(pctl, pin, arg, param);
a6df410d
HY		 357 break;
358 case PIN_CONFIG_OUTPUT:
359 mtk_gpio_set(pctl->chip, pin, arg);
25d76b21 360 ret = mtk_pmx_gpio_set_direction(pctldev, NULL, pin, false);
a6df410d
HY		 361 break;
362 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
25d76b21 363 ret = mtk_pconf_set_ies_smt(pctl, pin, arg, param);
a6df410d
HY		 364 break;
365 case PIN_CONFIG_DRIVE_STRENGTH:
25d76b21 366 ret = mtk_pconf_set_driving(pctl, pin, arg);
a6df410d
HY		 367 break;
368 default:
25d76b21 369 ret = -EINVAL;
a6df410d
HY		 370 }
371
25d76b21 372 return ret;
a6df410d
HY		 373}
374
375static int mtk_pconf_group_get(struct pinctrl_dev *pctldev,
376 unsigned group,
377 unsigned long *config)
378{
379 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
380
381 *config = pctl->groups[group].config;
382
383 return 0;
384}
385
386static int mtk_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
387 unsigned long *configs, unsigned num_configs)
388{
389 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
390 struct mtk_pinctrl_group *g = &pctl->groups[group];
25d76b21 391 int i, ret;
a6df410d
HY		 392
393 for (i = 0; i < num_configs; i++) {
25d76b21 394 ret = mtk_pconf_parse_conf(pctldev, g->pin,
a6df410d
HY		 395 pinconf_to_config_param(configs[i]),
396 pinconf_to_config_argument(configs[i]));
25d76b21
HY		 397 if (ret < 0)
398 return ret;
a6df410d
HY		 399
400 g->config = configs[i];
401 }
402
403 return 0;
404}
405
406static const struct pinconf_ops mtk_pconf_ops = {
407 .pin_config_group_get = mtk_pconf_group_get,
408 .pin_config_group_set = mtk_pconf_group_set,
409};
410
411static struct mtk_pinctrl_group *
412mtk_pctrl_find_group_by_pin(struct mtk_pinctrl *pctl, u32 pin)
413{
414 int i;
415
416 for (i = 0; i < pctl->ngroups; i++) {
417 struct mtk_pinctrl_group *grp = pctl->groups + i;
418
419 if (grp->pin == pin)
420 return grp;
421 }
422
423 return NULL;
424}
425
426static const struct mtk_desc_function *mtk_pctrl_find_function_by_pin(
427 struct mtk_pinctrl *pctl, u32 pin_num, u32 fnum)
428{
429 const struct mtk_desc_pin *pin = pctl->devdata->pins + pin_num;
430 const struct mtk_desc_function *func = pin->functions;
431
432 while (func && func->name) {
433 if (func->muxval == fnum)
434 return func;
435 func++;
436 }
437
438 return NULL;
439}
440
441static bool mtk_pctrl_is_function_valid(struct mtk_pinctrl *pctl,
442 u32 pin_num, u32 fnum)
443{
444 int i;
445
446 for (i = 0; i < pctl->devdata->npins; i++) {
447 const struct mtk_desc_pin *pin = pctl->devdata->pins + i;
448
449 if (pin->pin.number == pin_num) {
450 const struct mtk_desc_function *func =
451 pin->functions;
452
453 while (func && func->name) {
454 if (func->muxval == fnum)
455 return true;
456 func++;
457 }
458
459 break;
460 }
461 }
462
463 return false;
464}
465
466static int mtk_pctrl_dt_node_to_map_func(struct mtk_pinctrl *pctl,
467 u32 pin, u32 fnum, struct mtk_pinctrl_group *grp,
468 struct pinctrl_map **map, unsigned *reserved_maps,
469 unsigned *num_maps)
470{
471 bool ret;
472
473 if (*num_maps == *reserved_maps)
474 return -ENOSPC;
475
476 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
477 (*map)[*num_maps].data.mux.group = grp->name;
478
479 ret = mtk_pctrl_is_function_valid(pctl, pin, fnum);
480 if (!ret) {
481 dev_err(pctl->dev, "invalid function %d on pin %d .\n",
482 fnum, pin);
483 return -EINVAL;
484 }
485
486 (*map)[*num_maps].data.mux.function = mtk_gpio_functions[fnum];
487 (*num_maps)++;
488
489 return 0;
490}
491
492static int mtk_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
493 struct device_node *node,
494 struct pinctrl_map **map,
495 unsigned *reserved_maps,
496 unsigned *num_maps)
497{
498 struct property *pins;
499 u32 pinfunc, pin, func;
500 int num_pins, num_funcs, maps_per_pin;
501 unsigned long *configs;
502 unsigned int num_configs;
503 bool has_config = 0;
504 int i, err;
505 unsigned reserve = 0;
506 struct mtk_pinctrl_group *grp;
507 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
508
509 pins = of_find_property(node, "pinmux", NULL);
510 if (!pins) {
511 dev_err(pctl->dev, "missing pins property in node %s .\n",
512 node->name);
513 return -EINVAL;
514 }
515
c445cac3
HY		 516 err = pinconf_generic_parse_dt_config(node, pctldev, &configs,
517 &num_configs);
b04a23b0
HY		 518 if (err)
519 return err;
520
a6df410d
HY		 521 if (num_configs)
522 has_config = 1;
523
524 num_pins = pins->length / sizeof(u32);
525 num_funcs = num_pins;
526 maps_per_pin = 0;
527 if (num_funcs)
528 maps_per_pin++;
529 if (has_config && num_pins >= 1)
530 maps_per_pin++;
531
b04a23b0
HY		 532 if (!num_pins || !maps_per_pin) {
533 err = -EINVAL;
534 goto exit;
535 }
a6df410d
HY		 536
537 reserve = num_pins * maps_per_pin;
538
539 err = pinctrl_utils_reserve_map(pctldev, map,
540 reserved_maps, num_maps, reserve);
541 if (err < 0)
b04a23b0 542 goto exit;
a6df410d
HY		 543
544 for (i = 0; i < num_pins; i++) {
545 err = of_property_read_u32_index(node, "pinmux",
546 i, &pinfunc);
547 if (err)
b04a23b0 548 goto exit;
a6df410d
HY		 549
550 pin = MTK_GET_PIN_NO(pinfunc);
551 func = MTK_GET_PIN_FUNC(pinfunc);
552
553 if (pin >= pctl->devdata->npins ||
554 func >= ARRAY_SIZE(mtk_gpio_functions)) {
555 dev_err(pctl->dev, "invalid pins value.\n");
556 err = -EINVAL;
b04a23b0 557 goto exit;
a6df410d
HY		 558 }
559
560 grp = mtk_pctrl_find_group_by_pin(pctl, pin);
561 if (!grp) {
562 dev_err(pctl->dev, "unable to match pin %d to group\n",
563 pin);
b04a23b0
HY		 564 err = -EINVAL;
565 goto exit;
a6df410d
HY		 566 }
567
568 err = mtk_pctrl_dt_node_to_map_func(pctl, pin, func, grp, map,
569 reserved_maps, num_maps);
570 if (err < 0)
b04a23b0 571 goto exit;
a6df410d
HY		 572
573 if (has_config) {
574 err = pinctrl_utils_add_map_configs(pctldev, map,
575 reserved_maps, num_maps, grp->name,
576 configs, num_configs,
577 PIN_MAP_TYPE_CONFIGS_GROUP);
578 if (err < 0)
b04a23b0 579 goto exit;
a6df410d
HY		 580 }
581 }
582
b04a23b0 583 err = 0;
a6df410d 584
b04a23b0
HY		 585exit:
586 kfree(configs);
a6df410d
HY		 587 return err;
588}
589
590static int mtk_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
591 struct device_node *np_config,
592 struct pinctrl_map **map, unsigned *num_maps)
593{
594 struct device_node *np;
595 unsigned reserved_maps;
596 int ret;
597
598 *map = NULL;
599 *num_maps = 0;
600 reserved_maps = 0;
601
602 for_each_child_of_node(np_config, np) {
603 ret = mtk_pctrl_dt_subnode_to_map(pctldev, np, map,
604 &reserved_maps, num_maps);
605 if (ret < 0) {
606 pinctrl_utils_dt_free_map(pctldev, *map, *num_maps);
4fc8a4b2 607 of_node_put(np);
a6df410d
HY		 608 return ret;
609 }
610 }
611
612 return 0;
613}
614
615static int mtk_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
616{
617 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
618
619 return pctl->ngroups;
620}
621
622static const char *mtk_pctrl_get_group_name(struct pinctrl_dev *pctldev,
623 unsigned group)
624{
625 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
626
627 return pctl->groups[group].name;
628}
629
630static int mtk_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
631 unsigned group,
632 const unsigned **pins,
633 unsigned *num_pins)
634{
635 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
636
637 *pins = (unsigned *)&pctl->groups[group].pin;
638 *num_pins = 1;
639
640 return 0;
641}
642
643static const struct pinctrl_ops mtk_pctrl_ops = {
644 .dt_node_to_map = mtk_pctrl_dt_node_to_map,
645 .dt_free_map = pinctrl_utils_dt_free_map,
646 .get_groups_count = mtk_pctrl_get_groups_count,
647 .get_group_name = mtk_pctrl_get_group_name,
648 .get_group_pins = mtk_pctrl_get_group_pins,
649};
650
651static int mtk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
652{
653 return ARRAY_SIZE(mtk_gpio_functions);
654}
655
656static const char *mtk_pmx_get_func_name(struct pinctrl_dev *pctldev,
657 unsigned selector)
658{
659 return mtk_gpio_functions[selector];
660}
661
662static int mtk_pmx_get_func_groups(struct pinctrl_dev *pctldev,
663 unsigned function,
664 const char * const **groups,
665 unsigned * const num_groups)
666{
667 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
668
669 *groups = pctl->grp_names;
670 *num_groups = pctl->ngroups;
671
672 return 0;
673}
674
675static int mtk_pmx_set_mode(struct pinctrl_dev *pctldev,
676 unsigned long pin, unsigned long mode)
677{
678 unsigned int reg_addr;
679 unsigned char bit;
680 unsigned int val;
681 unsigned int mask = (1L << GPIO_MODE_BITS) - 1;
682 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
683
148b95ee
BH		 684 if (pctl->devdata->spec_pinmux_set)
685 pctl->devdata->spec_pinmux_set(mtk_get_regmap(pctl, pin),
686 pin, mode);
687
a6df410d
HY		 688 reg_addr = ((pin / MAX_GPIO_MODE_PER_REG) << pctl->devdata->port_shf)
689 + pctl->devdata->pinmux_offset;
690
148b95ee 691 mode &= mask;
a6df410d
HY		 692 bit = pin % MAX_GPIO_MODE_PER_REG;
693 mask <<= (GPIO_MODE_BITS * bit);
694 val = (mode << (GPIO_MODE_BITS * bit));
695 return regmap_update_bits(mtk_get_regmap(pctl, pin),
696 reg_addr, mask, val);
697}
698
d9819eb9
MM		 699static const struct mtk_desc_pin *
700mtk_find_pin_by_eint_num(struct mtk_pinctrl *pctl, unsigned int eint_num)
701{
702 int i;
703 const struct mtk_desc_pin *pin;
704
705 for (i = 0; i < pctl->devdata->npins; i++) {
706 pin = pctl->devdata->pins + i;
707 if (pin->eint.eintnum == eint_num)
708 return pin;
709 }
710
711 return NULL;
712}
713
a6df410d
HY		 714static int mtk_pmx_set_mux(struct pinctrl_dev *pctldev,
715 unsigned function,
716 unsigned group)
717{
718 bool ret;
719 const struct mtk_desc_function *desc;
720 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
721 struct mtk_pinctrl_group *g = pctl->groups + group;
722
723 ret = mtk_pctrl_is_function_valid(pctl, g->pin, function);
724 if (!ret) {
c70336cc 725 dev_err(pctl->dev, "invalid function %d on group %d .\n",
a6df410d
HY		 726 function, group);
727 return -EINVAL;
728 }
729
730 desc = mtk_pctrl_find_function_by_pin(pctl, g->pin, function);
731 if (!desc)
732 return -EINVAL;
733 mtk_pmx_set_mode(pctldev, g->pin, desc->muxval);
734 return 0;
735}
736
59ee9c96
BH		 737static int mtk_pmx_find_gpio_mode(struct mtk_pinctrl *pctl,
738 unsigned offset)
739{
740 const struct mtk_desc_pin *pin = pctl->devdata->pins + offset;
741 const struct mtk_desc_function *func = pin->functions;
742
743 while (func && func->name) {
744 if (!strncmp(func->name, GPIO_MODE_PREFIX,
745 sizeof(GPIO_MODE_PREFIX)-1))
746 return func->muxval;
747 func++;
748 }
749 return -EINVAL;
750}
751
752static int mtk_pmx_gpio_request_enable(struct pinctrl_dev *pctldev,
753 struct pinctrl_gpio_range *range,
754 unsigned offset)
755{
756 unsigned long muxval;
757 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
758
759 muxval = mtk_pmx_find_gpio_mode(pctl, offset);
760
761 if (muxval < 0) {
762 dev_err(pctl->dev, "invalid gpio pin %d.\n", offset);
763 return -EINVAL;
764 }
765
766 mtk_pmx_set_mode(pctldev, offset, muxval);
767
768 return 0;
769}
770
a6df410d
HY		 771static const struct pinmux_ops mtk_pmx_ops = {
772 .get_functions_count = mtk_pmx_get_funcs_cnt,
773 .get_function_name = mtk_pmx_get_func_name,
774 .get_function_groups = mtk_pmx_get_func_groups,
775 .set_mux = mtk_pmx_set_mux,
776 .gpio_set_direction = mtk_pmx_gpio_set_direction,
59ee9c96 777 .gpio_request_enable = mtk_pmx_gpio_request_enable,
a6df410d
HY		 778};
779
a6df410d
HY		 780static int mtk_gpio_direction_input(struct gpio_chip *chip,
781 unsigned offset)
782{
783 return pinctrl_gpio_direction_input(chip->base + offset);
784}
785
786static int mtk_gpio_direction_output(struct gpio_chip *chip,
787 unsigned offset, int value)
788{
789 mtk_gpio_set(chip, offset, value);
790 return pinctrl_gpio_direction_output(chip->base + offset);
791}
792
793static int mtk_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
794{
795 unsigned int reg_addr;
796 unsigned int bit;
797 unsigned int read_val = 0;
798
11aa679a 799 struct mtk_pinctrl *pctl = gpiochip_get_data(chip);
a6df410d
HY		 800
801 reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dir_offset;
802 bit = BIT(offset & 0xf);
148b95ee
BH		 803
804 if (pctl->devdata->spec_dir_set)
805 pctl->devdata->spec_dir_set(&reg_addr, offset);
806
a6df410d 807 regmap_read(pctl->regmap1, reg_addr, &read_val);
f97c2309 808 return !(read_val & bit);
a6df410d
HY		 809}
810
811static int mtk_gpio_get(struct gpio_chip *chip, unsigned offset)
812{
813 unsigned int reg_addr;
814 unsigned int bit;
815 unsigned int read_val = 0;
11aa679a 816 struct mtk_pinctrl *pctl = gpiochip_get_data(chip);
a6df410d 817
f97c2309
HY		 818 reg_addr = mtk_get_port(pctl, offset) +
819 pctl->devdata->din_offset;
a6df410d
HY		 820
821 bit = BIT(offset & 0xf);
822 regmap_read(pctl->regmap1, reg_addr, &read_val);
823 return !!(read_val & bit);
824}
825
d9819eb9
MM		 826static int mtk_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
827{
828 const struct mtk_desc_pin *pin;
11aa679a 829 struct mtk_pinctrl *pctl = gpiochip_get_data(chip);
d9819eb9
MM		 830 int irq;
831
832 pin = pctl->devdata->pins + offset;
833 if (pin->eint.eintnum == NO_EINT_SUPPORT)
834 return -EINVAL;
835
836 irq = irq_find_mapping(pctl->domain, pin->eint.eintnum);
837 if (!irq)
838 return -EINVAL;
839
840 return irq;
841}
842
843static int mtk_pinctrl_irq_request_resources(struct irq_data *d)
844{
845 struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
846 const struct mtk_desc_pin *pin;
847 int ret;
848
849 pin = mtk_find_pin_by_eint_num(pctl, d->hwirq);
850
851 if (!pin) {
852 dev_err(pctl->dev, "Can not find pin\n");
853 return -EINVAL;
854 }
855
856 ret = gpiochip_lock_as_irq(pctl->chip, pin->pin.number);
857 if (ret) {
858 dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n",
859 irqd_to_hwirq(d));
860 return ret;
861 }
862
863 /* set mux to INT mode */
864 mtk_pmx_set_mode(pctl->pctl_dev, pin->pin.number, pin->eint.eintmux);
865
866 return 0;
867}
868
869static void mtk_pinctrl_irq_release_resources(struct irq_data *d)
870{
871 struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
872 const struct mtk_desc_pin *pin;
873
874 pin = mtk_find_pin_by_eint_num(pctl, d->hwirq);
875
876 if (!pin) {
877 dev_err(pctl->dev, "Can not find pin\n");
878 return;
879 }
880
881 gpiochip_unlock_as_irq(pctl->chip, pin->pin.number);
882}
883
884static void __iomem *mtk_eint_get_offset(struct mtk_pinctrl *pctl,
885 unsigned int eint_num, unsigned int offset)
886{
887 unsigned int eint_base = 0;
888 void __iomem *reg;
889
890 if (eint_num >= pctl->devdata->ap_num)
891 eint_base = pctl->devdata->ap_num;
892
893 reg = pctl->eint_reg_base + offset + ((eint_num - eint_base) / 32) * 4;
894
895 return reg;
896}
897
898/*
899 * mtk_can_en_debounce: Check the EINT number is able to enable debounce or not
900 * @eint_num: the EINT number to setmtk_pinctrl
901 */
902static unsigned int mtk_eint_can_en_debounce(struct mtk_pinctrl *pctl,
903 unsigned int eint_num)
904{
905 unsigned int sens;
906 unsigned int bit = BIT(eint_num % 32);
907 const struct mtk_eint_offsets *eint_offsets =
908 &pctl->devdata->eint_offsets;
909
910 void __iomem *reg = mtk_eint_get_offset(pctl, eint_num,
911 eint_offsets->sens);
912
913 if (readl(reg) & bit)
914 sens = MT_LEVEL_SENSITIVE;
915 else
916 sens = MT_EDGE_SENSITIVE;
917
918 if ((eint_num < pctl->devdata->db_cnt) && (sens != MT_EDGE_SENSITIVE))
919 return 1;
920 else
921 return 0;
922}
923
924/*
925 * mtk_eint_get_mask: To get the eint mask
926 * @eint_num: the EINT number to get
927 */
928static unsigned int mtk_eint_get_mask(struct mtk_pinctrl *pctl,
929 unsigned int eint_num)
930{
931 unsigned int bit = BIT(eint_num % 32);
932 const struct mtk_eint_offsets *eint_offsets =
933 &pctl->devdata->eint_offsets;
934
935 void __iomem *reg = mtk_eint_get_offset(pctl, eint_num,
936 eint_offsets->mask);
937
938 return !!(readl(reg) & bit);
939}
940
3221f40b
YC		 941static int mtk_eint_flip_edge(struct mtk_pinctrl *pctl, int hwirq)
942{
943 int start_level, curr_level;
944 unsigned int reg_offset;
945 const struct mtk_eint_offsets *eint_offsets = &(pctl->devdata->eint_offsets);
b4b05b9a 946 u32 mask = BIT(hwirq & 0x1f);
3221f40b
YC		 947 u32 port = (hwirq >> 5) & eint_offsets->port_mask;
948 void __iomem *reg = pctl->eint_reg_base + (port << 2);
949 const struct mtk_desc_pin *pin;
950
951 pin = mtk_find_pin_by_eint_num(pctl, hwirq);
952 curr_level = mtk_gpio_get(pctl->chip, pin->pin.number);
953 do {
954 start_level = curr_level;
955 if (start_level)
956 reg_offset = eint_offsets->pol_clr;
957 else
958 reg_offset = eint_offsets->pol_set;
959 writel(mask, reg + reg_offset);
960
961 curr_level = mtk_gpio_get(pctl->chip, pin->pin.number);
962 } while (start_level != curr_level);
963
964 return start_level;
965}
966
d9819eb9
MM		 967static void mtk_eint_mask(struct irq_data *d)
968{
969 struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
970 const struct mtk_eint_offsets *eint_offsets =
971 &pctl->devdata->eint_offsets;
972 u32 mask = BIT(d->hwirq & 0x1f);
973 void __iomem *reg = mtk_eint_get_offset(pctl, d->hwirq,
974 eint_offsets->mask_set);
975
976 writel(mask, reg);
977}
978
979static void mtk_eint_unmask(struct irq_data *d)
980{
981 struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
982 const struct mtk_eint_offsets *eint_offsets =
983 &pctl->devdata->eint_offsets;
984 u32 mask = BIT(d->hwirq & 0x1f);
985 void __iomem *reg = mtk_eint_get_offset(pctl, d->hwirq,
986 eint_offsets->mask_clr);
987
988 writel(mask, reg);
3221f40b
YC		 989
990 if (pctl->eint_dual_edges[d->hwirq])
991 mtk_eint_flip_edge(pctl, d->hwirq);
d9819eb9
MM		 992}
993
994static int mtk_gpio_set_debounce(struct gpio_chip *chip, unsigned offset,
995 unsigned debounce)
996{
58383c78 997 struct mtk_pinctrl *pctl = dev_get_drvdata(chip->parent);
d9819eb9
MM		 998 int eint_num, virq, eint_offset;
999 unsigned int set_offset, bit, clr_bit, clr_offset, rst, i, unmask, dbnc;
1000 static const unsigned int dbnc_arr[] = {0 , 1, 16, 32, 64, 128, 256};
1001 const struct mtk_desc_pin *pin;
1002 struct irq_data *d;
1003
1004 pin = pctl->devdata->pins + offset;
1005 if (pin->eint.eintnum == NO_EINT_SUPPORT)
1006 return -EINVAL;
1007
1008 eint_num = pin->eint.eintnum;
1009 virq = irq_find_mapping(pctl->domain, eint_num);
1010 eint_offset = (eint_num % 4) * 8;
1011 d = irq_get_irq_data(virq);
1012
1013 set_offset = (eint_num / 4) * 4 + pctl->devdata->eint_offsets.dbnc_set;
1014 clr_offset = (eint_num / 4) * 4 + pctl->devdata->eint_offsets.dbnc_clr;
1015 if (!mtk_eint_can_en_debounce(pctl, eint_num))
1016 return -ENOSYS;
1017
1018 dbnc = ARRAY_SIZE(dbnc_arr);
1019 for (i = 0; i < ARRAY_SIZE(dbnc_arr); i++) {
1020 if (debounce <= dbnc_arr[i]) {
1021 dbnc = i;
1022 break;
1023 }
1024 }
1025
1026 if (!mtk_eint_get_mask(pctl, eint_num)) {
1027 mtk_eint_mask(d);
1028 unmask = 1;
74d77e50
CIK		 1029 } else {
1030 unmask = 0;
d9819eb9
MM		 1031 }
1032
1033 clr_bit = 0xff << eint_offset;
1034 writel(clr_bit, pctl->eint_reg_base + clr_offset);
1035
1036 bit = ((dbnc << EINT_DBNC_SET_DBNC_BITS) | EINT_DBNC_SET_EN) <<
1037 eint_offset;
1038 rst = EINT_DBNC_RST_BIT << eint_offset;
1039 writel(rst | bit, pctl->eint_reg_base + set_offset);
1040
1041 /* Delay a while (more than 2T) to wait for hw debounce counter reset
1042 work correctly */
1043 udelay(1);
1044 if (unmask == 1)
1045 mtk_eint_unmask(d);
1046
1047 return 0;
1048}
1049
a6df410d
HY		 1050static struct gpio_chip mtk_gpio_chip = {
1051 .owner = THIS_MODULE,
98c85d58
JG		 1052 .request = gpiochip_generic_request,
1053 .free = gpiochip_generic_free,
f97c2309 1054 .get_direction = mtk_gpio_get_direction,
a6df410d
HY		 1055 .direction_input = mtk_gpio_direction_input,
1056 .direction_output = mtk_gpio_direction_output,
1057 .get = mtk_gpio_get,
1058 .set = mtk_gpio_set,
d9819eb9
MM		 1059 .to_irq = mtk_gpio_to_irq,
1060 .set_debounce = mtk_gpio_set_debounce,
a6df410d
HY		 1061 .of_gpio_n_cells = 2,
1062};
1063
d9819eb9
MM		 1064static int mtk_eint_set_type(struct irq_data *d,
1065 unsigned int type)
1066{
1067 struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
1068 const struct mtk_eint_offsets *eint_offsets =
1069 &pctl->devdata->eint_offsets;
1070 u32 mask = BIT(d->hwirq & 0x1f);
1071 void __iomem *reg;
1072
1073 if (((type & IRQ_TYPE_EDGE_BOTH) && (type & IRQ_TYPE_LEVEL_MASK)) ||
d9819eb9
MM		 1074 ((type & IRQ_TYPE_LEVEL_MASK) == IRQ_TYPE_LEVEL_MASK)) {
1075 dev_err(pctl->dev, "Can't configure IRQ%d (EINT%lu) for type 0x%X\n",
1076 d->irq, d->hwirq, type);
1077 return -EINVAL;
1078 }
1079
3221f40b
YC		 1080 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
1081 pctl->eint_dual_edges[d->hwirq] = 1;
1082 else
1083 pctl->eint_dual_edges[d->hwirq] = 0;
1084
d9819eb9
MM		 1085 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING)) {
1086 reg = mtk_eint_get_offset(pctl, d->hwirq,
1087 eint_offsets->pol_clr);
1088 writel(mask, reg);
1089 } else {
1090 reg = mtk_eint_get_offset(pctl, d->hwirq,
1091 eint_offsets->pol_set);
1092 writel(mask, reg);
1093 }
1094
1095 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
1096 reg = mtk_eint_get_offset(pctl, d->hwirq,
1097 eint_offsets->sens_clr);
1098 writel(mask, reg);
1099 } else {
1100 reg = mtk_eint_get_offset(pctl, d->hwirq,
1101 eint_offsets->sens_set);
1102 writel(mask, reg);
1103 }
1104
3221f40b
YC		 1105 if (pctl->eint_dual_edges[d->hwirq])
1106 mtk_eint_flip_edge(pctl, d->hwirq);
1107
d9819eb9
MM		 1108 return 0;
1109}
1110
58a5e1b6
MM		 1111static int mtk_eint_irq_set_wake(struct irq_data *d, unsigned int on)
1112{
1113 struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
1114 int shift = d->hwirq & 0x1f;
1115 int reg = d->hwirq >> 5;
1116
1117 if (on)
1118 pctl->wake_mask[reg] |= BIT(shift);
1119 else
1120 pctl->wake_mask[reg] &= ~BIT(shift);
1121
1122 return 0;
1123}
1124
1125static void mtk_eint_chip_write_mask(const struct mtk_eint_offsets *chip,
1126 void __iomem *eint_reg_base, u32 *buf)
1127{
1128 int port;
1129 void __iomem *reg;
1130
1131 for (port = 0; port < chip->ports; port++) {
1132 reg = eint_reg_base + (port << 2);
1133 writel_relaxed(~buf[port], reg + chip->mask_set);
1134 writel_relaxed(buf[port], reg + chip->mask_clr);
1135 }
1136}
1137
1138static void mtk_eint_chip_read_mask(const struct mtk_eint_offsets *chip,
1139 void __iomem *eint_reg_base, u32 *buf)
1140{
1141 int port;
1142 void __iomem *reg;
1143
1144 for (port = 0; port < chip->ports; port++) {
1145 reg = eint_reg_base + chip->mask + (port << 2);
1146 buf[port] = ~readl_relaxed(reg);
1147 /* Mask is 0 when irq is enabled, and 1 when disabled. */
1148 }
1149}
1150
1151static int mtk_eint_suspend(struct device *device)
1152{
1153 void __iomem *reg;
1154 struct mtk_pinctrl *pctl = dev_get_drvdata(device);
1155 const struct mtk_eint_offsets *eint_offsets =
1156 &pctl->devdata->eint_offsets;
1157
1158 reg = pctl->eint_reg_base;
1159 mtk_eint_chip_read_mask(eint_offsets, reg, pctl->cur_mask);
1160 mtk_eint_chip_write_mask(eint_offsets, reg, pctl->wake_mask);
1161
1162 return 0;
1163}
1164
1165static int mtk_eint_resume(struct device *device)
1166{
1167 struct mtk_pinctrl *pctl = dev_get_drvdata(device);
1168 const struct mtk_eint_offsets *eint_offsets =
1169 &pctl->devdata->eint_offsets;
1170
1171 mtk_eint_chip_write_mask(eint_offsets,
1172 pctl->eint_reg_base, pctl->cur_mask);
1173
1174 return 0;
1175}
1176
1177const struct dev_pm_ops mtk_eint_pm_ops = {
1178 .suspend = mtk_eint_suspend,
1179 .resume = mtk_eint_resume,
1180};
1181
d9819eb9
MM		 1182static void mtk_eint_ack(struct irq_data *d)
1183{
1184 struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
1185 const struct mtk_eint_offsets *eint_offsets =
1186 &pctl->devdata->eint_offsets;
1187 u32 mask = BIT(d->hwirq & 0x1f);
1188 void __iomem *reg = mtk_eint_get_offset(pctl, d->hwirq,
1189 eint_offsets->ack);
1190
1191 writel(mask, reg);
1192}
1193
1194static struct irq_chip mtk_pinctrl_irq_chip = {
1195 .name = "mt-eint",
58a5e1b6 1196 .irq_disable = mtk_eint_mask,
d9819eb9
MM		 1197 .irq_mask = mtk_eint_mask,
1198 .irq_unmask = mtk_eint_unmask,
1199 .irq_ack = mtk_eint_ack,
1200 .irq_set_type = mtk_eint_set_type,
58a5e1b6 1201 .irq_set_wake = mtk_eint_irq_set_wake,
d9819eb9
MM		 1202 .irq_request_resources = mtk_pinctrl_irq_request_resources,
1203 .irq_release_resources = mtk_pinctrl_irq_release_resources,
1204};
1205
1206static unsigned int mtk_eint_init(struct mtk_pinctrl *pctl)
1207{
1208 const struct mtk_eint_offsets *eint_offsets =
1209 &pctl->devdata->eint_offsets;
1210 void __iomem *reg = pctl->eint_reg_base + eint_offsets->dom_en;
1211 unsigned int i;
1212
1213 for (i = 0; i < pctl->devdata->ap_num; i += 32) {
1214 writel(0xffffffff, reg);
1215 reg += 4;
1216 }
1217 return 0;
1218}
1219
1220static inline void
1221mtk_eint_debounce_process(struct mtk_pinctrl *pctl, int index)
1222{
1223 unsigned int rst, ctrl_offset;
1224 unsigned int bit, dbnc;
1225 const struct mtk_eint_offsets *eint_offsets =
1226 &pctl->devdata->eint_offsets;
1227
1228 ctrl_offset = (index / 4) * 4 + eint_offsets->dbnc_ctrl;
1229 dbnc = readl(pctl->eint_reg_base + ctrl_offset);
1230 bit = EINT_DBNC_SET_EN << ((index % 4) * 8);
1231 if ((bit & dbnc) > 0) {
1232 ctrl_offset = (index / 4) * 4 + eint_offsets->dbnc_set;
1233 rst = EINT_DBNC_RST_BIT << ((index % 4) * 8);
1234 writel(rst, pctl->eint_reg_base + ctrl_offset);
1235 }
1236}
1237
bd0b9ac4 1238static void mtk_eint_irq_handler(struct irq_desc *desc)
d9819eb9 1239{
5663bb27
JL		 1240 struct irq_chip *chip = irq_desc_get_chip(desc);
1241 struct mtk_pinctrl *pctl = irq_desc_get_handler_data(desc);
d9819eb9
MM		 1242 unsigned int status, eint_num;
1243 int offset, index, virq;
1244 const struct mtk_eint_offsets *eint_offsets =
1245 &pctl->devdata->eint_offsets;
1246 void __iomem *reg = mtk_eint_get_offset(pctl, 0, eint_offsets->stat);
3221f40b
YC		 1247 int dual_edges, start_level, curr_level;
1248 const struct mtk_desc_pin *pin;
d9819eb9
MM		 1249
1250 chained_irq_enter(chip, desc);
1251 for (eint_num = 0; eint_num < pctl->devdata->ap_num; eint_num += 32) {
1252 status = readl(reg);
1253 reg += 4;
1254 while (status) {
1255 offset = __ffs(status);
1256 index = eint_num + offset;
1257 virq = irq_find_mapping(pctl->domain, index);
1258 status &= ~BIT(offset);
1259
3221f40b
YC		 1260 dual_edges = pctl->eint_dual_edges[index];
1261 if (dual_edges) {
1262 /* Clear soft-irq in case we raised it
1263 last time */
1264 writel(BIT(offset), reg - eint_offsets->stat +
1265 eint_offsets->soft_clr);
1266
1267 pin = mtk_find_pin_by_eint_num(pctl, index);
1268 start_level = mtk_gpio_get(pctl->chip,
1269 pin->pin.number);
1270 }
1271
d9819eb9
MM		 1272 generic_handle_irq(virq);
1273
3221f40b
YC		 1274 if (dual_edges) {
1275 curr_level = mtk_eint_flip_edge(pctl, index);
1276
1277 /* If level changed, we might lost one edge
1278 interrupt, raised it through soft-irq */
1279 if (start_level != curr_level)
1280 writel(BIT(offset), reg -
1281 eint_offsets->stat +
1282 eint_offsets->soft_set);
1283 }
1284
d9819eb9
MM		 1285 if (index < pctl->devdata->db_cnt)
1286 mtk_eint_debounce_process(pctl , index);
1287 }
1288 }
1289 chained_irq_exit(chip, desc);
1290}
1291
a6df410d
HY		 1292static int mtk_pctrl_build_state(struct platform_device *pdev)
1293{
1294 struct mtk_pinctrl *pctl = platform_get_drvdata(pdev);
1295 int i;
1296
1297 pctl->ngroups = pctl->devdata->npins;
1298
1299 /* Allocate groups */
0206caa8
AL		 1300 pctl->groups = devm_kcalloc(&pdev->dev, pctl->ngroups,
1301 sizeof(*pctl->groups), GFP_KERNEL);
a6df410d
HY		 1302 if (!pctl->groups)
1303 return -ENOMEM;
1304
1305 /* We assume that one pin is one group, use pin name as group name. */
0206caa8
AL		 1306 pctl->grp_names = devm_kcalloc(&pdev->dev, pctl->ngroups,
1307 sizeof(*pctl->grp_names), GFP_KERNEL);
a6df410d
HY		 1308 if (!pctl->grp_names)
1309 return -ENOMEM;
1310
1311 for (i = 0; i < pctl->devdata->npins; i++) {
1312 const struct mtk_desc_pin *pin = pctl->devdata->pins + i;
1313 struct mtk_pinctrl_group *group = pctl->groups + i;
1314
1315 group->name = pin->pin.name;
1316 group->pin = pin->pin.number;
1317
1318 pctl->grp_names[i] = pin->pin.name;
1319 }
1320
1321 return 0;
1322}
1323
a6df410d 1324int mtk_pctrl_init(struct platform_device *pdev,
fc59e66c
HY		 1325 const struct mtk_pinctrl_devdata *data,
1326 struct regmap *regmap)
a6df410d
HY		 1327{
1328 struct pinctrl_pin_desc *pins;
1329 struct mtk_pinctrl *pctl;
1330 struct device_node *np = pdev->dev.of_node, *node;
1331 struct property *prop;
d9819eb9 1332 struct resource *res;
58a5e1b6 1333 int i, ret, irq, ports_buf;
a6df410d
HY		 1334
1335 pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
1336 if (!pctl)
1337 return -ENOMEM;
1338
1339 platform_set_drvdata(pdev, pctl);
1340
1341 prop = of_find_property(np, "pins-are-numbered", NULL);
1342 if (!prop) {
c445cac3 1343 dev_err(&pdev->dev, "only support pins-are-numbered format\n");
a6df410d
HY		 1344 return -EINVAL;
1345 }
1346
1347 node = of_parse_phandle(np, "mediatek,pctl-regmap", 0);
1348 if (node) {
1349 pctl->regmap1 = syscon_node_to_regmap(node);
1350 if (IS_ERR(pctl->regmap1))
1351 return PTR_ERR(pctl->regmap1);
fc59e66c
HY		 1352 } else if (regmap) {
1353 pctl->regmap1 = regmap;
1354 } else {
1355 dev_err(&pdev->dev, "Pinctrl node has not register regmap.\n");
1356 return -EINVAL;
a6df410d
HY		 1357 }
1358
1359 /* Only 8135 has two base addr, other SoCs have only one. */
1360 node = of_parse_phandle(np, "mediatek,pctl-regmap", 1);
1361 if (node) {
1362 pctl->regmap2 = syscon_node_to_regmap(node);
1363 if (IS_ERR(pctl->regmap2))
1364 return PTR_ERR(pctl->regmap2);
1365 }
1366
1367 pctl->devdata = data;
1368 ret = mtk_pctrl_build_state(pdev);
1369 if (ret) {
1370 dev_err(&pdev->dev, "build state failed: %d\n", ret);
1371 return -EINVAL;
1372 }
1373
0206caa8 1374 pins = devm_kcalloc(&pdev->dev, pctl->devdata->npins, sizeof(*pins),
a6df410d
HY		 1375 GFP_KERNEL);
1376 if (!pins)
1377 return -ENOMEM;
1378
1379 for (i = 0; i < pctl->devdata->npins; i++)
1380 pins[i] = pctl->devdata->pins[i].pin;
d48c2c02
HY		 1381
1382 pctl->pctl_desc.name = dev_name(&pdev->dev);
1383 pctl->pctl_desc.owner = THIS_MODULE;
1384 pctl->pctl_desc.pins = pins;
1385 pctl->pctl_desc.npins = pctl->devdata->npins;
1386 pctl->pctl_desc.confops = &mtk_pconf_ops;
1387 pctl->pctl_desc.pctlops = &mtk_pctrl_ops;
1388 pctl->pctl_desc.pmxops = &mtk_pmx_ops;
a6df410d 1389 pctl->dev = &pdev->dev;
d48c2c02
HY		 1390
1391 pctl->pctl_dev = pinctrl_register(&pctl->pctl_desc, &pdev->dev, pctl);
323de9ef 1392 if (IS_ERR(pctl->pctl_dev)) {
a6df410d 1393 dev_err(&pdev->dev, "couldn't register pinctrl driver\n");
323de9ef 1394 return PTR_ERR(pctl->pctl_dev);
a6df410d
HY		 1395 }
1396
1397 pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL);
1398 if (!pctl->chip) {
1399 ret = -ENOMEM;
1400 goto pctrl_error;
1401 }
1402
fc63d854 1403 *pctl->chip = mtk_gpio_chip;
a6df410d
HY		 1404 pctl->chip->ngpio = pctl->devdata->npins;
1405 pctl->chip->label = dev_name(&pdev->dev);
58383c78 1406 pctl->chip->parent = &pdev->dev;
fc59e66c 1407 pctl->chip->base = -1;
a6df410d 1408
11aa679a 1409 ret = gpiochip_add_data(pctl->chip, pctl);
a6df410d
HY		 1410 if (ret) {
1411 ret = -EINVAL;
1412 goto pctrl_error;
1413 }
1414
1415 /* Register the GPIO to pin mappings. */
1416 ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev),
1417 0, 0, pctl->devdata->npins);
1418 if (ret) {
1419 ret = -EINVAL;
1420 goto chip_error;
1421 }
1422
fc63d854 1423 if (!of_property_read_bool(np, "interrupt-controller"))
fc59e66c
HY		 1424 return 0;
1425
d9819eb9
MM		 1426 /* Get EINT register base from dts. */
1427 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1428 if (!res) {
1429 dev_err(&pdev->dev, "Unable to get Pinctrl resource\n");
1430 ret = -EINVAL;
1431 goto chip_error;
1432 }
1433
1434 pctl->eint_reg_base = devm_ioremap_resource(&pdev->dev, res);
1435 if (IS_ERR(pctl->eint_reg_base)) {
1436 ret = -EINVAL;
1437 goto chip_error;
1438 }
1439
58a5e1b6
MM		 1440 ports_buf = pctl->devdata->eint_offsets.ports;
1441 pctl->wake_mask = devm_kcalloc(&pdev->dev, ports_buf,
1442 sizeof(*pctl->wake_mask), GFP_KERNEL);
1443 if (!pctl->wake_mask) {
1444 ret = -ENOMEM;
1445 goto chip_error;
1446 }
1447
1448 pctl->cur_mask = devm_kcalloc(&pdev->dev, ports_buf,
1449 sizeof(*pctl->cur_mask), GFP_KERNEL);
1450 if (!pctl->cur_mask) {
1451 ret = -ENOMEM;
1452 goto chip_error;
1453 }
1454
0206caa8
AL		 1455 pctl->eint_dual_edges = devm_kcalloc(&pdev->dev, pctl->devdata->ap_num,
1456 sizeof(int), GFP_KERNEL);
3221f40b
YC		 1457 if (!pctl->eint_dual_edges) {
1458 ret = -ENOMEM;
1459 goto chip_error;
1460 }
1461
d9819eb9
MM		 1462 irq = irq_of_parse_and_map(np, 0);
1463 if (!irq) {
1464 dev_err(&pdev->dev, "couldn't parse and map irq\n");
1465 ret = -EINVAL;
61a35576 1466 goto chip_error;
d9819eb9
MM		 1467 }
1468
1469 pctl->domain = irq_domain_add_linear(np,
1470 pctl->devdata->ap_num, &irq_domain_simple_ops, NULL);
1471 if (!pctl->domain) {
1472 dev_err(&pdev->dev, "Couldn't register IRQ domain\n");
1473 ret = -ENOMEM;
61a35576 1474 goto chip_error;
d9819eb9
MM		 1475 }
1476
1477 mtk_eint_init(pctl);
1478 for (i = 0; i < pctl->devdata->ap_num; i++) {
1479 int virq = irq_create_mapping(pctl->domain, i);
1480
1481 irq_set_chip_and_handler(virq, &mtk_pinctrl_irq_chip,
1482 handle_level_irq);
1483 irq_set_chip_data(virq, pctl);
e4411899 1484 }
d9819eb9 1485
1e105921 1486 irq_set_chained_handler_and_data(irq, mtk_eint_irq_handler, pctl);
a6df410d
HY		 1487 return 0;
1488
1489chip_error:
1490 gpiochip_remove(pctl->chip);
1491pctrl_error:
1492 pinctrl_unregister(pctl->pctl_dev);
1493 return ret;
1494}
1495
1496MODULE_LICENSE("GPL");
1497MODULE_DESCRIPTION("MediaTek Pinctrl Driver");
1498MODULE_AUTHOR("Hongzhou Yang <hongzhou.yang@mediatek.com>");
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