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[mirror_ubuntu-artful-kernel.git] / drivers / pinctrl / mediatek / pinctrl-mtk-common.c
CommitLineData
a6df410d
HY		 1/*
2 * mt65xx pinctrl driver based on Allwinner A1X pinctrl driver.
3 * Copyright (c) 2014 MediaTek Inc.
4 * Author: Hongzhou.Yang <hongzhou.yang@mediatek.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/io.h>
11aa679a 17#include <linux/gpio/driver.h>
a6df410d
HY		 18#include <linux/module.h>
19#include <linux/of.h>
20#include <linux/of_address.h>
21#include <linux/of_device.h>
22#include <linux/of_irq.h>
23#include <linux/pinctrl/consumer.h>
24#include <linux/pinctrl/machine.h>
25#include <linux/pinctrl/pinconf.h>
26#include <linux/pinctrl/pinconf-generic.h>
27#include <linux/pinctrl/pinctrl.h>
28#include <linux/pinctrl/pinmux.h>
29#include <linux/platform_device.h>
30#include <linux/slab.h>
31#include <linux/bitops.h>
32#include <linux/regmap.h>
33#include <linux/mfd/syscon.h>
d9819eb9 34#include <linux/delay.h>
30f010f5 35#include <linux/interrupt.h>
58a5e1b6 36#include <linux/pm.h>
a6df410d
HY		 37#include <dt-bindings/pinctrl/mt65xx.h>
38
39#include "../core.h"
40#include "../pinconf.h"
41#include "../pinctrl-utils.h"
42#include "pinctrl-mtk-common.h"
43
44#define MAX_GPIO_MODE_PER_REG 5
45#define GPIO_MODE_BITS 3
46
47static const char * const mtk_gpio_functions[] = {
48 "func0", "func1", "func2", "func3",
49 "func4", "func5", "func6", "func7",
50};
51
52/*
53 * There are two base address for pull related configuration
54 * in mt8135, and different GPIO pins use different base address.
55 * When pin number greater than type1_start and less than type1_end,
56 * should use the second base address.
57 */
58static struct regmap *mtk_get_regmap(struct mtk_pinctrl *pctl,
59 unsigned long pin)
60{
61 if (pin >= pctl->devdata->type1_start && pin < pctl->devdata->type1_end)
62 return pctl->regmap2;
63 return pctl->regmap1;
64}
65
66static unsigned int mtk_get_port(struct mtk_pinctrl *pctl, unsigned long pin)
67{
68 /* Different SoC has different mask and port shift. */
69 return ((pin >> 4) & pctl->devdata->port_mask)
70 << pctl->devdata->port_shf;
71}
72
73static int mtk_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
74 struct pinctrl_gpio_range *range, unsigned offset,
75 bool input)
76{
77 unsigned int reg_addr;
78 unsigned int bit;
79 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
80
81 reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dir_offset;
82 bit = BIT(offset & 0xf);
83
84 if (input)
85 /* Different SoC has different alignment offset. */
86 reg_addr = CLR_ADDR(reg_addr, pctl);
87 else
88 reg_addr = SET_ADDR(reg_addr, pctl);
89
90 regmap_write(mtk_get_regmap(pctl, offset), reg_addr, bit);
91 return 0;
92}
93
94static void mtk_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
95{
96 unsigned int reg_addr;
97 unsigned int bit;
11aa679a 98 struct mtk_pinctrl *pctl = gpiochip_get_data(chip);
a6df410d
HY		 99
100 reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dout_offset;
101 bit = BIT(offset & 0xf);
102
103 if (value)
104 reg_addr = SET_ADDR(reg_addr, pctl);
105 else
106 reg_addr = CLR_ADDR(reg_addr, pctl);
107
108 regmap_write(mtk_get_regmap(pctl, offset), reg_addr, bit);
109}
110
25d76b21
HY		 111static int mtk_pconf_set_ies_smt(struct mtk_pinctrl *pctl, unsigned pin,
112 int value, enum pin_config_param arg)
a6df410d
HY		 113{
114 unsigned int reg_addr, offset;
115 unsigned int bit;
25d76b21
HY		 116
117 /**
118 * Due to some soc are not support ies/smt config, add this special
119 * control to handle it.
120 */
121 if (!pctl->devdata->spec_ies_smt_set &&
122 pctl->devdata->ies_offset == MTK_PINCTRL_NOT_SUPPORT &&
123 arg == PIN_CONFIG_INPUT_ENABLE)
124 return -EINVAL;
125
126 if (!pctl->devdata->spec_ies_smt_set &&
127 pctl->devdata->smt_offset == MTK_PINCTRL_NOT_SUPPORT &&
128 arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE)
129 return -EINVAL;
30f010f5
HY		 130
131 /*
132 * Due to some pins are irregular, their input enable and smt
25d76b21 133 * control register are discontinuous, so we need this special handle.
30f010f5
HY		 134 */
135 if (pctl->devdata->spec_ies_smt_set) {
25d76b21
HY		 136 return pctl->devdata->spec_ies_smt_set(mtk_get_regmap(pctl, pin),
137 pin, pctl->devdata->port_align, value, arg);
30f010f5 138 }
a6df410d
HY		 139
140 bit = BIT(pin & 0xf);
141
25d76b21 142 if (arg == PIN_CONFIG_INPUT_ENABLE)
a6df410d
HY		 143 offset = pctl->devdata->ies_offset;
144 else
145 offset = pctl->devdata->smt_offset;
146
147 if (value)
148 reg_addr = SET_ADDR(mtk_get_port(pctl, pin) + offset, pctl);
149 else
150 reg_addr = CLR_ADDR(mtk_get_port(pctl, pin) + offset, pctl);
151
152 regmap_write(mtk_get_regmap(pctl, pin), reg_addr, bit);
25d76b21
HY		 153 return 0;
154}
155
156int mtk_pconf_spec_set_ies_smt_range(struct regmap *regmap,
157 const struct mtk_pin_ies_smt_set *ies_smt_infos, unsigned int info_num,
158 unsigned int pin, unsigned char align, int value)
159{
160 unsigned int i, reg_addr, bit;
161
162 for (i = 0; i < info_num; i++) {
163 if (pin >= ies_smt_infos[i].start &&
164 pin <= ies_smt_infos[i].end) {
165 break;
166 }
167 }
168
169 if (i == info_num)
170 return -EINVAL;
171
172 if (value)
173 reg_addr = ies_smt_infos[i].offset + align;
174 else
175 reg_addr = ies_smt_infos[i].offset + (align << 1);
176
177 bit = BIT(ies_smt_infos[i].bit);
178 regmap_write(regmap, reg_addr, bit);
179 return 0;
a6df410d
HY		 180}
181
182static const struct mtk_pin_drv_grp *mtk_find_pin_drv_grp_by_pin(
183 struct mtk_pinctrl *pctl, unsigned long pin) {
184 int i;
185
186 for (i = 0; i < pctl->devdata->n_pin_drv_grps; i++) {
187 const struct mtk_pin_drv_grp *pin_drv =
188 pctl->devdata->pin_drv_grp + i;
189 if (pin == pin_drv->pin)
190 return pin_drv;
191 }
192
193 return NULL;
194}
195
196static int mtk_pconf_set_driving(struct mtk_pinctrl *pctl,
197 unsigned int pin, unsigned char driving)
198{
199 const struct mtk_pin_drv_grp *pin_drv;
200 unsigned int val;
201 unsigned int bits, mask, shift;
202 const struct mtk_drv_group_desc *drv_grp;
203
204 if (pin >= pctl->devdata->npins)
205 return -EINVAL;
206
207 pin_drv = mtk_find_pin_drv_grp_by_pin(pctl, pin);
208 if (!pin_drv || pin_drv->grp > pctl->devdata->n_grp_cls)
209 return -EINVAL;
210
211 drv_grp = pctl->devdata->grp_desc + pin_drv->grp;
212 if (driving >= drv_grp->min_drv && driving <= drv_grp->max_drv
213 && !(driving % drv_grp->step)) {
214 val = driving / drv_grp->step - 1;
215 bits = drv_grp->high_bit - drv_grp->low_bit + 1;
216 mask = BIT(bits) - 1;
217 shift = pin_drv->bit + drv_grp->low_bit;
218 mask <<= shift;
219 val <<= shift;
220 return regmap_update_bits(mtk_get_regmap(pctl, pin),
221 pin_drv->offset, mask, val);
222 }
223
224 return -EINVAL;
225}
226
e73fe271
YC		 227int mtk_pctrl_spec_pull_set_samereg(struct regmap *regmap,
228 const struct mtk_pin_spec_pupd_set_samereg *pupd_infos,
229 unsigned int info_num, unsigned int pin,
230 unsigned char align, bool isup, unsigned int r1r0)
231{
232 unsigned int i;
233 unsigned int reg_pupd, reg_set, reg_rst;
234 unsigned int bit_pupd, bit_r0, bit_r1;
235 const struct mtk_pin_spec_pupd_set_samereg *spec_pupd_pin;
236 bool find = false;
237
238 for (i = 0; i < info_num; i++) {
239 if (pin == pupd_infos[i].pin) {
240 find = true;
241 break;
242 }
243 }
244
245 if (!find)
246 return -EINVAL;
247
248 spec_pupd_pin = pupd_infos + i;
249 reg_set = spec_pupd_pin->offset + align;
250 reg_rst = spec_pupd_pin->offset + (align << 1);
251
252 if (isup)
253 reg_pupd = reg_rst;
254 else
255 reg_pupd = reg_set;
256
257 bit_pupd = BIT(spec_pupd_pin->pupd_bit);
258 regmap_write(regmap, reg_pupd, bit_pupd);
259
260 bit_r0 = BIT(spec_pupd_pin->r0_bit);
261 bit_r1 = BIT(spec_pupd_pin->r1_bit);
262
263 switch (r1r0) {
264 case MTK_PUPD_SET_R1R0_00:
265 regmap_write(regmap, reg_rst, bit_r0);
266 regmap_write(regmap, reg_rst, bit_r1);
267 break;
268 case MTK_PUPD_SET_R1R0_01:
269 regmap_write(regmap, reg_set, bit_r0);
270 regmap_write(regmap, reg_rst, bit_r1);
271 break;
272 case MTK_PUPD_SET_R1R0_10:
273 regmap_write(regmap, reg_rst, bit_r0);
274 regmap_write(regmap, reg_set, bit_r1);
275 break;
276 case MTK_PUPD_SET_R1R0_11:
277 regmap_write(regmap, reg_set, bit_r0);
278 regmap_write(regmap, reg_set, bit_r1);
279 break;
280 default:
281 return -EINVAL;
282 }
283
284 return 0;
285}
286
a6df410d
HY		 287static int mtk_pconf_set_pull_select(struct mtk_pinctrl *pctl,
288 unsigned int pin, bool enable, bool isup, unsigned int arg)
289{
290 unsigned int bit;
291 unsigned int reg_pullen, reg_pullsel;
292 int ret;
293
294 /* Some pins' pull setting are very different,
295 * they have separate pull up/down bit, R0 and R1
296 * resistor bit, so we need this special handle.
297 */
298 if (pctl->devdata->spec_pull_set) {
299 ret = pctl->devdata->spec_pull_set(mtk_get_regmap(pctl, pin),
300 pin, pctl->devdata->port_align, isup, arg);
301 if (!ret)
302 return 0;
303 }
304
305 /* For generic pull config, default arg value should be 0 or 1. */
306 if (arg != 0 && arg != 1) {
307 dev_err(pctl->dev, "invalid pull-up argument %d on pin %d .\n",
308 arg, pin);
309 return -EINVAL;
310 }
311
312 bit = BIT(pin & 0xf);
313 if (enable)
314 reg_pullen = SET_ADDR(mtk_get_port(pctl, pin) +
315 pctl->devdata->pullen_offset, pctl);
316 else
317 reg_pullen = CLR_ADDR(mtk_get_port(pctl, pin) +
318 pctl->devdata->pullen_offset, pctl);
319
320 if (isup)
321 reg_pullsel = SET_ADDR(mtk_get_port(pctl, pin) +
322 pctl->devdata->pullsel_offset, pctl);
323 else
324 reg_pullsel = CLR_ADDR(mtk_get_port(pctl, pin) +
325 pctl->devdata->pullsel_offset, pctl);
326
327 regmap_write(mtk_get_regmap(pctl, pin), reg_pullen, bit);
328 regmap_write(mtk_get_regmap(pctl, pin), reg_pullsel, bit);
329 return 0;
330}
331
332static int mtk_pconf_parse_conf(struct pinctrl_dev *pctldev,
333 unsigned int pin, enum pin_config_param param,
334 enum pin_config_param arg)
335{
25d76b21 336 int ret = 0;
a6df410d
HY		 337 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
338
339 switch (param) {
340 case PIN_CONFIG_BIAS_DISABLE:
25d76b21 341 ret = mtk_pconf_set_pull_select(pctl, pin, false, false, arg);
a6df410d
HY		 342 break;
343 case PIN_CONFIG_BIAS_PULL_UP:
25d76b21 344 ret = mtk_pconf_set_pull_select(pctl, pin, true, true, arg);
a6df410d
HY		 345 break;
346 case PIN_CONFIG_BIAS_PULL_DOWN:
25d76b21 347 ret = mtk_pconf_set_pull_select(pctl, pin, true, false, arg);
a6df410d
HY		 348 break;
349 case PIN_CONFIG_INPUT_ENABLE:
25d76b21 350 ret = mtk_pconf_set_ies_smt(pctl, pin, arg, param);
a6df410d
HY		 351 break;
352 case PIN_CONFIG_OUTPUT:
353 mtk_gpio_set(pctl->chip, pin, arg);
25d76b21 354 ret = mtk_pmx_gpio_set_direction(pctldev, NULL, pin, false);
a6df410d
HY		 355 break;
356 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
25d76b21 357 ret = mtk_pconf_set_ies_smt(pctl, pin, arg, param);
a6df410d
HY		 358 break;
359 case PIN_CONFIG_DRIVE_STRENGTH:
25d76b21 360 ret = mtk_pconf_set_driving(pctl, pin, arg);
a6df410d
HY		 361 break;
362 default:
25d76b21 363 ret = -EINVAL;
a6df410d
HY		 364 }
365
25d76b21 366 return ret;
a6df410d
HY		 367}
368
369static int mtk_pconf_group_get(struct pinctrl_dev *pctldev,
370 unsigned group,
371 unsigned long *config)
372{
373 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
374
375 *config = pctl->groups[group].config;
376
377 return 0;
378}
379
380static int mtk_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
381 unsigned long *configs, unsigned num_configs)
382{
383 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
384 struct mtk_pinctrl_group *g = &pctl->groups[group];
25d76b21 385 int i, ret;
a6df410d
HY		 386
387 for (i = 0; i < num_configs; i++) {
25d76b21 388 ret = mtk_pconf_parse_conf(pctldev, g->pin,
a6df410d
HY		 389 pinconf_to_config_param(configs[i]),
390 pinconf_to_config_argument(configs[i]));
25d76b21
HY		 391 if (ret < 0)
392 return ret;
a6df410d
HY		 393
394 g->config = configs[i];
395 }
396
397 return 0;
398}
399
400static const struct pinconf_ops mtk_pconf_ops = {
401 .pin_config_group_get = mtk_pconf_group_get,
402 .pin_config_group_set = mtk_pconf_group_set,
403};
404
405static struct mtk_pinctrl_group *
406mtk_pctrl_find_group_by_pin(struct mtk_pinctrl *pctl, u32 pin)
407{
408 int i;
409
410 for (i = 0; i < pctl->ngroups; i++) {
411 struct mtk_pinctrl_group *grp = pctl->groups + i;
412
413 if (grp->pin == pin)
414 return grp;
415 }
416
417 return NULL;
418}
419
420static const struct mtk_desc_function *mtk_pctrl_find_function_by_pin(
421 struct mtk_pinctrl *pctl, u32 pin_num, u32 fnum)
422{
423 const struct mtk_desc_pin *pin = pctl->devdata->pins + pin_num;
424 const struct mtk_desc_function *func = pin->functions;
425
426 while (func && func->name) {
427 if (func->muxval == fnum)
428 return func;
429 func++;
430 }
431
432 return NULL;
433}
434
435static bool mtk_pctrl_is_function_valid(struct mtk_pinctrl *pctl,
436 u32 pin_num, u32 fnum)
437{
438 int i;
439
440 for (i = 0; i < pctl->devdata->npins; i++) {
441 const struct mtk_desc_pin *pin = pctl->devdata->pins + i;
442
443 if (pin->pin.number == pin_num) {
444 const struct mtk_desc_function *func =
445 pin->functions;
446
447 while (func && func->name) {
448 if (func->muxval == fnum)
449 return true;
450 func++;
451 }
452
453 break;
454 }
455 }
456
457 return false;
458}
459
460static int mtk_pctrl_dt_node_to_map_func(struct mtk_pinctrl *pctl,
461 u32 pin, u32 fnum, struct mtk_pinctrl_group *grp,
462 struct pinctrl_map **map, unsigned *reserved_maps,
463 unsigned *num_maps)
464{
465 bool ret;
466
467 if (*num_maps == *reserved_maps)
468 return -ENOSPC;
469
470 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
471 (*map)[*num_maps].data.mux.group = grp->name;
472
473 ret = mtk_pctrl_is_function_valid(pctl, pin, fnum);
474 if (!ret) {
475 dev_err(pctl->dev, "invalid function %d on pin %d .\n",
476 fnum, pin);
477 return -EINVAL;
478 }
479
480 (*map)[*num_maps].data.mux.function = mtk_gpio_functions[fnum];
481 (*num_maps)++;
482
483 return 0;
484}
485
486static int mtk_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
487 struct device_node *node,
488 struct pinctrl_map **map,
489 unsigned *reserved_maps,
490 unsigned *num_maps)
491{
492 struct property *pins;
493 u32 pinfunc, pin, func;
494 int num_pins, num_funcs, maps_per_pin;
495 unsigned long *configs;
496 unsigned int num_configs;
497 bool has_config = 0;
498 int i, err;
499 unsigned reserve = 0;
500 struct mtk_pinctrl_group *grp;
501 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
502
503 pins = of_find_property(node, "pinmux", NULL);
504 if (!pins) {
505 dev_err(pctl->dev, "missing pins property in node %s .\n",
506 node->name);
507 return -EINVAL;
508 }
509
c445cac3
HY		 510 err = pinconf_generic_parse_dt_config(node, pctldev, &configs,
511 &num_configs);
b04a23b0
HY		 512 if (err)
513 return err;
514
a6df410d
HY		 515 if (num_configs)
516 has_config = 1;
517
518 num_pins = pins->length / sizeof(u32);
519 num_funcs = num_pins;
520 maps_per_pin = 0;
521 if (num_funcs)
522 maps_per_pin++;
523 if (has_config && num_pins >= 1)
524 maps_per_pin++;
525
b04a23b0
HY		 526 if (!num_pins || !maps_per_pin) {
527 err = -EINVAL;
528 goto exit;
529 }
a6df410d
HY		 530
531 reserve = num_pins * maps_per_pin;
532
533 err = pinctrl_utils_reserve_map(pctldev, map,
534 reserved_maps, num_maps, reserve);
535 if (err < 0)
b04a23b0 536 goto exit;
a6df410d
HY		 537
538 for (i = 0; i < num_pins; i++) {
539 err = of_property_read_u32_index(node, "pinmux",
540 i, &pinfunc);
541 if (err)
b04a23b0 542 goto exit;
a6df410d
HY		 543
544 pin = MTK_GET_PIN_NO(pinfunc);
545 func = MTK_GET_PIN_FUNC(pinfunc);
546
547 if (pin >= pctl->devdata->npins ||
548 func >= ARRAY_SIZE(mtk_gpio_functions)) {
549 dev_err(pctl->dev, "invalid pins value.\n");
550 err = -EINVAL;
b04a23b0 551 goto exit;
a6df410d
HY		 552 }
553
554 grp = mtk_pctrl_find_group_by_pin(pctl, pin);
555 if (!grp) {
556 dev_err(pctl->dev, "unable to match pin %d to group\n",
557 pin);
b04a23b0
HY		 558 err = -EINVAL;
559 goto exit;
a6df410d
HY		 560 }
561
562 err = mtk_pctrl_dt_node_to_map_func(pctl, pin, func, grp, map,
563 reserved_maps, num_maps);
564 if (err < 0)
b04a23b0 565 goto exit;
a6df410d
HY		 566
567 if (has_config) {
568 err = pinctrl_utils_add_map_configs(pctldev, map,
569 reserved_maps, num_maps, grp->name,
570 configs, num_configs,
571 PIN_MAP_TYPE_CONFIGS_GROUP);
572 if (err < 0)
b04a23b0 573 goto exit;
a6df410d
HY		 574 }
575 }
576
b04a23b0 577 err = 0;
a6df410d 578
b04a23b0
HY		 579exit:
580 kfree(configs);
a6df410d
HY		 581 return err;
582}
583
584static int mtk_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
585 struct device_node *np_config,
586 struct pinctrl_map **map, unsigned *num_maps)
587{
588 struct device_node *np;
589 unsigned reserved_maps;
590 int ret;
591
592 *map = NULL;
593 *num_maps = 0;
594 reserved_maps = 0;
595
596 for_each_child_of_node(np_config, np) {
597 ret = mtk_pctrl_dt_subnode_to_map(pctldev, np, map,
598 &reserved_maps, num_maps);
599 if (ret < 0) {
600 pinctrl_utils_dt_free_map(pctldev, *map, *num_maps);
4fc8a4b2 601 of_node_put(np);
a6df410d
HY		 602 return ret;
603 }
604 }
605
606 return 0;
607}
608
609static int mtk_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
610{
611 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
612
613 return pctl->ngroups;
614}
615
616static const char *mtk_pctrl_get_group_name(struct pinctrl_dev *pctldev,
617 unsigned group)
618{
619 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
620
621 return pctl->groups[group].name;
622}
623
624static int mtk_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
625 unsigned group,
626 const unsigned **pins,
627 unsigned *num_pins)
628{
629 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
630
631 *pins = (unsigned *)&pctl->groups[group].pin;
632 *num_pins = 1;
633
634 return 0;
635}
636
637static const struct pinctrl_ops mtk_pctrl_ops = {
638 .dt_node_to_map = mtk_pctrl_dt_node_to_map,
639 .dt_free_map = pinctrl_utils_dt_free_map,
640 .get_groups_count = mtk_pctrl_get_groups_count,
641 .get_group_name = mtk_pctrl_get_group_name,
642 .get_group_pins = mtk_pctrl_get_group_pins,
643};
644
645static int mtk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
646{
647 return ARRAY_SIZE(mtk_gpio_functions);
648}
649
650static const char *mtk_pmx_get_func_name(struct pinctrl_dev *pctldev,
651 unsigned selector)
652{
653 return mtk_gpio_functions[selector];
654}
655
656static int mtk_pmx_get_func_groups(struct pinctrl_dev *pctldev,
657 unsigned function,
658 const char * const **groups,
659 unsigned * const num_groups)
660{
661 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
662
663 *groups = pctl->grp_names;
664 *num_groups = pctl->ngroups;
665
666 return 0;
667}
668
669static int mtk_pmx_set_mode(struct pinctrl_dev *pctldev,
670 unsigned long pin, unsigned long mode)
671{
672 unsigned int reg_addr;
673 unsigned char bit;
674 unsigned int val;
675 unsigned int mask = (1L << GPIO_MODE_BITS) - 1;
676 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
677
678 reg_addr = ((pin / MAX_GPIO_MODE_PER_REG) << pctl->devdata->port_shf)
679 + pctl->devdata->pinmux_offset;
680
681 bit = pin % MAX_GPIO_MODE_PER_REG;
682 mask <<= (GPIO_MODE_BITS * bit);
683 val = (mode << (GPIO_MODE_BITS * bit));
684 return regmap_update_bits(mtk_get_regmap(pctl, pin),
685 reg_addr, mask, val);
686}
687
d9819eb9
MM		 688static const struct mtk_desc_pin *
689mtk_find_pin_by_eint_num(struct mtk_pinctrl *pctl, unsigned int eint_num)
690{
691 int i;
692 const struct mtk_desc_pin *pin;
693
694 for (i = 0; i < pctl->devdata->npins; i++) {
695 pin = pctl->devdata->pins + i;
696 if (pin->eint.eintnum == eint_num)
697 return pin;
698 }
699
700 return NULL;
701}
702
a6df410d
HY		 703static int mtk_pmx_set_mux(struct pinctrl_dev *pctldev,
704 unsigned function,
705 unsigned group)
706{
707 bool ret;
708 const struct mtk_desc_function *desc;
709 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
710 struct mtk_pinctrl_group *g = pctl->groups + group;
711
712 ret = mtk_pctrl_is_function_valid(pctl, g->pin, function);
713 if (!ret) {
c70336cc 714 dev_err(pctl->dev, "invalid function %d on group %d .\n",
a6df410d
HY		 715 function, group);
716 return -EINVAL;
717 }
718
719 desc = mtk_pctrl_find_function_by_pin(pctl, g->pin, function);
720 if (!desc)
721 return -EINVAL;
722 mtk_pmx_set_mode(pctldev, g->pin, desc->muxval);
723 return 0;
724}
725
726static const struct pinmux_ops mtk_pmx_ops = {
727 .get_functions_count = mtk_pmx_get_funcs_cnt,
728 .get_function_name = mtk_pmx_get_func_name,
729 .get_function_groups = mtk_pmx_get_func_groups,
730 .set_mux = mtk_pmx_set_mux,
731 .gpio_set_direction = mtk_pmx_gpio_set_direction,
732};
733
a6df410d
HY		 734static int mtk_gpio_direction_input(struct gpio_chip *chip,
735 unsigned offset)
736{
737 return pinctrl_gpio_direction_input(chip->base + offset);
738}
739
740static int mtk_gpio_direction_output(struct gpio_chip *chip,
741 unsigned offset, int value)
742{
743 mtk_gpio_set(chip, offset, value);
744 return pinctrl_gpio_direction_output(chip->base + offset);
745}
746
747static int mtk_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
748{
749 unsigned int reg_addr;
750 unsigned int bit;
751 unsigned int read_val = 0;
752
11aa679a 753 struct mtk_pinctrl *pctl = gpiochip_get_data(chip);
a6df410d
HY		 754
755 reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dir_offset;
756 bit = BIT(offset & 0xf);
757 regmap_read(pctl->regmap1, reg_addr, &read_val);
f97c2309 758 return !(read_val & bit);
a6df410d
HY		 759}
760
761static int mtk_gpio_get(struct gpio_chip *chip, unsigned offset)
762{
763 unsigned int reg_addr;
764 unsigned int bit;
765 unsigned int read_val = 0;
11aa679a 766 struct mtk_pinctrl *pctl = gpiochip_get_data(chip);
a6df410d 767
f97c2309
HY		 768 reg_addr = mtk_get_port(pctl, offset) +
769 pctl->devdata->din_offset;
a6df410d
HY		 770
771 bit = BIT(offset & 0xf);
772 regmap_read(pctl->regmap1, reg_addr, &read_val);
773 return !!(read_val & bit);
774}
775
d9819eb9
MM		 776static int mtk_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
777{
778 const struct mtk_desc_pin *pin;
11aa679a 779 struct mtk_pinctrl *pctl = gpiochip_get_data(chip);
d9819eb9
MM		 780 int irq;
781
782 pin = pctl->devdata->pins + offset;
783 if (pin->eint.eintnum == NO_EINT_SUPPORT)
784 return -EINVAL;
785
786 irq = irq_find_mapping(pctl->domain, pin->eint.eintnum);
787 if (!irq)
788 return -EINVAL;
789
790 return irq;
791}
792
793static int mtk_pinctrl_irq_request_resources(struct irq_data *d)
794{
795 struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
796 const struct mtk_desc_pin *pin;
797 int ret;
798
799 pin = mtk_find_pin_by_eint_num(pctl, d->hwirq);
800
801 if (!pin) {
802 dev_err(pctl->dev, "Can not find pin\n");
803 return -EINVAL;
804 }
805
806 ret = gpiochip_lock_as_irq(pctl->chip, pin->pin.number);
807 if (ret) {
808 dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n",
809 irqd_to_hwirq(d));
810 return ret;
811 }
812
813 /* set mux to INT mode */
814 mtk_pmx_set_mode(pctl->pctl_dev, pin->pin.number, pin->eint.eintmux);
815
816 return 0;
817}
818
819static void mtk_pinctrl_irq_release_resources(struct irq_data *d)
820{
821 struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
822 const struct mtk_desc_pin *pin;
823
824 pin = mtk_find_pin_by_eint_num(pctl, d->hwirq);
825
826 if (!pin) {
827 dev_err(pctl->dev, "Can not find pin\n");
828 return;
829 }
830
831 gpiochip_unlock_as_irq(pctl->chip, pin->pin.number);
832}
833
834static void __iomem *mtk_eint_get_offset(struct mtk_pinctrl *pctl,
835 unsigned int eint_num, unsigned int offset)
836{
837 unsigned int eint_base = 0;
838 void __iomem *reg;
839
840 if (eint_num >= pctl->devdata->ap_num)
841 eint_base = pctl->devdata->ap_num;
842
843 reg = pctl->eint_reg_base + offset + ((eint_num - eint_base) / 32) * 4;
844
845 return reg;
846}
847
848/*
849 * mtk_can_en_debounce: Check the EINT number is able to enable debounce or not
850 * @eint_num: the EINT number to setmtk_pinctrl
851 */
852static unsigned int mtk_eint_can_en_debounce(struct mtk_pinctrl *pctl,
853 unsigned int eint_num)
854{
855 unsigned int sens;
856 unsigned int bit = BIT(eint_num % 32);
857 const struct mtk_eint_offsets *eint_offsets =
858 &pctl->devdata->eint_offsets;
859
860 void __iomem *reg = mtk_eint_get_offset(pctl, eint_num,
861 eint_offsets->sens);
862
863 if (readl(reg) & bit)
864 sens = MT_LEVEL_SENSITIVE;
865 else
866 sens = MT_EDGE_SENSITIVE;
867
868 if ((eint_num < pctl->devdata->db_cnt) && (sens != MT_EDGE_SENSITIVE))
869 return 1;
870 else
871 return 0;
872}
873
874/*
875 * mtk_eint_get_mask: To get the eint mask
876 * @eint_num: the EINT number to get
877 */
878static unsigned int mtk_eint_get_mask(struct mtk_pinctrl *pctl,
879 unsigned int eint_num)
880{
881 unsigned int bit = BIT(eint_num % 32);
882 const struct mtk_eint_offsets *eint_offsets =
883 &pctl->devdata->eint_offsets;
884
885 void __iomem *reg = mtk_eint_get_offset(pctl, eint_num,
886 eint_offsets->mask);
887
888 return !!(readl(reg) & bit);
889}
890
3221f40b
YC		 891static int mtk_eint_flip_edge(struct mtk_pinctrl *pctl, int hwirq)
892{
893 int start_level, curr_level;
894 unsigned int reg_offset;
895 const struct mtk_eint_offsets *eint_offsets = &(pctl->devdata->eint_offsets);
b4b05b9a 896 u32 mask = BIT(hwirq & 0x1f);
3221f40b
YC		 897 u32 port = (hwirq >> 5) & eint_offsets->port_mask;
898 void __iomem *reg = pctl->eint_reg_base + (port << 2);
899 const struct mtk_desc_pin *pin;
900
901 pin = mtk_find_pin_by_eint_num(pctl, hwirq);
902 curr_level = mtk_gpio_get(pctl->chip, pin->pin.number);
903 do {
904 start_level = curr_level;
905 if (start_level)
906 reg_offset = eint_offsets->pol_clr;
907 else
908 reg_offset = eint_offsets->pol_set;
909 writel(mask, reg + reg_offset);
910
911 curr_level = mtk_gpio_get(pctl->chip, pin->pin.number);
912 } while (start_level != curr_level);
913
914 return start_level;
915}
916
d9819eb9
MM		 917static void mtk_eint_mask(struct irq_data *d)
918{
919 struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
920 const struct mtk_eint_offsets *eint_offsets =
921 &pctl->devdata->eint_offsets;
922 u32 mask = BIT(d->hwirq & 0x1f);
923 void __iomem *reg = mtk_eint_get_offset(pctl, d->hwirq,
924 eint_offsets->mask_set);
925
926 writel(mask, reg);
927}
928
929static void mtk_eint_unmask(struct irq_data *d)
930{
931 struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
932 const struct mtk_eint_offsets *eint_offsets =
933 &pctl->devdata->eint_offsets;
934 u32 mask = BIT(d->hwirq & 0x1f);
935 void __iomem *reg = mtk_eint_get_offset(pctl, d->hwirq,
936 eint_offsets->mask_clr);
937
938 writel(mask, reg);
3221f40b
YC		 939
940 if (pctl->eint_dual_edges[d->hwirq])
941 mtk_eint_flip_edge(pctl, d->hwirq);
d9819eb9
MM		 942}
943
944static int mtk_gpio_set_debounce(struct gpio_chip *chip, unsigned offset,
945 unsigned debounce)
946{
58383c78 947 struct mtk_pinctrl *pctl = dev_get_drvdata(chip->parent);
d9819eb9
MM		 948 int eint_num, virq, eint_offset;
949 unsigned int set_offset, bit, clr_bit, clr_offset, rst, i, unmask, dbnc;
950 static const unsigned int dbnc_arr[] = {0 , 1, 16, 32, 64, 128, 256};
951 const struct mtk_desc_pin *pin;
952 struct irq_data *d;
953
954 pin = pctl->devdata->pins + offset;
955 if (pin->eint.eintnum == NO_EINT_SUPPORT)
956 return -EINVAL;
957
958 eint_num = pin->eint.eintnum;
959 virq = irq_find_mapping(pctl->domain, eint_num);
960 eint_offset = (eint_num % 4) * 8;
961 d = irq_get_irq_data(virq);
962
963 set_offset = (eint_num / 4) * 4 + pctl->devdata->eint_offsets.dbnc_set;
964 clr_offset = (eint_num / 4) * 4 + pctl->devdata->eint_offsets.dbnc_clr;
965 if (!mtk_eint_can_en_debounce(pctl, eint_num))
966 return -ENOSYS;
967
968 dbnc = ARRAY_SIZE(dbnc_arr);
969 for (i = 0; i < ARRAY_SIZE(dbnc_arr); i++) {
970 if (debounce <= dbnc_arr[i]) {
971 dbnc = i;
972 break;
973 }
974 }
975
976 if (!mtk_eint_get_mask(pctl, eint_num)) {
977 mtk_eint_mask(d);
978 unmask = 1;
74d77e50
CIK		 979 } else {
980 unmask = 0;
d9819eb9
MM		 981 }
982
983 clr_bit = 0xff << eint_offset;
984 writel(clr_bit, pctl->eint_reg_base + clr_offset);
985
986 bit = ((dbnc << EINT_DBNC_SET_DBNC_BITS) | EINT_DBNC_SET_EN) <<
987 eint_offset;
988 rst = EINT_DBNC_RST_BIT << eint_offset;
989 writel(rst | bit, pctl->eint_reg_base + set_offset);
990
991 /* Delay a while (more than 2T) to wait for hw debounce counter reset
992 work correctly */
993 udelay(1);
994 if (unmask == 1)
995 mtk_eint_unmask(d);
996
997 return 0;
998}
999
a6df410d
HY		 1000static struct gpio_chip mtk_gpio_chip = {
1001 .owner = THIS_MODULE,
98c85d58
JG		 1002 .request = gpiochip_generic_request,
1003 .free = gpiochip_generic_free,
f97c2309 1004 .get_direction = mtk_gpio_get_direction,
a6df410d
HY		 1005 .direction_input = mtk_gpio_direction_input,
1006 .direction_output = mtk_gpio_direction_output,
1007 .get = mtk_gpio_get,
1008 .set = mtk_gpio_set,
d9819eb9
MM		 1009 .to_irq = mtk_gpio_to_irq,
1010 .set_debounce = mtk_gpio_set_debounce,
a6df410d
HY		 1011 .of_gpio_n_cells = 2,
1012};
1013
d9819eb9
MM		 1014static int mtk_eint_set_type(struct irq_data *d,
1015 unsigned int type)
1016{
1017 struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
1018 const struct mtk_eint_offsets *eint_offsets =
1019 &pctl->devdata->eint_offsets;
1020 u32 mask = BIT(d->hwirq & 0x1f);
1021 void __iomem *reg;
1022
1023 if (((type & IRQ_TYPE_EDGE_BOTH) && (type & IRQ_TYPE_LEVEL_MASK)) ||
d9819eb9
MM		 1024 ((type & IRQ_TYPE_LEVEL_MASK) == IRQ_TYPE_LEVEL_MASK)) {
1025 dev_err(pctl->dev, "Can't configure IRQ%d (EINT%lu) for type 0x%X\n",
1026 d->irq, d->hwirq, type);
1027 return -EINVAL;
1028 }
1029
3221f40b
YC		 1030 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
1031 pctl->eint_dual_edges[d->hwirq] = 1;
1032 else
1033 pctl->eint_dual_edges[d->hwirq] = 0;
1034
d9819eb9
MM		 1035 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING)) {
1036 reg = mtk_eint_get_offset(pctl, d->hwirq,
1037 eint_offsets->pol_clr);
1038 writel(mask, reg);
1039 } else {
1040 reg = mtk_eint_get_offset(pctl, d->hwirq,
1041 eint_offsets->pol_set);
1042 writel(mask, reg);
1043 }
1044
1045 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
1046 reg = mtk_eint_get_offset(pctl, d->hwirq,
1047 eint_offsets->sens_clr);
1048 writel(mask, reg);
1049 } else {
1050 reg = mtk_eint_get_offset(pctl, d->hwirq,
1051 eint_offsets->sens_set);
1052 writel(mask, reg);
1053 }
1054
3221f40b
YC		 1055 if (pctl->eint_dual_edges[d->hwirq])
1056 mtk_eint_flip_edge(pctl, d->hwirq);
1057
d9819eb9
MM		 1058 return 0;
1059}
1060
58a5e1b6
MM		 1061static int mtk_eint_irq_set_wake(struct irq_data *d, unsigned int on)
1062{
1063 struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
1064 int shift = d->hwirq & 0x1f;
1065 int reg = d->hwirq >> 5;
1066
1067 if (on)
1068 pctl->wake_mask[reg] |= BIT(shift);
1069 else
1070 pctl->wake_mask[reg] &= ~BIT(shift);
1071
1072 return 0;
1073}
1074
1075static void mtk_eint_chip_write_mask(const struct mtk_eint_offsets *chip,
1076 void __iomem *eint_reg_base, u32 *buf)
1077{
1078 int port;
1079 void __iomem *reg;
1080
1081 for (port = 0; port < chip->ports; port++) {
1082 reg = eint_reg_base + (port << 2);
1083 writel_relaxed(~buf[port], reg + chip->mask_set);
1084 writel_relaxed(buf[port], reg + chip->mask_clr);
1085 }
1086}
1087
1088static void mtk_eint_chip_read_mask(const struct mtk_eint_offsets *chip,
1089 void __iomem *eint_reg_base, u32 *buf)
1090{
1091 int port;
1092 void __iomem *reg;
1093
1094 for (port = 0; port < chip->ports; port++) {
1095 reg = eint_reg_base + chip->mask + (port << 2);
1096 buf[port] = ~readl_relaxed(reg);
1097 /* Mask is 0 when irq is enabled, and 1 when disabled. */
1098 }
1099}
1100
1101static int mtk_eint_suspend(struct device *device)
1102{
1103 void __iomem *reg;
1104 struct mtk_pinctrl *pctl = dev_get_drvdata(device);
1105 const struct mtk_eint_offsets *eint_offsets =
1106 &pctl->devdata->eint_offsets;
1107
1108 reg = pctl->eint_reg_base;
1109 mtk_eint_chip_read_mask(eint_offsets, reg, pctl->cur_mask);
1110 mtk_eint_chip_write_mask(eint_offsets, reg, pctl->wake_mask);
1111
1112 return 0;
1113}
1114
1115static int mtk_eint_resume(struct device *device)
1116{
1117 struct mtk_pinctrl *pctl = dev_get_drvdata(device);
1118 const struct mtk_eint_offsets *eint_offsets =
1119 &pctl->devdata->eint_offsets;
1120
1121 mtk_eint_chip_write_mask(eint_offsets,
1122 pctl->eint_reg_base, pctl->cur_mask);
1123
1124 return 0;
1125}
1126
1127const struct dev_pm_ops mtk_eint_pm_ops = {
1128 .suspend = mtk_eint_suspend,
1129 .resume = mtk_eint_resume,
1130};
1131
d9819eb9
MM		 1132static void mtk_eint_ack(struct irq_data *d)
1133{
1134 struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
1135 const struct mtk_eint_offsets *eint_offsets =
1136 &pctl->devdata->eint_offsets;
1137 u32 mask = BIT(d->hwirq & 0x1f);
1138 void __iomem *reg = mtk_eint_get_offset(pctl, d->hwirq,
1139 eint_offsets->ack);
1140
1141 writel(mask, reg);
1142}
1143
1144static struct irq_chip mtk_pinctrl_irq_chip = {
1145 .name = "mt-eint",
58a5e1b6 1146 .irq_disable = mtk_eint_mask,
d9819eb9
MM		 1147 .irq_mask = mtk_eint_mask,
1148 .irq_unmask = mtk_eint_unmask,
1149 .irq_ack = mtk_eint_ack,
1150 .irq_set_type = mtk_eint_set_type,
58a5e1b6 1151 .irq_set_wake = mtk_eint_irq_set_wake,
d9819eb9
MM		 1152 .irq_request_resources = mtk_pinctrl_irq_request_resources,
1153 .irq_release_resources = mtk_pinctrl_irq_release_resources,
1154};
1155
1156static unsigned int mtk_eint_init(struct mtk_pinctrl *pctl)
1157{
1158 const struct mtk_eint_offsets *eint_offsets =
1159 &pctl->devdata->eint_offsets;
1160 void __iomem *reg = pctl->eint_reg_base + eint_offsets->dom_en;
1161 unsigned int i;
1162
1163 for (i = 0; i < pctl->devdata->ap_num; i += 32) {
1164 writel(0xffffffff, reg);
1165 reg += 4;
1166 }
1167 return 0;
1168}
1169
1170static inline void
1171mtk_eint_debounce_process(struct mtk_pinctrl *pctl, int index)
1172{
1173 unsigned int rst, ctrl_offset;
1174 unsigned int bit, dbnc;
1175 const struct mtk_eint_offsets *eint_offsets =
1176 &pctl->devdata->eint_offsets;
1177
1178 ctrl_offset = (index / 4) * 4 + eint_offsets->dbnc_ctrl;
1179 dbnc = readl(pctl->eint_reg_base + ctrl_offset);
1180 bit = EINT_DBNC_SET_EN << ((index % 4) * 8);
1181 if ((bit & dbnc) > 0) {
1182 ctrl_offset = (index / 4) * 4 + eint_offsets->dbnc_set;
1183 rst = EINT_DBNC_RST_BIT << ((index % 4) * 8);
1184 writel(rst, pctl->eint_reg_base + ctrl_offset);
1185 }
1186}
1187
bd0b9ac4 1188static void mtk_eint_irq_handler(struct irq_desc *desc)
d9819eb9 1189{
5663bb27
JL		 1190 struct irq_chip *chip = irq_desc_get_chip(desc);
1191 struct mtk_pinctrl *pctl = irq_desc_get_handler_data(desc);
d9819eb9
MM		 1192 unsigned int status, eint_num;
1193 int offset, index, virq;
1194 const struct mtk_eint_offsets *eint_offsets =
1195 &pctl->devdata->eint_offsets;
1196 void __iomem *reg = mtk_eint_get_offset(pctl, 0, eint_offsets->stat);
3221f40b
YC		 1197 int dual_edges, start_level, curr_level;
1198 const struct mtk_desc_pin *pin;
d9819eb9
MM		 1199
1200 chained_irq_enter(chip, desc);
1201 for (eint_num = 0; eint_num < pctl->devdata->ap_num; eint_num += 32) {
1202 status = readl(reg);
1203 reg += 4;
1204 while (status) {
1205 offset = __ffs(status);
1206 index = eint_num + offset;
1207 virq = irq_find_mapping(pctl->domain, index);
1208 status &= ~BIT(offset);
1209
3221f40b
YC		 1210 dual_edges = pctl->eint_dual_edges[index];
1211 if (dual_edges) {
1212 /* Clear soft-irq in case we raised it
1213 last time */
1214 writel(BIT(offset), reg - eint_offsets->stat +
1215 eint_offsets->soft_clr);
1216
1217 pin = mtk_find_pin_by_eint_num(pctl, index);
1218 start_level = mtk_gpio_get(pctl->chip,
1219 pin->pin.number);
1220 }
1221
d9819eb9
MM		 1222 generic_handle_irq(virq);
1223
3221f40b
YC		 1224 if (dual_edges) {
1225 curr_level = mtk_eint_flip_edge(pctl, index);
1226
1227 /* If level changed, we might lost one edge
1228 interrupt, raised it through soft-irq */
1229 if (start_level != curr_level)
1230 writel(BIT(offset), reg -
1231 eint_offsets->stat +
1232 eint_offsets->soft_set);
1233 }
1234
d9819eb9
MM		 1235 if (index < pctl->devdata->db_cnt)
1236 mtk_eint_debounce_process(pctl , index);
1237 }
1238 }
1239 chained_irq_exit(chip, desc);
1240}
1241
a6df410d
HY		 1242static int mtk_pctrl_build_state(struct platform_device *pdev)
1243{
1244 struct mtk_pinctrl *pctl = platform_get_drvdata(pdev);
1245 int i;
1246
1247 pctl->ngroups = pctl->devdata->npins;
1248
1249 /* Allocate groups */
0206caa8
AL		 1250 pctl->groups = devm_kcalloc(&pdev->dev, pctl->ngroups,
1251 sizeof(*pctl->groups), GFP_KERNEL);
a6df410d
HY		 1252 if (!pctl->groups)
1253 return -ENOMEM;
1254
1255 /* We assume that one pin is one group, use pin name as group name. */
0206caa8
AL		 1256 pctl->grp_names = devm_kcalloc(&pdev->dev, pctl->ngroups,
1257 sizeof(*pctl->grp_names), GFP_KERNEL);
a6df410d
HY		 1258 if (!pctl->grp_names)
1259 return -ENOMEM;
1260
1261 for (i = 0; i < pctl->devdata->npins; i++) {
1262 const struct mtk_desc_pin *pin = pctl->devdata->pins + i;
1263 struct mtk_pinctrl_group *group = pctl->groups + i;
1264
1265 group->name = pin->pin.name;
1266 group->pin = pin->pin.number;
1267
1268 pctl->grp_names[i] = pin->pin.name;
1269 }
1270
1271 return 0;
1272}
1273
a6df410d 1274int mtk_pctrl_init(struct platform_device *pdev,
fc59e66c
HY		 1275 const struct mtk_pinctrl_devdata *data,
1276 struct regmap *regmap)
a6df410d
HY		 1277{
1278 struct pinctrl_pin_desc *pins;
1279 struct mtk_pinctrl *pctl;
1280 struct device_node *np = pdev->dev.of_node, *node;
1281 struct property *prop;
d9819eb9 1282 struct resource *res;
58a5e1b6 1283 int i, ret, irq, ports_buf;
a6df410d
HY		 1284
1285 pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
1286 if (!pctl)
1287 return -ENOMEM;
1288
1289 platform_set_drvdata(pdev, pctl);
1290
1291 prop = of_find_property(np, "pins-are-numbered", NULL);
1292 if (!prop) {
c445cac3 1293 dev_err(&pdev->dev, "only support pins-are-numbered format\n");
a6df410d
HY		 1294 return -EINVAL;
1295 }
1296
1297 node = of_parse_phandle(np, "mediatek,pctl-regmap", 0);
1298 if (node) {
1299 pctl->regmap1 = syscon_node_to_regmap(node);
1300 if (IS_ERR(pctl->regmap1))
1301 return PTR_ERR(pctl->regmap1);
fc59e66c
HY		 1302 } else if (regmap) {
1303 pctl->regmap1 = regmap;
1304 } else {
1305 dev_err(&pdev->dev, "Pinctrl node has not register regmap.\n");
1306 return -EINVAL;
a6df410d
HY		 1307 }
1308
1309 /* Only 8135 has two base addr, other SoCs have only one. */
1310 node = of_parse_phandle(np, "mediatek,pctl-regmap", 1);
1311 if (node) {
1312 pctl->regmap2 = syscon_node_to_regmap(node);
1313 if (IS_ERR(pctl->regmap2))
1314 return PTR_ERR(pctl->regmap2);
1315 }
1316
1317 pctl->devdata = data;
1318 ret = mtk_pctrl_build_state(pdev);
1319 if (ret) {
1320 dev_err(&pdev->dev, "build state failed: %d\n", ret);
1321 return -EINVAL;
1322 }
1323
0206caa8 1324 pins = devm_kcalloc(&pdev->dev, pctl->devdata->npins, sizeof(*pins),
a6df410d
HY		 1325 GFP_KERNEL);
1326 if (!pins)
1327 return -ENOMEM;
1328
1329 for (i = 0; i < pctl->devdata->npins; i++)
1330 pins[i] = pctl->devdata->pins[i].pin;
d48c2c02
HY		 1331
1332 pctl->pctl_desc.name = dev_name(&pdev->dev);
1333 pctl->pctl_desc.owner = THIS_MODULE;
1334 pctl->pctl_desc.pins = pins;
1335 pctl->pctl_desc.npins = pctl->devdata->npins;
1336 pctl->pctl_desc.confops = &mtk_pconf_ops;
1337 pctl->pctl_desc.pctlops = &mtk_pctrl_ops;
1338 pctl->pctl_desc.pmxops = &mtk_pmx_ops;
a6df410d 1339 pctl->dev = &pdev->dev;
d48c2c02
HY		 1340
1341 pctl->pctl_dev = pinctrl_register(&pctl->pctl_desc, &pdev->dev, pctl);
323de9ef 1342 if (IS_ERR(pctl->pctl_dev)) {
a6df410d 1343 dev_err(&pdev->dev, "couldn't register pinctrl driver\n");
323de9ef 1344 return PTR_ERR(pctl->pctl_dev);
a6df410d
HY		 1345 }
1346
1347 pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL);
1348 if (!pctl->chip) {
1349 ret = -ENOMEM;
1350 goto pctrl_error;
1351 }
1352
fc63d854 1353 *pctl->chip = mtk_gpio_chip;
a6df410d
HY		 1354 pctl->chip->ngpio = pctl->devdata->npins;
1355 pctl->chip->label = dev_name(&pdev->dev);
58383c78 1356 pctl->chip->parent = &pdev->dev;
fc59e66c 1357 pctl->chip->base = -1;
a6df410d 1358
11aa679a 1359 ret = gpiochip_add_data(pctl->chip, pctl);
a6df410d
HY		 1360 if (ret) {
1361 ret = -EINVAL;
1362 goto pctrl_error;
1363 }
1364
1365 /* Register the GPIO to pin mappings. */
1366 ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev),
1367 0, 0, pctl->devdata->npins);
1368 if (ret) {
1369 ret = -EINVAL;
1370 goto chip_error;
1371 }
1372
fc63d854 1373 if (!of_property_read_bool(np, "interrupt-controller"))
fc59e66c
HY		 1374 return 0;
1375
d9819eb9
MM		 1376 /* Get EINT register base from dts. */
1377 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1378 if (!res) {
1379 dev_err(&pdev->dev, "Unable to get Pinctrl resource\n");
1380 ret = -EINVAL;
1381 goto chip_error;
1382 }
1383
1384 pctl->eint_reg_base = devm_ioremap_resource(&pdev->dev, res);
1385 if (IS_ERR(pctl->eint_reg_base)) {
1386 ret = -EINVAL;
1387 goto chip_error;
1388 }
1389
58a5e1b6
MM		 1390 ports_buf = pctl->devdata->eint_offsets.ports;
1391 pctl->wake_mask = devm_kcalloc(&pdev->dev, ports_buf,
1392 sizeof(*pctl->wake_mask), GFP_KERNEL);
1393 if (!pctl->wake_mask) {
1394 ret = -ENOMEM;
1395 goto chip_error;
1396 }
1397
1398 pctl->cur_mask = devm_kcalloc(&pdev->dev, ports_buf,
1399 sizeof(*pctl->cur_mask), GFP_KERNEL);
1400 if (!pctl->cur_mask) {
1401 ret = -ENOMEM;
1402 goto chip_error;
1403 }
1404
0206caa8
AL		 1405 pctl->eint_dual_edges = devm_kcalloc(&pdev->dev, pctl->devdata->ap_num,
1406 sizeof(int), GFP_KERNEL);
3221f40b
YC		 1407 if (!pctl->eint_dual_edges) {
1408 ret = -ENOMEM;
1409 goto chip_error;
1410 }
1411
d9819eb9
MM		 1412 irq = irq_of_parse_and_map(np, 0);
1413 if (!irq) {
1414 dev_err(&pdev->dev, "couldn't parse and map irq\n");
1415 ret = -EINVAL;
61a35576 1416 goto chip_error;
d9819eb9
MM		 1417 }
1418
1419 pctl->domain = irq_domain_add_linear(np,
1420 pctl->devdata->ap_num, &irq_domain_simple_ops, NULL);
1421 if (!pctl->domain) {
1422 dev_err(&pdev->dev, "Couldn't register IRQ domain\n");
1423 ret = -ENOMEM;
61a35576 1424 goto chip_error;
d9819eb9
MM		 1425 }
1426
1427 mtk_eint_init(pctl);
1428 for (i = 0; i < pctl->devdata->ap_num; i++) {
1429 int virq = irq_create_mapping(pctl->domain, i);
1430
1431 irq_set_chip_and_handler(virq, &mtk_pinctrl_irq_chip,
1432 handle_level_irq);
1433 irq_set_chip_data(virq, pctl);
e4411899 1434 }
d9819eb9 1435
1e105921 1436 irq_set_chained_handler_and_data(irq, mtk_eint_irq_handler, pctl);
a6df410d
HY		 1437 return 0;
1438
1439chip_error:
1440 gpiochip_remove(pctl->chip);
1441pctrl_error:
1442 pinctrl_unregister(pctl->pctl_dev);
1443 return ret;
1444}
1445
1446MODULE_LICENSE("GPL");
1447MODULE_DESCRIPTION("MediaTek Pinctrl Driver");
1448MODULE_AUTHOR("Hongzhou Yang <hongzhou.yang@mediatek.com>");
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