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83c56680 XC |
1 | /* |
2 | * Pin controller and GPIO driver for Amlogic Meson AXG SoC. | |
3 | * | |
4 | * Copyright (c) 2017 Amlogic, Inc. All rights reserved. | |
5 | * Author: Xingyu Chen <xingyu.chen@amlogic.com> | |
6 | * | |
7 | * SPDX-License-Identifier: (GPL-2.0+ or MIT) | |
8 | */ | |
9 | ||
10 | #include <dt-bindings/gpio/meson-axg-gpio.h> | |
11 | #include "pinctrl-meson.h" | |
12 | #include "pinctrl-meson-axg-pmx.h" | |
13 | ||
14 | static const struct pinctrl_pin_desc meson_axg_periphs_pins[] = { | |
15 | MESON_PIN(GPIOZ_0), | |
16 | MESON_PIN(GPIOZ_1), | |
17 | MESON_PIN(GPIOZ_2), | |
18 | MESON_PIN(GPIOZ_3), | |
19 | MESON_PIN(GPIOZ_4), | |
20 | MESON_PIN(GPIOZ_5), | |
21 | MESON_PIN(GPIOZ_6), | |
22 | MESON_PIN(GPIOZ_7), | |
23 | MESON_PIN(GPIOZ_8), | |
24 | MESON_PIN(GPIOZ_9), | |
25 | MESON_PIN(GPIOZ_10), | |
26 | MESON_PIN(BOOT_0), | |
27 | MESON_PIN(BOOT_1), | |
28 | MESON_PIN(BOOT_2), | |
29 | MESON_PIN(BOOT_3), | |
30 | MESON_PIN(BOOT_4), | |
31 | MESON_PIN(BOOT_5), | |
32 | MESON_PIN(BOOT_6), | |
33 | MESON_PIN(BOOT_7), | |
34 | MESON_PIN(BOOT_8), | |
35 | MESON_PIN(BOOT_9), | |
36 | MESON_PIN(BOOT_10), | |
37 | MESON_PIN(BOOT_11), | |
38 | MESON_PIN(BOOT_12), | |
39 | MESON_PIN(BOOT_13), | |
40 | MESON_PIN(BOOT_14), | |
41 | MESON_PIN(GPIOA_0), | |
42 | MESON_PIN(GPIOA_1), | |
43 | MESON_PIN(GPIOA_2), | |
44 | MESON_PIN(GPIOA_3), | |
45 | MESON_PIN(GPIOA_4), | |
46 | MESON_PIN(GPIOA_5), | |
47 | MESON_PIN(GPIOA_6), | |
48 | MESON_PIN(GPIOA_7), | |
49 | MESON_PIN(GPIOA_8), | |
50 | MESON_PIN(GPIOA_9), | |
51 | MESON_PIN(GPIOA_10), | |
52 | MESON_PIN(GPIOA_11), | |
53 | MESON_PIN(GPIOA_12), | |
54 | MESON_PIN(GPIOA_13), | |
55 | MESON_PIN(GPIOA_14), | |
56 | MESON_PIN(GPIOA_15), | |
57 | MESON_PIN(GPIOA_16), | |
58 | MESON_PIN(GPIOA_17), | |
59 | MESON_PIN(GPIOA_18), | |
60 | MESON_PIN(GPIOA_19), | |
61 | MESON_PIN(GPIOA_20), | |
62 | MESON_PIN(GPIOX_0), | |
63 | MESON_PIN(GPIOX_1), | |
64 | MESON_PIN(GPIOX_2), | |
65 | MESON_PIN(GPIOX_3), | |
66 | MESON_PIN(GPIOX_4), | |
67 | MESON_PIN(GPIOX_5), | |
68 | MESON_PIN(GPIOX_6), | |
69 | MESON_PIN(GPIOX_7), | |
70 | MESON_PIN(GPIOX_8), | |
71 | MESON_PIN(GPIOX_9), | |
72 | MESON_PIN(GPIOX_10), | |
73 | MESON_PIN(GPIOX_11), | |
74 | MESON_PIN(GPIOX_12), | |
75 | MESON_PIN(GPIOX_13), | |
76 | MESON_PIN(GPIOX_14), | |
77 | MESON_PIN(GPIOX_15), | |
78 | MESON_PIN(GPIOX_16), | |
79 | MESON_PIN(GPIOX_17), | |
80 | MESON_PIN(GPIOX_18), | |
81 | MESON_PIN(GPIOX_19), | |
82 | MESON_PIN(GPIOX_20), | |
83 | MESON_PIN(GPIOX_21), | |
84 | MESON_PIN(GPIOX_22), | |
85 | MESON_PIN(GPIOY_0), | |
86 | MESON_PIN(GPIOY_1), | |
87 | MESON_PIN(GPIOY_2), | |
88 | MESON_PIN(GPIOY_3), | |
89 | MESON_PIN(GPIOY_4), | |
90 | MESON_PIN(GPIOY_5), | |
91 | MESON_PIN(GPIOY_6), | |
92 | MESON_PIN(GPIOY_7), | |
93 | MESON_PIN(GPIOY_8), | |
94 | MESON_PIN(GPIOY_9), | |
95 | MESON_PIN(GPIOY_10), | |
96 | MESON_PIN(GPIOY_11), | |
97 | MESON_PIN(GPIOY_12), | |
98 | MESON_PIN(GPIOY_13), | |
99 | MESON_PIN(GPIOY_14), | |
100 | MESON_PIN(GPIOY_15), | |
101 | }; | |
102 | ||
103 | static const struct pinctrl_pin_desc meson_axg_aobus_pins[] = { | |
104 | MESON_PIN(GPIOAO_0), | |
105 | MESON_PIN(GPIOAO_1), | |
106 | MESON_PIN(GPIOAO_2), | |
107 | MESON_PIN(GPIOAO_3), | |
108 | MESON_PIN(GPIOAO_4), | |
109 | MESON_PIN(GPIOAO_5), | |
110 | MESON_PIN(GPIOAO_6), | |
111 | MESON_PIN(GPIOAO_7), | |
112 | MESON_PIN(GPIOAO_8), | |
113 | MESON_PIN(GPIOAO_9), | |
114 | MESON_PIN(GPIOAO_10), | |
115 | MESON_PIN(GPIOAO_11), | |
116 | MESON_PIN(GPIOAO_12), | |
117 | MESON_PIN(GPIOAO_13), | |
118 | MESON_PIN(GPIO_TEST_N), | |
119 | }; | |
120 | ||
121 | /* emmc */ | |
122 | static const unsigned int emmc_nand_d0_pins[] = {BOOT_0}; | |
123 | static const unsigned int emmc_nand_d1_pins[] = {BOOT_1}; | |
124 | static const unsigned int emmc_nand_d2_pins[] = {BOOT_2}; | |
125 | static const unsigned int emmc_nand_d3_pins[] = {BOOT_3}; | |
126 | static const unsigned int emmc_nand_d4_pins[] = {BOOT_4}; | |
127 | static const unsigned int emmc_nand_d5_pins[] = {BOOT_5}; | |
128 | static const unsigned int emmc_nand_d6_pins[] = {BOOT_6}; | |
129 | static const unsigned int emmc_nand_d7_pins[] = {BOOT_7}; | |
130 | ||
131 | static const unsigned int emmc_clk_pins[] = {BOOT_8}; | |
132 | static const unsigned int emmc_cmd_pins[] = {BOOT_10}; | |
133 | static const unsigned int emmc_ds_pins[] = {BOOT_13}; | |
134 | ||
135 | /* nand */ | |
136 | static const unsigned int nand_ce0_pins[] = {BOOT_8}; | |
137 | static const unsigned int nand_ale_pins[] = {BOOT_9}; | |
138 | static const unsigned int nand_cle_pins[] = {BOOT_10}; | |
139 | static const unsigned int nand_wen_clk_pins[] = {BOOT_11}; | |
140 | static const unsigned int nand_ren_wr_pins[] = {BOOT_12}; | |
141 | static const unsigned int nand_rb0_pins[] = {BOOT_13}; | |
142 | ||
143 | /* nor */ | |
144 | static const unsigned int nor_hold_pins[] = {BOOT_3}; | |
145 | static const unsigned int nor_d_pins[] = {BOOT_4}; | |
146 | static const unsigned int nor_q_pins[] = {BOOT_5}; | |
147 | static const unsigned int nor_c_pins[] = {BOOT_6}; | |
148 | static const unsigned int nor_wp_pins[] = {BOOT_9}; | |
149 | static const unsigned int nor_cs_pins[] = {BOOT_14}; | |
150 | ||
151 | /* sdio */ | |
152 | static const unsigned int sdio_d0_pins[] = {GPIOX_0}; | |
153 | static const unsigned int sdio_d1_pins[] = {GPIOX_1}; | |
154 | static const unsigned int sdio_d2_pins[] = {GPIOX_2}; | |
155 | static const unsigned int sdio_d3_pins[] = {GPIOX_3}; | |
156 | static const unsigned int sdio_clk_pins[] = {GPIOX_4}; | |
157 | static const unsigned int sdio_cmd_pins[] = {GPIOX_5}; | |
158 | ||
d72ebbcc YL |
159 | /* spi0 */ |
160 | static const unsigned int spi0_clk_pins[] = {GPIOZ_0}; | |
161 | static const unsigned int spi0_mosi_pins[] = {GPIOZ_1}; | |
162 | static const unsigned int spi0_miso_pins[] = {GPIOZ_2}; | |
163 | static const unsigned int spi0_ss0_pins[] = {GPIOZ_3}; | |
164 | static const unsigned int spi0_ss1_pins[] = {GPIOZ_4}; | |
165 | static const unsigned int spi0_ss2_pins[] = {GPIOZ_5}; | |
166 | ||
167 | /* spi1 */ | |
168 | static const unsigned int spi1_clk_x_pins[] = {GPIOX_19}; | |
169 | static const unsigned int spi1_mosi_x_pins[] = {GPIOX_17}; | |
170 | static const unsigned int spi1_miso_x_pins[] = {GPIOX_18}; | |
171 | static const unsigned int spi1_ss0_x_pins[] = {GPIOX_16}; | |
172 | ||
173 | static const unsigned int spi1_clk_a_pins[] = {GPIOA_4}; | |
174 | static const unsigned int spi1_mosi_a_pins[] = {GPIOA_2}; | |
175 | static const unsigned int spi1_miso_a_pins[] = {GPIOA_3}; | |
176 | static const unsigned int spi1_ss0_a_pins[] = {GPIOA_5}; | |
177 | static const unsigned int spi1_ss1_pins[] = {GPIOA_6}; | |
83c56680 XC |
178 | |
179 | /* i2c0 */ | |
180 | static const unsigned int i2c0_sck_pins[] = {GPIOZ_6}; | |
181 | static const unsigned int i2c0_sda_pins[] = {GPIOZ_7}; | |
182 | ||
183 | /* i2c1 */ | |
184 | static const unsigned int i2c1_sck_z_pins[] = {GPIOZ_8}; | |
185 | static const unsigned int i2c1_sda_z_pins[] = {GPIOZ_9}; | |
186 | ||
187 | static const unsigned int i2c1_sck_x_pins[] = {GPIOX_16}; | |
188 | static const unsigned int i2c1_sda_x_pins[] = {GPIOX_17}; | |
189 | ||
190 | /* i2c2 */ | |
191 | static const unsigned int i2c2_sck_x_pins[] = {GPIOX_18}; | |
192 | static const unsigned int i2c2_sda_x_pins[] = {GPIOX_19}; | |
193 | ||
194 | static const unsigned int i2c2_sda_a_pins[] = {GPIOA_17}; | |
195 | static const unsigned int i2c2_sck_a_pins[] = {GPIOA_18}; | |
196 | ||
197 | /* i2c3 */ | |
198 | static const unsigned int i2c3_sda_a6_pins[] = {GPIOA_6}; | |
199 | static const unsigned int i2c3_sck_a7_pins[] = {GPIOA_7}; | |
200 | ||
201 | static const unsigned int i2c3_sda_a12_pins[] = {GPIOA_12}; | |
202 | static const unsigned int i2c3_sck_a13_pins[] = {GPIOA_13}; | |
203 | ||
204 | static const unsigned int i2c3_sda_a19_pins[] = {GPIOA_19}; | |
205 | static const unsigned int i2c3_sck_a20_pins[] = {GPIOA_20}; | |
206 | ||
207 | /* uart_a */ | |
208 | static const unsigned int uart_rts_a_pins[] = {GPIOX_11}; | |
209 | static const unsigned int uart_cts_a_pins[] = {GPIOX_10}; | |
210 | static const unsigned int uart_tx_a_pins[] = {GPIOX_8}; | |
211 | static const unsigned int uart_rx_a_pins[] = {GPIOX_9}; | |
212 | ||
213 | /* uart_b */ | |
214 | static const unsigned int uart_rts_b_z_pins[] = {GPIOZ_0}; | |
215 | static const unsigned int uart_cts_b_z_pins[] = {GPIOZ_1}; | |
216 | static const unsigned int uart_tx_b_z_pins[] = {GPIOZ_2}; | |
217 | static const unsigned int uart_rx_b_z_pins[] = {GPIOZ_3}; | |
218 | ||
219 | static const unsigned int uart_rts_b_x_pins[] = {GPIOX_18}; | |
220 | static const unsigned int uart_cts_b_x_pins[] = {GPIOX_19}; | |
221 | static const unsigned int uart_tx_b_x_pins[] = {GPIOX_16}; | |
222 | static const unsigned int uart_rx_b_x_pins[] = {GPIOX_17}; | |
223 | ||
224 | /* uart_ao_b */ | |
225 | static const unsigned int uart_ao_tx_b_z_pins[] = {GPIOZ_8}; | |
226 | static const unsigned int uart_ao_rx_b_z_pins[] = {GPIOZ_9}; | |
227 | static const unsigned int uart_ao_cts_b_z_pins[] = {GPIOZ_6}; | |
228 | static const unsigned int uart_ao_rts_b_z_pins[] = {GPIOZ_7}; | |
229 | ||
230 | /* pwm_a */ | |
231 | static const unsigned int pwm_a_z_pins[] = {GPIOZ_5}; | |
232 | ||
233 | static const unsigned int pwm_a_x18_pins[] = {GPIOX_18}; | |
234 | static const unsigned int pwm_a_x20_pins[] = {GPIOX_20}; | |
235 | ||
236 | static const unsigned int pwm_a_a_pins[] = {GPIOA_14}; | |
237 | ||
238 | /* pwm_b */ | |
239 | static const unsigned int pwm_b_z_pins[] = {GPIOZ_4}; | |
240 | ||
241 | static const unsigned int pwm_b_x_pins[] = {GPIOX_19}; | |
242 | ||
243 | static const unsigned int pwm_b_a_pins[] = {GPIOA_15}; | |
244 | ||
245 | /* pwm_c */ | |
246 | static const unsigned int pwm_c_x10_pins[] = {GPIOX_10}; | |
247 | static const unsigned int pwm_c_x17_pins[] = {GPIOX_17}; | |
248 | ||
249 | static const unsigned int pwm_c_a_pins[] = {GPIOA_16}; | |
250 | ||
251 | /* pwm_d */ | |
252 | static const unsigned int pwm_d_x11_pins[] = {GPIOX_11}; | |
253 | static const unsigned int pwm_d_x16_pins[] = {GPIOX_16}; | |
254 | ||
255 | /* pwm_vs */ | |
256 | static const unsigned int pwm_vs_pins[] = {GPIOA_0}; | |
257 | ||
258 | /* spdif_in */ | |
259 | static const unsigned int spdif_in_z_pins[] = {GPIOZ_4}; | |
260 | ||
261 | static const unsigned int spdif_in_a1_pins[] = {GPIOA_1}; | |
262 | static const unsigned int spdif_in_a7_pins[] = {GPIOA_7}; | |
263 | static const unsigned int spdif_in_a19_pins[] = {GPIOA_19}; | |
264 | static const unsigned int spdif_in_a20_pins[] = {GPIOA_20}; | |
265 | ||
266 | /* spdif_out */ | |
267 | static const unsigned int spdif_out_z_pins[] = {GPIOZ_5}; | |
268 | ||
269 | static const unsigned int spdif_out_a1_pins[] = {GPIOA_1}; | |
270 | static const unsigned int spdif_out_a11_pins[] = {GPIOA_11}; | |
271 | static const unsigned int spdif_out_a19_pins[] = {GPIOA_19}; | |
272 | static const unsigned int spdif_out_a20_pins[] = {GPIOA_20}; | |
273 | ||
274 | /* jtag_ee */ | |
275 | static const unsigned int jtag_tdo_x_pins[] = {GPIOX_0}; | |
276 | static const unsigned int jtag_tdi_x_pins[] = {GPIOX_1}; | |
277 | static const unsigned int jtag_clk_x_pins[] = {GPIOX_4}; | |
278 | static const unsigned int jtag_tms_x_pins[] = {GPIOX_5}; | |
279 | ||
280 | /* eth */ | |
281 | static const unsigned int eth_txd0_x_pins[] = {GPIOX_8}; | |
282 | static const unsigned int eth_txd1_x_pins[] = {GPIOX_9}; | |
283 | static const unsigned int eth_txen_x_pins[] = {GPIOX_10}; | |
284 | static const unsigned int eth_rgmii_rx_clk_x_pins[] = {GPIOX_12}; | |
285 | static const unsigned int eth_rxd0_x_pins[] = {GPIOX_13}; | |
286 | static const unsigned int eth_rxd1_x_pins[] = {GPIOX_14}; | |
287 | static const unsigned int eth_rx_dv_x_pins[] = {GPIOX_15}; | |
288 | static const unsigned int eth_mdio_x_pins[] = {GPIOX_21}; | |
289 | static const unsigned int eth_mdc_x_pins[] = {GPIOX_22}; | |
290 | ||
291 | static const unsigned int eth_txd0_y_pins[] = {GPIOY_10}; | |
292 | static const unsigned int eth_txd1_y_pins[] = {GPIOY_11}; | |
293 | static const unsigned int eth_txen_y_pins[] = {GPIOY_9}; | |
294 | static const unsigned int eth_rgmii_rx_clk_y_pins[] = {GPIOY_2}; | |
295 | static const unsigned int eth_rxd0_y_pins[] = {GPIOY_4}; | |
296 | static const unsigned int eth_rxd1_y_pins[] = {GPIOY_5}; | |
297 | static const unsigned int eth_rx_dv_y_pins[] = {GPIOY_3}; | |
298 | static const unsigned int eth_mdio_y_pins[] = {GPIOY_0}; | |
299 | static const unsigned int eth_mdc_y_pins[] = {GPIOY_1}; | |
300 | ||
301 | static const unsigned int eth_rxd2_rgmii_pins[] = {GPIOY_6}; | |
302 | static const unsigned int eth_rxd3_rgmii_pins[] = {GPIOY_7}; | |
303 | static const unsigned int eth_rgmii_tx_clk_pins[] = {GPIOY_8}; | |
304 | static const unsigned int eth_txd2_rgmii_pins[] = {GPIOY_12}; | |
305 | static const unsigned int eth_txd3_rgmii_pins[] = {GPIOY_13}; | |
306 | ||
307 | /* pdm */ | |
308 | static const unsigned int pdm_dclk_a14_pins[] = {GPIOA_14}; | |
309 | static const unsigned int pdm_dclk_a19_pins[] = {GPIOA_19}; | |
310 | static const unsigned int pdm_din0_pins[] = {GPIOA_15}; | |
311 | static const unsigned int pdm_din1_pins[] = {GPIOA_16}; | |
312 | static const unsigned int pdm_din2_pins[] = {GPIOA_17}; | |
313 | static const unsigned int pdm_din3_pins[] = {GPIOA_18}; | |
314 | ||
315 | static struct meson_pmx_group meson_axg_periphs_groups[] = { | |
316 | GPIO_GROUP(GPIOZ_0), | |
317 | GPIO_GROUP(GPIOZ_1), | |
318 | GPIO_GROUP(GPIOZ_2), | |
319 | GPIO_GROUP(GPIOZ_3), | |
320 | GPIO_GROUP(GPIOZ_4), | |
321 | GPIO_GROUP(GPIOZ_5), | |
322 | GPIO_GROUP(GPIOZ_6), | |
323 | GPIO_GROUP(GPIOZ_7), | |
324 | GPIO_GROUP(GPIOZ_8), | |
325 | GPIO_GROUP(GPIOZ_9), | |
326 | GPIO_GROUP(GPIOZ_10), | |
327 | ||
328 | GPIO_GROUP(BOOT_0), | |
329 | GPIO_GROUP(BOOT_1), | |
330 | GPIO_GROUP(BOOT_2), | |
331 | GPIO_GROUP(BOOT_3), | |
332 | GPIO_GROUP(BOOT_4), | |
333 | GPIO_GROUP(BOOT_5), | |
334 | GPIO_GROUP(BOOT_6), | |
335 | GPIO_GROUP(BOOT_7), | |
336 | GPIO_GROUP(BOOT_8), | |
337 | GPIO_GROUP(BOOT_9), | |
338 | GPIO_GROUP(BOOT_10), | |
339 | GPIO_GROUP(BOOT_11), | |
340 | GPIO_GROUP(BOOT_12), | |
341 | GPIO_GROUP(BOOT_13), | |
342 | GPIO_GROUP(BOOT_14), | |
343 | ||
344 | GPIO_GROUP(GPIOA_0), | |
345 | GPIO_GROUP(GPIOA_1), | |
346 | GPIO_GROUP(GPIOA_2), | |
347 | GPIO_GROUP(GPIOA_3), | |
348 | GPIO_GROUP(GPIOA_4), | |
349 | GPIO_GROUP(GPIOA_5), | |
350 | GPIO_GROUP(GPIOA_6), | |
351 | GPIO_GROUP(GPIOA_7), | |
352 | GPIO_GROUP(GPIOA_8), | |
353 | GPIO_GROUP(GPIOA_9), | |
354 | GPIO_GROUP(GPIOA_10), | |
355 | GPIO_GROUP(GPIOA_11), | |
356 | GPIO_GROUP(GPIOA_12), | |
357 | GPIO_GROUP(GPIOA_13), | |
358 | GPIO_GROUP(GPIOA_14), | |
359 | GPIO_GROUP(GPIOA_15), | |
360 | GPIO_GROUP(GPIOA_16), | |
361 | GPIO_GROUP(GPIOA_17), | |
362 | GPIO_GROUP(GPIOA_19), | |
363 | GPIO_GROUP(GPIOA_20), | |
364 | ||
365 | GPIO_GROUP(GPIOX_0), | |
366 | GPIO_GROUP(GPIOX_1), | |
367 | GPIO_GROUP(GPIOX_2), | |
368 | GPIO_GROUP(GPIOX_3), | |
369 | GPIO_GROUP(GPIOX_4), | |
370 | GPIO_GROUP(GPIOX_5), | |
371 | GPIO_GROUP(GPIOX_6), | |
372 | GPIO_GROUP(GPIOX_7), | |
373 | GPIO_GROUP(GPIOX_8), | |
374 | GPIO_GROUP(GPIOX_9), | |
375 | GPIO_GROUP(GPIOX_10), | |
376 | GPIO_GROUP(GPIOX_11), | |
377 | GPIO_GROUP(GPIOX_12), | |
378 | GPIO_GROUP(GPIOX_13), | |
379 | GPIO_GROUP(GPIOX_14), | |
380 | GPIO_GROUP(GPIOX_15), | |
381 | GPIO_GROUP(GPIOX_16), | |
382 | GPIO_GROUP(GPIOX_17), | |
383 | GPIO_GROUP(GPIOX_18), | |
384 | GPIO_GROUP(GPIOX_19), | |
385 | GPIO_GROUP(GPIOX_20), | |
386 | GPIO_GROUP(GPIOX_21), | |
387 | GPIO_GROUP(GPIOX_22), | |
388 | ||
389 | GPIO_GROUP(GPIOY_0), | |
390 | GPIO_GROUP(GPIOY_1), | |
391 | GPIO_GROUP(GPIOY_2), | |
392 | GPIO_GROUP(GPIOY_3), | |
393 | GPIO_GROUP(GPIOY_4), | |
394 | GPIO_GROUP(GPIOY_5), | |
395 | GPIO_GROUP(GPIOY_6), | |
396 | GPIO_GROUP(GPIOY_7), | |
397 | GPIO_GROUP(GPIOY_8), | |
398 | GPIO_GROUP(GPIOY_9), | |
399 | GPIO_GROUP(GPIOY_10), | |
400 | GPIO_GROUP(GPIOY_11), | |
401 | GPIO_GROUP(GPIOY_12), | |
402 | GPIO_GROUP(GPIOY_13), | |
403 | GPIO_GROUP(GPIOY_14), | |
404 | GPIO_GROUP(GPIOY_15), | |
405 | ||
406 | /* bank BOOT */ | |
407 | GROUP(emmc_nand_d0, 1), | |
408 | GROUP(emmc_nand_d1, 1), | |
409 | GROUP(emmc_nand_d2, 1), | |
410 | GROUP(emmc_nand_d3, 1), | |
411 | GROUP(emmc_nand_d4, 1), | |
412 | GROUP(emmc_nand_d5, 1), | |
413 | GROUP(emmc_nand_d6, 1), | |
414 | GROUP(emmc_nand_d7, 1), | |
415 | GROUP(emmc_clk, 1), | |
416 | GROUP(emmc_cmd, 1), | |
417 | GROUP(emmc_ds, 1), | |
418 | GROUP(nand_ce0, 2), | |
419 | GROUP(nand_ale, 2), | |
420 | GROUP(nand_cle, 2), | |
421 | GROUP(nand_wen_clk, 2), | |
422 | GROUP(nand_ren_wr, 2), | |
423 | GROUP(nand_rb0, 2), | |
424 | GROUP(nor_hold, 3), | |
425 | GROUP(nor_d, 3), | |
426 | GROUP(nor_q, 3), | |
427 | GROUP(nor_c, 3), | |
428 | GROUP(nor_wp, 3), | |
429 | GROUP(nor_cs, 3), | |
430 | ||
431 | /* bank GPIOZ */ | |
d72ebbcc YL |
432 | GROUP(spi0_clk, 1), |
433 | GROUP(spi0_mosi, 1), | |
434 | GROUP(spi0_miso, 1), | |
435 | GROUP(spi0_ss0, 1), | |
436 | GROUP(spi0_ss1, 1), | |
437 | GROUP(spi0_ss2, 1), | |
83c56680 XC |
438 | GROUP(i2c0_sck, 1), |
439 | GROUP(i2c0_sda, 1), | |
440 | GROUP(i2c1_sck_z, 1), | |
441 | GROUP(i2c1_sda_z, 1), | |
442 | GROUP(uart_rts_b_z, 2), | |
443 | GROUP(uart_cts_b_z, 2), | |
444 | GROUP(uart_tx_b_z, 2), | |
445 | GROUP(uart_rx_b_z, 2), | |
446 | GROUP(pwm_a_z, 2), | |
447 | GROUP(pwm_b_z, 2), | |
448 | GROUP(spdif_in_z, 3), | |
449 | GROUP(spdif_out_z, 3), | |
450 | GROUP(uart_ao_tx_b_z, 2), | |
451 | GROUP(uart_ao_rx_b_z, 2), | |
452 | GROUP(uart_ao_cts_b_z, 2), | |
453 | GROUP(uart_ao_rts_b_z, 2), | |
454 | ||
455 | /* bank GPIOX */ | |
456 | GROUP(sdio_d0, 1), | |
457 | GROUP(sdio_d1, 1), | |
458 | GROUP(sdio_d2, 1), | |
459 | GROUP(sdio_d3, 1), | |
460 | GROUP(sdio_clk, 1), | |
461 | GROUP(sdio_cmd, 1), | |
462 | GROUP(i2c1_sck_x, 1), | |
463 | GROUP(i2c1_sda_x, 1), | |
464 | GROUP(i2c2_sck_x, 1), | |
465 | GROUP(i2c2_sda_x, 1), | |
466 | GROUP(uart_rts_a, 1), | |
467 | GROUP(uart_cts_a, 1), | |
468 | GROUP(uart_tx_a, 1), | |
469 | GROUP(uart_rx_a, 1), | |
470 | GROUP(uart_rts_b_x, 2), | |
471 | GROUP(uart_cts_b_x, 2), | |
472 | GROUP(uart_tx_b_x, 2), | |
473 | GROUP(uart_rx_b_x, 2), | |
474 | GROUP(jtag_tdo_x, 2), | |
475 | GROUP(jtag_tdi_x, 2), | |
476 | GROUP(jtag_clk_x, 2), | |
477 | GROUP(jtag_tms_x, 2), | |
d72ebbcc YL |
478 | GROUP(spi1_clk_x, 4), |
479 | GROUP(spi1_mosi_x, 4), | |
480 | GROUP(spi1_miso_x, 4), | |
481 | GROUP(spi1_ss0_x, 4), | |
83c56680 XC |
482 | GROUP(pwm_a_x18, 3), |
483 | GROUP(pwm_a_x20, 1), | |
484 | GROUP(pwm_b_x, 3), | |
485 | GROUP(pwm_c_x10, 3), | |
486 | GROUP(pwm_c_x17, 3), | |
487 | GROUP(pwm_d_x11, 3), | |
488 | GROUP(pwm_d_x16, 3), | |
489 | GROUP(eth_txd0_x, 4), | |
490 | GROUP(eth_txd1_x, 4), | |
491 | GROUP(eth_txen_x, 4), | |
492 | GROUP(eth_rgmii_rx_clk_x, 4), | |
493 | GROUP(eth_rxd0_x, 4), | |
494 | GROUP(eth_rxd1_x, 4), | |
495 | GROUP(eth_rx_dv_x, 4), | |
496 | GROUP(eth_mdio_x, 4), | |
497 | GROUP(eth_mdc_x, 4), | |
498 | ||
499 | /* bank GPIOY */ | |
500 | GROUP(eth_txd0_y, 1), | |
501 | GROUP(eth_txd1_y, 1), | |
502 | GROUP(eth_txen_y, 1), | |
503 | GROUP(eth_rgmii_rx_clk_y, 1), | |
504 | GROUP(eth_rxd0_y, 1), | |
505 | GROUP(eth_rxd1_y, 1), | |
506 | GROUP(eth_rx_dv_y, 1), | |
507 | GROUP(eth_mdio_y, 1), | |
508 | GROUP(eth_mdc_y, 1), | |
509 | GROUP(eth_rxd2_rgmii, 1), | |
510 | GROUP(eth_rxd3_rgmii, 1), | |
511 | GROUP(eth_rgmii_tx_clk, 1), | |
512 | GROUP(eth_txd2_rgmii, 1), | |
513 | GROUP(eth_txd3_rgmii, 1), | |
514 | ||
515 | /* bank GPIOA */ | |
516 | GROUP(spdif_out_a1, 4), | |
517 | GROUP(spdif_out_a11, 3), | |
518 | GROUP(spdif_out_a19, 2), | |
519 | GROUP(spdif_out_a20, 1), | |
520 | GROUP(spdif_in_a1, 3), | |
521 | GROUP(spdif_in_a7, 3), | |
522 | GROUP(spdif_in_a19, 1), | |
523 | GROUP(spdif_in_a20, 2), | |
d72ebbcc YL |
524 | GROUP(spi1_clk_a, 3), |
525 | GROUP(spi1_mosi_a, 3), | |
526 | GROUP(spi1_miso_a, 3), | |
527 | GROUP(spi1_ss0_a, 3), | |
528 | GROUP(spi1_ss1, 3), | |
83c56680 XC |
529 | GROUP(pwm_a_a, 3), |
530 | GROUP(pwm_b_a, 3), | |
531 | GROUP(pwm_c_a, 3), | |
532 | GROUP(pwm_vs, 2), | |
533 | GROUP(i2c2_sda_a, 3), | |
534 | GROUP(i2c2_sck_a, 3), | |
535 | GROUP(i2c3_sda_a6, 4), | |
536 | GROUP(i2c3_sck_a7, 4), | |
537 | GROUP(i2c3_sda_a12, 4), | |
538 | GROUP(i2c3_sck_a13, 4), | |
539 | GROUP(i2c3_sda_a19, 4), | |
540 | GROUP(i2c3_sck_a20, 4), | |
541 | GROUP(pdm_dclk_a14, 1), | |
542 | GROUP(pdm_dclk_a19, 3), | |
543 | GROUP(pdm_din0, 1), | |
544 | GROUP(pdm_din1, 1), | |
545 | GROUP(pdm_din2, 1), | |
546 | GROUP(pdm_din3, 1), | |
547 | }; | |
548 | ||
549 | /* uart_ao_a */ | |
550 | static const unsigned int uart_ao_tx_a_pins[] = {GPIOAO_0}; | |
551 | static const unsigned int uart_ao_rx_a_pins[] = {GPIOAO_1}; | |
552 | static const unsigned int uart_ao_cts_a_pins[] = {GPIOAO_2}; | |
553 | static const unsigned int uart_ao_rts_a_pins[] = {GPIOAO_3}; | |
554 | ||
555 | /* uart_ao_b */ | |
556 | static const unsigned int uart_ao_tx_b_pins[] = {GPIOAO_4}; | |
557 | static const unsigned int uart_ao_rx_b_pins[] = {GPIOAO_5}; | |
558 | static const unsigned int uart_ao_cts_b_pins[] = {GPIOAO_2}; | |
559 | static const unsigned int uart_ao_rts_b_pins[] = {GPIOAO_3}; | |
560 | ||
561 | /* i2c_ao */ | |
562 | static const unsigned int i2c_ao_sck_4_pins[] = {GPIOAO_4}; | |
563 | static const unsigned int i2c_ao_sda_5_pins[] = {GPIOAO_5}; | |
564 | static const unsigned int i2c_ao_sck_8_pins[] = {GPIOAO_8}; | |
565 | static const unsigned int i2c_ao_sda_9_pins[] = {GPIOAO_9}; | |
566 | static const unsigned int i2c_ao_sck_10_pins[] = {GPIOAO_10}; | |
567 | static const unsigned int i2c_ao_sda_11_pins[] = {GPIOAO_11}; | |
568 | ||
569 | /* i2c_ao_slave */ | |
570 | static const unsigned int i2c_ao_slave_sck_pins[] = {GPIOAO_10}; | |
571 | static const unsigned int i2c_ao_slave_sda_pins[] = {GPIOAO_11}; | |
572 | ||
573 | /* ir_in */ | |
574 | static const unsigned int remote_input_ao_pins[] = {GPIOAO_6}; | |
575 | ||
576 | /* ir_out */ | |
577 | static const unsigned int remote_out_ao_pins[] = {GPIOAO_7}; | |
578 | ||
579 | /* pwm_ao_a */ | |
580 | static const unsigned int pwm_ao_a_pins[] = {GPIOAO_3}; | |
581 | ||
582 | /* pwm_ao_b */ | |
583 | static const unsigned int pwm_ao_b_ao2_pins[] = {GPIOAO_2}; | |
584 | static const unsigned int pwm_ao_b_ao12_pins[] = {GPIOAO_12}; | |
585 | ||
586 | /* pwm_ao_c */ | |
587 | static const unsigned int pwm_ao_c_ao8_pins[] = {GPIOAO_8}; | |
588 | static const unsigned int pwm_ao_c_ao13_pins[] = {GPIOAO_13}; | |
589 | ||
590 | /* pwm_ao_d */ | |
591 | static const unsigned int pwm_ao_d_pins[] = {GPIOAO_9}; | |
592 | ||
593 | /* jtag_ao */ | |
594 | static const unsigned int jtag_ao_tdi_pins[] = {GPIOAO_3}; | |
595 | static const unsigned int jtag_ao_tdo_pins[] = {GPIOAO_4}; | |
596 | static const unsigned int jtag_ao_clk_pins[] = {GPIOAO_5}; | |
597 | static const unsigned int jtag_ao_tms_pins[] = {GPIOAO_7}; | |
598 | ||
599 | static struct meson_pmx_group meson_axg_aobus_groups[] = { | |
600 | GPIO_GROUP(GPIOAO_0), | |
601 | GPIO_GROUP(GPIOAO_1), | |
602 | GPIO_GROUP(GPIOAO_2), | |
603 | GPIO_GROUP(GPIOAO_3), | |
604 | GPIO_GROUP(GPIOAO_4), | |
605 | GPIO_GROUP(GPIOAO_5), | |
606 | GPIO_GROUP(GPIOAO_6), | |
607 | GPIO_GROUP(GPIOAO_7), | |
608 | GPIO_GROUP(GPIOAO_8), | |
609 | GPIO_GROUP(GPIOAO_9), | |
610 | GPIO_GROUP(GPIOAO_10), | |
611 | GPIO_GROUP(GPIOAO_11), | |
612 | GPIO_GROUP(GPIOAO_12), | |
613 | GPIO_GROUP(GPIOAO_13), | |
614 | GPIO_GROUP(GPIO_TEST_N), | |
615 | ||
616 | /* bank AO */ | |
617 | GROUP(uart_ao_tx_a, 1), | |
618 | GROUP(uart_ao_rx_a, 1), | |
619 | GROUP(uart_ao_cts_a, 2), | |
620 | GROUP(uart_ao_rts_a, 2), | |
621 | GROUP(uart_ao_tx_b, 1), | |
622 | GROUP(uart_ao_rx_b, 1), | |
623 | GROUP(uart_ao_cts_b, 1), | |
624 | GROUP(uart_ao_rts_b, 1), | |
625 | GROUP(i2c_ao_sck_4, 2), | |
626 | GROUP(i2c_ao_sda_5, 2), | |
627 | GROUP(i2c_ao_sck_8, 2), | |
628 | GROUP(i2c_ao_sda_9, 2), | |
629 | GROUP(i2c_ao_sck_10, 2), | |
630 | GROUP(i2c_ao_sda_11, 2), | |
631 | GROUP(i2c_ao_slave_sck, 1), | |
632 | GROUP(i2c_ao_slave_sda, 1), | |
633 | GROUP(remote_input_ao, 1), | |
634 | GROUP(remote_out_ao, 1), | |
635 | GROUP(pwm_ao_a, 3), | |
636 | GROUP(pwm_ao_b_ao2, 3), | |
637 | GROUP(pwm_ao_b_ao12, 3), | |
638 | GROUP(pwm_ao_c_ao8, 3), | |
639 | GROUP(pwm_ao_c_ao13, 3), | |
640 | GROUP(pwm_ao_d, 3), | |
641 | GROUP(jtag_ao_tdi, 4), | |
642 | GROUP(jtag_ao_tdo, 4), | |
643 | GROUP(jtag_ao_clk, 4), | |
644 | GROUP(jtag_ao_tms, 4), | |
645 | }; | |
646 | ||
647 | static const char * const gpio_periphs_groups[] = { | |
648 | "GPIOZ_0", "GPIOZ_1", "GPIOZ_2", "GPIOZ_3", "GPIOZ_4", | |
649 | "GPIOZ_5", "GPIOZ_6", "GPIOZ_7", "GPIOZ_8", "GPIOZ_9", | |
650 | "GPIOZ_10", | |
651 | ||
652 | "BOOT_0", "BOOT_1", "BOOT_2", "BOOT_3", "BOOT_4", | |
653 | "BOOT_5", "BOOT_6", "BOOT_7", "BOOT_8", "BOOT_9", | |
654 | "BOOT_10", "BOOT_11", "BOOT_12", "BOOT_13", "BOOT_14", | |
655 | ||
656 | "GPIOA_0", "GPIOA_1", "GPIOA_2", "GPIOA_3", "GPIOA_4", | |
657 | "GPIOA_5", "GPIOA_6", "GPIOA_7", "GPIOA_8", "GPIOA_9", | |
658 | "GPIOA_10", "GPIOA_11", "GPIOA_12", "GPIOA_13", "GPIOA_14", | |
659 | "GPIOA_15", "GPIOA_16", "GPIOA_17", "GPIOA_18", "GPIOA_19", | |
660 | "GPIOA_20", | |
661 | ||
662 | "GPIOX_0", "GPIOX_1", "GPIOX_2", "GPIOX_3", "GPIOX_4", | |
663 | "GPIOX_5", "GPIOX_6", "GPIOX_7", "GPIOX_8", "GPIOX_9", | |
664 | "GPIOX_10", "GPIOX_11", "GPIOX_12", "GPIOX_13", "GPIOX_14", | |
665 | "GPIOX_15", "GPIOX_16", "GPIOX_17", "GPIOX_18", "GPIOX_19", | |
666 | "GPIOX_20", "GPIOX_21", "GPIOX_22", | |
667 | ||
668 | "GPIOY_0", "GPIOY_1", "GPIOY_2", "GPIOY_3", "GPIOY_4", | |
669 | "GPIOY_5", "GPIOY_6", "GPIOY_7", "GPIOY_8", "GPIOY_9", | |
670 | "GPIOY_10", "GPIOY_11", "GPIOY_12", "GPIOY_13", "GPIOY_14", | |
671 | "GPIOY_15", | |
672 | }; | |
673 | ||
674 | static const char * const emmc_groups[] = { | |
675 | "emmc_nand_d0", "emmc_nand_d1", "emmc_nand_d2", | |
676 | "emmc_nand_d3", "emmc_nand_d4", "emmc_nand_d5", | |
677 | "emmc_nand_d6", "emmc_nand_d7", | |
678 | "emmc_clk", "emmc_cmd", "emmc_ds", | |
679 | }; | |
680 | ||
681 | static const char * const nand_groups[] = { | |
682 | "emmc_nand_d0", "emmc_nand_d1", "emmc_nand_d2", | |
683 | "emmc_nand_d3", "emmc_nand_d4", "emmc_nand_d5", | |
684 | "emmc_nand_d6", "emmc_nand_d7", | |
685 | "nand_ce0", "nand_ale", "nand_cle", | |
686 | "nand_wen_clk", "nand_ren_wr", "nand_rb0", | |
687 | }; | |
688 | ||
689 | static const char * const nor_groups[] = { | |
690 | "nor_d", "nor_q", "nor_c", "nor_cs", | |
691 | "nor_hold", "nor_wp", | |
692 | }; | |
693 | ||
694 | static const char * const sdio_groups[] = { | |
695 | "sdio_d0", "sdio_d1", "sdio_d2", "sdio_d3", | |
696 | "sdio_cmd", "sdio_clk", | |
697 | }; | |
698 | ||
d72ebbcc YL |
699 | static const char * const spi0_groups[] = { |
700 | "spi0_clk", "spi0_mosi", "spi0_miso", "spi0_ss0", | |
701 | "spi0_ss1", "spi0_ss2" | |
83c56680 XC |
702 | }; |
703 | ||
d72ebbcc YL |
704 | static const char * const spi1_groups[] = { |
705 | "spi1_clk_x", "spi1_mosi_x", "spi1_miso_x", "spi1_ss0_x", | |
706 | "spi1_clk_a", "spi1_mosi_a", "spi1_miso_a", "spi1_ss0_a", | |
707 | "spi1_ss1" | |
83c56680 XC |
708 | }; |
709 | ||
710 | static const char * const uart_a_groups[] = { | |
711 | "uart_tx_a", "uart_rx_a", "uart_cts_a", "uart_rts_a", | |
712 | }; | |
713 | ||
714 | static const char * const uart_b_groups[] = { | |
715 | "uart_tx_b_z", "uart_rx_b_z", "uart_cts_b_z", "uart_rts_b_z", | |
716 | "uart_tx_b_x", "uart_rx_b_x", "uart_cts_b_x", "uart_rts_b_x", | |
717 | }; | |
718 | ||
49527bc0 | 719 | static const char * const uart_ao_b_z_groups[] = { |
83c56680 XC |
720 | "uart_ao_tx_b_z", "uart_ao_rx_b_z", |
721 | "uart_ao_cts_b_z", "uart_ao_rts_b_z", | |
722 | }; | |
723 | ||
724 | static const char * const i2c0_groups[] = { | |
725 | "i2c0_sck", "i2c0_sda", | |
726 | }; | |
727 | ||
728 | static const char * const i2c1_groups[] = { | |
729 | "i2c1_sck_z", "i2c1_sda_z", | |
730 | "i2c1_sck_x", "i2c1_sda_x", | |
731 | }; | |
732 | ||
733 | static const char * const i2c2_groups[] = { | |
734 | "i2c2_sck_x", "i2c2_sda_x", | |
735 | "i2c2_sda_a", "i2c2_sck_a", | |
736 | }; | |
737 | ||
738 | static const char * const i2c3_groups[] = { | |
739 | "i2c3_sda_a6", "i2c3_sck_a7", | |
740 | "i2c3_sda_a12", "i2c3_sck_a13", | |
741 | "i2c3_sda_a19", "i2c3_sck_a20", | |
742 | }; | |
743 | ||
744 | static const char * const eth_groups[] = { | |
745 | "eth_rxd2_rgmii", "eth_rxd3_rgmii", "eth_rgmii_tx_clk", | |
746 | "eth_txd2_rgmii", "eth_txd3_rgmii", | |
747 | "eth_txd0_x", "eth_txd1_x", "eth_txen_x", "eth_rgmii_rx_clk_x", | |
748 | "eth_rxd0_x", "eth_rxd1_x", "eth_rx_dv_x", "eth_mdio_x", | |
749 | "eth_mdc_x", | |
750 | "eth_txd0_y", "eth_txd1_y", "eth_txen_y", "eth_rgmii_rx_clk_y", | |
751 | "eth_rxd0_y", "eth_rxd1_y", "eth_rx_dv_y", "eth_mdio_y", | |
752 | "eth_mdc_y", | |
753 | }; | |
754 | ||
755 | static const char * const pwm_a_groups[] = { | |
756 | "pwm_a_z", "pwm_a_x18", "pwm_a_x20", "pwm_a_a", | |
757 | }; | |
758 | ||
759 | static const char * const pwm_b_groups[] = { | |
760 | "pwm_b_z", "pwm_b_x", "pwm_b_a", | |
761 | }; | |
762 | ||
763 | static const char * const pwm_c_groups[] = { | |
764 | "pwm_c_x10", "pwm_c_x17", "pwm_c_a", | |
765 | }; | |
766 | ||
767 | static const char * const pwm_d_groups[] = { | |
768 | "pwm_d_x11", "pwm_d_x16", | |
769 | }; | |
770 | ||
771 | static const char * const pwm_vs_groups[] = { | |
772 | "pwm_vs", | |
773 | }; | |
774 | ||
775 | static const char * const spdif_out_groups[] = { | |
776 | "spdif_out_z", "spdif_out_a1", "spdif_out_a11", | |
777 | "spdif_out_a19", "spdif_out_a20", | |
778 | }; | |
779 | ||
780 | static const char * const spdif_in_groups[] = { | |
781 | "spdif_in_z", "spdif_in_a1", "spdif_in_a7", | |
782 | "spdif_in_a19", "spdif_in_a20", | |
783 | }; | |
784 | ||
785 | static const char * const jtag_ee_groups[] = { | |
786 | "jtag_tdo_x", "jtag_tdi_x", "jtag_clk_x", | |
787 | "jtag_tms_x", | |
788 | }; | |
789 | ||
790 | static const char * const pdm_groups[] = { | |
791 | "pdm_din0", "pdm_din1", "pdm_din2", "pdm_din3", | |
792 | "pdm_dclk_a14", "pdm_dclk_a19", | |
793 | }; | |
794 | ||
795 | static const char * const gpio_aobus_groups[] = { | |
796 | "GPIOAO_0", "GPIOAO_1", "GPIOAO_2", "GPIOAO_3", "GPIOAO_4", | |
797 | "GPIOAO_5", "GPIOAO_6", "GPIOAO_7", "GPIOAO_8", "GPIOAO_9", | |
798 | "GPIOAO_10", "GPIOAO_11", "GPIOAO_12", "GPIOAO_13", | |
799 | "GPIO_TEST_N", | |
800 | }; | |
801 | ||
802 | static const char * const uart_ao_a_groups[] = { | |
803 | "uart_ao_tx_a", "uart_ao_rx_a", "uart_ao_cts_a", "uart_ao_rts_a", | |
804 | }; | |
805 | ||
806 | static const char * const uart_ao_b_groups[] = { | |
807 | "uart_ao_tx_b", "uart_ao_rx_b", "uart_ao_cts_b", "uart_ao_rts_b", | |
808 | }; | |
809 | ||
810 | static const char * const i2c_ao_groups[] = { | |
811 | "i2c_ao_sck_4", "i2c_ao_sda_5", | |
812 | "i2c_ao_sck_8", "i2c_ao_sda_9", | |
813 | "i2c_ao_sck_10", "i2c_ao_sda_11", | |
814 | }; | |
815 | ||
816 | static const char * const i2c_ao_slave_groups[] = { | |
817 | "i2c_ao_slave_sck", "i2c_ao_slave_sda", | |
818 | }; | |
819 | ||
820 | static const char * const remote_input_ao_groups[] = { | |
821 | "remote_input_ao", | |
822 | }; | |
823 | ||
824 | static const char * const remote_out_ao_groups[] = { | |
825 | "remote_out_ao", | |
826 | }; | |
827 | ||
828 | static const char * const pwm_ao_a_groups[] = { | |
829 | "pwm_ao_a", | |
830 | }; | |
831 | ||
832 | static const char * const pwm_ao_b_groups[] = { | |
833 | "pwm_ao_b_ao2", "pwm_ao_b_ao12", | |
834 | }; | |
835 | ||
836 | static const char * const pwm_ao_c_groups[] = { | |
837 | "pwm_ao_c_ao8", "pwm_ao_c_ao13", | |
838 | }; | |
839 | ||
840 | static const char * const pwm_ao_d_groups[] = { | |
841 | "pwm_ao_d", | |
842 | }; | |
843 | ||
844 | static const char * const jtag_ao_groups[] = { | |
845 | "jtag_ao_tdi", "jtag_ao_tdo", "jtag_ao_clk", "jtag_ao_tms", | |
846 | }; | |
847 | ||
848 | static struct meson_pmx_func meson_axg_periphs_functions[] = { | |
849 | FUNCTION(gpio_periphs), | |
850 | FUNCTION(emmc), | |
851 | FUNCTION(nor), | |
d72ebbcc YL |
852 | FUNCTION(spi0), |
853 | FUNCTION(spi1), | |
83c56680 XC |
854 | FUNCTION(sdio), |
855 | FUNCTION(nand), | |
856 | FUNCTION(uart_a), | |
857 | FUNCTION(uart_b), | |
49527bc0 | 858 | FUNCTION(uart_ao_b_z), |
83c56680 XC |
859 | FUNCTION(i2c0), |
860 | FUNCTION(i2c1), | |
861 | FUNCTION(i2c2), | |
862 | FUNCTION(i2c3), | |
863 | FUNCTION(eth), | |
864 | FUNCTION(pwm_a), | |
865 | FUNCTION(pwm_b), | |
866 | FUNCTION(pwm_c), | |
867 | FUNCTION(pwm_d), | |
868 | FUNCTION(pwm_vs), | |
869 | FUNCTION(spdif_out), | |
870 | FUNCTION(spdif_in), | |
871 | FUNCTION(jtag_ee), | |
872 | FUNCTION(pdm), | |
873 | }; | |
874 | ||
875 | static struct meson_pmx_func meson_axg_aobus_functions[] = { | |
876 | FUNCTION(gpio_aobus), | |
877 | FUNCTION(uart_ao_a), | |
878 | FUNCTION(uart_ao_b), | |
879 | FUNCTION(i2c_ao), | |
880 | FUNCTION(i2c_ao_slave), | |
881 | FUNCTION(remote_input_ao), | |
882 | FUNCTION(remote_out_ao), | |
883 | FUNCTION(pwm_ao_a), | |
884 | FUNCTION(pwm_ao_b), | |
885 | FUNCTION(pwm_ao_c), | |
886 | FUNCTION(pwm_ao_d), | |
887 | FUNCTION(jtag_ao), | |
888 | }; | |
889 | ||
890 | static struct meson_bank meson_axg_periphs_banks[] = { | |
891 | /* name first last irq pullen pull dir out in */ | |
892 | BANK("Z", GPIOZ_0, GPIOZ_10, 14, 24, 3, 0, 3, 0, 9, 0, 10, 0, 11, 0), | |
893 | BANK("BOOT", BOOT_0, BOOT_14, 25, 39, 4, 0, 4, 0, 12, 0, 13, 0, 14, 0), | |
894 | BANK("A", GPIOA_0, GPIOA_20, 40, 60, 0, 0, 0, 0, 0, 0, 1, 0, 2, 0), | |
895 | BANK("X", GPIOX_0, GPIOX_22, 61, 83, 2, 0, 2, 0, 6, 0, 7, 0, 8, 0), | |
896 | BANK("Y", GPIOY_0, GPIOY_15, 84, 99, 1, 0, 1, 0, 3, 0, 4, 0, 5, 0), | |
897 | }; | |
898 | ||
899 | static struct meson_bank meson_axg_aobus_banks[] = { | |
900 | /* name first last irq pullen pull dir out in */ | |
b84e5461 | 901 | BANK("AO", GPIOAO_0, GPIOAO_13, 0, 13, 0, 16, 0, 0, 0, 0, 0, 16, 1, 0), |
83c56680 XC |
902 | }; |
903 | ||
904 | static struct meson_pmx_bank meson_axg_periphs_pmx_banks[] = { | |
905 | /* name first lask reg offset */ | |
906 | BANK_PMX("Z", GPIOZ_0, GPIOZ_10, 0x2, 0), | |
907 | BANK_PMX("BOOT", BOOT_0, BOOT_14, 0x0, 0), | |
908 | BANK_PMX("A", GPIOA_0, GPIOA_20, 0xb, 0), | |
909 | BANK_PMX("X", GPIOX_0, GPIOX_22, 0x4, 0), | |
910 | BANK_PMX("Y", GPIOY_0, GPIOY_15, 0x8, 0), | |
911 | }; | |
912 | ||
913 | static struct meson_axg_pmx_data meson_axg_periphs_pmx_banks_data = { | |
914 | .pmx_banks = meson_axg_periphs_pmx_banks, | |
915 | .num_pmx_banks = ARRAY_SIZE(meson_axg_periphs_pmx_banks), | |
916 | }; | |
917 | ||
918 | static struct meson_pmx_bank meson_axg_aobus_pmx_banks[] = { | |
919 | BANK_PMX("AO", GPIOAO_0, GPIOAO_13, 0x0, 0), | |
920 | }; | |
921 | ||
922 | static struct meson_axg_pmx_data meson_axg_aobus_pmx_banks_data = { | |
923 | .pmx_banks = meson_axg_aobus_pmx_banks, | |
924 | .num_pmx_banks = ARRAY_SIZE(meson_axg_aobus_pmx_banks), | |
925 | }; | |
926 | ||
927 | static struct meson_pinctrl_data meson_axg_periphs_pinctrl_data = { | |
928 | .name = "periphs-banks", | |
929 | .pins = meson_axg_periphs_pins, | |
930 | .groups = meson_axg_periphs_groups, | |
931 | .funcs = meson_axg_periphs_functions, | |
932 | .banks = meson_axg_periphs_banks, | |
933 | .num_pins = ARRAY_SIZE(meson_axg_periphs_pins), | |
934 | .num_groups = ARRAY_SIZE(meson_axg_periphs_groups), | |
935 | .num_funcs = ARRAY_SIZE(meson_axg_periphs_functions), | |
936 | .num_banks = ARRAY_SIZE(meson_axg_periphs_banks), | |
937 | .pmx_ops = &meson_axg_pmx_ops, | |
938 | .pmx_data = &meson_axg_periphs_pmx_banks_data, | |
939 | }; | |
940 | ||
941 | static struct meson_pinctrl_data meson_axg_aobus_pinctrl_data = { | |
942 | .name = "aobus-banks", | |
943 | .pins = meson_axg_aobus_pins, | |
944 | .groups = meson_axg_aobus_groups, | |
945 | .funcs = meson_axg_aobus_functions, | |
946 | .banks = meson_axg_aobus_banks, | |
947 | .num_pins = ARRAY_SIZE(meson_axg_aobus_pins), | |
948 | .num_groups = ARRAY_SIZE(meson_axg_aobus_groups), | |
949 | .num_funcs = ARRAY_SIZE(meson_axg_aobus_functions), | |
950 | .num_banks = ARRAY_SIZE(meson_axg_aobus_banks), | |
951 | .pmx_ops = &meson_axg_pmx_ops, | |
952 | .pmx_data = &meson_axg_aobus_pmx_banks_data, | |
953 | }; | |
954 | ||
955 | static const struct of_device_id meson_axg_pinctrl_dt_match[] = { | |
956 | { | |
957 | .compatible = "amlogic,meson-axg-periphs-pinctrl", | |
958 | .data = &meson_axg_periphs_pinctrl_data, | |
959 | }, | |
960 | { | |
961 | .compatible = "amlogic,meson-axg-aobus-pinctrl", | |
962 | .data = &meson_axg_aobus_pinctrl_data, | |
963 | }, | |
964 | { }, | |
965 | }; | |
966 | ||
967 | static struct platform_driver meson_axg_pinctrl_driver = { | |
968 | .probe = meson_pinctrl_probe, | |
969 | .driver = { | |
970 | .name = "meson-axg-pinctrl", | |
971 | .of_match_table = meson_axg_pinctrl_dt_match, | |
972 | }, | |
973 | }; | |
974 | ||
975 | builtin_platform_driver(meson_axg_pinctrl_driver); |