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[mirror_ubuntu-artful-kernel.git] / drivers / pinctrl / mvebu / pinctrl-armada-37xx.c
CommitLineData
87466ccd
GC		 1/*
2 * Marvell 37xx SoC pinctrl driver
3 *
4 * Copyright (C) 2017 Marvell
5 *
6 * Gregory CLEMENT <gregory.clement@free-electrons.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2 or later. This program is licensed "as is"
10 * without any warranty of any kind, whether express or implied.
11 */
12
5715092a 13#include <linux/gpio/driver.h>
87466ccd
GC		 14#include <linux/mfd/syscon.h>
15#include <linux/of.h>
2f227605 16#include <linux/of_address.h>
87466ccd 17#include <linux/of_device.h>
2f227605 18#include <linux/of_irq.h>
87466ccd
GC		 19#include <linux/pinctrl/pinconf-generic.h>
20#include <linux/pinctrl/pinconf.h>
21#include <linux/pinctrl/pinctrl.h>
22#include <linux/pinctrl/pinmux.h>
23#include <linux/platform_device.h>
24#include <linux/regmap.h>
25#include <linux/slab.h>
26
27#include "../pinctrl-utils.h"
28
29#define OUTPUT_EN 0x0
5715092a
GC		 30#define INPUT_VAL 0x10
31#define OUTPUT_VAL 0x18
87466ccd
GC		 32#define OUTPUT_CTL 0x20
33#define SELECTION 0x30
34
2f227605
GC		 35#define IRQ_EN 0x0
36#define IRQ_POL 0x08
37#define IRQ_STATUS 0x10
38#define IRQ_WKUP 0x18
39
9ac6e7cc 40#define NB_FUNCS 3
87466ccd
GC		 41#define GPIO_PER_REG 32
42
43/**
44 * struct armada_37xx_pin_group: represents group of pins of a pinmux function.
45 * The pins of a pinmux groups are composed of one or two groups of contiguous
46 * pins.
47 * @name: Name of the pin group, used to lookup the group.
48 * @start_pins: Index of the first pin of the main range of pins belonging to
49 * the group
50 * @npins: Number of pins included in the first range
51 * @reg_mask: Bit mask matching the group in the selection register
52 * @extra_pins: Index of the first pin of the optional second range of pins
53 * belonging to the group
54 * @npins: Number of pins included in the second optional range
55 * @funcs: A list of pinmux functions that can be selected for this group.
56 * @pins: List of the pins included in the group
57 */
58struct armada_37xx_pin_group {
59 const char *name;
60 unsigned int start_pin;
61 unsigned int npins;
62 u32 reg_mask;
63 u32 val[NB_FUNCS];
64 unsigned int extra_pin;
65 unsigned int extra_npins;
66 const char *funcs[NB_FUNCS];
67 unsigned int *pins;
68};
69
70struct armada_37xx_pin_data {
71 u8 nr_pins;
72 char *name;
73 struct armada_37xx_pin_group *groups;
74 int ngroups;
75};
76
77struct armada_37xx_pmx_func {
78 const char *name;
79 const char **groups;
80 unsigned int ngroups;
81};
82
83struct armada_37xx_pinctrl {
84 struct regmap *regmap;
2f227605 85 void __iomem *base;
87466ccd
GC		 86 const struct armada_37xx_pin_data *data;
87 struct device *dev;
5715092a 88 struct gpio_chip gpio_chip;
2f227605
GC		 89 struct irq_chip irq_chip;
90 spinlock_t irq_lock;
87466ccd
GC		 91 struct pinctrl_desc pctl;
92 struct pinctrl_dev *pctl_dev;
93 struct armada_37xx_pin_group *groups;
94 unsigned int ngroups;
95 struct armada_37xx_pmx_func *funcs;
96 unsigned int nfuncs;
97};
98
99#define PIN_GRP(_name, _start, _nr, _mask, _func1, _func2) \
100 { \
101 .name = _name, \
102 .start_pin = _start, \
103 .npins = _nr, \
104 .reg_mask = _mask, \
105 .val = {0, _mask}, \
106 .funcs = {_func1, _func2} \
107 }
108
109#define PIN_GRP_GPIO(_name, _start, _nr, _mask, _func1) \
110 { \
111 .name = _name, \
112 .start_pin = _start, \
113 .npins = _nr, \
114 .reg_mask = _mask, \
115 .val = {0, _mask}, \
116 .funcs = {_func1, "gpio"} \
117 }
118
119#define PIN_GRP_GPIO_2(_name, _start, _nr, _mask, _val1, _val2, _func1) \
120 { \
121 .name = _name, \
122 .start_pin = _start, \
123 .npins = _nr, \
124 .reg_mask = _mask, \
125 .val = {_val1, _val2}, \
126 .funcs = {_func1, "gpio"} \
127 }
128
9ac6e7cc
GC		 129#define PIN_GRP_GPIO_3(_name, _start, _nr, _mask, _v1, _v2, _v3, _f1, _f2) \
130 { \
131 .name = _name, \
132 .start_pin = _start, \
133 .npins = _nr, \
134 .reg_mask = _mask, \
135 .val = {_v1, _v2, _v3}, \
136 .funcs = {_f1, _f2, "gpio"} \
137 }
138
87466ccd
GC		 139#define PIN_GRP_EXTRA(_name, _start, _nr, _mask, _v1, _v2, _start2, _nr2, \
140 _f1, _f2) \
141 { \
142 .name = _name, \
143 .start_pin = _start, \
144 .npins = _nr, \
145 .reg_mask = _mask, \
146 .val = {_v1, _v2}, \
147 .extra_pin = _start2, \
148 .extra_npins = _nr2, \
149 .funcs = {_f1, _f2} \
150 }
151
152static struct armada_37xx_pin_group armada_37xx_nb_groups[] = {
153 PIN_GRP_GPIO("jtag", 20, 5, BIT(0), "jtag"),
154 PIN_GRP_GPIO("sdio0", 8, 3, BIT(1), "sdio"),
155 PIN_GRP_GPIO("emmc_nb", 27, 9, BIT(2), "emmc"),
156 PIN_GRP_GPIO("pwm0", 11, 1, BIT(3), "pwm"),
157 PIN_GRP_GPIO("pwm1", 12, 1, BIT(4), "pwm"),
158 PIN_GRP_GPIO("pwm2", 13, 1, BIT(5), "pwm"),
159 PIN_GRP_GPIO("pwm3", 14, 1, BIT(6), "pwm"),
160 PIN_GRP_GPIO("pmic1", 17, 1, BIT(7), "pmic"),
161 PIN_GRP_GPIO("pmic0", 16, 1, BIT(8), "pmic"),
162 PIN_GRP_GPIO("i2c2", 2, 2, BIT(9), "i2c"),
163 PIN_GRP_GPIO("i2c1", 0, 2, BIT(10), "i2c"),
164 PIN_GRP_GPIO("spi_cs1", 17, 1, BIT(12), "spi"),
165 PIN_GRP_GPIO_2("spi_cs2", 18, 1, BIT(13) | BIT(19), 0, BIT(13), "spi"),
166 PIN_GRP_GPIO_2("spi_cs3", 19, 1, BIT(14) | BIT(19), 0, BIT(14), "spi"),
167 PIN_GRP_GPIO("onewire", 4, 1, BIT(16), "onewire"),
168 PIN_GRP_GPIO("uart1", 25, 2, BIT(17), "uart"),
169 PIN_GRP_GPIO("spi_quad", 15, 2, BIT(18), "spi"),
ce8a4a38
KM		 170 PIN_GRP_EXTRA("uart2", 9, 2, BIT(1) | BIT(13) | BIT(14) | BIT(19),
171 BIT(1) | BIT(13) | BIT(14), BIT(1) | BIT(19),
172 18, 2, "gpio", "uart"),
87466ccd
GC		 173 PIN_GRP_GPIO("led0_od", 11, 1, BIT(20), "led"),
174 PIN_GRP_GPIO("led1_od", 12, 1, BIT(21), "led"),
175 PIN_GRP_GPIO("led2_od", 13, 1, BIT(22), "led"),
176 PIN_GRP_GPIO("led3_od", 14, 1, BIT(23), "led"),
177
178};
179
180static struct armada_37xx_pin_group armada_37xx_sb_groups[] = {
181 PIN_GRP_GPIO("usb32_drvvbus0", 0, 1, BIT(0), "drvbus"),
182 PIN_GRP_GPIO("usb2_drvvbus1", 1, 1, BIT(1), "drvbus"),
8137f78a 183 PIN_GRP_GPIO("sdio_sb", 24, 6, BIT(2), "sdio"),
9ac6e7cc 184 PIN_GRP_GPIO("rgmii", 6, 12, BIT(3), "mii"),
87466ccd
GC		 185 PIN_GRP_GPIO("pcie1", 3, 2, BIT(4), "pcie"),
186 PIN_GRP_GPIO("ptp", 20, 3, BIT(5), "ptp"),
187 PIN_GRP("ptp_clk", 21, 1, BIT(6), "ptp", "mii"),
188 PIN_GRP("ptp_trig", 22, 1, BIT(7), "ptp", "mii"),
9ac6e7cc
GC		 189 PIN_GRP_GPIO_3("mii_col", 23, 1, BIT(8) | BIT(14), 0, BIT(8), BIT(14),
190 "mii", "mii_err"),
87466ccd
GC		 191};
192
193const struct armada_37xx_pin_data armada_37xx_pin_nb = {
194 .nr_pins = 36,
195 .name = "GPIO1",
196 .groups = armada_37xx_nb_groups,
197 .ngroups = ARRAY_SIZE(armada_37xx_nb_groups),
198};
199
200const struct armada_37xx_pin_data armada_37xx_pin_sb = {
6b67c390 201 .nr_pins = 30,
87466ccd
GC		 202 .name = "GPIO2",
203 .groups = armada_37xx_sb_groups,
204 .ngroups = ARRAY_SIZE(armada_37xx_sb_groups),
205};
206
5715092a
GC		 207static inline void armada_37xx_update_reg(unsigned int *reg,
208 unsigned int offset)
209{
210 /* We never have more than 2 registers */
211 if (offset >= GPIO_PER_REG) {
212 offset -= GPIO_PER_REG;
213 *reg += sizeof(u32);
214 }
215}
216
87466ccd
GC		 217static int armada_37xx_get_func_reg(struct armada_37xx_pin_group *grp,
218 const char *func)
219{
220 int f;
221
9ac6e7cc 222 for (f = 0; (f < NB_FUNCS) && grp->funcs[f]; f++)
87466ccd
GC		 223 if (!strcmp(grp->funcs[f], func))
224 return f;
225
226 return -ENOTSUPP;
227}
228
229static struct armada_37xx_pin_group *armada_37xx_find_next_grp_by_pin(
230 struct armada_37xx_pinctrl *info, int pin, int *grp)
231{
232 while (*grp < info->ngroups) {
233 struct armada_37xx_pin_group *group = &info->groups[*grp];
234 int j;
235
236 *grp = *grp + 1;
237 for (j = 0; j < (group->npins + group->extra_npins); j++)
238 if (group->pins[j] == pin)
239 return group;
240 }
241 return NULL;
242}
243
244static int armada_37xx_pin_config_group_get(struct pinctrl_dev *pctldev,
245 unsigned int selector, unsigned long *config)
246{
247 return -ENOTSUPP;
248}
249
250static int armada_37xx_pin_config_group_set(struct pinctrl_dev *pctldev,
251 unsigned int selector, unsigned long *configs,
252 unsigned int num_configs)
253{
254 return -ENOTSUPP;
255}
256
257static struct pinconf_ops armada_37xx_pinconf_ops = {
258 .is_generic = true,
259 .pin_config_group_get = armada_37xx_pin_config_group_get,
260 .pin_config_group_set = armada_37xx_pin_config_group_set,
261};
262
263static int armada_37xx_get_groups_count(struct pinctrl_dev *pctldev)
264{
265 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
266
267 return info->ngroups;
268}
269
270static const char *armada_37xx_get_group_name(struct pinctrl_dev *pctldev,
271 unsigned int group)
272{
273 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
274
275 return info->groups[group].name;
276}
277
278static int armada_37xx_get_group_pins(struct pinctrl_dev *pctldev,
279 unsigned int selector,
280 const unsigned int **pins,
281 unsigned int *npins)
282{
283 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
284
285 if (selector >= info->ngroups)
286 return -EINVAL;
287
288 *pins = info->groups[selector].pins;
289 *npins = info->groups[selector].npins +
290 info->groups[selector].extra_npins;
291
292 return 0;
293}
294
295static const struct pinctrl_ops armada_37xx_pctrl_ops = {
296 .get_groups_count = armada_37xx_get_groups_count,
297 .get_group_name = armada_37xx_get_group_name,
298 .get_group_pins = armada_37xx_get_group_pins,
299 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
300 .dt_free_map = pinctrl_utils_free_map,
301};
302
303/*
304 * Pinmux_ops handling
305 */
306
307static int armada_37xx_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
308{
309 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
310
311 return info->nfuncs;
312}
313
314static const char *armada_37xx_pmx_get_func_name(struct pinctrl_dev *pctldev,
315 unsigned int selector)
316{
317 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
318
319 return info->funcs[selector].name;
320}
321
322static int armada_37xx_pmx_get_groups(struct pinctrl_dev *pctldev,
323 unsigned int selector,
324 const char * const **groups,
325 unsigned int * const num_groups)
326{
327 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
328
329 *groups = info->funcs[selector].groups;
330 *num_groups = info->funcs[selector].ngroups;
331
332 return 0;
333}
334
335static int armada_37xx_pmx_set_by_name(struct pinctrl_dev *pctldev,
336 const char *name,
337 struct armada_37xx_pin_group *grp)
338{
339 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
340 unsigned int reg = SELECTION;
341 unsigned int mask = grp->reg_mask;
342 int func, val;
343
344 dev_dbg(info->dev, "enable function %s group %s\n",
345 name, grp->name);
346
347 func = armada_37xx_get_func_reg(grp, name);
348
349 if (func < 0)
350 return func;
351
352 val = grp->val[func];
353
354 regmap_update_bits(info->regmap, reg, mask, val);
355
356 return 0;
357}
358
359static int armada_37xx_pmx_set(struct pinctrl_dev *pctldev,
360 unsigned int selector,
361 unsigned int group)
362{
363
364 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
365 struct armada_37xx_pin_group *grp = &info->groups[group];
366 const char *name = info->funcs[selector].name;
367
368 return armada_37xx_pmx_set_by_name(pctldev, name, grp);
369}
370
2f227605
GC		 371static inline void armada_37xx_irq_update_reg(unsigned int *reg,
372 struct irq_data *d)
373{
374 int offset = irqd_to_hwirq(d);
375
376 armada_37xx_update_reg(reg, offset);
377}
378
5715092a
GC		 379static int armada_37xx_gpio_direction_input(struct gpio_chip *chip,
380 unsigned int offset)
87466ccd 381{
5715092a 382 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
87466ccd
GC		 383 unsigned int reg = OUTPUT_EN;
384 unsigned int mask;
385
5715092a 386 armada_37xx_update_reg(&reg, offset);
87466ccd
GC		 387 mask = BIT(offset);
388
389 return regmap_update_bits(info->regmap, reg, mask, 0);
390}
391
5715092a
GC		 392static int armada_37xx_gpio_get_direction(struct gpio_chip *chip,
393 unsigned int offset)
87466ccd 394{
5715092a
GC		 395 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
396 unsigned int reg = OUTPUT_EN;
397 unsigned int val, mask;
398
399 armada_37xx_update_reg(&reg, offset);
400 mask = BIT(offset);
401 regmap_read(info->regmap, reg, &val);
402
403 return !(val & mask);
404}
405
406static int armada_37xx_gpio_direction_output(struct gpio_chip *chip,
407 unsigned int offset, int value)
408{
409 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
87466ccd
GC		 410 unsigned int reg = OUTPUT_EN;
411 unsigned int mask;
412
5715092a 413 armada_37xx_update_reg(&reg, offset);
87466ccd
GC		 414 mask = BIT(offset);
415
416 return regmap_update_bits(info->regmap, reg, mask, mask);
417}
418
5715092a
GC		 419static int armada_37xx_gpio_get(struct gpio_chip *chip, unsigned int offset)
420{
421 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
422 unsigned int reg = INPUT_VAL;
423 unsigned int val, mask;
424
425 armada_37xx_update_reg(&reg, offset);
426 mask = BIT(offset);
427
428 regmap_read(info->regmap, reg, &val);
429
430 return (val & mask) != 0;
431}
432
433static void armada_37xx_gpio_set(struct gpio_chip *chip, unsigned int offset,
434 int value)
435{
436 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
437 unsigned int reg = OUTPUT_VAL;
438 unsigned int mask, val;
439
440 armada_37xx_update_reg(&reg, offset);
441 mask = BIT(offset);
442 val = value ? mask : 0;
443
444 regmap_update_bits(info->regmap, reg, mask, val);
445}
446
87466ccd
GC		 447static int armada_37xx_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
448 struct pinctrl_gpio_range *range,
449 unsigned int offset, bool input)
450{
451 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
5715092a 452 struct gpio_chip *chip = range->gc;
87466ccd
GC		 453
454 dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n",
455 offset, range->name, offset, input ? "input" : "output");
456
457 if (input)
5715092a 458 armada_37xx_gpio_direction_input(chip, offset);
87466ccd 459 else
5715092a 460 armada_37xx_gpio_direction_output(chip, offset, 0);
87466ccd
GC		 461
462 return 0;
463}
464
465static int armada_37xx_gpio_request_enable(struct pinctrl_dev *pctldev,
466 struct pinctrl_gpio_range *range,
467 unsigned int offset)
468{
469 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
470 struct armada_37xx_pin_group *group;
471 int grp = 0;
472
473 dev_dbg(info->dev, "requesting gpio %d\n", offset);
474
475 while ((group = armada_37xx_find_next_grp_by_pin(info, offset, &grp)))
476 armada_37xx_pmx_set_by_name(pctldev, "gpio", group);
477
478 return 0;
479}
480
481static const struct pinmux_ops armada_37xx_pmx_ops = {
482 .get_functions_count = armada_37xx_pmx_get_funcs_count,
483 .get_function_name = armada_37xx_pmx_get_func_name,
484 .get_function_groups = armada_37xx_pmx_get_groups,
485 .set_mux = armada_37xx_pmx_set,
486 .gpio_request_enable = armada_37xx_gpio_request_enable,
487 .gpio_set_direction = armada_37xx_pmx_gpio_set_direction,
488};
489
5715092a
GC		 490static const struct gpio_chip armada_37xx_gpiolib_chip = {
491 .request = gpiochip_generic_request,
492 .free = gpiochip_generic_free,
493 .set = armada_37xx_gpio_set,
494 .get = armada_37xx_gpio_get,
495 .get_direction = armada_37xx_gpio_get_direction,
496 .direction_input = armada_37xx_gpio_direction_input,
497 .direction_output = armada_37xx_gpio_direction_output,
498 .owner = THIS_MODULE,
499};
500
2f227605
GC		 501static void armada_37xx_irq_ack(struct irq_data *d)
502{
503 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
504 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
505 u32 reg = IRQ_STATUS;
506 unsigned long flags;
507
508 armada_37xx_irq_update_reg(&reg, d);
509 spin_lock_irqsave(&info->irq_lock, flags);
510 writel(d->mask, info->base + reg);
511 spin_unlock_irqrestore(&info->irq_lock, flags);
512}
513
514static void armada_37xx_irq_mask(struct irq_data *d)
515{
516 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
517 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
518 u32 val, reg = IRQ_EN;
519 unsigned long flags;
520
521 armada_37xx_irq_update_reg(&reg, d);
522 spin_lock_irqsave(&info->irq_lock, flags);
523 val = readl(info->base + reg);
524 writel(val & ~d->mask, info->base + reg);
525 spin_unlock_irqrestore(&info->irq_lock, flags);
526}
527
528static void armada_37xx_irq_unmask(struct irq_data *d)
529{
530 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
531 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
532 u32 val, reg = IRQ_EN;
533 unsigned long flags;
534
535 armada_37xx_irq_update_reg(&reg, d);
536 spin_lock_irqsave(&info->irq_lock, flags);
537 val = readl(info->base + reg);
538 writel(val | d->mask, info->base + reg);
539 spin_unlock_irqrestore(&info->irq_lock, flags);
540}
541
542static int armada_37xx_irq_set_wake(struct irq_data *d, unsigned int on)
543{
544 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
545 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
546 u32 val, reg = IRQ_WKUP;
547 unsigned long flags;
548
549 armada_37xx_irq_update_reg(&reg, d);
550 spin_lock_irqsave(&info->irq_lock, flags);
551 val = readl(info->base + reg);
552 if (on)
553 val |= d->mask;
554 else
555 val &= ~d->mask;
556 writel(val, info->base + reg);
557 spin_unlock_irqrestore(&info->irq_lock, flags);
558
559 return 0;
560}
561
562static int armada_37xx_irq_set_type(struct irq_data *d, unsigned int type)
563{
564 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
565 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
566 u32 val, reg = IRQ_POL;
567 unsigned long flags;
568
569 spin_lock_irqsave(&info->irq_lock, flags);
570 armada_37xx_irq_update_reg(&reg, d);
571 val = readl(info->base + reg);
572 switch (type) {
573 case IRQ_TYPE_EDGE_RISING:
574 val &= ~d->mask;
575 break;
576 case IRQ_TYPE_EDGE_FALLING:
577 val |= d->mask;
578 break;
579 default:
580 spin_unlock_irqrestore(&info->irq_lock, flags);
581 return -EINVAL;
582 }
583 writel(val, info->base + reg);
584 spin_unlock_irqrestore(&info->irq_lock, flags);
585
586 return 0;
587}
588
589
590static void armada_37xx_irq_handler(struct irq_desc *desc)
591{
592 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
593 struct irq_chip *chip = irq_desc_get_chip(desc);
594 struct armada_37xx_pinctrl *info = gpiochip_get_data(gc);
595 struct irq_domain *d = gc->irqdomain;
596 int i;
597
598 chained_irq_enter(chip, desc);
599 for (i = 0; i <= d->revmap_size / GPIO_PER_REG; i++) {
600 u32 status;
601 unsigned long flags;
602
603 spin_lock_irqsave(&info->irq_lock, flags);
604 status = readl_relaxed(info->base + IRQ_STATUS + 4 * i);
605 /* Manage only the interrupt that was enabled */
606 status &= readl_relaxed(info->base + IRQ_EN + 4 * i);
607 spin_unlock_irqrestore(&info->irq_lock, flags);
608 while (status) {
609 u32 hwirq = ffs(status) - 1;
610 u32 virq = irq_find_mapping(d, hwirq +
611 i * GPIO_PER_REG);
612
613 generic_handle_irq(virq);
614
615 /* Update status in case a new IRQ appears */
616 spin_lock_irqsave(&info->irq_lock, flags);
617 status = readl_relaxed(info->base +
618 IRQ_STATUS + 4 * i);
619 /* Manage only the interrupt that was enabled */
620 status &= readl_relaxed(info->base + IRQ_EN + 4 * i);
621 spin_unlock_irqrestore(&info->irq_lock, flags);
622 }
623 }
624 chained_irq_exit(chip, desc);
625}
626
627static int armada_37xx_irqchip_register(struct platform_device *pdev,
628 struct armada_37xx_pinctrl *info)
629{
630 struct device_node *np = info->dev->of_node;
631 int nrirqs = info->data->nr_pins;
632 struct gpio_chip *gc = &info->gpio_chip;
633 struct irq_chip *irqchip = &info->irq_chip;
634 struct resource res;
635 int ret = -ENODEV, i, nr_irq_parent;
636
637 /* Check if we have at least one gpio-controller child node */
638 for_each_child_of_node(info->dev->of_node, np) {
639 if (of_property_read_bool(np, "gpio-controller")) {
640 ret = 0;
641 break;
642 }
643 };
644 if (ret)
645 return ret;
646
647 nr_irq_parent = of_irq_count(np);
648 spin_lock_init(&info->irq_lock);
649
650 if (!nr_irq_parent) {
651 dev_err(&pdev->dev, "Invalid or no IRQ\n");
652 return 0;
653 }
654
655 if (of_address_to_resource(info->dev->of_node, 1, &res)) {
656 dev_err(info->dev, "cannot find IO resource\n");
657 return -ENOENT;
658 }
659
660 info->base = devm_ioremap_resource(info->dev, &res);
661 if (IS_ERR(info->base))
662 return PTR_ERR(info->base);
663
664 irqchip->irq_ack = armada_37xx_irq_ack;
665 irqchip->irq_mask = armada_37xx_irq_mask;
666 irqchip->irq_unmask = armada_37xx_irq_unmask;
667 irqchip->irq_set_wake = armada_37xx_irq_set_wake;
668 irqchip->irq_set_type = armada_37xx_irq_set_type;
669 irqchip->name = info->data->name;
670
671 ret = gpiochip_irqchip_add(gc, irqchip, 0,
672 handle_edge_irq, IRQ_TYPE_NONE);
673 if (ret) {
674 dev_info(&pdev->dev, "could not add irqchip\n");
675 return ret;
676 }
677
678 /*
679 * Many interrupts are connected to the parent interrupt
680 * controller. But we do not take advantage of this and use
681 * the chained irq with all of them.
682 */
683 for (i = 0; i < nrirqs; i++) {
684 struct irq_data *d = irq_get_irq_data(gc->irq_base + i);
685
686 /*
687 * The mask field is a "precomputed bitmask for
688 * accessing the chip registers" which was introduced
689 * for the generic irqchip framework. As we don't use
690 * this framework, we can reuse this field for our own
691 * usage.
692 */
693 d->mask = BIT(i % GPIO_PER_REG);
694 }
695
696 for (i = 0; i < nr_irq_parent; i++) {
697 int irq = irq_of_parse_and_map(np, i);
698
699 if (irq < 0)
700 continue;
701
702 gpiochip_set_chained_irqchip(gc, irqchip, irq,
703 armada_37xx_irq_handler);
704 }
705
706 return 0;
707}
708
5715092a
GC		 709static int armada_37xx_gpiochip_register(struct platform_device *pdev,
710 struct armada_37xx_pinctrl *info)
711{
712 struct device_node *np;
713 struct gpio_chip *gc;
714 int ret = -ENODEV;
715
716 for_each_child_of_node(info->dev->of_node, np) {
717 if (of_find_property(np, "gpio-controller", NULL)) {
718 ret = 0;
719 break;
720 }
721 };
722 if (ret)
723 return ret;
724
725 info->gpio_chip = armada_37xx_gpiolib_chip;
726
727 gc = &info->gpio_chip;
728 gc->ngpio = info->data->nr_pins;
729 gc->parent = &pdev->dev;
730 gc->base = -1;
731 gc->of_node = np;
732 gc->label = info->data->name;
733
734 ret = devm_gpiochip_add_data(&pdev->dev, gc, info);
2f227605
GC		 735 if (ret)
736 return ret;
737 ret = armada_37xx_irqchip_register(pdev, info);
5715092a
GC		 738 if (ret)
739 return ret;
740
741 return 0;
742}
743
87466ccd
GC		 744/**
745 * armada_37xx_add_function() - Add a new function to the list
746 * @funcs: array of function to add the new one
747 * @funcsize: size of the remaining space for the function
748 * @name: name of the function to add
749 *
750 * If it is a new function then create it by adding its name else
751 * increment the number of group associated to this function.
752 */
753static int armada_37xx_add_function(struct armada_37xx_pmx_func *funcs,
754 int *funcsize, const char *name)
755{
756 int i = 0;
757
758 if (*funcsize <= 0)
759 return -EOVERFLOW;
760
761 while (funcs->ngroups) {
762 /* function already there */
763 if (strcmp(funcs->name, name) == 0) {
764 funcs->ngroups++;
765
766 return -EEXIST;
767 }
768 funcs++;
769 i++;
770 }
771
772 /* append new unique function */
773 funcs->name = name;
774 funcs->ngroups = 1;
775 (*funcsize)--;
776
777 return 0;
778}
779
780/**
781 * armada_37xx_fill_group() - complete the group array
782 * @info: info driver instance
783 *
784 * Based on the data available from the armada_37xx_pin_group array
785 * completes the last member of the struct for each function: the list
786 * of the groups associated to this function.
787 *
788 */
789static int armada_37xx_fill_group(struct armada_37xx_pinctrl *info)
790{
791 int n, num = 0, funcsize = info->data->nr_pins;
792
793 for (n = 0; n < info->ngroups; n++) {
794 struct armada_37xx_pin_group *grp = &info->groups[n];
795 int i, j, f;
796
797 grp->pins = devm_kzalloc(info->dev,
798 (grp->npins + grp->extra_npins) *
799 sizeof(*grp->pins), GFP_KERNEL);
800 if (!grp->pins)
801 return -ENOMEM;
802
803 for (i = 0; i < grp->npins; i++)
804 grp->pins[i] = grp->start_pin + i;
805
806 for (j = 0; j < grp->extra_npins; j++)
807 grp->pins[i+j] = grp->extra_pin + j;
808
9ac6e7cc 809 for (f = 0; (f < NB_FUNCS) && grp->funcs[f]; f++) {
87466ccd
GC		 810 int ret;
811 /* check for unique functions and count groups */
812 ret = armada_37xx_add_function(info->funcs, &funcsize,
813 grp->funcs[f]);
814 if (ret == -EOVERFLOW)
815 dev_err(info->dev,
816 "More functions than pins(%d)\n",
817 info->data->nr_pins);
818 if (ret < 0)
819 continue;
820 num++;
821 }
822 }
823
824 info->nfuncs = num;
825
826 return 0;
827}
828
829/**
830 * armada_37xx_fill_funcs() - complete the funcs array
831 * @info: info driver instance
832 *
833 * Based on the data available from the armada_37xx_pin_group array
834 * completes the last two member of the struct for each group:
835 * - the list of the pins included in the group
836 * - the list of pinmux functions that can be selected for this group
837 *
838 */
839static int armada_37xx_fill_func(struct armada_37xx_pinctrl *info)
840{
841 struct armada_37xx_pmx_func *funcs = info->funcs;
842 int n;
843
844 for (n = 0; n < info->nfuncs; n++) {
845 const char *name = funcs[n].name;
846 const char **groups;
847 int g;
848
849 funcs[n].groups = devm_kzalloc(info->dev, funcs[n].ngroups *
850 sizeof(*(funcs[n].groups)),
851 GFP_KERNEL);
852 if (!funcs[n].groups)
853 return -ENOMEM;
854
855 groups = funcs[n].groups;
856
857 for (g = 0; g < info->ngroups; g++) {
858 struct armada_37xx_pin_group *gp = &info->groups[g];
859 int f;
860
9ac6e7cc 861 for (f = 0; (f < NB_FUNCS) && gp->funcs[f]; f++) {
87466ccd
GC		 862 if (strcmp(gp->funcs[f], name) == 0) {
863 *groups = gp->name;
864 groups++;
865 }
866 }
867 }
868 }
869 return 0;
870}
871
872static int armada_37xx_pinctrl_register(struct platform_device *pdev,
873 struct armada_37xx_pinctrl *info)
874{
875 const struct armada_37xx_pin_data *pin_data = info->data;
876 struct pinctrl_desc *ctrldesc = &info->pctl;
877 struct pinctrl_pin_desc *pindesc, *pdesc;
878 int pin, ret;
879
880 info->groups = pin_data->groups;
881 info->ngroups = pin_data->ngroups;
882
883 ctrldesc->name = "armada_37xx-pinctrl";
884 ctrldesc->owner = THIS_MODULE;
885 ctrldesc->pctlops = &armada_37xx_pctrl_ops;
886 ctrldesc->pmxops = &armada_37xx_pmx_ops;
887 ctrldesc->confops = &armada_37xx_pinconf_ops;
888
889 pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) *
890 pin_data->nr_pins, GFP_KERNEL);
891 if (!pindesc)
892 return -ENOMEM;
893
894 ctrldesc->pins = pindesc;
895 ctrldesc->npins = pin_data->nr_pins;
896
897 pdesc = pindesc;
898 for (pin = 0; pin < pin_data->nr_pins; pin++) {
899 pdesc->number = pin;
900 pdesc->name = kasprintf(GFP_KERNEL, "%s-%d",
901 pin_data->name, pin);
902 pdesc++;
903 }
904
905 /*
906 * we allocate functions for number of pins and hope there are
907 * fewer unique functions than pins available
908 */
909 info->funcs = devm_kzalloc(&pdev->dev, pin_data->nr_pins *
910 sizeof(struct armada_37xx_pmx_func), GFP_KERNEL);
911 if (!info->funcs)
912 return -ENOMEM;
913
914
915 ret = armada_37xx_fill_group(info);
916 if (ret)
917 return ret;
918
919 ret = armada_37xx_fill_func(info);
920 if (ret)
921 return ret;
922
923 info->pctl_dev = devm_pinctrl_register(&pdev->dev, ctrldesc, info);
924 if (IS_ERR(info->pctl_dev)) {
925 dev_err(&pdev->dev, "could not register pinctrl driver\n");
926 return PTR_ERR(info->pctl_dev);
927 }
928
929 return 0;
930}
931
932static const struct of_device_id armada_37xx_pinctrl_of_match[] = {
933 {
934 .compatible = "marvell,armada3710-sb-pinctrl",
935 .data = (void *)&armada_37xx_pin_sb,
936 },
937 {
938 .compatible = "marvell,armada3710-nb-pinctrl",
939 .data = (void *)&armada_37xx_pin_nb,
940 },
941 { },
942};
943
944static int __init armada_37xx_pinctrl_probe(struct platform_device *pdev)
945{
946 struct armada_37xx_pinctrl *info;
947 struct device *dev = &pdev->dev;
948 struct device_node *np = dev->of_node;
949 struct regmap *regmap;
950 int ret;
951
952 info = devm_kzalloc(dev, sizeof(struct armada_37xx_pinctrl),
953 GFP_KERNEL);
954 if (!info)
955 return -ENOMEM;
956
957 info->dev = dev;
958
959 regmap = syscon_node_to_regmap(np);
960 if (IS_ERR(regmap)) {
961 dev_err(&pdev->dev, "cannot get regmap\n");
962 return PTR_ERR(regmap);
963 }
964 info->regmap = regmap;
965
966 info->data = of_device_get_match_data(dev);
967
968 ret = armada_37xx_pinctrl_register(pdev, info);
969 if (ret)
970 return ret;
971
5715092a
GC		 972 ret = armada_37xx_gpiochip_register(pdev, info);
973 if (ret)
974 return ret;
975
87466ccd
GC		 976 platform_set_drvdata(pdev, info);
977
978 return 0;
979}
980
981static struct platform_driver armada_37xx_pinctrl_driver = {
982 .driver = {
983 .name = "armada-37xx-pinctrl",
984 .of_match_table = armada_37xx_pinctrl_of_match,
985 },
986};
987
988builtin_platform_driver_probe(armada_37xx_pinctrl_driver,
989 armada_37xx_pinctrl_probe);
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