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Merge back PM core material for v4.16.
[mirror_ubuntu-jammy-kernel.git] / drivers / pinctrl / mvebu / pinctrl-armada-37xx.c
CommitLineData
87466ccd
GC		 1/*
2 * Marvell 37xx SoC pinctrl driver
3 *
4 * Copyright (C) 2017 Marvell
5 *
6 * Gregory CLEMENT <gregory.clement@free-electrons.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2 or later. This program is licensed "as is"
10 * without any warranty of any kind, whether express or implied.
11 */
12
5715092a 13#include <linux/gpio/driver.h>
87466ccd
GC		 14#include <linux/mfd/syscon.h>
15#include <linux/of.h>
2f227605 16#include <linux/of_address.h>
87466ccd 17#include <linux/of_device.h>
2f227605 18#include <linux/of_irq.h>
87466ccd
GC		 19#include <linux/pinctrl/pinconf-generic.h>
20#include <linux/pinctrl/pinconf.h>
21#include <linux/pinctrl/pinctrl.h>
22#include <linux/pinctrl/pinmux.h>
23#include <linux/platform_device.h>
24#include <linux/regmap.h>
25#include <linux/slab.h>
26
27#include "../pinctrl-utils.h"
28
29#define OUTPUT_EN 0x0
5715092a
GC		 30#define INPUT_VAL 0x10
31#define OUTPUT_VAL 0x18
87466ccd
GC		 32#define OUTPUT_CTL 0x20
33#define SELECTION 0x30
34
2f227605
GC		 35#define IRQ_EN 0x0
36#define IRQ_POL 0x08
37#define IRQ_STATUS 0x10
38#define IRQ_WKUP 0x18
39
9ac6e7cc 40#define NB_FUNCS 3
87466ccd
GC		 41#define GPIO_PER_REG 32
42
43/**
44 * struct armada_37xx_pin_group: represents group of pins of a pinmux function.
45 * The pins of a pinmux groups are composed of one or two groups of contiguous
46 * pins.
47 * @name: Name of the pin group, used to lookup the group.
48 * @start_pins: Index of the first pin of the main range of pins belonging to
49 * the group
50 * @npins: Number of pins included in the first range
51 * @reg_mask: Bit mask matching the group in the selection register
52 * @extra_pins: Index of the first pin of the optional second range of pins
53 * belonging to the group
54 * @npins: Number of pins included in the second optional range
55 * @funcs: A list of pinmux functions that can be selected for this group.
56 * @pins: List of the pins included in the group
57 */
58struct armada_37xx_pin_group {
59 const char *name;
60 unsigned int start_pin;
61 unsigned int npins;
62 u32 reg_mask;
63 u32 val[NB_FUNCS];
64 unsigned int extra_pin;
65 unsigned int extra_npins;
66 const char *funcs[NB_FUNCS];
67 unsigned int *pins;
68};
69
70struct armada_37xx_pin_data {
71 u8 nr_pins;
72 char *name;
73 struct armada_37xx_pin_group *groups;
74 int ngroups;
75};
76
77struct armada_37xx_pmx_func {
78 const char *name;
79 const char **groups;
80 unsigned int ngroups;
81};
82
83struct armada_37xx_pinctrl {
84 struct regmap *regmap;
2f227605 85 void __iomem *base;
87466ccd
GC		 86 const struct armada_37xx_pin_data *data;
87 struct device *dev;
5715092a 88 struct gpio_chip gpio_chip;
2f227605
GC		 89 struct irq_chip irq_chip;
90 spinlock_t irq_lock;
87466ccd
GC		 91 struct pinctrl_desc pctl;
92 struct pinctrl_dev *pctl_dev;
93 struct armada_37xx_pin_group *groups;
94 unsigned int ngroups;
95 struct armada_37xx_pmx_func *funcs;
96 unsigned int nfuncs;
97};
98
99#define PIN_GRP(_name, _start, _nr, _mask, _func1, _func2) \
100 { \
101 .name = _name, \
102 .start_pin = _start, \
103 .npins = _nr, \
104 .reg_mask = _mask, \
105 .val = {0, _mask}, \
106 .funcs = {_func1, _func2} \
107 }
108
109#define PIN_GRP_GPIO(_name, _start, _nr, _mask, _func1) \
110 { \
111 .name = _name, \
112 .start_pin = _start, \
113 .npins = _nr, \
114 .reg_mask = _mask, \
115 .val = {0, _mask}, \
116 .funcs = {_func1, "gpio"} \
117 }
118
119#define PIN_GRP_GPIO_2(_name, _start, _nr, _mask, _val1, _val2, _func1) \
120 { \
121 .name = _name, \
122 .start_pin = _start, \
123 .npins = _nr, \
124 .reg_mask = _mask, \
125 .val = {_val1, _val2}, \
126 .funcs = {_func1, "gpio"} \
127 }
128
9ac6e7cc
GC		 129#define PIN_GRP_GPIO_3(_name, _start, _nr, _mask, _v1, _v2, _v3, _f1, _f2) \
130 { \
131 .name = _name, \
132 .start_pin = _start, \
133 .npins = _nr, \
134 .reg_mask = _mask, \
135 .val = {_v1, _v2, _v3}, \
136 .funcs = {_f1, _f2, "gpio"} \
137 }
138
87466ccd
GC		 139#define PIN_GRP_EXTRA(_name, _start, _nr, _mask, _v1, _v2, _start2, _nr2, \
140 _f1, _f2) \
141 { \
142 .name = _name, \
143 .start_pin = _start, \
144 .npins = _nr, \
145 .reg_mask = _mask, \
146 .val = {_v1, _v2}, \
147 .extra_pin = _start2, \
148 .extra_npins = _nr2, \
149 .funcs = {_f1, _f2} \
150 }
151
152static struct armada_37xx_pin_group armada_37xx_nb_groups[] = {
153 PIN_GRP_GPIO("jtag", 20, 5, BIT(0), "jtag"),
154 PIN_GRP_GPIO("sdio0", 8, 3, BIT(1), "sdio"),
155 PIN_GRP_GPIO("emmc_nb", 27, 9, BIT(2), "emmc"),
156 PIN_GRP_GPIO("pwm0", 11, 1, BIT(3), "pwm"),
157 PIN_GRP_GPIO("pwm1", 12, 1, BIT(4), "pwm"),
158 PIN_GRP_GPIO("pwm2", 13, 1, BIT(5), "pwm"),
159 PIN_GRP_GPIO("pwm3", 14, 1, BIT(6), "pwm"),
160 PIN_GRP_GPIO("pmic1", 17, 1, BIT(7), "pmic"),
161 PIN_GRP_GPIO("pmic0", 16, 1, BIT(8), "pmic"),
162 PIN_GRP_GPIO("i2c2", 2, 2, BIT(9), "i2c"),
163 PIN_GRP_GPIO("i2c1", 0, 2, BIT(10), "i2c"),
164 PIN_GRP_GPIO("spi_cs1", 17, 1, BIT(12), "spi"),
165 PIN_GRP_GPIO_2("spi_cs2", 18, 1, BIT(13) | BIT(19), 0, BIT(13), "spi"),
166 PIN_GRP_GPIO_2("spi_cs3", 19, 1, BIT(14) | BIT(19), 0, BIT(14), "spi"),
167 PIN_GRP_GPIO("onewire", 4, 1, BIT(16), "onewire"),
168 PIN_GRP_GPIO("uart1", 25, 2, BIT(17), "uart"),
169 PIN_GRP_GPIO("spi_quad", 15, 2, BIT(18), "spi"),
ce8a4a38
KM		 170 PIN_GRP_EXTRA("uart2", 9, 2, BIT(1) | BIT(13) | BIT(14) | BIT(19),
171 BIT(1) | BIT(13) | BIT(14), BIT(1) | BIT(19),
172 18, 2, "gpio", "uart"),
87466ccd
GC		 173 PIN_GRP_GPIO("led0_od", 11, 1, BIT(20), "led"),
174 PIN_GRP_GPIO("led1_od", 12, 1, BIT(21), "led"),
175 PIN_GRP_GPIO("led2_od", 13, 1, BIT(22), "led"),
176 PIN_GRP_GPIO("led3_od", 14, 1, BIT(23), "led"),
177
178};
179
180static struct armada_37xx_pin_group armada_37xx_sb_groups[] = {
181 PIN_GRP_GPIO("usb32_drvvbus0", 0, 1, BIT(0), "drvbus"),
182 PIN_GRP_GPIO("usb2_drvvbus1", 1, 1, BIT(1), "drvbus"),
8137f78a 183 PIN_GRP_GPIO("sdio_sb", 24, 6, BIT(2), "sdio"),
9ac6e7cc 184 PIN_GRP_GPIO("rgmii", 6, 12, BIT(3), "mii"),
87466ccd
GC		 185 PIN_GRP_GPIO("pcie1", 3, 2, BIT(4), "pcie"),
186 PIN_GRP_GPIO("ptp", 20, 3, BIT(5), "ptp"),
187 PIN_GRP("ptp_clk", 21, 1, BIT(6), "ptp", "mii"),
188 PIN_GRP("ptp_trig", 22, 1, BIT(7), "ptp", "mii"),
9ac6e7cc
GC		 189 PIN_GRP_GPIO_3("mii_col", 23, 1, BIT(8) | BIT(14), 0, BIT(8), BIT(14),
190 "mii", "mii_err"),
87466ccd
GC		 191};
192
aea1dd4b 193static const struct armada_37xx_pin_data armada_37xx_pin_nb = {
87466ccd
GC		 194 .nr_pins = 36,
195 .name = "GPIO1",
196 .groups = armada_37xx_nb_groups,
197 .ngroups = ARRAY_SIZE(armada_37xx_nb_groups),
198};
199
aea1dd4b 200static const struct armada_37xx_pin_data armada_37xx_pin_sb = {
6b67c390 201 .nr_pins = 30,
87466ccd
GC		 202 .name = "GPIO2",
203 .groups = armada_37xx_sb_groups,
204 .ngroups = ARRAY_SIZE(armada_37xx_sb_groups),
205};
206
5715092a
GC		 207static inline void armada_37xx_update_reg(unsigned int *reg,
208 unsigned int offset)
209{
210 /* We never have more than 2 registers */
211 if (offset >= GPIO_PER_REG) {
212 offset -= GPIO_PER_REG;
213 *reg += sizeof(u32);
214 }
215}
216
87466ccd
GC		 217static int armada_37xx_get_func_reg(struct armada_37xx_pin_group *grp,
218 const char *func)
219{
220 int f;
221
9ac6e7cc 222 for (f = 0; (f < NB_FUNCS) && grp->funcs[f]; f++)
87466ccd
GC		 223 if (!strcmp(grp->funcs[f], func))
224 return f;
225
226 return -ENOTSUPP;
227}
228
229static struct armada_37xx_pin_group *armada_37xx_find_next_grp_by_pin(
230 struct armada_37xx_pinctrl *info, int pin, int *grp)
231{
232 while (*grp < info->ngroups) {
233 struct armada_37xx_pin_group *group = &info->groups[*grp];
234 int j;
235
236 *grp = *grp + 1;
237 for (j = 0; j < (group->npins + group->extra_npins); j++)
238 if (group->pins[j] == pin)
239 return group;
240 }
241 return NULL;
242}
243
244static int armada_37xx_pin_config_group_get(struct pinctrl_dev *pctldev,
245 unsigned int selector, unsigned long *config)
246{
247 return -ENOTSUPP;
248}
249
250static int armada_37xx_pin_config_group_set(struct pinctrl_dev *pctldev,
251 unsigned int selector, unsigned long *configs,
252 unsigned int num_configs)
253{
254 return -ENOTSUPP;
255}
256
9b4e2ba4 257static const struct pinconf_ops armada_37xx_pinconf_ops = {
87466ccd
GC		 258 .is_generic = true,
259 .pin_config_group_get = armada_37xx_pin_config_group_get,
260 .pin_config_group_set = armada_37xx_pin_config_group_set,
261};
262
263static int armada_37xx_get_groups_count(struct pinctrl_dev *pctldev)
264{
265 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
266
267 return info->ngroups;
268}
269
270static const char *armada_37xx_get_group_name(struct pinctrl_dev *pctldev,
271 unsigned int group)
272{
273 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
274
275 return info->groups[group].name;
276}
277
278static int armada_37xx_get_group_pins(struct pinctrl_dev *pctldev,
279 unsigned int selector,
280 const unsigned int **pins,
281 unsigned int *npins)
282{
283 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
284
285 if (selector >= info->ngroups)
286 return -EINVAL;
287
288 *pins = info->groups[selector].pins;
289 *npins = info->groups[selector].npins +
290 info->groups[selector].extra_npins;
291
292 return 0;
293}
294
295static const struct pinctrl_ops armada_37xx_pctrl_ops = {
296 .get_groups_count = armada_37xx_get_groups_count,
297 .get_group_name = armada_37xx_get_group_name,
298 .get_group_pins = armada_37xx_get_group_pins,
299 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
300 .dt_free_map = pinctrl_utils_free_map,
301};
302
303/*
304 * Pinmux_ops handling
305 */
306
307static int armada_37xx_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
308{
309 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
310
311 return info->nfuncs;
312}
313
314static const char *armada_37xx_pmx_get_func_name(struct pinctrl_dev *pctldev,
315 unsigned int selector)
316{
317 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
318
319 return info->funcs[selector].name;
320}
321
322static int armada_37xx_pmx_get_groups(struct pinctrl_dev *pctldev,
323 unsigned int selector,
324 const char * const **groups,
325 unsigned int * const num_groups)
326{
327 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
328
329 *groups = info->funcs[selector].groups;
330 *num_groups = info->funcs[selector].ngroups;
331
332 return 0;
333}
334
335static int armada_37xx_pmx_set_by_name(struct pinctrl_dev *pctldev,
336 const char *name,
337 struct armada_37xx_pin_group *grp)
338{
339 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
340 unsigned int reg = SELECTION;
341 unsigned int mask = grp->reg_mask;
342 int func, val;
343
344 dev_dbg(info->dev, "enable function %s group %s\n",
345 name, grp->name);
346
347 func = armada_37xx_get_func_reg(grp, name);
348
349 if (func < 0)
350 return func;
351
352 val = grp->val[func];
353
354 regmap_update_bits(info->regmap, reg, mask, val);
355
356 return 0;
357}
358
359static int armada_37xx_pmx_set(struct pinctrl_dev *pctldev,
360 unsigned int selector,
361 unsigned int group)
362{
363
364 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
365 struct armada_37xx_pin_group *grp = &info->groups[group];
366 const char *name = info->funcs[selector].name;
367
368 return armada_37xx_pmx_set_by_name(pctldev, name, grp);
369}
370
2f227605
GC		 371static inline void armada_37xx_irq_update_reg(unsigned int *reg,
372 struct irq_data *d)
373{
374 int offset = irqd_to_hwirq(d);
375
376 armada_37xx_update_reg(reg, offset);
377}
378
5715092a
GC		 379static int armada_37xx_gpio_direction_input(struct gpio_chip *chip,
380 unsigned int offset)
87466ccd 381{
5715092a 382 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
87466ccd
GC		 383 unsigned int reg = OUTPUT_EN;
384 unsigned int mask;
385
5715092a 386 armada_37xx_update_reg(&reg, offset);
87466ccd
GC		 387 mask = BIT(offset);
388
389 return regmap_update_bits(info->regmap, reg, mask, 0);
390}
391
5715092a
GC		 392static int armada_37xx_gpio_get_direction(struct gpio_chip *chip,
393 unsigned int offset)
87466ccd 394{
5715092a
GC		 395 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
396 unsigned int reg = OUTPUT_EN;
397 unsigned int val, mask;
398
399 armada_37xx_update_reg(&reg, offset);
400 mask = BIT(offset);
401 regmap_read(info->regmap, reg, &val);
402
403 return !(val & mask);
404}
405
406static int armada_37xx_gpio_direction_output(struct gpio_chip *chip,
407 unsigned int offset, int value)
408{
409 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
87466ccd 410 unsigned int reg = OUTPUT_EN;
6702abb3 411 unsigned int mask, val, ret;
87466ccd 412
5715092a 413 armada_37xx_update_reg(&reg, offset);
87466ccd
GC		 414 mask = BIT(offset);
415
6702abb3
GC		 416 ret = regmap_update_bits(info->regmap, reg, mask, mask);
417
418 if (ret)
419 return ret;
420
421 reg = OUTPUT_VAL;
422 val = value ? mask : 0;
423 regmap_update_bits(info->regmap, reg, mask, val);
424
425 return 0;
87466ccd
GC		 426}
427
5715092a
GC		 428static int armada_37xx_gpio_get(struct gpio_chip *chip, unsigned int offset)
429{
430 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
431 unsigned int reg = INPUT_VAL;
432 unsigned int val, mask;
433
434 armada_37xx_update_reg(&reg, offset);
435 mask = BIT(offset);
436
437 regmap_read(info->regmap, reg, &val);
438
439 return (val & mask) != 0;
440}
441
442static void armada_37xx_gpio_set(struct gpio_chip *chip, unsigned int offset,
443 int value)
444{
445 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
446 unsigned int reg = OUTPUT_VAL;
447 unsigned int mask, val;
448
449 armada_37xx_update_reg(&reg, offset);
450 mask = BIT(offset);
451 val = value ? mask : 0;
452
453 regmap_update_bits(info->regmap, reg, mask, val);
454}
455
87466ccd
GC		 456static int armada_37xx_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
457 struct pinctrl_gpio_range *range,
458 unsigned int offset, bool input)
459{
460 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
5715092a 461 struct gpio_chip *chip = range->gc;
87466ccd
GC		 462
463 dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n",
464 offset, range->name, offset, input ? "input" : "output");
465
466 if (input)
5715092a 467 armada_37xx_gpio_direction_input(chip, offset);
87466ccd 468 else
5715092a 469 armada_37xx_gpio_direction_output(chip, offset, 0);
87466ccd
GC		 470
471 return 0;
472}
473
474static int armada_37xx_gpio_request_enable(struct pinctrl_dev *pctldev,
475 struct pinctrl_gpio_range *range,
476 unsigned int offset)
477{
478 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
479 struct armada_37xx_pin_group *group;
480 int grp = 0;
481
482 dev_dbg(info->dev, "requesting gpio %d\n", offset);
483
484 while ((group = armada_37xx_find_next_grp_by_pin(info, offset, &grp)))
485 armada_37xx_pmx_set_by_name(pctldev, "gpio", group);
486
487 return 0;
488}
489
490static const struct pinmux_ops armada_37xx_pmx_ops = {
491 .get_functions_count = armada_37xx_pmx_get_funcs_count,
492 .get_function_name = armada_37xx_pmx_get_func_name,
493 .get_function_groups = armada_37xx_pmx_get_groups,
494 .set_mux = armada_37xx_pmx_set,
495 .gpio_request_enable = armada_37xx_gpio_request_enable,
496 .gpio_set_direction = armada_37xx_pmx_gpio_set_direction,
497};
498
5715092a
GC		 499static const struct gpio_chip armada_37xx_gpiolib_chip = {
500 .request = gpiochip_generic_request,
501 .free = gpiochip_generic_free,
502 .set = armada_37xx_gpio_set,
503 .get = armada_37xx_gpio_get,
504 .get_direction = armada_37xx_gpio_get_direction,
505 .direction_input = armada_37xx_gpio_direction_input,
506 .direction_output = armada_37xx_gpio_direction_output,
507 .owner = THIS_MODULE,
508};
509
2f227605
GC		 510static void armada_37xx_irq_ack(struct irq_data *d)
511{
512 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
513 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
514 u32 reg = IRQ_STATUS;
515 unsigned long flags;
516
517 armada_37xx_irq_update_reg(&reg, d);
518 spin_lock_irqsave(&info->irq_lock, flags);
519 writel(d->mask, info->base + reg);
520 spin_unlock_irqrestore(&info->irq_lock, flags);
521}
522
523static void armada_37xx_irq_mask(struct irq_data *d)
524{
525 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
526 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
527 u32 val, reg = IRQ_EN;
528 unsigned long flags;
529
530 armada_37xx_irq_update_reg(&reg, d);
531 spin_lock_irqsave(&info->irq_lock, flags);
532 val = readl(info->base + reg);
533 writel(val & ~d->mask, info->base + reg);
534 spin_unlock_irqrestore(&info->irq_lock, flags);
535}
536
537static void armada_37xx_irq_unmask(struct irq_data *d)
538{
539 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
540 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
541 u32 val, reg = IRQ_EN;
542 unsigned long flags;
543
544 armada_37xx_irq_update_reg(&reg, d);
545 spin_lock_irqsave(&info->irq_lock, flags);
546 val = readl(info->base + reg);
547 writel(val | d->mask, info->base + reg);
548 spin_unlock_irqrestore(&info->irq_lock, flags);
549}
550
551static int armada_37xx_irq_set_wake(struct irq_data *d, unsigned int on)
552{
553 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
554 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
555 u32 val, reg = IRQ_WKUP;
556 unsigned long flags;
557
558 armada_37xx_irq_update_reg(&reg, d);
559 spin_lock_irqsave(&info->irq_lock, flags);
560 val = readl(info->base + reg);
561 if (on)
a9a1a483 562 val |= (BIT(d->hwirq % GPIO_PER_REG));
2f227605 563 else
a9a1a483 564 val &= ~(BIT(d->hwirq % GPIO_PER_REG));
2f227605
GC		 565 writel(val, info->base + reg);
566 spin_unlock_irqrestore(&info->irq_lock, flags);
567
568 return 0;
569}
570
571static int armada_37xx_irq_set_type(struct irq_data *d, unsigned int type)
572{
573 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
574 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
575 u32 val, reg = IRQ_POL;
576 unsigned long flags;
577
578 spin_lock_irqsave(&info->irq_lock, flags);
579 armada_37xx_irq_update_reg(&reg, d);
580 val = readl(info->base + reg);
581 switch (type) {
582 case IRQ_TYPE_EDGE_RISING:
a9a1a483 583 val &= ~(BIT(d->hwirq % GPIO_PER_REG));
2f227605
GC		 584 break;
585 case IRQ_TYPE_EDGE_FALLING:
a9a1a483 586 val |= (BIT(d->hwirq % GPIO_PER_REG));
2f227605 587 break;
30ac0d3b
KM		 588 case IRQ_TYPE_EDGE_BOTH: {
589 u32 in_val, in_reg = INPUT_VAL;
590
591 armada_37xx_irq_update_reg(&in_reg, d);
592 regmap_read(info->regmap, in_reg, &in_val);
593
594 /* Set initial polarity based on current input level. */
595 if (in_val & d->mask)
596 val |= d->mask; /* falling */
597 else
598 val &= ~d->mask; /* rising */
599 break;
600 }
2f227605
GC		 601 default:
602 spin_unlock_irqrestore(&info->irq_lock, flags);
603 return -EINVAL;
604 }
605 writel(val, info->base + reg);
606 spin_unlock_irqrestore(&info->irq_lock, flags);
607
608 return 0;
609}
610
30ac0d3b
KM		 611static int armada_37xx_edge_both_irq_swap_pol(struct armada_37xx_pinctrl *info,
612 u32 pin_idx)
613{
614 u32 reg_idx = pin_idx / GPIO_PER_REG;
615 u32 bit_num = pin_idx % GPIO_PER_REG;
616 u32 p, l, ret;
617 unsigned long flags;
618
619 regmap_read(info->regmap, INPUT_VAL + 4*reg_idx, &l);
620
621 spin_lock_irqsave(&info->irq_lock, flags);
622 p = readl(info->base + IRQ_POL + 4 * reg_idx);
623 if ((p ^ l) & (1 << bit_num)) {
624 /*
625 * For the gpios which are used for both-edge irqs, when their
626 * interrupts happen, their input levels are changed,
627 * yet their interrupt polarities are kept in old values, we
628 * should synchronize their interrupt polarities; for example,
629 * at first a gpio's input level is low and its interrupt
630 * polarity control is "Detect rising edge", then the gpio has
631 * a interrupt , its level turns to high, we should change its
632 * polarity control to "Detect falling edge" correspondingly.
633 */
634 p ^= 1 << bit_num;
635 writel(p, info->base + IRQ_POL + 4 * reg_idx);
636 ret = 0;
637 } else {
638 /* Spurious irq */
639 ret = -1;
640 }
641
642 spin_unlock_irqrestore(&info->irq_lock, flags);
643 return ret;
644}
2f227605
GC		 645
646static void armada_37xx_irq_handler(struct irq_desc *desc)
647{
648 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
649 struct irq_chip *chip = irq_desc_get_chip(desc);
650 struct armada_37xx_pinctrl *info = gpiochip_get_data(gc);
f0fbe7bc 651 struct irq_domain *d = gc->irq.domain;
2f227605
GC		 652 int i;
653
654 chained_irq_enter(chip, desc);
655 for (i = 0; i <= d->revmap_size / GPIO_PER_REG; i++) {
656 u32 status;
657 unsigned long flags;
658
659 spin_lock_irqsave(&info->irq_lock, flags);
660 status = readl_relaxed(info->base + IRQ_STATUS + 4 * i);
661 /* Manage only the interrupt that was enabled */
662 status &= readl_relaxed(info->base + IRQ_EN + 4 * i);
663 spin_unlock_irqrestore(&info->irq_lock, flags);
664 while (status) {
665 u32 hwirq = ffs(status) - 1;
666 u32 virq = irq_find_mapping(d, hwirq +
667 i * GPIO_PER_REG);
30ac0d3b
KM		 668 u32 t = irq_get_trigger_type(virq);
669
670 if ((t & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
671 /* Swap polarity (race with GPIO line) */
672 if (armada_37xx_edge_both_irq_swap_pol(info,
673 hwirq + i * GPIO_PER_REG)) {
674 /*
675 * For spurious irq, which gpio level
676 * is not as expected after incoming
677 * edge, just ack the gpio irq.
678 */
679 writel(1 << hwirq,
680 info->base +
681 IRQ_STATUS + 4 * i);
682 continue;
683 }
684 }
2f227605
GC		 685
686 generic_handle_irq(virq);
687
688 /* Update status in case a new IRQ appears */
689 spin_lock_irqsave(&info->irq_lock, flags);
690 status = readl_relaxed(info->base +
691 IRQ_STATUS + 4 * i);
692 /* Manage only the interrupt that was enabled */
693 status &= readl_relaxed(info->base + IRQ_EN + 4 * i);
694 spin_unlock_irqrestore(&info->irq_lock, flags);
695 }
696 }
697 chained_irq_exit(chip, desc);
698}
699
a9a1a483
GC		 700static unsigned int armada_37xx_irq_startup(struct irq_data *d)
701{
a9a1a483
GC		 702 /*
703 * The mask field is a "precomputed bitmask for accessing the
704 * chip registers" which was introduced for the generic
705 * irqchip framework. As we don't use this framework, we can
706 * reuse this field for our own usage.
707 */
3ee9e605 708 d->mask = BIT(d->hwirq % GPIO_PER_REG);
a9a1a483
GC		 709
710 armada_37xx_irq_unmask(d);
711
712 return 0;
713}
714
2f227605
GC		 715static int armada_37xx_irqchip_register(struct platform_device *pdev,
716 struct armada_37xx_pinctrl *info)
717{
718 struct device_node *np = info->dev->of_node;
2f227605
GC		 719 struct gpio_chip *gc = &info->gpio_chip;
720 struct irq_chip *irqchip = &info->irq_chip;
721 struct resource res;
722 int ret = -ENODEV, i, nr_irq_parent;
723
724 /* Check if we have at least one gpio-controller child node */
725 for_each_child_of_node(info->dev->of_node, np) {
726 if (of_property_read_bool(np, "gpio-controller")) {
727 ret = 0;
728 break;
729 }
730 };
731 if (ret)
732 return ret;
733
734 nr_irq_parent = of_irq_count(np);
735 spin_lock_init(&info->irq_lock);
736
737 if (!nr_irq_parent) {
738 dev_err(&pdev->dev, "Invalid or no IRQ\n");
739 return 0;
740 }
741
742 if (of_address_to_resource(info->dev->of_node, 1, &res)) {
743 dev_err(info->dev, "cannot find IO resource\n");
744 return -ENOENT;
745 }
746
747 info->base = devm_ioremap_resource(info->dev, &res);
748 if (IS_ERR(info->base))
749 return PTR_ERR(info->base);
750
751 irqchip->irq_ack = armada_37xx_irq_ack;
752 irqchip->irq_mask = armada_37xx_irq_mask;
753 irqchip->irq_unmask = armada_37xx_irq_unmask;
754 irqchip->irq_set_wake = armada_37xx_irq_set_wake;
755 irqchip->irq_set_type = armada_37xx_irq_set_type;
a9a1a483 756 irqchip->irq_startup = armada_37xx_irq_startup;
2f227605 757 irqchip->name = info->data->name;
2f227605
GC		 758 ret = gpiochip_irqchip_add(gc, irqchip, 0,
759 handle_edge_irq, IRQ_TYPE_NONE);
760 if (ret) {
761 dev_info(&pdev->dev, "could not add irqchip\n");
762 return ret;
763 }
764
765 /*
766 * Many interrupts are connected to the parent interrupt
767 * controller. But we do not take advantage of this and use
768 * the chained irq with all of them.
769 */
2f227605
GC		 770 for (i = 0; i < nr_irq_parent; i++) {
771 int irq = irq_of_parse_and_map(np, i);
772
773 if (irq < 0)
774 continue;
775
776 gpiochip_set_chained_irqchip(gc, irqchip, irq,
777 armada_37xx_irq_handler);
778 }
779
780 return 0;
781}
782
5715092a
GC		 783static int armada_37xx_gpiochip_register(struct platform_device *pdev,
784 struct armada_37xx_pinctrl *info)
785{
786 struct device_node *np;
787 struct gpio_chip *gc;
788 int ret = -ENODEV;
789
790 for_each_child_of_node(info->dev->of_node, np) {
791 if (of_find_property(np, "gpio-controller", NULL)) {
792 ret = 0;
793 break;
794 }
795 };
796 if (ret)
797 return ret;
798
799 info->gpio_chip = armada_37xx_gpiolib_chip;
800
801 gc = &info->gpio_chip;
802 gc->ngpio = info->data->nr_pins;
803 gc->parent = &pdev->dev;
804 gc->base = -1;
805 gc->of_node = np;
806 gc->label = info->data->name;
807
808 ret = devm_gpiochip_add_data(&pdev->dev, gc, info);
2f227605
GC		 809 if (ret)
810 return ret;
811 ret = armada_37xx_irqchip_register(pdev, info);
5715092a
GC		 812 if (ret)
813 return ret;
814
815 return 0;
816}
817
87466ccd
GC		 818/**
819 * armada_37xx_add_function() - Add a new function to the list
820 * @funcs: array of function to add the new one
821 * @funcsize: size of the remaining space for the function
822 * @name: name of the function to add
823 *
824 * If it is a new function then create it by adding its name else
825 * increment the number of group associated to this function.
826 */
827static int armada_37xx_add_function(struct armada_37xx_pmx_func *funcs,
828 int *funcsize, const char *name)
829{
830 int i = 0;
831
832 if (*funcsize <= 0)
833 return -EOVERFLOW;
834
835 while (funcs->ngroups) {
836 /* function already there */
837 if (strcmp(funcs->name, name) == 0) {
838 funcs->ngroups++;
839
840 return -EEXIST;
841 }
842 funcs++;
843 i++;
844 }
845
846 /* append new unique function */
847 funcs->name = name;
848 funcs->ngroups = 1;
849 (*funcsize)--;
850
851 return 0;
852}
853
854/**
855 * armada_37xx_fill_group() - complete the group array
856 * @info: info driver instance
857 *
858 * Based on the data available from the armada_37xx_pin_group array
859 * completes the last member of the struct for each function: the list
860 * of the groups associated to this function.
861 *
862 */
863static int armada_37xx_fill_group(struct armada_37xx_pinctrl *info)
864{
865 int n, num = 0, funcsize = info->data->nr_pins;
866
867 for (n = 0; n < info->ngroups; n++) {
868 struct armada_37xx_pin_group *grp = &info->groups[n];
869 int i, j, f;
870
871 grp->pins = devm_kzalloc(info->dev,
872 (grp->npins + grp->extra_npins) *
873 sizeof(*grp->pins), GFP_KERNEL);
874 if (!grp->pins)
875 return -ENOMEM;
876
877 for (i = 0; i < grp->npins; i++)
878 grp->pins[i] = grp->start_pin + i;
879
880 for (j = 0; j < grp->extra_npins; j++)
881 grp->pins[i+j] = grp->extra_pin + j;
882
9ac6e7cc 883 for (f = 0; (f < NB_FUNCS) && grp->funcs[f]; f++) {
87466ccd
GC		 884 int ret;
885 /* check for unique functions and count groups */
886 ret = armada_37xx_add_function(info->funcs, &funcsize,
887 grp->funcs[f]);
888 if (ret == -EOVERFLOW)
889 dev_err(info->dev,
890 "More functions than pins(%d)\n",
891 info->data->nr_pins);
892 if (ret < 0)
893 continue;
894 num++;
895 }
896 }
897
898 info->nfuncs = num;
899
900 return 0;
901}
902
903/**
904 * armada_37xx_fill_funcs() - complete the funcs array
905 * @info: info driver instance
906 *
907 * Based on the data available from the armada_37xx_pin_group array
908 * completes the last two member of the struct for each group:
909 * - the list of the pins included in the group
910 * - the list of pinmux functions that can be selected for this group
911 *
912 */
913static int armada_37xx_fill_func(struct armada_37xx_pinctrl *info)
914{
915 struct armada_37xx_pmx_func *funcs = info->funcs;
916 int n;
917
918 for (n = 0; n < info->nfuncs; n++) {
919 const char *name = funcs[n].name;
920 const char **groups;
921 int g;
922
923 funcs[n].groups = devm_kzalloc(info->dev, funcs[n].ngroups *
924 sizeof(*(funcs[n].groups)),
925 GFP_KERNEL);
926 if (!funcs[n].groups)
927 return -ENOMEM;
928
929 groups = funcs[n].groups;
930
931 for (g = 0; g < info->ngroups; g++) {
932 struct armada_37xx_pin_group *gp = &info->groups[g];
933 int f;
934
9ac6e7cc 935 for (f = 0; (f < NB_FUNCS) && gp->funcs[f]; f++) {
87466ccd
GC		 936 if (strcmp(gp->funcs[f], name) == 0) {
937 *groups = gp->name;
938 groups++;
939 }
940 }
941 }
942 }
943 return 0;
944}
945
946static int armada_37xx_pinctrl_register(struct platform_device *pdev,
947 struct armada_37xx_pinctrl *info)
948{
949 const struct armada_37xx_pin_data *pin_data = info->data;
950 struct pinctrl_desc *ctrldesc = &info->pctl;
951 struct pinctrl_pin_desc *pindesc, *pdesc;
952 int pin, ret;
953
954 info->groups = pin_data->groups;
955 info->ngroups = pin_data->ngroups;
956
957 ctrldesc->name = "armada_37xx-pinctrl";
958 ctrldesc->owner = THIS_MODULE;
959 ctrldesc->pctlops = &armada_37xx_pctrl_ops;
960 ctrldesc->pmxops = &armada_37xx_pmx_ops;
961 ctrldesc->confops = &armada_37xx_pinconf_ops;
962
963 pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) *
964 pin_data->nr_pins, GFP_KERNEL);
965 if (!pindesc)
966 return -ENOMEM;
967
968 ctrldesc->pins = pindesc;
969 ctrldesc->npins = pin_data->nr_pins;
970
971 pdesc = pindesc;
972 for (pin = 0; pin < pin_data->nr_pins; pin++) {
973 pdesc->number = pin;
974 pdesc->name = kasprintf(GFP_KERNEL, "%s-%d",
975 pin_data->name, pin);
976 pdesc++;
977 }
978
979 /*
980 * we allocate functions for number of pins and hope there are
981 * fewer unique functions than pins available
982 */
983 info->funcs = devm_kzalloc(&pdev->dev, pin_data->nr_pins *
984 sizeof(struct armada_37xx_pmx_func), GFP_KERNEL);
985 if (!info->funcs)
986 return -ENOMEM;
987
988
989 ret = armada_37xx_fill_group(info);
990 if (ret)
991 return ret;
992
993 ret = armada_37xx_fill_func(info);
994 if (ret)
995 return ret;
996
997 info->pctl_dev = devm_pinctrl_register(&pdev->dev, ctrldesc, info);
998 if (IS_ERR(info->pctl_dev)) {
999 dev_err(&pdev->dev, "could not register pinctrl driver\n");
1000 return PTR_ERR(info->pctl_dev);
1001 }
1002
1003 return 0;
1004}
1005
1006static const struct of_device_id armada_37xx_pinctrl_of_match[] = {
1007 {
1008 .compatible = "marvell,armada3710-sb-pinctrl",
1009 .data = (void *)&armada_37xx_pin_sb,
1010 },
1011 {
1012 .compatible = "marvell,armada3710-nb-pinctrl",
1013 .data = (void *)&armada_37xx_pin_nb,
1014 },
1015 { },
1016};
1017
1018static int __init armada_37xx_pinctrl_probe(struct platform_device *pdev)
1019{
1020 struct armada_37xx_pinctrl *info;
1021 struct device *dev = &pdev->dev;
1022 struct device_node *np = dev->of_node;
1023 struct regmap *regmap;
1024 int ret;
1025
1026 info = devm_kzalloc(dev, sizeof(struct armada_37xx_pinctrl),
1027 GFP_KERNEL);
1028 if (!info)
1029 return -ENOMEM;
1030
1031 info->dev = dev;
1032
1033 regmap = syscon_node_to_regmap(np);
1034 if (IS_ERR(regmap)) {
1035 dev_err(&pdev->dev, "cannot get regmap\n");
1036 return PTR_ERR(regmap);
1037 }
1038 info->regmap = regmap;
1039
1040 info->data = of_device_get_match_data(dev);
1041
1042 ret = armada_37xx_pinctrl_register(pdev, info);
1043 if (ret)
1044 return ret;
1045
5715092a
GC		 1046 ret = armada_37xx_gpiochip_register(pdev, info);
1047 if (ret)
1048 return ret;
1049
87466ccd
GC		 1050 platform_set_drvdata(pdev, info);
1051
1052 return 0;
1053}
1054
1055static struct platform_driver armada_37xx_pinctrl_driver = {
1056 .driver = {
1057 .name = "armada-37xx-pinctrl",
1058 .of_match_table = armada_37xx_pinctrl_of_match,
1059 },
1060};
1061
1062builtin_platform_driver_probe(armada_37xx_pinctrl_driver,
1063 armada_37xx_pinctrl_probe);
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