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Merge back PM core material for v4.16.
[mirror_ubuntu-jammy-kernel.git] / drivers / pinctrl / mvebu / pinctrl-dove.c
CommitLineData
c9f95ced
SH		 1/*
2 * Marvell Dove pinctrl driver based on mvebu pinctrl core
3 *
4 * Author: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12#include <linux/err.h>
13#include <linux/init.h>
14#include <linux/io.h>
c9f95ced
SH		 15#include <linux/bitops.h>
16#include <linux/platform_device.h>
17#include <linux/clk.h>
18#include <linux/of.h>
19#include <linux/of_device.h>
e91f7916 20#include <linux/mfd/syscon.h>
c9f95ced 21#include <linux/pinctrl/pinctrl.h>
e91f7916 22#include <linux/regmap.h>
c9f95ced
SH		 23
24#include "pinctrl-mvebu.h"
25
4d73fc77
SH		 26/* Internal registers can be configured at any 1 MiB aligned address */
27#define INT_REGS_MASK ~(SZ_1M - 1)
28#define MPP4_REGS_OFFS 0xd0440
29#define PMU_REGS_OFFS 0xd802c
e91f7916 30#define GC_REGS_OFFS 0xe802c
4d73fc77 31
00202b01
SH		 32/* MPP Base registers */
33#define PMU_MPP_GENERAL_CTRL 0x10
34#define AU0_AC97_SEL BIT(16)
35
2c4b229b
SH		 36/* MPP Control 4 register */
37#define SPI_GPIO_SEL BIT(5)
38#define UART1_GPIO_SEL BIT(4)
39#define AU1_GPIO_SEL BIT(3)
40#define CAM_GPIO_SEL BIT(2)
41#define SD1_GPIO_SEL BIT(1)
42#define SD0_GPIO_SEL BIT(0)
43
18e6f28e
SH		 44/* PMU Signal Select registers */
45#define PMU_SIGNAL_SELECT_0 0x00
46#define PMU_SIGNAL_SELECT_1 0x04
47
6da67cab
SH		 48/* Global Config regmap registers */
49#define GLOBAL_CONFIG_1 0x00
50#define TWSI_ENABLE_OPTION1 BIT(7)
51#define GLOBAL_CONFIG_2 0x04
52#define TWSI_ENABLE_OPTION2 BIT(20)
53#define TWSI_ENABLE_OPTION3 BIT(21)
54#define TWSI_OPTION3_GPIO BIT(22)
55#define SSP_CTRL_STATUS_1 0x08
56#define SSP_ON_AU1 BIT(0)
57#define MPP_GENERAL_CONFIG 0x10
58#define AU1_SPDIFO_GPIO_EN BIT(1)
59#define NAND_GPIO_EN BIT(0)
60
c9f95ced
SH		 61#define CONFIG_PMU BIT(4)
62
4d73fc77
SH		 63static void __iomem *mpp4_base;
64static void __iomem *pmu_base;
e91f7916 65static struct regmap *gconfmap;
17bdec67 66
20955c5f
RK		 67static int dove_pmu_mpp_ctrl_get(struct mvebu_mpp_ctrl_data *data,
68 unsigned pid, unsigned long *config)
c9f95ced 69{
17bdec67
SH		 70 unsigned off = (pid / MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
71 unsigned shift = (pid % MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
ad9ec4ec 72 unsigned long pmu = readl(data->base + PMU_MPP_GENERAL_CTRL);
bbd7b275
SH		 73 unsigned long func;
74
78c2c3d3 75 if ((pmu & BIT(pid)) == 0)
ad9ec4ec 76 return mvebu_mmio_mpp_ctrl_get(data, pid, config);
78c2c3d3 77
18e6f28e 78 func = readl(pmu_base + PMU_SIGNAL_SELECT_0 + off);
78c2c3d3
SH		 79 *config = (func >> shift) & MVEBU_MPP_MASK;
80 *config |= CONFIG_PMU;
81
c9f95ced
SH		 82 return 0;
83}
84
20955c5f
RK		 85static int dove_pmu_mpp_ctrl_set(struct mvebu_mpp_ctrl_data *data,
86 unsigned pid, unsigned long config)
c9f95ced 87{
17bdec67
SH		 88 unsigned off = (pid / MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
89 unsigned shift = (pid % MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
ad9ec4ec 90 unsigned long pmu = readl(data->base + PMU_MPP_GENERAL_CTRL);
bbd7b275 91 unsigned long func;
c9f95ced 92
78c2c3d3 93 if ((config & CONFIG_PMU) == 0) {
ad9ec4ec
RK		 94 writel(pmu & ~BIT(pid), data->base + PMU_MPP_GENERAL_CTRL);
95 return mvebu_mmio_mpp_ctrl_set(data, pid, config);
c9f95ced 96 }
78c2c3d3 97
ad9ec4ec 98 writel(pmu | BIT(pid), data->base + PMU_MPP_GENERAL_CTRL);
18e6f28e 99 func = readl(pmu_base + PMU_SIGNAL_SELECT_0 + off);
78c2c3d3
SH		 100 func &= ~(MVEBU_MPP_MASK << shift);
101 func |= (config & MVEBU_MPP_MASK) << shift;
18e6f28e 102 writel(func, pmu_base + PMU_SIGNAL_SELECT_0 + off);
78c2c3d3 103
c9f95ced
SH		 104 return 0;
105}
106
20955c5f
RK		 107static int dove_mpp4_ctrl_get(struct mvebu_mpp_ctrl_data *data, unsigned pid,
108 unsigned long *config)
c9f95ced 109{
2c4b229b 110 unsigned long mpp4 = readl(mpp4_base);
c9f95ced
SH		 111 unsigned long mask;
112
2035d39d 113 switch (pid) {
c9f95ced 114 case 24: /* mpp_camera */
2c4b229b 115 mask = CAM_GPIO_SEL;
c9f95ced
SH		 116 break;
117 case 40: /* mpp_sdio0 */
2c4b229b 118 mask = SD0_GPIO_SEL;
c9f95ced
SH		 119 break;
120 case 46: /* mpp_sdio1 */
2c4b229b 121 mask = SD1_GPIO_SEL;
c9f95ced
SH		 122 break;
123 case 58: /* mpp_spi0 */
2c4b229b 124 mask = SPI_GPIO_SEL;
c9f95ced
SH		 125 break;
126 case 62: /* mpp_uart1 */
2c4b229b 127 mask = UART1_GPIO_SEL;
c9f95ced
SH		 128 break;
129 default:
130 return -EINVAL;
131 }
132
133 *config = ((mpp4 & mask) != 0);
134
135 return 0;
136}
137
20955c5f
RK		 138static int dove_mpp4_ctrl_set(struct mvebu_mpp_ctrl_data *data, unsigned pid,
139 unsigned long config)
c9f95ced 140{
2c4b229b 141 unsigned long mpp4 = readl(mpp4_base);
c9f95ced
SH		 142 unsigned long mask;
143
2035d39d 144 switch (pid) {
c9f95ced 145 case 24: /* mpp_camera */
2c4b229b 146 mask = CAM_GPIO_SEL;
c9f95ced
SH		 147 break;
148 case 40: /* mpp_sdio0 */
2c4b229b 149 mask = SD0_GPIO_SEL;
c9f95ced
SH		 150 break;
151 case 46: /* mpp_sdio1 */
2c4b229b 152 mask = SD1_GPIO_SEL;
c9f95ced
SH		 153 break;
154 case 58: /* mpp_spi0 */
2c4b229b 155 mask = SPI_GPIO_SEL;
c9f95ced
SH		 156 break;
157 case 62: /* mpp_uart1 */
2c4b229b 158 mask = UART1_GPIO_SEL;
c9f95ced
SH		 159 break;
160 default:
161 return -EINVAL;
162 }
163
164 mpp4 &= ~mask;
165 if (config)
166 mpp4 |= mask;
167
2c4b229b 168 writel(mpp4, mpp4_base);
c9f95ced
SH		 169
170 return 0;
171}
172
20955c5f
RK		 173static int dove_nand_ctrl_get(struct mvebu_mpp_ctrl_data *data, unsigned pid,
174 unsigned long *config)
c9f95ced 175{
6da67cab 176 unsigned int gmpp;
c9f95ced 177
6da67cab
SH		 178 regmap_read(gconfmap, MPP_GENERAL_CONFIG, &gmpp);
179 *config = ((gmpp & NAND_GPIO_EN) != 0);
c9f95ced
SH		 180
181 return 0;
182}
183
20955c5f
RK		 184static int dove_nand_ctrl_set(struct mvebu_mpp_ctrl_data *data, unsigned pid,
185 unsigned long config)
c9f95ced 186{
6da67cab
SH		 187 regmap_update_bits(gconfmap, MPP_GENERAL_CONFIG,
188 NAND_GPIO_EN,
189 (config) ? NAND_GPIO_EN : 0);
c9f95ced
SH		 190 return 0;
191}
192
20955c5f
RK		 193static int dove_audio0_ctrl_get(struct mvebu_mpp_ctrl_data *data, unsigned pid,
194 unsigned long *config)
c9f95ced 195{
ad9ec4ec 196 unsigned long pmu = readl(data->base + PMU_MPP_GENERAL_CTRL);
c9f95ced 197
00202b01 198 *config = ((pmu & AU0_AC97_SEL) != 0);
c9f95ced
SH		 199
200 return 0;
201}
202
20955c5f
RK		 203static int dove_audio0_ctrl_set(struct mvebu_mpp_ctrl_data *data, unsigned pid,
204 unsigned long config)
c9f95ced 205{
ad9ec4ec 206 unsigned long pmu = readl(data->base + PMU_MPP_GENERAL_CTRL);
c9f95ced 207
00202b01 208 pmu &= ~AU0_AC97_SEL;
c9f95ced 209 if (config)
00202b01 210 pmu |= AU0_AC97_SEL;
ad9ec4ec 211 writel(pmu, data->base + PMU_MPP_GENERAL_CTRL);
c9f95ced
SH		 212
213 return 0;
214}
215
20955c5f
RK		 216static int dove_audio1_ctrl_get(struct mvebu_mpp_ctrl_data *data, unsigned pid,
217 unsigned long *config)
c9f95ced 218{
2c4b229b 219 unsigned int mpp4 = readl(mpp4_base);
6da67cab
SH		 220 unsigned int sspc1;
221 unsigned int gmpp;
222 unsigned int gcfg2;
223
224 regmap_read(gconfmap, SSP_CTRL_STATUS_1, &sspc1);
225 regmap_read(gconfmap, MPP_GENERAL_CONFIG, &gmpp);
226 regmap_read(gconfmap, GLOBAL_CONFIG_2, &gcfg2);
c9f95ced
SH		 227
228 *config = 0;
2c4b229b 229 if (mpp4 & AU1_GPIO_SEL)
c9f95ced 230 *config |= BIT(3);
6da67cab 231 if (sspc1 & SSP_ON_AU1)
c9f95ced 232 *config |= BIT(2);
6da67cab 233 if (gmpp & AU1_SPDIFO_GPIO_EN)
c9f95ced 234 *config |= BIT(1);
6da67cab 235 if (gcfg2 & TWSI_OPTION3_GPIO)
c9f95ced
SH		 236 *config |= BIT(0);
237
238 /* SSP/TWSI only if I2S1 not set*/
239 if ((*config & BIT(3)) == 0)
240 *config &= ~(BIT(2) | BIT(0));
241 /* TWSI only if SPDIFO not set*/
242 if ((*config & BIT(1)) == 0)
243 *config &= ~BIT(0);
244 return 0;
245}
246
20955c5f
RK		 247static int dove_audio1_ctrl_set(struct mvebu_mpp_ctrl_data *data, unsigned pid,
248 unsigned long config)
c9f95ced 249{
2c4b229b 250 unsigned int mpp4 = readl(mpp4_base);
63ace077 251
6da67cab 252 mpp4 &= ~AU1_GPIO_SEL;
c9f95ced 253 if (config & BIT(3))
2c4b229b 254 mpp4 |= AU1_GPIO_SEL;
2c4b229b 255 writel(mpp4, mpp4_base);
6da67cab
SH		 256
257 regmap_update_bits(gconfmap, SSP_CTRL_STATUS_1,
258 SSP_ON_AU1,
259 (config & BIT(2)) ? SSP_ON_AU1 : 0);
260 regmap_update_bits(gconfmap, MPP_GENERAL_CONFIG,
261 AU1_SPDIFO_GPIO_EN,
262 (config & BIT(1)) ? AU1_SPDIFO_GPIO_EN : 0);
263 regmap_update_bits(gconfmap, GLOBAL_CONFIG_2,
264 TWSI_OPTION3_GPIO,
265 (config & BIT(0)) ? TWSI_OPTION3_GPIO : 0);
c9f95ced
SH		 266
267 return 0;
268}
269
270/* mpp[52:57] gpio pins depend heavily on current config;
271 * gpio_req does not try to mux in gpio capabilities to not
272 * break other functions. If you require all mpps as gpio
273 * enforce gpio setting by pinctrl mapping.
274 */
20955c5f
RK		 275static int dove_audio1_ctrl_gpio_req(struct mvebu_mpp_ctrl_data *data,
276 unsigned pid)
c9f95ced
SH		 277{
278 unsigned long config;
279
20955c5f 280 dove_audio1_ctrl_get(data, pid, &config);
c9f95ced
SH		 281
282 switch (config) {
283 case 0x02: /* i2s1 : gpio[56:57] */
284 case 0x0e: /* ssp : gpio[56:57] */
285 if (pid >= 56)
286 return 0;
287 return -ENOTSUPP;
288 case 0x08: /* spdifo : gpio[52:55] */
289 case 0x0b: /* twsi : gpio[52:55] */
290 if (pid <= 55)
291 return 0;
292 return -ENOTSUPP;
293 case 0x0a: /* all gpio */
294 return 0;
295 /* 0x00 : i2s1/spdifo : no gpio */
296 /* 0x0c : ssp/spdifo : no gpio */
297 /* 0x0f : ssp/twsi : no gpio */
298 }
299 return -ENOTSUPP;
300}
301
302/* mpp[52:57] has gpio pins capable of in and out */
20955c5f
RK		 303static int dove_audio1_ctrl_gpio_dir(struct mvebu_mpp_ctrl_data *data,
304 unsigned pid, bool input)
c9f95ced
SH		 305{
306 if (pid < 52 || pid > 57)
307 return -ENOTSUPP;
308 return 0;
309}
310
20955c5f
RK		 311static int dove_twsi_ctrl_get(struct mvebu_mpp_ctrl_data *data, unsigned pid,
312 unsigned long *config)
c9f95ced 313{
6da67cab
SH		 314 unsigned int gcfg1;
315 unsigned int gcfg2;
316
317 regmap_read(gconfmap, GLOBAL_CONFIG_1, &gcfg1);
318 regmap_read(gconfmap, GLOBAL_CONFIG_2, &gcfg2);
c9f95ced
SH		 319
320 *config = 0;
6da67cab 321 if (gcfg1 & TWSI_ENABLE_OPTION1)
c9f95ced 322 *config = 1;
6da67cab 323 else if (gcfg2 & TWSI_ENABLE_OPTION2)
c9f95ced 324 *config = 2;
6da67cab 325 else if (gcfg2 & TWSI_ENABLE_OPTION3)
c9f95ced
SH		 326 *config = 3;
327
328 return 0;
329}
330
20955c5f
RK		 331static int dove_twsi_ctrl_set(struct mvebu_mpp_ctrl_data *data, unsigned pid,
332 unsigned long config)
c9f95ced 333{
6da67cab
SH		 334 unsigned int gcfg1 = 0;
335 unsigned int gcfg2 = 0;
c9f95ced
SH		 336
337 switch (config) {
338 case 1:
6da67cab 339 gcfg1 = TWSI_ENABLE_OPTION1;
c9f95ced
SH		 340 break;
341 case 2:
6da67cab 342 gcfg2 = TWSI_ENABLE_OPTION2;
c9f95ced
SH		 343 break;
344 case 3:
6da67cab 345 gcfg2 = TWSI_ENABLE_OPTION3;
c9f95ced
SH		 346 break;
347 }
348
6da67cab
SH		 349 regmap_update_bits(gconfmap, GLOBAL_CONFIG_1,
350 TWSI_ENABLE_OPTION1,
351 gcfg1);
352 regmap_update_bits(gconfmap, GLOBAL_CONFIG_2,
353 TWSI_ENABLE_OPTION2 | TWSI_ENABLE_OPTION3,
354 gcfg2);
c9f95ced
SH		 355
356 return 0;
357}
358
30be3fb9 359static const struct mvebu_mpp_ctrl dove_mpp_controls[] = {
c2f082fe 360 MPP_FUNC_CTRL(0, 15, NULL, dove_pmu_mpp_ctrl),
ad9ec4ec 361 MPP_FUNC_CTRL(16, 23, NULL, mvebu_mmio_mpp_ctrl),
c9f95ced
SH		 362 MPP_FUNC_CTRL(24, 39, "mpp_camera", dove_mpp4_ctrl),
363 MPP_FUNC_CTRL(40, 45, "mpp_sdio0", dove_mpp4_ctrl),
364 MPP_FUNC_CTRL(46, 51, "mpp_sdio1", dove_mpp4_ctrl),
365 MPP_FUNC_GPIO_CTRL(52, 57, "mpp_audio1", dove_audio1_ctrl),
366 MPP_FUNC_CTRL(58, 61, "mpp_spi0", dove_mpp4_ctrl),
367 MPP_FUNC_CTRL(62, 63, "mpp_uart1", dove_mpp4_ctrl),
368 MPP_FUNC_CTRL(64, 71, "mpp_nand", dove_nand_ctrl),
369 MPP_FUNC_CTRL(72, 72, "audio0", dove_audio0_ctrl),
370 MPP_FUNC_CTRL(73, 73, "twsi", dove_twsi_ctrl),
371};
372
373static struct mvebu_mpp_mode dove_mpp_modes[] = {
374 MPP_MODE(0,
375 MPP_FUNCTION(0x00, "gpio", NULL),
376 MPP_FUNCTION(0x02, "uart2", "rts"),
377 MPP_FUNCTION(0x03, "sdio0", "cd"),
378 MPP_FUNCTION(0x0f, "lcd0", "pwm"),
bbd7b275
SH		 379 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
380 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
381 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
382 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
383 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
384 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
385 MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL),
386 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
387 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
388 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
389 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
390 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
c9f95ced
SH		 391 MPP_MODE(1,
392 MPP_FUNCTION(0x00, "gpio", NULL),
393 MPP_FUNCTION(0x02, "uart2", "cts"),
394 MPP_FUNCTION(0x03, "sdio0", "wp"),
395 MPP_FUNCTION(0x0f, "lcd1", "pwm"),
bbd7b275
SH		 396 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
397 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
398 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
399 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
400 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
401 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
402 MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL),
403 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
404 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
405 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
406 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
407 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
c9f95ced
SH		 408 MPP_MODE(2,
409 MPP_FUNCTION(0x00, "gpio", NULL),
410 MPP_FUNCTION(0x01, "sata", "prsnt"),
411 MPP_FUNCTION(0x02, "uart2", "txd"),
412 MPP_FUNCTION(0x03, "sdio0", "buspwr"),
413 MPP_FUNCTION(0x04, "uart1", "rts"),
bbd7b275
SH		 414 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
415 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
416 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
417 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
418 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
419 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
420 MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL),
421 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
422 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
423 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
424 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
425 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
c9f95ced
SH		 426 MPP_MODE(3,
427 MPP_FUNCTION(0x00, "gpio", NULL),
428 MPP_FUNCTION(0x01, "sata", "act"),
429 MPP_FUNCTION(0x02, "uart2", "rxd"),
430 MPP_FUNCTION(0x03, "sdio0", "ledctrl"),
431 MPP_FUNCTION(0x04, "uart1", "cts"),
432 MPP_FUNCTION(0x0f, "lcd-spi", "cs1"),
bbd7b275
SH		 433 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
434 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
435 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
436 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
437 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
438 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
439 MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL),
440 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
441 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
442 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
443 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
444 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
c9f95ced
SH		 445 MPP_MODE(4,
446 MPP_FUNCTION(0x00, "gpio", NULL),
447 MPP_FUNCTION(0x02, "uart3", "rts"),
448 MPP_FUNCTION(0x03, "sdio1", "cd"),
449 MPP_FUNCTION(0x04, "spi1", "miso"),
bbd7b275
SH		 450 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
451 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
452 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
453 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
454 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
455 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
456 MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL),
457 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
458 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
459 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
460 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
461 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
c9f95ced
SH		 462 MPP_MODE(5,
463 MPP_FUNCTION(0x00, "gpio", NULL),
464 MPP_FUNCTION(0x02, "uart3", "cts"),
465 MPP_FUNCTION(0x03, "sdio1", "wp"),
466 MPP_FUNCTION(0x04, "spi1", "cs"),
bbd7b275
SH		 467 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
468 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
469 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
470 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
471 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
472 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
473 MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL),
474 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
475 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
476 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
477 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
478 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
c9f95ced
SH		 479 MPP_MODE(6,
480 MPP_FUNCTION(0x00, "gpio", NULL),
481 MPP_FUNCTION(0x02, "uart3", "txd"),
482 MPP_FUNCTION(0x03, "sdio1", "buspwr"),
483 MPP_FUNCTION(0x04, "spi1", "mosi"),
bbd7b275
SH		 484 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
485 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
486 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
487 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
488 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
489 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
490 MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL),
491 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
492 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
493 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
494 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
495 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
c9f95ced
SH		 496 MPP_MODE(7,
497 MPP_FUNCTION(0x00, "gpio", NULL),
498 MPP_FUNCTION(0x02, "uart3", "rxd"),
499 MPP_FUNCTION(0x03, "sdio1", "ledctrl"),
500 MPP_FUNCTION(0x04, "spi1", "sck"),
bbd7b275
SH		 501 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
502 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
503 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
504 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
505 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
506 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
507 MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL),
508 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
509 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
510 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
511 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
512 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
c9f95ced
SH		 513 MPP_MODE(8,
514 MPP_FUNCTION(0x00, "gpio", NULL),
515 MPP_FUNCTION(0x01, "watchdog", "rstout"),
bbd7b275
SH		 516 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
517 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
518 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
519 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
520 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
521 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
522 MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL),
523 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
524 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
525 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
526 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
527 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
c9f95ced
SH		 528 MPP_MODE(9,
529 MPP_FUNCTION(0x00, "gpio", NULL),
530 MPP_FUNCTION(0x05, "pex1", "clkreq"),
bbd7b275
SH		 531 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
532 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
533 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
534 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
535 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
536 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
537 MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL),
538 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
539 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
540 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
541 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
542 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
c9f95ced
SH		 543 MPP_MODE(10,
544 MPP_FUNCTION(0x00, "gpio", NULL),
545 MPP_FUNCTION(0x05, "ssp", "sclk"),
bbd7b275
SH		 546 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
547 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
548 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
549 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
550 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
551 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
552 MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL),
553 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
554 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
555 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
556 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
557 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
c9f95ced
SH		 558 MPP_MODE(11,
559 MPP_FUNCTION(0x00, "gpio", NULL),
560 MPP_FUNCTION(0x01, "sata", "prsnt"),
561 MPP_FUNCTION(0x02, "sata-1", "act"),
562 MPP_FUNCTION(0x03, "sdio0", "ledctrl"),
563 MPP_FUNCTION(0x04, "sdio1", "ledctrl"),
564 MPP_FUNCTION(0x05, "pex0", "clkreq"),
bbd7b275
SH		 565 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
566 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
567 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
568 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
569 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
570 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
571 MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL),
572 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
573 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
574 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
575 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
576 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
c9f95ced
SH		 577 MPP_MODE(12,
578 MPP_FUNCTION(0x00, "gpio", NULL),
579 MPP_FUNCTION(0x01, "sata", "act"),
580 MPP_FUNCTION(0x02, "uart2", "rts"),
581 MPP_FUNCTION(0x03, "audio0", "extclk"),
582 MPP_FUNCTION(0x04, "sdio1", "cd"),
bbd7b275
SH		 583 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
584 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
585 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
586 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
587 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
588 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
589 MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL),
590 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
591 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
592 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
593 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
594 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
c9f95ced
SH		 595 MPP_MODE(13,
596 MPP_FUNCTION(0x00, "gpio", NULL),
597 MPP_FUNCTION(0x02, "uart2", "cts"),
598 MPP_FUNCTION(0x03, "audio1", "extclk"),
599 MPP_FUNCTION(0x04, "sdio1", "wp"),
600 MPP_FUNCTION(0x05, "ssp", "extclk"),
bbd7b275
SH		 601 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
602 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
603 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
604 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
605 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
606 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
607 MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL),
608 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
609 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
610 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
611 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
612 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
c9f95ced
SH		 613 MPP_MODE(14,
614 MPP_FUNCTION(0x00, "gpio", NULL),
615 MPP_FUNCTION(0x02, "uart2", "txd"),
616 MPP_FUNCTION(0x04, "sdio1", "buspwr"),
617 MPP_FUNCTION(0x05, "ssp", "rxd"),
bbd7b275
SH		 618 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
619 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
620 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
621 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
622 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
623 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
624 MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL),
625 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
626 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
627 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
628 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
629 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
c9f95ced
SH		 630 MPP_MODE(15,
631 MPP_FUNCTION(0x00, "gpio", NULL),
632 MPP_FUNCTION(0x02, "uart2", "rxd"),
633 MPP_FUNCTION(0x04, "sdio1", "ledctrl"),
634 MPP_FUNCTION(0x05, "ssp", "sfrm"),
bbd7b275
SH		 635 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
636 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
637 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
638 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
639 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
640 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
641 MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL),
642 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
643 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
644 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
645 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
646 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
c9f95ced
SH		 647 MPP_MODE(16,
648 MPP_FUNCTION(0x00, "gpio", NULL),
649 MPP_FUNCTION(0x02, "uart3", "rts"),
650 MPP_FUNCTION(0x03, "sdio0", "cd"),
651 MPP_FUNCTION(0x04, "lcd-spi", "cs1"),
652 MPP_FUNCTION(0x05, "ac97", "sdi1")),
653 MPP_MODE(17,
654 MPP_FUNCTION(0x00, "gpio", NULL),
655 MPP_FUNCTION(0x01, "ac97-1", "sysclko"),
656 MPP_FUNCTION(0x02, "uart3", "cts"),
657 MPP_FUNCTION(0x03, "sdio0", "wp"),
658 MPP_FUNCTION(0x04, "twsi", "sda"),
659 MPP_FUNCTION(0x05, "ac97", "sdi2")),
660 MPP_MODE(18,
661 MPP_FUNCTION(0x00, "gpio", NULL),
662 MPP_FUNCTION(0x02, "uart3", "txd"),
663 MPP_FUNCTION(0x03, "sdio0", "buspwr"),
664 MPP_FUNCTION(0x04, "lcd0", "pwm"),
665 MPP_FUNCTION(0x05, "ac97", "sdi3")),
666 MPP_MODE(19,
667 MPP_FUNCTION(0x00, "gpio", NULL),
668 MPP_FUNCTION(0x02, "uart3", "rxd"),
669 MPP_FUNCTION(0x03, "sdio0", "ledctrl"),
670 MPP_FUNCTION(0x04, "twsi", "sck")),
671 MPP_MODE(20,
672 MPP_FUNCTION(0x00, "gpio", NULL),
673 MPP_FUNCTION(0x01, "ac97", "sysclko"),
674 MPP_FUNCTION(0x02, "lcd-spi", "miso"),
675 MPP_FUNCTION(0x03, "sdio1", "cd"),
676 MPP_FUNCTION(0x05, "sdio0", "cd"),
677 MPP_FUNCTION(0x06, "spi1", "miso")),
678 MPP_MODE(21,
679 MPP_FUNCTION(0x00, "gpio", NULL),
680 MPP_FUNCTION(0x01, "uart1", "rts"),
681 MPP_FUNCTION(0x02, "lcd-spi", "cs0"),
682 MPP_FUNCTION(0x03, "sdio1", "wp"),
683 MPP_FUNCTION(0x04, "ssp", "sfrm"),
684 MPP_FUNCTION(0x05, "sdio0", "wp"),
685 MPP_FUNCTION(0x06, "spi1", "cs")),
686 MPP_MODE(22,
687 MPP_FUNCTION(0x00, "gpio", NULL),
688 MPP_FUNCTION(0x01, "uart1", "cts"),
689 MPP_FUNCTION(0x02, "lcd-spi", "mosi"),
690 MPP_FUNCTION(0x03, "sdio1", "buspwr"),
691 MPP_FUNCTION(0x04, "ssp", "txd"),
692 MPP_FUNCTION(0x05, "sdio0", "buspwr"),
693 MPP_FUNCTION(0x06, "spi1", "mosi")),
694 MPP_MODE(23,
695 MPP_FUNCTION(0x00, "gpio", NULL),
696 MPP_FUNCTION(0x02, "lcd-spi", "sck"),
697 MPP_FUNCTION(0x03, "sdio1", "ledctrl"),
698 MPP_FUNCTION(0x04, "ssp", "sclk"),
699 MPP_FUNCTION(0x05, "sdio0", "ledctrl"),
700 MPP_FUNCTION(0x06, "spi1", "sck")),
701 MPP_MODE(24,
702 MPP_FUNCTION(0x00, "camera", NULL),
703 MPP_FUNCTION(0x01, "gpio", NULL)),
704 MPP_MODE(40,
705 MPP_FUNCTION(0x00, "sdio0", NULL),
706 MPP_FUNCTION(0x01, "gpio", NULL)),
707 MPP_MODE(46,
708 MPP_FUNCTION(0x00, "sdio1", NULL),
709 MPP_FUNCTION(0x01, "gpio", NULL)),
710 MPP_MODE(52,
711 MPP_FUNCTION(0x00, "i2s1/spdifo", NULL),
712 MPP_FUNCTION(0x02, "i2s1", NULL),
713 MPP_FUNCTION(0x08, "spdifo", NULL),
714 MPP_FUNCTION(0x0a, "gpio", NULL),
715 MPP_FUNCTION(0x0b, "twsi", NULL),
716 MPP_FUNCTION(0x0c, "ssp/spdifo", NULL),
717 MPP_FUNCTION(0x0e, "ssp", NULL),
718 MPP_FUNCTION(0x0f, "ssp/twsi", NULL)),
719 MPP_MODE(58,
720 MPP_FUNCTION(0x00, "spi0", NULL),
721 MPP_FUNCTION(0x01, "gpio", NULL)),
722 MPP_MODE(62,
723 MPP_FUNCTION(0x00, "uart1", NULL),
724 MPP_FUNCTION(0x01, "gpio", NULL)),
725 MPP_MODE(64,
726 MPP_FUNCTION(0x00, "nand", NULL),
727 MPP_FUNCTION(0x01, "gpo", NULL)),
728 MPP_MODE(72,
729 MPP_FUNCTION(0x00, "i2s", NULL),
730 MPP_FUNCTION(0x01, "ac97", NULL)),
731 MPP_MODE(73,
732 MPP_FUNCTION(0x00, "twsi-none", NULL),
733 MPP_FUNCTION(0x01, "twsi-opt1", NULL),
734 MPP_FUNCTION(0x02, "twsi-opt2", NULL),
735 MPP_FUNCTION(0x03, "twsi-opt3", NULL)),
736};
737
738static struct pinctrl_gpio_range dove_mpp_gpio_ranges[] = {
739 MPP_GPIO_RANGE(0, 0, 0, 32),
740 MPP_GPIO_RANGE(1, 32, 32, 32),
741 MPP_GPIO_RANGE(2, 64, 64, 8),
742};
743
744static struct mvebu_pinctrl_soc_info dove_pinctrl_info = {
745 .controls = dove_mpp_controls,
746 .ncontrols = ARRAY_SIZE(dove_mpp_controls),
747 .modes = dove_mpp_modes,
748 .nmodes = ARRAY_SIZE(dove_mpp_modes),
749 .gpioranges = dove_mpp_gpio_ranges,
750 .ngpioranges = ARRAY_SIZE(dove_mpp_gpio_ranges),
751 .variant = 0,
752};
753
754static struct clk *clk;
755
23259f19 756static const struct of_device_id dove_pinctrl_of_match[] = {
c9f95ced
SH		 757 { .compatible = "marvell,dove-pinctrl", .data = &dove_pinctrl_info },
758 { }
759};
760
23259f19 761static const struct regmap_config gc_regmap_config = {
e91f7916
SH		 762 .reg_bits = 32,
763 .val_bits = 32,
764 .reg_stride = 4,
765 .max_register = 5,
766};
767
150632b0 768static int dove_pinctrl_probe(struct platform_device *pdev)
c9f95ced 769{
4d73fc77
SH		 770 struct resource *res, *mpp_res;
771 struct resource fb_res;
c9f95ced
SH		 772 const struct of_device_id *match =
773 of_match_device(dove_pinctrl_of_match, &pdev->dev);
ad9ec4ec
RK		 774 struct mvebu_mpp_ctrl_data *mpp_data;
775 void __iomem *base;
776 int i;
777
16fa36be 778 pdev->dev.platform_data = (void *)match->data;
c9f95ced
SH		 779
780 /*
781 * General MPP Configuration Register is part of pdma registers.
782 * grab clk to make sure it is ticking.
783 */
784 clk = devm_clk_get(&pdev->dev, NULL);
ba607b62
SH		 785 if (IS_ERR(clk)) {
786 dev_err(&pdev->dev, "Unable to get pdma clock");
5795c6ac 787 return PTR_ERR(clk);
ba607b62
SH		 788 }
789 clk_prepare_enable(clk);
c9f95ced 790
4d73fc77 791 mpp_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
ad9ec4ec
RK		 792 base = devm_ioremap_resource(&pdev->dev, mpp_res);
793 if (IS_ERR(base))
794 return PTR_ERR(base);
795
796 mpp_data = devm_kcalloc(&pdev->dev, dove_pinctrl_info.ncontrols,
797 sizeof(*mpp_data), GFP_KERNEL);
798 if (!mpp_data)
799 return -ENOMEM;
800
801 dove_pinctrl_info.control_data = mpp_data;
802 for (i = 0; i < ARRAY_SIZE(dove_mpp_controls); i++)
803 mpp_data[i].base = base;
1217b790 804
4d73fc77
SH		 805 /* prepare fallback resource */
806 memcpy(&fb_res, mpp_res, sizeof(struct resource));
807 fb_res.start = 0;
808
809 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
810 if (!res) {
811 dev_warn(&pdev->dev, "falling back to hardcoded MPP4 resource\n");
812 adjust_resource(&fb_res,
813 (mpp_res->start & INT_REGS_MASK) + MPP4_REGS_OFFS, 0x4);
814 res = &fb_res;
815 }
816
817 mpp4_base = devm_ioremap_resource(&pdev->dev, res);
818 if (IS_ERR(mpp4_base))
819 return PTR_ERR(mpp4_base);
820
821 res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
822 if (!res) {
823 dev_warn(&pdev->dev, "falling back to hardcoded PMU resource\n");
824 adjust_resource(&fb_res,
825 (mpp_res->start & INT_REGS_MASK) + PMU_REGS_OFFS, 0x8);
826 res = &fb_res;
827 }
828
829 pmu_base = devm_ioremap_resource(&pdev->dev, res);
830 if (IS_ERR(pmu_base))
831 return PTR_ERR(pmu_base);
832
e91f7916
SH		 833 gconfmap = syscon_regmap_lookup_by_compatible("marvell,dove-global-config");
834 if (IS_ERR(gconfmap)) {
835 void __iomem *gc_base;
836
837 dev_warn(&pdev->dev, "falling back to hardcoded global registers\n");
838 adjust_resource(&fb_res,
839 (mpp_res->start & INT_REGS_MASK) + GC_REGS_OFFS, 0x14);
840 gc_base = devm_ioremap_resource(&pdev->dev, &fb_res);
841 if (IS_ERR(gc_base))
842 return PTR_ERR(gc_base);
843 gconfmap = devm_regmap_init_mmio(&pdev->dev,
844 gc_base, &gc_regmap_config);
845 if (IS_ERR(gconfmap))
846 return PTR_ERR(gconfmap);
847 }
848
4d73fc77 849 /* Warn on any missing DT resource */
3c7d5637
SH		 850 if (fb_res.start)
851 dev_warn(&pdev->dev, FW_BUG "Missing pinctrl regs in DTB. Please update your firmware.\n");
4d73fc77 852
c9f95ced
SH		 853 return mvebu_pinctrl_probe(pdev);
854}
855
c9f95ced
SH		 856static struct platform_driver dove_pinctrl_driver = {
857 .driver = {
858 .name = "dove-pinctrl",
fdbde81b 859 .suppress_bind_attrs = true,
f2e9394d 860 .of_match_table = dove_pinctrl_of_match,
c9f95ced
SH		 861 },
862 .probe = dove_pinctrl_probe,
c9f95ced 863};
fdbde81b 864builtin_platform_driver(dove_pinctrl_driver);
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