[mirror_ubuntu-artful-kernel.git] / drivers / pinctrl / mvebu / pinctrl-orion.c

/*
 * Marvell Orion pinctrl driver based on mvebu pinctrl core
 *
 * Author: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * The first 16 MPP pins on Orion are easy to handle: they are
 * configured through 2 consecutive registers, located at the base
 * address of the MPP device.
 *
 * However the last 4 MPP pins are handled by a register at offset
 * 0x50 from the base address, so it is not consecutive with the first
 * two registers.
 */

#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/pinctrl.h>

#include "pinctrl-mvebu.h"

static void __iomem *mpp_base;
static void __iomem *high_mpp_base;

static int orion_mpp_ctrl_get(struct mvebu_mpp_ctrl_data *data,
			      unsigned pid, unsigned long *config)
{
	unsigned shift = (pid % MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;

	if (pid < 16) {
		unsigned off = (pid / MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
		*config = (readl(mpp_base + off) >> shift) & MVEBU_MPP_MASK;
	}
	else {
		*config = (readl(high_mpp_base) >> shift) & MVEBU_MPP_MASK;
	}

	return 0;
}

static int orion_mpp_ctrl_set(struct mvebu_mpp_ctrl_data *data,
			      unsigned pid, unsigned long config)
{
	unsigned shift = (pid % MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;

	if (pid < 16) {
		unsigned off = (pid / MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
		u32 reg = readl(mpp_base + off) & ~(MVEBU_MPP_MASK << shift);
		writel(reg | (config << shift), mpp_base + off);
	}
	else {
		u32 reg = readl(high_mpp_base) & ~(MVEBU_MPP_MASK << shift);
		writel(reg | (config << shift), high_mpp_base);
	}

	return 0;
}

#define V(f5181, f5182, f5281) \
	((f5181 << 0) | (f5182 << 1) | (f5281 << 2))

enum orion_variant {
	V_5181  = V(1, 0, 0),
	V_5182  = V(0, 1, 0),
	V_5281  = V(0, 0, 1),
	V_ALL   = V(1, 1, 1),
};

static struct mvebu_mpp_mode orion_mpp_modes[] = {
	MPP_MODE(0,
		 MPP_VAR_FUNCTION(0x0, "pcie", "rstout",    V_ALL),
		 MPP_VAR_FUNCTION(0x2, "pci", "req2",       V_ALL),
		 MPP_VAR_FUNCTION(0x3, "gpio", NULL,        V_ALL)),
	MPP_MODE(1,
		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_ALL),
		 MPP_VAR_FUNCTION(0x2, "pci", "gnt2",       V_ALL)),
	MPP_MODE(2,
		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_ALL),
		 MPP_VAR_FUNCTION(0x2, "pci", "req3",       V_ALL),
		 MPP_VAR_FUNCTION(0x3, "pci-1", "pme",      V_ALL)),
	MPP_MODE(3,
		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_ALL),
		 MPP_VAR_FUNCTION(0x2, "pci", "gnt3",       V_ALL)),
	MPP_MODE(4,
		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_ALL),
		 MPP_VAR_FUNCTION(0x2, "pci", "req4",       V_ALL),
		 MPP_VAR_FUNCTION(0x4, "bootnand", "re",    V_5182 | V_5281),
		 MPP_VAR_FUNCTION(0x5, "sata0", "prsnt",    V_5182)),
	MPP_MODE(5,
		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_ALL),
		 MPP_VAR_FUNCTION(0x2, "pci", "gnt4",       V_ALL),
		 MPP_VAR_FUNCTION(0x4, "bootnand", "we",    V_5182 | V_5281),
		 MPP_VAR_FUNCTION(0x5, "sata1", "prsnt",    V_5182)),
	MPP_MODE(6,
		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_ALL),
		 MPP_VAR_FUNCTION(0x2, "pci", "req5",       V_ALL),
		 MPP_VAR_FUNCTION(0x4, "nand", "re0",       V_5182 | V_5281),
		 MPP_VAR_FUNCTION(0x5, "pci-1", "clk",      V_5181),
		 MPP_VAR_FUNCTION(0x5, "sata0", "act",      V_5182)),
	MPP_MODE(7,
		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_ALL),
		 MPP_VAR_FUNCTION(0x2, "pci", "gnt5",       V_ALL),
		 MPP_VAR_FUNCTION(0x4, "nand", "we0",       V_5182 | V_5281),
		 MPP_VAR_FUNCTION(0x5, "pci-1", "clk",      V_5181),
		 MPP_VAR_FUNCTION(0x5, "sata1", "act",      V_5182)),
	MPP_MODE(8,
		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_ALL),
		 MPP_VAR_FUNCTION(0x1, "ge", "col",         V_ALL)),
	MPP_MODE(9,
		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_ALL),
		 MPP_VAR_FUNCTION(0x1, "ge", "rxerr",       V_ALL)),
	MPP_MODE(10,
		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_ALL),
		 MPP_VAR_FUNCTION(0x1, "ge", "crs",         V_ALL)),
	MPP_MODE(11,
		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_ALL),
		 MPP_VAR_FUNCTION(0x1, "ge", "txerr",       V_ALL)),
	MPP_MODE(12,
		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_ALL),
		 MPP_VAR_FUNCTION(0x1, "ge", "txd4",        V_ALL),
		 MPP_VAR_FUNCTION(0x4, "nand", "re1",       V_5182 | V_5281),
		 MPP_VAR_FUNCTION(0x5, "sata0", "ledprsnt", V_5182)),
	MPP_MODE(13,
		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_ALL),
		 MPP_VAR_FUNCTION(0x1, "ge", "txd5",        V_ALL),
		 MPP_VAR_FUNCTION(0x4, "nand", "we1",       V_5182 | V_5281),
		 MPP_VAR_FUNCTION(0x5, "sata1", "ledprsnt", V_5182)),
	MPP_MODE(14,
		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_ALL),
		 MPP_VAR_FUNCTION(0x1, "ge", "txd6",        V_ALL),
		 MPP_VAR_FUNCTION(0x4, "nand", "re2",       V_5182 | V_5281),
		 MPP_VAR_FUNCTION(0x5, "sata0", "ledact",   V_5182)),
	MPP_MODE(15,
		 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_ALL),
		 MPP_VAR_FUNCTION(0x1, "ge", "txd7",        V_ALL),
		 MPP_VAR_FUNCTION(0x4, "nand", "we2",       V_5182 | V_5281),
		 MPP_VAR_FUNCTION(0x5, "sata1", "ledact",   V_5182)),
	MPP_MODE(16,
		 MPP_VAR_FUNCTION(0x0, "uart1", "rxd",      V_5182 | V_5281),
		 MPP_VAR_FUNCTION(0x1, "ge", "rxd4",        V_ALL),
		 MPP_VAR_FUNCTION(0x5, "gpio", NULL,        V_5182)),
	MPP_MODE(17,
		 MPP_VAR_FUNCTION(0x0, "uart1", "txd",      V_5182 | V_5281),
		 MPP_VAR_FUNCTION(0x1, "ge", "rxd5",        V_ALL),
		 MPP_VAR_FUNCTION(0x5, "gpio", NULL,        V_5182)),
	MPP_MODE(18,
		 MPP_VAR_FUNCTION(0x0, "uart1", "cts",      V_5182 | V_5281),
		 MPP_VAR_FUNCTION(0x1, "ge", "rxd6",        V_ALL),
		 MPP_VAR_FUNCTION(0x5, "gpio", NULL,        V_5182)),
	MPP_MODE(19,
		 MPP_VAR_FUNCTION(0x0, "uart1", "rts",      V_5182 | V_5281),
		 MPP_VAR_FUNCTION(0x1, "ge", "rxd7",        V_ALL),
		 MPP_VAR_FUNCTION(0x5, "gpio", NULL,        V_5182)),
};

static const struct mvebu_mpp_ctrl orion_mpp_controls[] = {
	MPP_FUNC_CTRL(0, 19, NULL, orion_mpp_ctrl),
};

static struct pinctrl_gpio_range mv88f5181_gpio_ranges[] = {
	MPP_GPIO_RANGE(0, 0, 0, 16),
};

static struct pinctrl_gpio_range mv88f5182_gpio_ranges[] = {
	MPP_GPIO_RANGE(0, 0, 0, 19),
};

static struct pinctrl_gpio_range mv88f5281_gpio_ranges[] = {
	MPP_GPIO_RANGE(0, 0, 0, 16),
};

static struct mvebu_pinctrl_soc_info mv88f5181_info = {
	.variant = V_5181,
	.controls = orion_mpp_controls,
	.ncontrols = ARRAY_SIZE(orion_mpp_controls),
	.modes = orion_mpp_modes,
	.nmodes = ARRAY_SIZE(orion_mpp_modes),
	.gpioranges = mv88f5181_gpio_ranges,
	.ngpioranges = ARRAY_SIZE(mv88f5181_gpio_ranges),
};

static struct mvebu_pinctrl_soc_info mv88f5182_info = {
	.variant = V_5182,
	.controls = orion_mpp_controls,
	.ncontrols = ARRAY_SIZE(orion_mpp_controls),
	.modes = orion_mpp_modes,
	.nmodes = ARRAY_SIZE(orion_mpp_modes),
	.gpioranges = mv88f5182_gpio_ranges,
	.ngpioranges = ARRAY_SIZE(mv88f5182_gpio_ranges),
};

static struct mvebu_pinctrl_soc_info mv88f5281_info = {
	.variant = V_5281,
	.controls = orion_mpp_controls,
	.ncontrols = ARRAY_SIZE(orion_mpp_controls),
	.modes = orion_mpp_modes,
	.nmodes = ARRAY_SIZE(orion_mpp_modes),
	.gpioranges = mv88f5281_gpio_ranges,
	.ngpioranges = ARRAY_SIZE(mv88f5281_gpio_ranges),
};

/*
 * There are multiple variants of the Orion SoCs, but in terms of pin
 * muxing, they are identical.
 */
static const struct of_device_id orion_pinctrl_of_match[] = {
	{ .compatible = "marvell,88f5181-pinctrl", .data = &mv88f5181_info },
	{ .compatible = "marvell,88f5181l-pinctrl", .data = &mv88f5181_info },
	{ .compatible = "marvell,88f5182-pinctrl", .data = &mv88f5182_info },
	{ .compatible = "marvell,88f5281-pinctrl", .data = &mv88f5281_info },
	{ }
};

static int orion_pinctrl_probe(struct platform_device *pdev)
{
	const struct of_device_id *match =
		of_match_device(orion_pinctrl_of_match, &pdev->dev);
	struct resource *res;

	pdev->dev.platform_data = (void*)match->data;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	mpp_base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(mpp_base))
		return PTR_ERR(mpp_base);

	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	high_mpp_base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(high_mpp_base))
		return PTR_ERR(high_mpp_base);

	return mvebu_pinctrl_probe(pdev);
}

static struct platform_driver orion_pinctrl_driver = {
	.driver = {
		.name = "orion-pinctrl",
		.of_match_table = of_match_ptr(orion_pinctrl_of_match),
	},
	.probe = orion_pinctrl_probe,
};

module_platform_driver(orion_pinctrl_driver);

MODULE_AUTHOR("Thomas Petazzoni <thomas.petazzoni@free-electrons.com>");
MODULE_DESCRIPTION("Marvell Orion pinctrl driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
fd67f884 TP	1	/*
	2	* Marvell Orion pinctrl driver based on mvebu pinctrl core
	3	*
	4	* Author: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	* The first 16 MPP pins on Orion are easy to handle: they are
	12	* configured through 2 consecutive registers, located at the base
	13	* address of the MPP device.
	14	*
	15	* However the last 4 MPP pins are handled by a register at offset
	16	* 0x50 from the base address, so it is not consecutive with the first
	17	* two registers.
	18	*/
	19
	20	#include <linux/err.h>
	21	#include <linux/init.h>
	22	#include <linux/io.h>
	23	#include <linux/module.h>
	24	#include <linux/platform_device.h>
	25	#include <linux/clk.h>
	26	#include <linux/of.h>
	27	#include <linux/of_device.h>
	28	#include <linux/pinctrl/pinctrl.h>
	29
	30	#include "pinctrl-mvebu.h"
	31
	32	static void __iomem *mpp_base;
	33	static void __iomem *high_mpp_base;
	34
20955c5f RK	35	static int orion_mpp_ctrl_get(struct mvebu_mpp_ctrl_data *data,
20955c5f RK	36	unsigned pid, unsigned long *config)
fd67f884 TP	37	{
	38	unsigned shift = (pid % MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
	39
	40	if (pid < 16) {
	41	unsigned off = (pid / MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
	42	*config = (readl(mpp_base + off) >> shift) & MVEBU_MPP_MASK;
	43	}
	44	else {
	45	*config = (readl(high_mpp_base) >> shift) & MVEBU_MPP_MASK;
	46	}
	47
	48	return 0;
	49	}
	50
20955c5f RK	51	static int orion_mpp_ctrl_set(struct mvebu_mpp_ctrl_data *data,
20955c5f RK	52	unsigned pid, unsigned long config)
fd67f884 TP	53	{
	54	unsigned shift = (pid % MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
	55
	56	if (pid < 16) {
	57	unsigned off = (pid / MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
	58	u32 reg = readl(mpp_base + off) & ~(MVEBU_MPP_MASK << shift);
	59	writel(reg \| (config << shift), mpp_base + off);
	60	}
	61	else {
	62	u32 reg = readl(high_mpp_base) & ~(MVEBU_MPP_MASK << shift);
	63	writel(reg \| (config << shift), high_mpp_base);
	64	}
	65
	66	return 0;
	67	}
	68
c336dc7d JL	69	#define V(f5181, f5182, f5281) \
c336dc7d JL	70	((f5181 << 0) \| (f5182 << 1) \| (f5281 << 2))
fd67f884 TP	71
fd67f884 TP	72	enum orion_variant {
c336dc7d	73	V_5181 = V(1, 0, 0),
fd67f884 TP	74	V_5182 = V(0, 1, 0),
	75	V_5281 = V(0, 0, 1),
	76	V_ALL = V(1, 1, 1),
	77	};
	78
	79	static struct mvebu_mpp_mode orion_mpp_modes[] = {
	80	MPP_MODE(0,
	81	MPP_VAR_FUNCTION(0x0, "pcie", "rstout", V_ALL),
	82	MPP_VAR_FUNCTION(0x2, "pci", "req2", V_ALL),
	83	MPP_VAR_FUNCTION(0x3, "gpio", NULL, V_ALL)),
	84	MPP_MODE(1,
	85	MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL),
	86	MPP_VAR_FUNCTION(0x2, "pci", "gnt2", V_ALL)),
	87	MPP_MODE(2,
	88	MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL),
	89	MPP_VAR_FUNCTION(0x2, "pci", "req3", V_ALL),
	90	MPP_VAR_FUNCTION(0x3, "pci-1", "pme", V_ALL)),
	91	MPP_MODE(3,
	92	MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL),
	93	MPP_VAR_FUNCTION(0x2, "pci", "gnt3", V_ALL)),
	94	MPP_MODE(4,
	95	MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL),
	96	MPP_VAR_FUNCTION(0x2, "pci", "req4", V_ALL),
	97	MPP_VAR_FUNCTION(0x4, "bootnand", "re", V_5182 \| V_5281),
	98	MPP_VAR_FUNCTION(0x5, "sata0", "prsnt", V_5182)),
	99	MPP_MODE(5,
	100	MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL),
	101	MPP_VAR_FUNCTION(0x2, "pci", "gnt4", V_ALL),
	102	MPP_VAR_FUNCTION(0x4, "bootnand", "we", V_5182 \| V_5281),
	103	MPP_VAR_FUNCTION(0x5, "sata1", "prsnt", V_5182)),
	104	MPP_MODE(6,
	105	MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL),
	106	MPP_VAR_FUNCTION(0x2, "pci", "req5", V_ALL),
	107	MPP_VAR_FUNCTION(0x4, "nand", "re0", V_5182 \| V_5281),
c336dc7d	108	MPP_VAR_FUNCTION(0x5, "pci-1", "clk", V_5181),
fd67f884 TP	109	MPP_VAR_FUNCTION(0x5, "sata0", "act", V_5182)),
	110	MPP_MODE(7,
	111	MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL),
	112	MPP_VAR_FUNCTION(0x2, "pci", "gnt5", V_ALL),
	113	MPP_VAR_FUNCTION(0x4, "nand", "we0", V_5182 \| V_5281),
c336dc7d	114	MPP_VAR_FUNCTION(0x5, "pci-1", "clk", V_5181),
fd67f884 TP	115	MPP_VAR_FUNCTION(0x5, "sata1", "act", V_5182)),
	116	MPP_MODE(8,
	117	MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL),
	118	MPP_VAR_FUNCTION(0x1, "ge", "col", V_ALL)),
	119	MPP_MODE(9,
	120	MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL),
	121	MPP_VAR_FUNCTION(0x1, "ge", "rxerr", V_ALL)),
	122	MPP_MODE(10,
	123	MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL),
	124	MPP_VAR_FUNCTION(0x1, "ge", "crs", V_ALL)),
	125	MPP_MODE(11,
	126	MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL),
	127	MPP_VAR_FUNCTION(0x1, "ge", "txerr", V_ALL)),
	128	MPP_MODE(12,
	129	MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL),
	130	MPP_VAR_FUNCTION(0x1, "ge", "txd4", V_ALL),
	131	MPP_VAR_FUNCTION(0x4, "nand", "re1", V_5182 \| V_5281),
	132	MPP_VAR_FUNCTION(0x5, "sata0", "ledprsnt", V_5182)),
	133	MPP_MODE(13,
	134	MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL),
	135	MPP_VAR_FUNCTION(0x1, "ge", "txd5", V_ALL),
	136	MPP_VAR_FUNCTION(0x4, "nand", "we1", V_5182 \| V_5281),
	137	MPP_VAR_FUNCTION(0x5, "sata1", "ledprsnt", V_5182)),
	138	MPP_MODE(14,
	139	MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL),
	140	MPP_VAR_FUNCTION(0x1, "ge", "txd6", V_ALL),
	141	MPP_VAR_FUNCTION(0x4, "nand", "re2", V_5182 \| V_5281),
	142	MPP_VAR_FUNCTION(0x5, "sata0", "ledact", V_5182)),
	143	MPP_MODE(15,
	144	MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL),
	145	MPP_VAR_FUNCTION(0x1, "ge", "txd7", V_ALL),
	146	MPP_VAR_FUNCTION(0x4, "nand", "we2", V_5182 \| V_5281),
	147	MPP_VAR_FUNCTION(0x5, "sata1", "ledact", V_5182)),
	148	MPP_MODE(16,
	149	MPP_VAR_FUNCTION(0x0, "uart1", "rxd", V_5182 \| V_5281),
	150	MPP_VAR_FUNCTION(0x1, "ge", "rxd4", V_ALL),
	151	MPP_VAR_FUNCTION(0x5, "gpio", NULL, V_5182)),
	152	MPP_MODE(17,
	153	MPP_VAR_FUNCTION(0x0, "uart1", "txd", V_5182 \| V_5281),
	154	MPP_VAR_FUNCTION(0x1, "ge", "rxd5", V_ALL),
	155	MPP_VAR_FUNCTION(0x5, "gpio", NULL, V_5182)),
	156	MPP_MODE(18,
	157	MPP_VAR_FUNCTION(0x0, "uart1", "cts", V_5182 \| V_5281),
	158	MPP_VAR_FUNCTION(0x1, "ge", "rxd6", V_ALL),
	159	MPP_VAR_FUNCTION(0x5, "gpio", NULL, V_5182)),
	160	MPP_MODE(19,
	161	MPP_VAR_FUNCTION(0x0, "uart1", "rts", V_5182 \| V_5281),
	162	MPP_VAR_FUNCTION(0x1, "ge", "rxd7", V_ALL),
	163	MPP_VAR_FUNCTION(0x5, "gpio", NULL, V_5182)),
	164	};
	165
30be3fb9	166	static const struct mvebu_mpp_ctrl orion_mpp_controls[] = {
fd67f884 TP	167	MPP_FUNC_CTRL(0, 19, NULL, orion_mpp_ctrl),
	168	};
	169
c336dc7d	170	static struct pinctrl_gpio_range mv88f5181_gpio_ranges[] = {
fd67f884 TP	171	MPP_GPIO_RANGE(0, 0, 0, 16),
	172	};
	173
	174	static struct pinctrl_gpio_range mv88f5182_gpio_ranges[] = {
	175	MPP_GPIO_RANGE(0, 0, 0, 19),
	176	};
	177
	178	static struct pinctrl_gpio_range mv88f5281_gpio_ranges[] = {
	179	MPP_GPIO_RANGE(0, 0, 0, 16),
	180	};
	181
c336dc7d JL	182	static struct mvebu_pinctrl_soc_info mv88f5181_info = {
c336dc7d JL	183	.variant = V_5181,
fd67f884 TP	184	.controls = orion_mpp_controls,
	185	.ncontrols = ARRAY_SIZE(orion_mpp_controls),
	186	.modes = orion_mpp_modes,
	187	.nmodes = ARRAY_SIZE(orion_mpp_modes),
c336dc7d JL	188	.gpioranges = mv88f5181_gpio_ranges,
c336dc7d JL	189	.ngpioranges = ARRAY_SIZE(mv88f5181_gpio_ranges),
fd67f884 TP	190	};
	191
	192	static struct mvebu_pinctrl_soc_info mv88f5182_info = {
	193	.variant = V_5182,
	194	.controls = orion_mpp_controls,
	195	.ncontrols = ARRAY_SIZE(orion_mpp_controls),
	196	.modes = orion_mpp_modes,
	197	.nmodes = ARRAY_SIZE(orion_mpp_modes),
	198	.gpioranges = mv88f5182_gpio_ranges,
	199	.ngpioranges = ARRAY_SIZE(mv88f5182_gpio_ranges),
	200	};
	201
	202	static struct mvebu_pinctrl_soc_info mv88f5281_info = {
	203	.variant = V_5281,
	204	.controls = orion_mpp_controls,
	205	.ncontrols = ARRAY_SIZE(orion_mpp_controls),
	206	.modes = orion_mpp_modes,
	207	.nmodes = ARRAY_SIZE(orion_mpp_modes),
	208	.gpioranges = mv88f5281_gpio_ranges,
	209	.ngpioranges = ARRAY_SIZE(mv88f5281_gpio_ranges),
	210	};
	211
	212	/*
	213	* There are multiple variants of the Orion SoCs, but in terms of pin
	214	* muxing, they are identical.
	215	*/
baa9946e	216	static const struct of_device_id orion_pinctrl_of_match[] = {
c336dc7d JL	217	{ .compatible = "marvell,88f5181-pinctrl", .data = &mv88f5181_info },
c336dc7d JL	218	{ .compatible = "marvell,88f5181l-pinctrl", .data = &mv88f5181_info },
fd67f884 TP	219	{ .compatible = "marvell,88f5182-pinctrl", .data = &mv88f5182_info },
	220	{ .compatible = "marvell,88f5281-pinctrl", .data = &mv88f5281_info },
	221	{ }
	222	};
	223
	224	static int orion_pinctrl_probe(struct platform_device *pdev)
	225	{
	226	const struct of_device_id *match =
	227	of_match_device(orion_pinctrl_of_match, &pdev->dev);
	228	struct resource *res;
	229
	230	pdev->dev.platform_data = (void*)match->data;
	231
	232	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	233	mpp_base = devm_ioremap_resource(&pdev->dev, res);
	234	if (IS_ERR(mpp_base))
	235	return PTR_ERR(mpp_base);
	236
	237	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	238	high_mpp_base = devm_ioremap_resource(&pdev->dev, res);
	239	if (IS_ERR(high_mpp_base))
	240	return PTR_ERR(high_mpp_base);
	241
	242	return mvebu_pinctrl_probe(pdev);
	243	}
	244
fd67f884 TP	245	static struct platform_driver orion_pinctrl_driver = {
	246	.driver = {
	247	.name = "orion-pinctrl",
fd67f884 TP	248	.of_match_table = of_match_ptr(orion_pinctrl_of_match),
	249	},
	250	.probe = orion_pinctrl_probe,
fd67f884 TP	251	};
	252
	253	module_platform_driver(orion_pinctrl_driver);
	254
	255	MODULE_AUTHOR("Thomas Petazzoni <thomas.petazzoni@free-electrons.com>");
	256	MODULE_DESCRIPTION("Marvell Orion pinctrl driver");
	257	MODULE_LICENSE("GPL v2");