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[mirror_ubuntu-zesty-kernel.git] / drivers / pinctrl / pinctrl-amd.c
CommitLineData
dbad75dd
KX		 1/*
2 * GPIO driver for AMD
3 *
4 * Copyright (c) 2014,2015 AMD Corporation.
5 * Authors: Ken Xue <Ken.Xue@amd.com>
6 * Wu, Jeff <Jeff.Wu@amd.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2, as published by the Free Software Foundation.
11 */
12
13#include <linux/err.h>
14#include <linux/bug.h>
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/spinlock.h>
18#include <linux/compiler.h>
19#include <linux/types.h>
20#include <linux/errno.h>
21#include <linux/log2.h>
22#include <linux/io.h>
23#include <linux/gpio.h>
24#include <linux/slab.h>
25#include <linux/platform_device.h>
26#include <linux/mutex.h>
27#include <linux/acpi.h>
28#include <linux/seq_file.h>
29#include <linux/interrupt.h>
30#include <linux/list.h>
31#include <linux/bitops.h>
dbad75dd
KX		 32#include <linux/pinctrl/pinconf.h>
33#include <linux/pinctrl/pinconf-generic.h>
34
35#include "pinctrl-utils.h"
36#include "pinctrl-amd.h"
37
dbad75dd
KX		 38static int amd_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
39{
40 unsigned long flags;
41 u32 pin_reg;
04d36723 42 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
dbad75dd 43
3745128c 44 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
dbad75dd 45 pin_reg = readl(gpio_dev->base + offset * 4);
dbad75dd
KX		 46 pin_reg &= ~BIT(OUTPUT_ENABLE_OFF);
47 writel(pin_reg, gpio_dev->base + offset * 4);
3745128c 48 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
dbad75dd
KX		 49
50 return 0;
51}
52
53static int amd_gpio_direction_output(struct gpio_chip *gc, unsigned offset,
54 int value)
55{
56 u32 pin_reg;
57 unsigned long flags;
04d36723 58 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
dbad75dd 59
3745128c 60 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
dbad75dd
KX		 61 pin_reg = readl(gpio_dev->base + offset * 4);
62 pin_reg |= BIT(OUTPUT_ENABLE_OFF);
63 if (value)
64 pin_reg |= BIT(OUTPUT_VALUE_OFF);
65 else
66 pin_reg &= ~BIT(OUTPUT_VALUE_OFF);
67 writel(pin_reg, gpio_dev->base + offset * 4);
3745128c 68 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
dbad75dd
KX		 69
70 return 0;
71}
72
73static int amd_gpio_get_value(struct gpio_chip *gc, unsigned offset)
74{
75 u32 pin_reg;
76 unsigned long flags;
04d36723 77 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
dbad75dd 78
3745128c 79 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
dbad75dd 80 pin_reg = readl(gpio_dev->base + offset * 4);
3745128c 81 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
dbad75dd
KX		 82
83 return !!(pin_reg & BIT(PIN_STS_OFF));
84}
85
86static void amd_gpio_set_value(struct gpio_chip *gc, unsigned offset, int value)
87{
88 u32 pin_reg;
89 unsigned long flags;
04d36723 90 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
dbad75dd 91
3745128c 92 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
dbad75dd
KX		 93 pin_reg = readl(gpio_dev->base + offset * 4);
94 if (value)
95 pin_reg |= BIT(OUTPUT_VALUE_OFF);
96 else
97 pin_reg &= ~BIT(OUTPUT_VALUE_OFF);
98 writel(pin_reg, gpio_dev->base + offset * 4);
3745128c 99 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
dbad75dd
KX		 100}
101
102static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset,
103 unsigned debounce)
104{
dbad75dd 105 u32 time;
25a853d0
KX		 106 u32 pin_reg;
107 int ret = 0;
dbad75dd 108 unsigned long flags;
04d36723 109 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
dbad75dd 110
3745128c 111 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
dbad75dd
KX		 112 pin_reg = readl(gpio_dev->base + offset * 4);
113
114 if (debounce) {
115 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
116 pin_reg &= ~DB_TMR_OUT_MASK;
117 /*
118 Debounce Debounce Timer Max
119 TmrLarge TmrOutUnit Unit Debounce
120 Time
121 0 0 61 usec (2 RtcClk) 976 usec
122 0 1 244 usec (8 RtcClk) 3.9 msec
123 1 0 15.6 msec (512 RtcClk) 250 msec
124 1 1 62.5 msec (2048 RtcClk) 1 sec
125 */
126
127 if (debounce < 61) {
128 pin_reg |= 1;
129 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
130 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
131 } else if (debounce < 976) {
132 time = debounce / 61;
133 pin_reg |= time & DB_TMR_OUT_MASK;
134 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
135 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
136 } else if (debounce < 3900) {
137 time = debounce / 244;
138 pin_reg |= time & DB_TMR_OUT_MASK;
139 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
140 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
141 } else if (debounce < 250000) {
142 time = debounce / 15600;
143 pin_reg |= time & DB_TMR_OUT_MASK;
144 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
145 pin_reg |= BIT(DB_TMR_LARGE_OFF);
146 } else if (debounce < 1000000) {
147 time = debounce / 62500;
148 pin_reg |= time & DB_TMR_OUT_MASK;
149 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
150 pin_reg |= BIT(DB_TMR_LARGE_OFF);
151 } else {
152 pin_reg &= ~DB_CNTRl_MASK;
25a853d0 153 ret = -EINVAL;
dbad75dd
KX		 154 }
155 } else {
156 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
157 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
158 pin_reg &= ~DB_TMR_OUT_MASK;
159 pin_reg &= ~DB_CNTRl_MASK;
160 }
161 writel(pin_reg, gpio_dev->base + offset * 4);
3745128c 162 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
dbad75dd 163
25a853d0 164 return ret;
dbad75dd
KX		 165}
166
167#ifdef CONFIG_DEBUG_FS
168static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc)
169{
170 u32 pin_reg;
171 unsigned long flags;
172 unsigned int bank, i, pin_num;
04d36723 173 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
dbad75dd
KX		 174
175 char *level_trig;
176 char *active_level;
177 char *interrupt_enable;
178 char *interrupt_mask;
179 char *wake_cntrl0;
180 char *wake_cntrl1;
181 char *wake_cntrl2;
182 char *pin_sts;
183 char *pull_up_sel;
184 char *pull_up_enable;
185 char *pull_down_enable;
186 char *output_value;
187 char *output_enable;
188
189 for (bank = 0; bank < AMD_GPIO_TOTAL_BANKS; bank++) {
190 seq_printf(s, "GPIO bank%d\t", bank);
191
192 switch (bank) {
193 case 0:
194 i = 0;
195 pin_num = AMD_GPIO_PINS_BANK0;
196 break;
197 case 1:
198 i = 64;
199 pin_num = AMD_GPIO_PINS_BANK1 + i;
200 break;
201 case 2:
202 i = 128;
203 pin_num = AMD_GPIO_PINS_BANK2 + i;
204 break;
581d3c20
AB		 205 default:
206 return;
dbad75dd
KX		 207 }
208
209 for (; i < pin_num; i++) {
210 seq_printf(s, "pin%d\t", i);
3745128c 211 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
dbad75dd 212 pin_reg = readl(gpio_dev->base + i * 4);
3745128c 213 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
dbad75dd
KX		 214
215 if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) {
216 interrupt_enable = "interrupt is enabled|";
217
218 if (!(pin_reg & BIT(ACTIVE_LEVEL_OFF))
219 && !(pin_reg & BIT(ACTIVE_LEVEL_OFF+1)))
220 active_level = "Active low|";
221 else if (pin_reg & BIT(ACTIVE_LEVEL_OFF)
222 && !(pin_reg & BIT(ACTIVE_LEVEL_OFF+1)))
223 active_level = "Active high|";
224 else if (!(pin_reg & BIT(ACTIVE_LEVEL_OFF))
225 && pin_reg & BIT(ACTIVE_LEVEL_OFF+1))
226 active_level = "Active on both|";
227 else
228 active_level = "Unknow Active level|";
229
230 if (pin_reg & BIT(LEVEL_TRIG_OFF))
231 level_trig = "Level trigger|";
232 else
233 level_trig = "Edge trigger|";
234
235 } else {
236 interrupt_enable =
237 "interrupt is disabled|";
238 active_level = " ";
239 level_trig = " ";
240 }
241
242 if (pin_reg & BIT(INTERRUPT_MASK_OFF))
243 interrupt_mask =
244 "interrupt is unmasked|";
245 else
246 interrupt_mask =
247 "interrupt is masked|";
248
249 if (pin_reg & BIT(WAKE_CNTRL_OFF))
250 wake_cntrl0 = "enable wakeup in S0i3 state|";
251 else
252 wake_cntrl0 = "disable wakeup in S0i3 state|";
253
254 if (pin_reg & BIT(WAKE_CNTRL_OFF))
255 wake_cntrl1 = "enable wakeup in S3 state|";
256 else
257 wake_cntrl1 = "disable wakeup in S3 state|";
258
259 if (pin_reg & BIT(WAKE_CNTRL_OFF))
260 wake_cntrl2 = "enable wakeup in S4/S5 state|";
261 else
262 wake_cntrl2 = "disable wakeup in S4/S5 state|";
263
264 if (pin_reg & BIT(PULL_UP_ENABLE_OFF)) {
265 pull_up_enable = "pull-up is enabled|";
266 if (pin_reg & BIT(PULL_UP_SEL_OFF))
267 pull_up_sel = "8k pull-up|";
268 else
269 pull_up_sel = "4k pull-up|";
270 } else {
271 pull_up_enable = "pull-up is disabled|";
272 pull_up_sel = " ";
273 }
274
275 if (pin_reg & BIT(PULL_DOWN_ENABLE_OFF))
276 pull_down_enable = "pull-down is enabled|";
277 else
278 pull_down_enable = "Pull-down is disabled|";
279
280 if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) {
281 pin_sts = " ";
282 output_enable = "output is enabled|";
283 if (pin_reg & BIT(OUTPUT_VALUE_OFF))
284 output_value = "output is high|";
285 else
286 output_value = "output is low|";
287 } else {
288 output_enable = "output is disabled|";
289 output_value = " ";
290
291 if (pin_reg & BIT(PIN_STS_OFF))
292 pin_sts = "input is high|";
293 else
294 pin_sts = "input is low|";
295 }
296
297 seq_printf(s, "%s %s %s %s %s %s\n"
298 " %s %s %s %s %s %s %s 0x%x\n",
299 level_trig, active_level, interrupt_enable,
300 interrupt_mask, wake_cntrl0, wake_cntrl1,
301 wake_cntrl2, pin_sts, pull_up_sel,
302 pull_up_enable, pull_down_enable,
303 output_value, output_enable, pin_reg);
304 }
305 }
306}
307#else
308#define amd_gpio_dbg_show NULL
309#endif
310
311static void amd_gpio_irq_enable(struct irq_data *d)
312{
313 u32 pin_reg;
314 unsigned long flags;
315 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
04d36723 316 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
dbad75dd 317
3745128c 318 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
dbad75dd 319 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
dbad75dd
KX		 320 pin_reg |= BIT(INTERRUPT_ENABLE_OFF);
321 pin_reg |= BIT(INTERRUPT_MASK_OFF);
322 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
3745128c 323 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
dbad75dd
KX		 324}
325
326static void amd_gpio_irq_disable(struct irq_data *d)
327{
328 u32 pin_reg;
329 unsigned long flags;
330 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
04d36723 331 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
dbad75dd 332
3745128c 333 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
dbad75dd
KX		 334 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
335 pin_reg &= ~BIT(INTERRUPT_ENABLE_OFF);
336 pin_reg &= ~BIT(INTERRUPT_MASK_OFF);
337 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
3745128c 338 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
dbad75dd
KX		 339}
340
341static void amd_gpio_irq_mask(struct irq_data *d)
342{
343 u32 pin_reg;
344 unsigned long flags;
345 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
04d36723 346 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
dbad75dd 347
3745128c 348 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
dbad75dd
KX		 349 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
350 pin_reg &= ~BIT(INTERRUPT_MASK_OFF);
351 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
3745128c 352 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
dbad75dd
KX		 353}
354
355static void amd_gpio_irq_unmask(struct irq_data *d)
356{
357 u32 pin_reg;
358 unsigned long flags;
359 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
04d36723 360 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
dbad75dd 361
3745128c 362 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
dbad75dd
KX		 363 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
364 pin_reg |= BIT(INTERRUPT_MASK_OFF);
365 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
3745128c 366 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
dbad75dd
KX		 367}
368
369static void amd_gpio_irq_eoi(struct irq_data *d)
370{
371 u32 reg;
372 unsigned long flags;
373 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
04d36723 374 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
dbad75dd 375
3745128c 376 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
dbad75dd
KX		 377 reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
378 reg |= EOI_MASK;
379 writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG);
3745128c 380 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
dbad75dd
KX		 381}
382
383static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
384{
385 int ret = 0;
386 u32 pin_reg;
2983f296 387 unsigned long flags, irq_flags;
dbad75dd 388 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
04d36723 389 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
dbad75dd 390
3745128c 391 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
dbad75dd
KX		 392 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
393
2983f296
SS		 394 /* Ignore the settings coming from the client and
395 * read the values from the ACPI tables
396 * while setting the trigger type
499c7196 397 */
499c7196 398
2983f296
SS		 399 irq_flags = irq_get_trigger_type(d->irq);
400 if (irq_flags != IRQ_TYPE_NONE)
401 type = irq_flags;
499c7196 402
dbad75dd
KX		 403 switch (type & IRQ_TYPE_SENSE_MASK) {
404 case IRQ_TYPE_EDGE_RISING:
405 pin_reg &= ~BIT(LEVEL_TRIG_OFF);
406 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
407 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;
408 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
9d829314 409 irq_set_handler_locked(d, handle_edge_irq);
dbad75dd
KX		 410 break;
411
412 case IRQ_TYPE_EDGE_FALLING:
413 pin_reg &= ~BIT(LEVEL_TRIG_OFF);
414 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
415 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;
416 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
9d829314 417 irq_set_handler_locked(d, handle_edge_irq);
dbad75dd
KX		 418 break;
419
420 case IRQ_TYPE_EDGE_BOTH:
421 pin_reg &= ~BIT(LEVEL_TRIG_OFF);
422 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
423 pin_reg |= BOTH_EADGE << ACTIVE_LEVEL_OFF;
424 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
9d829314 425 irq_set_handler_locked(d, handle_edge_irq);
dbad75dd
KX		 426 break;
427
428 case IRQ_TYPE_LEVEL_HIGH:
429 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF;
430 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
431 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;
432 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
433 pin_reg |= DB_TYPE_PRESERVE_LOW_GLITCH << DB_CNTRL_OFF;
9d829314 434 irq_set_handler_locked(d, handle_level_irq);
dbad75dd
KX		 435 break;
436
437 case IRQ_TYPE_LEVEL_LOW:
438 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF;
439 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
440 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;
441 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
442 pin_reg |= DB_TYPE_PRESERVE_HIGH_GLITCH << DB_CNTRL_OFF;
9d829314 443 irq_set_handler_locked(d, handle_level_irq);
dbad75dd
KX		 444 break;
445
446 case IRQ_TYPE_NONE:
447 break;
448
449 default:
450 dev_err(&gpio_dev->pdev->dev, "Invalid type value\n");
451 ret = -EINVAL;
dbad75dd
KX		 452 }
453
454 pin_reg |= CLR_INTR_STAT << INTERRUPT_STS_OFF;
455 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
3745128c 456 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
dbad75dd 457
dbad75dd
KX		 458 return ret;
459}
460
461static void amd_irq_ack(struct irq_data *d)
462{
463 /*
464 * based on HW design,there is no need to ack HW
465 * before handle current irq. But this routine is
466 * necessary for handle_edge_irq
467 */
468}
469
470static struct irq_chip amd_gpio_irqchip = {
471 .name = "amd_gpio",
472 .irq_ack = amd_irq_ack,
473 .irq_enable = amd_gpio_irq_enable,
474 .irq_disable = amd_gpio_irq_disable,
475 .irq_mask = amd_gpio_irq_mask,
476 .irq_unmask = amd_gpio_irq_unmask,
477 .irq_eoi = amd_gpio_irq_eoi,
478 .irq_set_type = amd_gpio_irq_set_type,
479};
480
d928ac59
TG		 481#define PIN_IRQ_PENDING (BIT(INTERRUPT_STS_OFF) | BIT(WAKE_STS_OFF))
482
483static irqreturn_t amd_gpio_irq_handler(int irq, void *dev_id)
dbad75dd 484{
d928ac59
TG		 485 struct amd_gpio *gpio_dev = dev_id;
486 struct gpio_chip *gc = &gpio_dev->gc;
487 irqreturn_t ret = IRQ_NONE;
488 unsigned int i, irqnr;
dbad75dd 489 unsigned long flags;
d928ac59
TG		 490 u32 *regs, regval;
491 u64 status, mask;
dbad75dd 492
d928ac59 493 /* Read the wake status */
3745128c 494 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
d928ac59
TG		 495 status = readl(gpio_dev->base + WAKE_INT_STATUS_REG1);
496 status <<= 32;
497 status |= readl(gpio_dev->base + WAKE_INT_STATUS_REG0);
3745128c 498 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
dbad75dd 499
d928ac59
TG		 500 /* Bit 0-45 contain the relevant status bits */
501 status &= (1ULL << 46) - 1;
502 regs = gpio_dev->base;
503 for (mask = 1, irqnr = 0; status; mask <<= 1, regs += 4, irqnr += 4) {
504 if (!(status & mask))
505 continue;
506 status &= ~mask;
507
508 /* Each status bit covers four pins */
509 for (i = 0; i < 4; i++) {
510 regval = readl(regs + i);
511 if (!(regval & PIN_IRQ_PENDING))
512 continue;
513 irq = irq_find_mapping(gc->irqdomain, irqnr + i);
514 generic_handle_irq(irq);
515 /* Clear interrupt */
516 writel(regval, regs + i);
517 ret = IRQ_HANDLED;
dbad75dd
KX		 518 }
519 }
520
d928ac59 521 /* Signal EOI to the GPIO unit */
3745128c 522 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
d928ac59
TG		 523 regval = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
524 regval |= EOI_MASK;
525 writel(regval, gpio_dev->base + WAKE_INT_MASTER_REG);
3745128c 526 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
dbad75dd 527
d928ac59 528 return ret;
dbad75dd
KX		 529}
530
531static int amd_get_groups_count(struct pinctrl_dev *pctldev)
532{
533 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
534
535 return gpio_dev->ngroups;
536}
537
538static const char *amd_get_group_name(struct pinctrl_dev *pctldev,
539 unsigned group)
540{
541 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
542
543 return gpio_dev->groups[group].name;
544}
545
546static int amd_get_group_pins(struct pinctrl_dev *pctldev,
547 unsigned group,
548 const unsigned **pins,
549 unsigned *num_pins)
550{
551 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
552
553 *pins = gpio_dev->groups[group].pins;
554 *num_pins = gpio_dev->groups[group].npins;
555 return 0;
556}
557
558static const struct pinctrl_ops amd_pinctrl_ops = {
559 .get_groups_count = amd_get_groups_count,
560 .get_group_name = amd_get_group_name,
561 .get_group_pins = amd_get_group_pins,
562#ifdef CONFIG_OF
563 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
d32f7fd3 564 .dt_free_map = pinctrl_utils_free_map,
dbad75dd
KX		 565#endif
566};
567
568static int amd_pinconf_get(struct pinctrl_dev *pctldev,
569 unsigned int pin,
570 unsigned long *config)
571{
572 u32 pin_reg;
573 unsigned arg;
574 unsigned long flags;
575 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
576 enum pin_config_param param = pinconf_to_config_param(*config);
577
3745128c 578 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
dbad75dd 579 pin_reg = readl(gpio_dev->base + pin*4);
3745128c 580 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
dbad75dd
KX		 581 switch (param) {
582 case PIN_CONFIG_INPUT_DEBOUNCE:
583 arg = pin_reg & DB_TMR_OUT_MASK;
584 break;
585
586 case PIN_CONFIG_BIAS_PULL_DOWN:
587 arg = (pin_reg >> PULL_DOWN_ENABLE_OFF) & BIT(0);
588 break;
589
590 case PIN_CONFIG_BIAS_PULL_UP:
591 arg = (pin_reg >> PULL_UP_SEL_OFF) & (BIT(0) | BIT(1));
592 break;
593
594 case PIN_CONFIG_DRIVE_STRENGTH:
595 arg = (pin_reg >> DRV_STRENGTH_SEL_OFF) & DRV_STRENGTH_SEL_MASK;
596 break;
597
598 default:
599 dev_err(&gpio_dev->pdev->dev, "Invalid config param %04x\n",
600 param);
601 return -ENOTSUPP;
602 }
603
604 *config = pinconf_to_config_packed(param, arg);
605
606 return 0;
607}
608
609static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
610 unsigned long *configs, unsigned num_configs)
611{
612 int i;
dbad75dd 613 u32 arg;
25a853d0
KX		 614 int ret = 0;
615 u32 pin_reg;
dbad75dd
KX		 616 unsigned long flags;
617 enum pin_config_param param;
618 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
619
3745128c 620 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
dbad75dd
KX		 621 for (i = 0; i < num_configs; i++) {
622 param = pinconf_to_config_param(configs[i]);
623 arg = pinconf_to_config_argument(configs[i]);
624 pin_reg = readl(gpio_dev->base + pin*4);
625
626 switch (param) {
627 case PIN_CONFIG_INPUT_DEBOUNCE:
628 pin_reg &= ~DB_TMR_OUT_MASK;
629 pin_reg |= arg & DB_TMR_OUT_MASK;
630 break;
631
632 case PIN_CONFIG_BIAS_PULL_DOWN:
633 pin_reg &= ~BIT(PULL_DOWN_ENABLE_OFF);
634 pin_reg |= (arg & BIT(0)) << PULL_DOWN_ENABLE_OFF;
635 break;
636
637 case PIN_CONFIG_BIAS_PULL_UP:
638 pin_reg &= ~BIT(PULL_UP_SEL_OFF);
639 pin_reg |= (arg & BIT(0)) << PULL_UP_SEL_OFF;
640 pin_reg &= ~BIT(PULL_UP_ENABLE_OFF);
641 pin_reg |= ((arg>>1) & BIT(0)) << PULL_UP_ENABLE_OFF;
642 break;
643
644 case PIN_CONFIG_DRIVE_STRENGTH:
645 pin_reg &= ~(DRV_STRENGTH_SEL_MASK
646 << DRV_STRENGTH_SEL_OFF);
647 pin_reg |= (arg & DRV_STRENGTH_SEL_MASK)
648 << DRV_STRENGTH_SEL_OFF;
649 break;
650
651 default:
652 dev_err(&gpio_dev->pdev->dev,
653 "Invalid config param %04x\n", param);
25a853d0 654 ret = -ENOTSUPP;
dbad75dd
KX		 655 }
656
657 writel(pin_reg, gpio_dev->base + pin*4);
658 }
3745128c 659 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
dbad75dd 660
25a853d0 661 return ret;
dbad75dd
KX		 662}
663
664static int amd_pinconf_group_get(struct pinctrl_dev *pctldev,
665 unsigned int group,
666 unsigned long *config)
667{
668 const unsigned *pins;
669 unsigned npins;
670 int ret;
671
672 ret = amd_get_group_pins(pctldev, group, &pins, &npins);
673 if (ret)
674 return ret;
675
676 if (amd_pinconf_get(pctldev, pins[0], config))
677 return -ENOTSUPP;
678
679 return 0;
680}
681
682static int amd_pinconf_group_set(struct pinctrl_dev *pctldev,
683 unsigned group, unsigned long *configs,
684 unsigned num_configs)
685{
686 const unsigned *pins;
687 unsigned npins;
688 int i, ret;
689
690 ret = amd_get_group_pins(pctldev, group, &pins, &npins);
691 if (ret)
692 return ret;
693 for (i = 0; i < npins; i++) {
694 if (amd_pinconf_set(pctldev, pins[i], configs, num_configs))
695 return -ENOTSUPP;
696 }
697 return 0;
698}
699
700static const struct pinconf_ops amd_pinconf_ops = {
701 .pin_config_get = amd_pinconf_get,
702 .pin_config_set = amd_pinconf_set,
703 .pin_config_group_get = amd_pinconf_group_get,
704 .pin_config_group_set = amd_pinconf_group_set,
705};
706
707static struct pinctrl_desc amd_pinctrl_desc = {
708 .pins = kerncz_pins,
709 .npins = ARRAY_SIZE(kerncz_pins),
710 .pctlops = &amd_pinctrl_ops,
711 .confops = &amd_pinconf_ops,
712 .owner = THIS_MODULE,
713};
714
715static int amd_gpio_probe(struct platform_device *pdev)
716{
717 int ret = 0;
25a853d0 718 int irq_base;
dbad75dd
KX		 719 struct resource *res;
720 struct amd_gpio *gpio_dev;
721
722 gpio_dev = devm_kzalloc(&pdev->dev,
723 sizeof(struct amd_gpio), GFP_KERNEL);
724 if (!gpio_dev)
725 return -ENOMEM;
726
3745128c 727 raw_spin_lock_init(&gpio_dev->lock);
dbad75dd
KX		 728
729 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
730 if (!res) {
731 dev_err(&pdev->dev, "Failed to get gpio io resource.\n");
732 return -EINVAL;
733 }
734
735 gpio_dev->base = devm_ioremap_nocache(&pdev->dev, res->start,
736 resource_size(res));
424a6c60
WY		 737 if (!gpio_dev->base)
738 return -ENOMEM;
dbad75dd
KX		 739
740 irq_base = platform_get_irq(pdev, 0);
741 if (irq_base < 0) {
742 dev_err(&pdev->dev, "Failed to get gpio IRQ.\n");
743 return -EINVAL;
744 }
745
746 gpio_dev->pdev = pdev;
747 gpio_dev->gc.direction_input = amd_gpio_direction_input;
748 gpio_dev->gc.direction_output = amd_gpio_direction_output;
749 gpio_dev->gc.get = amd_gpio_get_value;
750 gpio_dev->gc.set = amd_gpio_set_value;
751 gpio_dev->gc.set_debounce = amd_gpio_set_debounce;
752 gpio_dev->gc.dbg_show = amd_gpio_dbg_show;
753
754 gpio_dev->gc.base = 0;
755 gpio_dev->gc.label = pdev->name;
756 gpio_dev->gc.owner = THIS_MODULE;
58383c78 757 gpio_dev->gc.parent = &pdev->dev;
dbad75dd
KX		 758 gpio_dev->gc.ngpio = TOTAL_NUMBER_OF_PINS;
759#if defined(CONFIG_OF_GPIO)
760 gpio_dev->gc.of_node = pdev->dev.of_node;
761#endif
762
763 gpio_dev->groups = kerncz_groups;
764 gpio_dev->ngroups = ARRAY_SIZE(kerncz_groups);
765
766 amd_pinctrl_desc.name = dev_name(&pdev->dev);
251e22ab
LD		 767 gpio_dev->pctrl = devm_pinctrl_register(&pdev->dev, &amd_pinctrl_desc,
768 gpio_dev);
323de9ef 769 if (IS_ERR(gpio_dev->pctrl)) {
dbad75dd 770 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
323de9ef 771 return PTR_ERR(gpio_dev->pctrl);
dbad75dd
KX		 772 }
773
04d36723 774 ret = gpiochip_add_data(&gpio_dev->gc, gpio_dev);
dbad75dd 775 if (ret)
251e22ab 776 return ret;
dbad75dd
KX		 777
778 ret = gpiochip_add_pin_range(&gpio_dev->gc, dev_name(&pdev->dev),
779 0, 0, TOTAL_NUMBER_OF_PINS);
780 if (ret) {
781 dev_err(&pdev->dev, "Failed to add pin range\n");
782 goto out2;
783 }
784
785 ret = gpiochip_irqchip_add(&gpio_dev->gc,
786 &amd_gpio_irqchip,
787 0,
788 handle_simple_irq,
789 IRQ_TYPE_NONE);
790 if (ret) {
791 dev_err(&pdev->dev, "could not add irqchip\n");
792 ret = -ENODEV;
793 goto out2;
794 }
795
d928ac59
TG		 796 ret = devm_request_irq(&pdev->dev, irq_base, amd_gpio_irq_handler, 0,
797 KBUILD_MODNAME, gpio_dev);
798 if (ret)
799 goto out2;
dbad75dd
KX		 800
801 platform_set_drvdata(pdev, gpio_dev);
802
803 dev_dbg(&pdev->dev, "amd gpio driver loaded\n");
804 return ret;
805
806out2:
807 gpiochip_remove(&gpio_dev->gc);
808
dbad75dd
KX		 809 return ret;
810}
811
812static int amd_gpio_remove(struct platform_device *pdev)
813{
814 struct amd_gpio *gpio_dev;
815
816 gpio_dev = platform_get_drvdata(pdev);
817
818 gpiochip_remove(&gpio_dev->gc);
dbad75dd
KX		 819
820 return 0;
821}
822
823static const struct acpi_device_id amd_gpio_acpi_match[] = {
824 { "AMD0030", 0 },
42a44402 825 { "AMDI0030", 0},
dbad75dd
KX		 826 { },
827};
828MODULE_DEVICE_TABLE(acpi, amd_gpio_acpi_match);
829
830static struct platform_driver amd_gpio_driver = {
831 .driver = {
832 .name = "amd_gpio",
dbad75dd
KX		 833 .acpi_match_table = ACPI_PTR(amd_gpio_acpi_match),
834 },
835 .probe = amd_gpio_probe,
836 .remove = amd_gpio_remove,
837};
838
839module_platform_driver(amd_gpio_driver);
840
841MODULE_LICENSE("GPL v2");
842MODULE_AUTHOR("Ken Xue <Ken.Xue@amd.com>, Jeff Wu <Jeff.Wu@amd.com>");
843MODULE_DESCRIPTION("AMD GPIO pinctrl driver");
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