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dbad75dd KX |
1 | /* |
2 | * GPIO driver for AMD | |
3 | * | |
4 | * Copyright (c) 2014,2015 AMD Corporation. | |
5 | * Authors: Ken Xue <Ken.Xue@amd.com> | |
6 | * Wu, Jeff <Jeff.Wu@amd.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms and conditions of the GNU General Public License, | |
10 | * version 2, as published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #include <linux/err.h> | |
14 | #include <linux/bug.h> | |
15 | #include <linux/kernel.h> | |
16 | #include <linux/module.h> | |
17 | #include <linux/spinlock.h> | |
18 | #include <linux/compiler.h> | |
19 | #include <linux/types.h> | |
20 | #include <linux/errno.h> | |
21 | #include <linux/log2.h> | |
22 | #include <linux/io.h> | |
23 | #include <linux/gpio.h> | |
24 | #include <linux/slab.h> | |
25 | #include <linux/platform_device.h> | |
26 | #include <linux/mutex.h> | |
27 | #include <linux/acpi.h> | |
28 | #include <linux/seq_file.h> | |
29 | #include <linux/interrupt.h> | |
30 | #include <linux/list.h> | |
31 | #include <linux/bitops.h> | |
dbad75dd KX |
32 | #include <linux/pinctrl/pinconf.h> |
33 | #include <linux/pinctrl/pinconf-generic.h> | |
34 | ||
35 | #include "pinctrl-utils.h" | |
36 | #include "pinctrl-amd.h" | |
37 | ||
dbad75dd KX |
38 | static int amd_gpio_direction_input(struct gpio_chip *gc, unsigned offset) |
39 | { | |
40 | unsigned long flags; | |
41 | u32 pin_reg; | |
04d36723 | 42 | struct amd_gpio *gpio_dev = gpiochip_get_data(gc); |
dbad75dd | 43 | |
229710fe | 44 | raw_spin_lock_irqsave(&gpio_dev->lock, flags); |
dbad75dd | 45 | pin_reg = readl(gpio_dev->base + offset * 4); |
dbad75dd KX |
46 | pin_reg &= ~BIT(OUTPUT_ENABLE_OFF); |
47 | writel(pin_reg, gpio_dev->base + offset * 4); | |
229710fe | 48 | raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); |
dbad75dd KX |
49 | |
50 | return 0; | |
51 | } | |
52 | ||
53 | static int amd_gpio_direction_output(struct gpio_chip *gc, unsigned offset, | |
54 | int value) | |
55 | { | |
56 | u32 pin_reg; | |
57 | unsigned long flags; | |
04d36723 | 58 | struct amd_gpio *gpio_dev = gpiochip_get_data(gc); |
dbad75dd | 59 | |
229710fe | 60 | raw_spin_lock_irqsave(&gpio_dev->lock, flags); |
dbad75dd KX |
61 | pin_reg = readl(gpio_dev->base + offset * 4); |
62 | pin_reg |= BIT(OUTPUT_ENABLE_OFF); | |
63 | if (value) | |
64 | pin_reg |= BIT(OUTPUT_VALUE_OFF); | |
65 | else | |
66 | pin_reg &= ~BIT(OUTPUT_VALUE_OFF); | |
67 | writel(pin_reg, gpio_dev->base + offset * 4); | |
229710fe | 68 | raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); |
dbad75dd KX |
69 | |
70 | return 0; | |
71 | } | |
72 | ||
73 | static int amd_gpio_get_value(struct gpio_chip *gc, unsigned offset) | |
74 | { | |
75 | u32 pin_reg; | |
76 | unsigned long flags; | |
04d36723 | 77 | struct amd_gpio *gpio_dev = gpiochip_get_data(gc); |
dbad75dd | 78 | |
229710fe | 79 | raw_spin_lock_irqsave(&gpio_dev->lock, flags); |
dbad75dd | 80 | pin_reg = readl(gpio_dev->base + offset * 4); |
229710fe | 81 | raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); |
dbad75dd KX |
82 | |
83 | return !!(pin_reg & BIT(PIN_STS_OFF)); | |
84 | } | |
85 | ||
86 | static void amd_gpio_set_value(struct gpio_chip *gc, unsigned offset, int value) | |
87 | { | |
88 | u32 pin_reg; | |
89 | unsigned long flags; | |
04d36723 | 90 | struct amd_gpio *gpio_dev = gpiochip_get_data(gc); |
dbad75dd | 91 | |
229710fe | 92 | raw_spin_lock_irqsave(&gpio_dev->lock, flags); |
dbad75dd KX |
93 | pin_reg = readl(gpio_dev->base + offset * 4); |
94 | if (value) | |
95 | pin_reg |= BIT(OUTPUT_VALUE_OFF); | |
96 | else | |
97 | pin_reg &= ~BIT(OUTPUT_VALUE_OFF); | |
98 | writel(pin_reg, gpio_dev->base + offset * 4); | |
229710fe | 99 | raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); |
dbad75dd KX |
100 | } |
101 | ||
102 | static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset, | |
103 | unsigned debounce) | |
104 | { | |
dbad75dd | 105 | u32 time; |
25a853d0 KX |
106 | u32 pin_reg; |
107 | int ret = 0; | |
dbad75dd | 108 | unsigned long flags; |
04d36723 | 109 | struct amd_gpio *gpio_dev = gpiochip_get_data(gc); |
dbad75dd | 110 | |
229710fe | 111 | raw_spin_lock_irqsave(&gpio_dev->lock, flags); |
dbad75dd KX |
112 | pin_reg = readl(gpio_dev->base + offset * 4); |
113 | ||
114 | if (debounce) { | |
115 | pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; | |
116 | pin_reg &= ~DB_TMR_OUT_MASK; | |
117 | /* | |
118 | Debounce Debounce Timer Max | |
119 | TmrLarge TmrOutUnit Unit Debounce | |
120 | Time | |
121 | 0 0 61 usec (2 RtcClk) 976 usec | |
122 | 0 1 244 usec (8 RtcClk) 3.9 msec | |
123 | 1 0 15.6 msec (512 RtcClk) 250 msec | |
124 | 1 1 62.5 msec (2048 RtcClk) 1 sec | |
125 | */ | |
126 | ||
127 | if (debounce < 61) { | |
128 | pin_reg |= 1; | |
129 | pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); | |
130 | pin_reg &= ~BIT(DB_TMR_LARGE_OFF); | |
131 | } else if (debounce < 976) { | |
132 | time = debounce / 61; | |
133 | pin_reg |= time & DB_TMR_OUT_MASK; | |
134 | pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); | |
135 | pin_reg &= ~BIT(DB_TMR_LARGE_OFF); | |
136 | } else if (debounce < 3900) { | |
137 | time = debounce / 244; | |
138 | pin_reg |= time & DB_TMR_OUT_MASK; | |
139 | pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); | |
140 | pin_reg &= ~BIT(DB_TMR_LARGE_OFF); | |
141 | } else if (debounce < 250000) { | |
142 | time = debounce / 15600; | |
143 | pin_reg |= time & DB_TMR_OUT_MASK; | |
144 | pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); | |
145 | pin_reg |= BIT(DB_TMR_LARGE_OFF); | |
146 | } else if (debounce < 1000000) { | |
147 | time = debounce / 62500; | |
148 | pin_reg |= time & DB_TMR_OUT_MASK; | |
149 | pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); | |
150 | pin_reg |= BIT(DB_TMR_LARGE_OFF); | |
151 | } else { | |
152 | pin_reg &= ~DB_CNTRl_MASK; | |
25a853d0 | 153 | ret = -EINVAL; |
dbad75dd KX |
154 | } |
155 | } else { | |
156 | pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); | |
157 | pin_reg &= ~BIT(DB_TMR_LARGE_OFF); | |
158 | pin_reg &= ~DB_TMR_OUT_MASK; | |
159 | pin_reg &= ~DB_CNTRl_MASK; | |
160 | } | |
161 | writel(pin_reg, gpio_dev->base + offset * 4); | |
229710fe | 162 | raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); |
dbad75dd | 163 | |
25a853d0 | 164 | return ret; |
dbad75dd KX |
165 | } |
166 | ||
2956b5d9 MW |
167 | static int amd_gpio_set_config(struct gpio_chip *gc, unsigned offset, |
168 | unsigned long config) | |
169 | { | |
170 | u32 debounce; | |
171 | ||
172 | if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE) | |
173 | return -ENOTSUPP; | |
174 | ||
175 | debounce = pinconf_to_config_argument(config); | |
176 | return amd_gpio_set_debounce(gc, offset, debounce); | |
177 | } | |
178 | ||
dbad75dd KX |
179 | #ifdef CONFIG_DEBUG_FS |
180 | static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc) | |
181 | { | |
182 | u32 pin_reg; | |
183 | unsigned long flags; | |
184 | unsigned int bank, i, pin_num; | |
04d36723 | 185 | struct amd_gpio *gpio_dev = gpiochip_get_data(gc); |
dbad75dd KX |
186 | |
187 | char *level_trig; | |
188 | char *active_level; | |
189 | char *interrupt_enable; | |
190 | char *interrupt_mask; | |
191 | char *wake_cntrl0; | |
192 | char *wake_cntrl1; | |
193 | char *wake_cntrl2; | |
194 | char *pin_sts; | |
195 | char *pull_up_sel; | |
196 | char *pull_up_enable; | |
197 | char *pull_down_enable; | |
198 | char *output_value; | |
199 | char *output_enable; | |
200 | ||
3bfd4430 | 201 | for (bank = 0; bank < gpio_dev->hwbank_num; bank++) { |
dbad75dd KX |
202 | seq_printf(s, "GPIO bank%d\t", bank); |
203 | ||
204 | switch (bank) { | |
205 | case 0: | |
206 | i = 0; | |
207 | pin_num = AMD_GPIO_PINS_BANK0; | |
208 | break; | |
209 | case 1: | |
210 | i = 64; | |
211 | pin_num = AMD_GPIO_PINS_BANK1 + i; | |
212 | break; | |
213 | case 2: | |
214 | i = 128; | |
215 | pin_num = AMD_GPIO_PINS_BANK2 + i; | |
216 | break; | |
3bfd4430 SN |
217 | case 3: |
218 | i = 192; | |
219 | pin_num = AMD_GPIO_PINS_BANK3 + i; | |
220 | break; | |
6ac4c1ad LW |
221 | default: |
222 | /* Illegal bank number, ignore */ | |
223 | continue; | |
dbad75dd | 224 | } |
dbad75dd KX |
225 | for (; i < pin_num; i++) { |
226 | seq_printf(s, "pin%d\t", i); | |
229710fe | 227 | raw_spin_lock_irqsave(&gpio_dev->lock, flags); |
dbad75dd | 228 | pin_reg = readl(gpio_dev->base + i * 4); |
229710fe | 229 | raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); |
dbad75dd KX |
230 | |
231 | if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) { | |
232 | interrupt_enable = "interrupt is enabled|"; | |
233 | ||
3775dac1 DC |
234 | if (!(pin_reg & BIT(ACTIVE_LEVEL_OFF)) && |
235 | !(pin_reg & BIT(ACTIVE_LEVEL_OFF + 1))) | |
dbad75dd | 236 | active_level = "Active low|"; |
3775dac1 DC |
237 | else if (pin_reg & BIT(ACTIVE_LEVEL_OFF) && |
238 | !(pin_reg & BIT(ACTIVE_LEVEL_OFF + 1))) | |
dbad75dd | 239 | active_level = "Active high|"; |
3775dac1 DC |
240 | else if (!(pin_reg & BIT(ACTIVE_LEVEL_OFF)) && |
241 | pin_reg & BIT(ACTIVE_LEVEL_OFF + 1)) | |
dbad75dd KX |
242 | active_level = "Active on both|"; |
243 | else | |
0a95160e | 244 | active_level = "Unknown Active level|"; |
dbad75dd KX |
245 | |
246 | if (pin_reg & BIT(LEVEL_TRIG_OFF)) | |
247 | level_trig = "Level trigger|"; | |
248 | else | |
249 | level_trig = "Edge trigger|"; | |
250 | ||
251 | } else { | |
252 | interrupt_enable = | |
253 | "interrupt is disabled|"; | |
254 | active_level = " "; | |
255 | level_trig = " "; | |
256 | } | |
257 | ||
258 | if (pin_reg & BIT(INTERRUPT_MASK_OFF)) | |
259 | interrupt_mask = | |
260 | "interrupt is unmasked|"; | |
261 | else | |
262 | interrupt_mask = | |
263 | "interrupt is masked|"; | |
264 | ||
3bfd4430 | 265 | if (pin_reg & BIT(WAKE_CNTRL_OFF_S0I3)) |
dbad75dd KX |
266 | wake_cntrl0 = "enable wakeup in S0i3 state|"; |
267 | else | |
268 | wake_cntrl0 = "disable wakeup in S0i3 state|"; | |
269 | ||
3bfd4430 | 270 | if (pin_reg & BIT(WAKE_CNTRL_OFF_S3)) |
dbad75dd KX |
271 | wake_cntrl1 = "enable wakeup in S3 state|"; |
272 | else | |
273 | wake_cntrl1 = "disable wakeup in S3 state|"; | |
274 | ||
3bfd4430 | 275 | if (pin_reg & BIT(WAKE_CNTRL_OFF_S4)) |
dbad75dd KX |
276 | wake_cntrl2 = "enable wakeup in S4/S5 state|"; |
277 | else | |
278 | wake_cntrl2 = "disable wakeup in S4/S5 state|"; | |
279 | ||
280 | if (pin_reg & BIT(PULL_UP_ENABLE_OFF)) { | |
281 | pull_up_enable = "pull-up is enabled|"; | |
282 | if (pin_reg & BIT(PULL_UP_SEL_OFF)) | |
283 | pull_up_sel = "8k pull-up|"; | |
284 | else | |
285 | pull_up_sel = "4k pull-up|"; | |
286 | } else { | |
287 | pull_up_enable = "pull-up is disabled|"; | |
288 | pull_up_sel = " "; | |
289 | } | |
290 | ||
291 | if (pin_reg & BIT(PULL_DOWN_ENABLE_OFF)) | |
292 | pull_down_enable = "pull-down is enabled|"; | |
293 | else | |
294 | pull_down_enable = "Pull-down is disabled|"; | |
295 | ||
296 | if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) { | |
297 | pin_sts = " "; | |
298 | output_enable = "output is enabled|"; | |
299 | if (pin_reg & BIT(OUTPUT_VALUE_OFF)) | |
300 | output_value = "output is high|"; | |
301 | else | |
302 | output_value = "output is low|"; | |
303 | } else { | |
304 | output_enable = "output is disabled|"; | |
305 | output_value = " "; | |
306 | ||
307 | if (pin_reg & BIT(PIN_STS_OFF)) | |
308 | pin_sts = "input is high|"; | |
309 | else | |
310 | pin_sts = "input is low|"; | |
311 | } | |
312 | ||
313 | seq_printf(s, "%s %s %s %s %s %s\n" | |
314 | " %s %s %s %s %s %s %s 0x%x\n", | |
315 | level_trig, active_level, interrupt_enable, | |
316 | interrupt_mask, wake_cntrl0, wake_cntrl1, | |
317 | wake_cntrl2, pin_sts, pull_up_sel, | |
318 | pull_up_enable, pull_down_enable, | |
319 | output_value, output_enable, pin_reg); | |
320 | } | |
321 | } | |
322 | } | |
323 | #else | |
324 | #define amd_gpio_dbg_show NULL | |
325 | #endif | |
326 | ||
327 | static void amd_gpio_irq_enable(struct irq_data *d) | |
328 | { | |
329 | u32 pin_reg; | |
330 | unsigned long flags; | |
331 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); | |
04d36723 | 332 | struct amd_gpio *gpio_dev = gpiochip_get_data(gc); |
dbad75dd | 333 | |
229710fe | 334 | raw_spin_lock_irqsave(&gpio_dev->lock, flags); |
dbad75dd | 335 | pin_reg = readl(gpio_dev->base + (d->hwirq)*4); |
dbad75dd KX |
336 | pin_reg |= BIT(INTERRUPT_ENABLE_OFF); |
337 | pin_reg |= BIT(INTERRUPT_MASK_OFF); | |
338 | writel(pin_reg, gpio_dev->base + (d->hwirq)*4); | |
229710fe | 339 | raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); |
dbad75dd KX |
340 | } |
341 | ||
342 | static void amd_gpio_irq_disable(struct irq_data *d) | |
343 | { | |
344 | u32 pin_reg; | |
345 | unsigned long flags; | |
346 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); | |
04d36723 | 347 | struct amd_gpio *gpio_dev = gpiochip_get_data(gc); |
dbad75dd | 348 | |
229710fe | 349 | raw_spin_lock_irqsave(&gpio_dev->lock, flags); |
dbad75dd KX |
350 | pin_reg = readl(gpio_dev->base + (d->hwirq)*4); |
351 | pin_reg &= ~BIT(INTERRUPT_ENABLE_OFF); | |
352 | pin_reg &= ~BIT(INTERRUPT_MASK_OFF); | |
353 | writel(pin_reg, gpio_dev->base + (d->hwirq)*4); | |
229710fe | 354 | raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); |
dbad75dd KX |
355 | } |
356 | ||
357 | static void amd_gpio_irq_mask(struct irq_data *d) | |
358 | { | |
359 | u32 pin_reg; | |
360 | unsigned long flags; | |
361 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); | |
04d36723 | 362 | struct amd_gpio *gpio_dev = gpiochip_get_data(gc); |
dbad75dd | 363 | |
229710fe | 364 | raw_spin_lock_irqsave(&gpio_dev->lock, flags); |
dbad75dd KX |
365 | pin_reg = readl(gpio_dev->base + (d->hwirq)*4); |
366 | pin_reg &= ~BIT(INTERRUPT_MASK_OFF); | |
367 | writel(pin_reg, gpio_dev->base + (d->hwirq)*4); | |
229710fe | 368 | raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); |
dbad75dd KX |
369 | } |
370 | ||
371 | static void amd_gpio_irq_unmask(struct irq_data *d) | |
372 | { | |
373 | u32 pin_reg; | |
374 | unsigned long flags; | |
375 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); | |
04d36723 | 376 | struct amd_gpio *gpio_dev = gpiochip_get_data(gc); |
dbad75dd | 377 | |
229710fe | 378 | raw_spin_lock_irqsave(&gpio_dev->lock, flags); |
dbad75dd KX |
379 | pin_reg = readl(gpio_dev->base + (d->hwirq)*4); |
380 | pin_reg |= BIT(INTERRUPT_MASK_OFF); | |
381 | writel(pin_reg, gpio_dev->base + (d->hwirq)*4); | |
229710fe | 382 | raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); |
dbad75dd KX |
383 | } |
384 | ||
385 | static void amd_gpio_irq_eoi(struct irq_data *d) | |
386 | { | |
387 | u32 reg; | |
388 | unsigned long flags; | |
389 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); | |
04d36723 | 390 | struct amd_gpio *gpio_dev = gpiochip_get_data(gc); |
dbad75dd | 391 | |
229710fe | 392 | raw_spin_lock_irqsave(&gpio_dev->lock, flags); |
dbad75dd KX |
393 | reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG); |
394 | reg |= EOI_MASK; | |
395 | writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG); | |
229710fe | 396 | raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); |
dbad75dd KX |
397 | } |
398 | ||
399 | static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type) | |
400 | { | |
401 | int ret = 0; | |
402 | u32 pin_reg; | |
2983f296 | 403 | unsigned long flags, irq_flags; |
dbad75dd | 404 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
04d36723 | 405 | struct amd_gpio *gpio_dev = gpiochip_get_data(gc); |
dbad75dd | 406 | |
229710fe | 407 | raw_spin_lock_irqsave(&gpio_dev->lock, flags); |
dbad75dd KX |
408 | pin_reg = readl(gpio_dev->base + (d->hwirq)*4); |
409 | ||
2983f296 SS |
410 | /* Ignore the settings coming from the client and |
411 | * read the values from the ACPI tables | |
412 | * while setting the trigger type | |
499c7196 | 413 | */ |
499c7196 | 414 | |
2983f296 SS |
415 | irq_flags = irq_get_trigger_type(d->irq); |
416 | if (irq_flags != IRQ_TYPE_NONE) | |
417 | type = irq_flags; | |
499c7196 | 418 | |
dbad75dd KX |
419 | switch (type & IRQ_TYPE_SENSE_MASK) { |
420 | case IRQ_TYPE_EDGE_RISING: | |
421 | pin_reg &= ~BIT(LEVEL_TRIG_OFF); | |
422 | pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); | |
423 | pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF; | |
424 | pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; | |
9d829314 | 425 | irq_set_handler_locked(d, handle_edge_irq); |
dbad75dd KX |
426 | break; |
427 | ||
428 | case IRQ_TYPE_EDGE_FALLING: | |
429 | pin_reg &= ~BIT(LEVEL_TRIG_OFF); | |
430 | pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); | |
431 | pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF; | |
432 | pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; | |
9d829314 | 433 | irq_set_handler_locked(d, handle_edge_irq); |
dbad75dd KX |
434 | break; |
435 | ||
436 | case IRQ_TYPE_EDGE_BOTH: | |
437 | pin_reg &= ~BIT(LEVEL_TRIG_OFF); | |
438 | pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); | |
439 | pin_reg |= BOTH_EADGE << ACTIVE_LEVEL_OFF; | |
440 | pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; | |
9d829314 | 441 | irq_set_handler_locked(d, handle_edge_irq); |
dbad75dd KX |
442 | break; |
443 | ||
444 | case IRQ_TYPE_LEVEL_HIGH: | |
445 | pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF; | |
446 | pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); | |
447 | pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF; | |
448 | pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); | |
449 | pin_reg |= DB_TYPE_PRESERVE_LOW_GLITCH << DB_CNTRL_OFF; | |
9d829314 | 450 | irq_set_handler_locked(d, handle_level_irq); |
dbad75dd KX |
451 | break; |
452 | ||
453 | case IRQ_TYPE_LEVEL_LOW: | |
454 | pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF; | |
455 | pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); | |
456 | pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF; | |
457 | pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); | |
458 | pin_reg |= DB_TYPE_PRESERVE_HIGH_GLITCH << DB_CNTRL_OFF; | |
9d829314 | 459 | irq_set_handler_locked(d, handle_level_irq); |
dbad75dd KX |
460 | break; |
461 | ||
462 | case IRQ_TYPE_NONE: | |
463 | break; | |
464 | ||
465 | default: | |
466 | dev_err(&gpio_dev->pdev->dev, "Invalid type value\n"); | |
467 | ret = -EINVAL; | |
dbad75dd KX |
468 | } |
469 | ||
470 | pin_reg |= CLR_INTR_STAT << INTERRUPT_STS_OFF; | |
471 | writel(pin_reg, gpio_dev->base + (d->hwirq)*4); | |
229710fe | 472 | raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); |
dbad75dd | 473 | |
dbad75dd KX |
474 | return ret; |
475 | } | |
476 | ||
477 | static void amd_irq_ack(struct irq_data *d) | |
478 | { | |
479 | /* | |
480 | * based on HW design,there is no need to ack HW | |
481 | * before handle current irq. But this routine is | |
482 | * necessary for handle_edge_irq | |
483 | */ | |
484 | } | |
485 | ||
486 | static struct irq_chip amd_gpio_irqchip = { | |
487 | .name = "amd_gpio", | |
488 | .irq_ack = amd_irq_ack, | |
489 | .irq_enable = amd_gpio_irq_enable, | |
490 | .irq_disable = amd_gpio_irq_disable, | |
491 | .irq_mask = amd_gpio_irq_mask, | |
492 | .irq_unmask = amd_gpio_irq_unmask, | |
493 | .irq_eoi = amd_gpio_irq_eoi, | |
494 | .irq_set_type = amd_gpio_irq_set_type, | |
3bfd4430 | 495 | .flags = IRQCHIP_SKIP_SET_WAKE, |
dbad75dd KX |
496 | }; |
497 | ||
bd0b9ac4 | 498 | static void amd_gpio_irq_handler(struct irq_desc *desc) |
dbad75dd KX |
499 | { |
500 | u32 i; | |
501 | u32 off; | |
502 | u32 reg; | |
503 | u32 pin_reg; | |
504 | u64 reg64; | |
505 | int handled = 0; | |
bd0b9ac4 | 506 | unsigned int irq; |
dbad75dd | 507 | unsigned long flags; |
5663bb27 | 508 | struct irq_chip *chip = irq_desc_get_chip(desc); |
dbad75dd | 509 | struct gpio_chip *gc = irq_desc_get_handler_data(desc); |
04d36723 | 510 | struct amd_gpio *gpio_dev = gpiochip_get_data(gc); |
dbad75dd KX |
511 | |
512 | chained_irq_enter(chip, desc); | |
513 | /*enable GPIO interrupt again*/ | |
229710fe | 514 | raw_spin_lock_irqsave(&gpio_dev->lock, flags); |
dbad75dd KX |
515 | reg = readl(gpio_dev->base + WAKE_INT_STATUS_REG1); |
516 | reg64 = reg; | |
517 | reg64 = reg64 << 32; | |
518 | ||
519 | reg = readl(gpio_dev->base + WAKE_INT_STATUS_REG0); | |
520 | reg64 |= reg; | |
229710fe | 521 | raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); |
dbad75dd KX |
522 | |
523 | /* | |
524 | * first 46 bits indicates interrupt status. | |
525 | * one bit represents four interrupt sources. | |
526 | */ | |
527 | for (off = 0; off < 46 ; off++) { | |
528 | if (reg64 & BIT(off)) { | |
529 | for (i = 0; i < 4; i++) { | |
530 | pin_reg = readl(gpio_dev->base + | |
531 | (off * 4 + i) * 4); | |
532 | if ((pin_reg & BIT(INTERRUPT_STS_OFF)) || | |
533 | (pin_reg & BIT(WAKE_STS_OFF))) { | |
534 | irq = irq_find_mapping(gc->irqdomain, | |
535 | off * 4 + i); | |
536 | generic_handle_irq(irq); | |
537 | writel(pin_reg, | |
538 | gpio_dev->base | |
539 | + (off * 4 + i) * 4); | |
540 | handled++; | |
541 | } | |
542 | } | |
543 | } | |
544 | } | |
545 | ||
546 | if (handled == 0) | |
bd0b9ac4 | 547 | handle_bad_irq(desc); |
dbad75dd | 548 | |
229710fe | 549 | raw_spin_lock_irqsave(&gpio_dev->lock, flags); |
dbad75dd KX |
550 | reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG); |
551 | reg |= EOI_MASK; | |
552 | writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG); | |
229710fe | 553 | raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); |
dbad75dd KX |
554 | |
555 | chained_irq_exit(chip, desc); | |
556 | } | |
557 | ||
558 | static int amd_get_groups_count(struct pinctrl_dev *pctldev) | |
559 | { | |
560 | struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); | |
561 | ||
562 | return gpio_dev->ngroups; | |
563 | } | |
564 | ||
565 | static const char *amd_get_group_name(struct pinctrl_dev *pctldev, | |
566 | unsigned group) | |
567 | { | |
568 | struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); | |
569 | ||
570 | return gpio_dev->groups[group].name; | |
571 | } | |
572 | ||
573 | static int amd_get_group_pins(struct pinctrl_dev *pctldev, | |
574 | unsigned group, | |
575 | const unsigned **pins, | |
576 | unsigned *num_pins) | |
577 | { | |
578 | struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); | |
579 | ||
580 | *pins = gpio_dev->groups[group].pins; | |
581 | *num_pins = gpio_dev->groups[group].npins; | |
582 | return 0; | |
583 | } | |
584 | ||
585 | static const struct pinctrl_ops amd_pinctrl_ops = { | |
586 | .get_groups_count = amd_get_groups_count, | |
587 | .get_group_name = amd_get_group_name, | |
588 | .get_group_pins = amd_get_group_pins, | |
589 | #ifdef CONFIG_OF | |
590 | .dt_node_to_map = pinconf_generic_dt_node_to_map_group, | |
d32f7fd3 | 591 | .dt_free_map = pinctrl_utils_free_map, |
dbad75dd KX |
592 | #endif |
593 | }; | |
594 | ||
595 | static int amd_pinconf_get(struct pinctrl_dev *pctldev, | |
596 | unsigned int pin, | |
597 | unsigned long *config) | |
598 | { | |
599 | u32 pin_reg; | |
600 | unsigned arg; | |
601 | unsigned long flags; | |
602 | struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); | |
603 | enum pin_config_param param = pinconf_to_config_param(*config); | |
604 | ||
229710fe | 605 | raw_spin_lock_irqsave(&gpio_dev->lock, flags); |
dbad75dd | 606 | pin_reg = readl(gpio_dev->base + pin*4); |
229710fe | 607 | raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); |
dbad75dd KX |
608 | switch (param) { |
609 | case PIN_CONFIG_INPUT_DEBOUNCE: | |
610 | arg = pin_reg & DB_TMR_OUT_MASK; | |
611 | break; | |
612 | ||
613 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
614 | arg = (pin_reg >> PULL_DOWN_ENABLE_OFF) & BIT(0); | |
615 | break; | |
616 | ||
617 | case PIN_CONFIG_BIAS_PULL_UP: | |
618 | arg = (pin_reg >> PULL_UP_SEL_OFF) & (BIT(0) | BIT(1)); | |
619 | break; | |
620 | ||
621 | case PIN_CONFIG_DRIVE_STRENGTH: | |
622 | arg = (pin_reg >> DRV_STRENGTH_SEL_OFF) & DRV_STRENGTH_SEL_MASK; | |
623 | break; | |
624 | ||
625 | default: | |
626 | dev_err(&gpio_dev->pdev->dev, "Invalid config param %04x\n", | |
627 | param); | |
628 | return -ENOTSUPP; | |
629 | } | |
630 | ||
631 | *config = pinconf_to_config_packed(param, arg); | |
632 | ||
633 | return 0; | |
634 | } | |
635 | ||
636 | static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, | |
637 | unsigned long *configs, unsigned num_configs) | |
638 | { | |
639 | int i; | |
dbad75dd | 640 | u32 arg; |
25a853d0 KX |
641 | int ret = 0; |
642 | u32 pin_reg; | |
dbad75dd KX |
643 | unsigned long flags; |
644 | enum pin_config_param param; | |
645 | struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); | |
646 | ||
229710fe | 647 | raw_spin_lock_irqsave(&gpio_dev->lock, flags); |
dbad75dd KX |
648 | for (i = 0; i < num_configs; i++) { |
649 | param = pinconf_to_config_param(configs[i]); | |
650 | arg = pinconf_to_config_argument(configs[i]); | |
651 | pin_reg = readl(gpio_dev->base + pin*4); | |
652 | ||
653 | switch (param) { | |
654 | case PIN_CONFIG_INPUT_DEBOUNCE: | |
655 | pin_reg &= ~DB_TMR_OUT_MASK; | |
656 | pin_reg |= arg & DB_TMR_OUT_MASK; | |
657 | break; | |
658 | ||
659 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
660 | pin_reg &= ~BIT(PULL_DOWN_ENABLE_OFF); | |
661 | pin_reg |= (arg & BIT(0)) << PULL_DOWN_ENABLE_OFF; | |
662 | break; | |
663 | ||
664 | case PIN_CONFIG_BIAS_PULL_UP: | |
665 | pin_reg &= ~BIT(PULL_UP_SEL_OFF); | |
666 | pin_reg |= (arg & BIT(0)) << PULL_UP_SEL_OFF; | |
667 | pin_reg &= ~BIT(PULL_UP_ENABLE_OFF); | |
668 | pin_reg |= ((arg>>1) & BIT(0)) << PULL_UP_ENABLE_OFF; | |
669 | break; | |
670 | ||
671 | case PIN_CONFIG_DRIVE_STRENGTH: | |
672 | pin_reg &= ~(DRV_STRENGTH_SEL_MASK | |
673 | << DRV_STRENGTH_SEL_OFF); | |
674 | pin_reg |= (arg & DRV_STRENGTH_SEL_MASK) | |
675 | << DRV_STRENGTH_SEL_OFF; | |
676 | break; | |
677 | ||
678 | default: | |
679 | dev_err(&gpio_dev->pdev->dev, | |
680 | "Invalid config param %04x\n", param); | |
25a853d0 | 681 | ret = -ENOTSUPP; |
dbad75dd KX |
682 | } |
683 | ||
684 | writel(pin_reg, gpio_dev->base + pin*4); | |
685 | } | |
229710fe | 686 | raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); |
dbad75dd | 687 | |
25a853d0 | 688 | return ret; |
dbad75dd KX |
689 | } |
690 | ||
691 | static int amd_pinconf_group_get(struct pinctrl_dev *pctldev, | |
692 | unsigned int group, | |
693 | unsigned long *config) | |
694 | { | |
695 | const unsigned *pins; | |
696 | unsigned npins; | |
697 | int ret; | |
698 | ||
699 | ret = amd_get_group_pins(pctldev, group, &pins, &npins); | |
700 | if (ret) | |
701 | return ret; | |
702 | ||
703 | if (amd_pinconf_get(pctldev, pins[0], config)) | |
704 | return -ENOTSUPP; | |
705 | ||
706 | return 0; | |
707 | } | |
708 | ||
709 | static int amd_pinconf_group_set(struct pinctrl_dev *pctldev, | |
710 | unsigned group, unsigned long *configs, | |
711 | unsigned num_configs) | |
712 | { | |
713 | const unsigned *pins; | |
714 | unsigned npins; | |
715 | int i, ret; | |
716 | ||
717 | ret = amd_get_group_pins(pctldev, group, &pins, &npins); | |
718 | if (ret) | |
719 | return ret; | |
720 | for (i = 0; i < npins; i++) { | |
721 | if (amd_pinconf_set(pctldev, pins[i], configs, num_configs)) | |
722 | return -ENOTSUPP; | |
723 | } | |
724 | return 0; | |
725 | } | |
726 | ||
727 | static const struct pinconf_ops amd_pinconf_ops = { | |
728 | .pin_config_get = amd_pinconf_get, | |
729 | .pin_config_set = amd_pinconf_set, | |
730 | .pin_config_group_get = amd_pinconf_group_get, | |
731 | .pin_config_group_set = amd_pinconf_group_set, | |
732 | }; | |
733 | ||
734 | static struct pinctrl_desc amd_pinctrl_desc = { | |
735 | .pins = kerncz_pins, | |
736 | .npins = ARRAY_SIZE(kerncz_pins), | |
737 | .pctlops = &amd_pinctrl_ops, | |
738 | .confops = &amd_pinconf_ops, | |
739 | .owner = THIS_MODULE, | |
740 | }; | |
741 | ||
742 | static int amd_gpio_probe(struct platform_device *pdev) | |
743 | { | |
744 | int ret = 0; | |
25a853d0 | 745 | int irq_base; |
dbad75dd KX |
746 | struct resource *res; |
747 | struct amd_gpio *gpio_dev; | |
748 | ||
749 | gpio_dev = devm_kzalloc(&pdev->dev, | |
750 | sizeof(struct amd_gpio), GFP_KERNEL); | |
751 | if (!gpio_dev) | |
752 | return -ENOMEM; | |
753 | ||
229710fe | 754 | raw_spin_lock_init(&gpio_dev->lock); |
dbad75dd KX |
755 | |
756 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
757 | if (!res) { | |
758 | dev_err(&pdev->dev, "Failed to get gpio io resource.\n"); | |
759 | return -EINVAL; | |
760 | } | |
761 | ||
762 | gpio_dev->base = devm_ioremap_nocache(&pdev->dev, res->start, | |
763 | resource_size(res)); | |
424a6c60 WY |
764 | if (!gpio_dev->base) |
765 | return -ENOMEM; | |
dbad75dd KX |
766 | |
767 | irq_base = platform_get_irq(pdev, 0); | |
768 | if (irq_base < 0) { | |
769 | dev_err(&pdev->dev, "Failed to get gpio IRQ.\n"); | |
770 | return -EINVAL; | |
771 | } | |
772 | ||
773 | gpio_dev->pdev = pdev; | |
774 | gpio_dev->gc.direction_input = amd_gpio_direction_input; | |
775 | gpio_dev->gc.direction_output = amd_gpio_direction_output; | |
776 | gpio_dev->gc.get = amd_gpio_get_value; | |
777 | gpio_dev->gc.set = amd_gpio_set_value; | |
2956b5d9 | 778 | gpio_dev->gc.set_config = amd_gpio_set_config; |
dbad75dd KX |
779 | gpio_dev->gc.dbg_show = amd_gpio_dbg_show; |
780 | ||
3bfd4430 | 781 | gpio_dev->gc.base = -1; |
dbad75dd KX |
782 | gpio_dev->gc.label = pdev->name; |
783 | gpio_dev->gc.owner = THIS_MODULE; | |
58383c78 | 784 | gpio_dev->gc.parent = &pdev->dev; |
3bfd4430 | 785 | gpio_dev->gc.ngpio = resource_size(res) / 4; |
dbad75dd KX |
786 | #if defined(CONFIG_OF_GPIO) |
787 | gpio_dev->gc.of_node = pdev->dev.of_node; | |
788 | #endif | |
789 | ||
3bfd4430 | 790 | gpio_dev->hwbank_num = gpio_dev->gc.ngpio / 64; |
dbad75dd KX |
791 | gpio_dev->groups = kerncz_groups; |
792 | gpio_dev->ngroups = ARRAY_SIZE(kerncz_groups); | |
793 | ||
794 | amd_pinctrl_desc.name = dev_name(&pdev->dev); | |
251e22ab LD |
795 | gpio_dev->pctrl = devm_pinctrl_register(&pdev->dev, &amd_pinctrl_desc, |
796 | gpio_dev); | |
323de9ef | 797 | if (IS_ERR(gpio_dev->pctrl)) { |
dbad75dd | 798 | dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); |
323de9ef | 799 | return PTR_ERR(gpio_dev->pctrl); |
dbad75dd KX |
800 | } |
801 | ||
04d36723 | 802 | ret = gpiochip_add_data(&gpio_dev->gc, gpio_dev); |
dbad75dd | 803 | if (ret) |
251e22ab | 804 | return ret; |
dbad75dd KX |
805 | |
806 | ret = gpiochip_add_pin_range(&gpio_dev->gc, dev_name(&pdev->dev), | |
3bfd4430 | 807 | 0, 0, gpio_dev->gc.ngpio); |
dbad75dd KX |
808 | if (ret) { |
809 | dev_err(&pdev->dev, "Failed to add pin range\n"); | |
810 | goto out2; | |
811 | } | |
812 | ||
813 | ret = gpiochip_irqchip_add(&gpio_dev->gc, | |
814 | &amd_gpio_irqchip, | |
815 | 0, | |
816 | handle_simple_irq, | |
817 | IRQ_TYPE_NONE); | |
818 | if (ret) { | |
819 | dev_err(&pdev->dev, "could not add irqchip\n"); | |
820 | ret = -ENODEV; | |
821 | goto out2; | |
822 | } | |
823 | ||
824 | gpiochip_set_chained_irqchip(&gpio_dev->gc, | |
825 | &amd_gpio_irqchip, | |
826 | irq_base, | |
827 | amd_gpio_irq_handler); | |
dbad75dd KX |
828 | platform_set_drvdata(pdev, gpio_dev); |
829 | ||
830 | dev_dbg(&pdev->dev, "amd gpio driver loaded\n"); | |
831 | return ret; | |
832 | ||
833 | out2: | |
834 | gpiochip_remove(&gpio_dev->gc); | |
835 | ||
dbad75dd KX |
836 | return ret; |
837 | } | |
838 | ||
839 | static int amd_gpio_remove(struct platform_device *pdev) | |
840 | { | |
841 | struct amd_gpio *gpio_dev; | |
842 | ||
843 | gpio_dev = platform_get_drvdata(pdev); | |
844 | ||
845 | gpiochip_remove(&gpio_dev->gc); | |
dbad75dd KX |
846 | |
847 | return 0; | |
848 | } | |
849 | ||
850 | static const struct acpi_device_id amd_gpio_acpi_match[] = { | |
851 | { "AMD0030", 0 }, | |
42a44402 | 852 | { "AMDI0030", 0}, |
dbad75dd KX |
853 | { }, |
854 | }; | |
855 | MODULE_DEVICE_TABLE(acpi, amd_gpio_acpi_match); | |
856 | ||
857 | static struct platform_driver amd_gpio_driver = { | |
858 | .driver = { | |
859 | .name = "amd_gpio", | |
dbad75dd KX |
860 | .acpi_match_table = ACPI_PTR(amd_gpio_acpi_match), |
861 | }, | |
862 | .probe = amd_gpio_probe, | |
863 | .remove = amd_gpio_remove, | |
864 | }; | |
865 | ||
866 | module_platform_driver(amd_gpio_driver); | |
867 | ||
868 | MODULE_LICENSE("GPL v2"); | |
869 | MODULE_AUTHOR("Ken Xue <Ken.Xue@amd.com>, Jeff Wu <Jeff.Wu@amd.com>"); | |
870 | MODULE_DESCRIPTION("AMD GPIO pinctrl driver"); |