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75a6faf6 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
dbad75dd KX |
2 | /* |
3 | * GPIO driver for AMD | |
4 | * | |
5 | * Copyright (c) 2014,2015 AMD Corporation. | |
6 | * Authors: Ken Xue <Ken.Xue@amd.com> | |
7 | * Wu, Jeff <Jeff.Wu@amd.com> | |
8 | * | |
add7bfce SS |
9 | * Contact Information: Nehal Shah <Nehal-bakulchandra.Shah@amd.com> |
10 | * Shyam Sundar S K <Shyam-sundar.S-k@amd.com> | |
dbad75dd KX |
11 | */ |
12 | ||
13 | #include <linux/err.h> | |
14 | #include <linux/bug.h> | |
15 | #include <linux/kernel.h> | |
16 | #include <linux/module.h> | |
17 | #include <linux/spinlock.h> | |
18 | #include <linux/compiler.h> | |
19 | #include <linux/types.h> | |
20 | #include <linux/errno.h> | |
21 | #include <linux/log2.h> | |
22 | #include <linux/io.h> | |
1c5fb66a | 23 | #include <linux/gpio/driver.h> |
dbad75dd KX |
24 | #include <linux/slab.h> |
25 | #include <linux/platform_device.h> | |
26 | #include <linux/mutex.h> | |
27 | #include <linux/acpi.h> | |
28 | #include <linux/seq_file.h> | |
29 | #include <linux/interrupt.h> | |
30 | #include <linux/list.h> | |
31 | #include <linux/bitops.h> | |
dbad75dd KX |
32 | #include <linux/pinctrl/pinconf.h> |
33 | #include <linux/pinctrl/pinconf-generic.h> | |
34 | ||
79d2c8be | 35 | #include "core.h" |
dbad75dd KX |
36 | #include "pinctrl-utils.h" |
37 | #include "pinctrl-amd.h" | |
38 | ||
12b10f47 DK |
39 | static int amd_gpio_get_direction(struct gpio_chip *gc, unsigned offset) |
40 | { | |
41 | unsigned long flags; | |
42 | u32 pin_reg; | |
43 | struct amd_gpio *gpio_dev = gpiochip_get_data(gc); | |
44 | ||
45 | raw_spin_lock_irqsave(&gpio_dev->lock, flags); | |
46 | pin_reg = readl(gpio_dev->base + offset * 4); | |
47 | raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); | |
48 | ||
3c827873 MV |
49 | if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) |
50 | return GPIO_LINE_DIRECTION_OUT; | |
51 | ||
52 | return GPIO_LINE_DIRECTION_IN; | |
12b10f47 DK |
53 | } |
54 | ||
dbad75dd KX |
55 | static int amd_gpio_direction_input(struct gpio_chip *gc, unsigned offset) |
56 | { | |
57 | unsigned long flags; | |
58 | u32 pin_reg; | |
04d36723 | 59 | struct amd_gpio *gpio_dev = gpiochip_get_data(gc); |
dbad75dd | 60 | |
229710fe | 61 | raw_spin_lock_irqsave(&gpio_dev->lock, flags); |
dbad75dd | 62 | pin_reg = readl(gpio_dev->base + offset * 4); |
dbad75dd KX |
63 | pin_reg &= ~BIT(OUTPUT_ENABLE_OFF); |
64 | writel(pin_reg, gpio_dev->base + offset * 4); | |
229710fe | 65 | raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); |
dbad75dd KX |
66 | |
67 | return 0; | |
68 | } | |
69 | ||
70 | static int amd_gpio_direction_output(struct gpio_chip *gc, unsigned offset, | |
71 | int value) | |
72 | { | |
73 | u32 pin_reg; | |
74 | unsigned long flags; | |
04d36723 | 75 | struct amd_gpio *gpio_dev = gpiochip_get_data(gc); |
dbad75dd | 76 | |
229710fe | 77 | raw_spin_lock_irqsave(&gpio_dev->lock, flags); |
dbad75dd KX |
78 | pin_reg = readl(gpio_dev->base + offset * 4); |
79 | pin_reg |= BIT(OUTPUT_ENABLE_OFF); | |
80 | if (value) | |
81 | pin_reg |= BIT(OUTPUT_VALUE_OFF); | |
82 | else | |
83 | pin_reg &= ~BIT(OUTPUT_VALUE_OFF); | |
84 | writel(pin_reg, gpio_dev->base + offset * 4); | |
229710fe | 85 | raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); |
dbad75dd KX |
86 | |
87 | return 0; | |
88 | } | |
89 | ||
90 | static int amd_gpio_get_value(struct gpio_chip *gc, unsigned offset) | |
91 | { | |
92 | u32 pin_reg; | |
93 | unsigned long flags; | |
04d36723 | 94 | struct amd_gpio *gpio_dev = gpiochip_get_data(gc); |
dbad75dd | 95 | |
229710fe | 96 | raw_spin_lock_irqsave(&gpio_dev->lock, flags); |
dbad75dd | 97 | pin_reg = readl(gpio_dev->base + offset * 4); |
229710fe | 98 | raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); |
dbad75dd KX |
99 | |
100 | return !!(pin_reg & BIT(PIN_STS_OFF)); | |
101 | } | |
102 | ||
103 | static void amd_gpio_set_value(struct gpio_chip *gc, unsigned offset, int value) | |
104 | { | |
105 | u32 pin_reg; | |
106 | unsigned long flags; | |
04d36723 | 107 | struct amd_gpio *gpio_dev = gpiochip_get_data(gc); |
dbad75dd | 108 | |
229710fe | 109 | raw_spin_lock_irqsave(&gpio_dev->lock, flags); |
dbad75dd KX |
110 | pin_reg = readl(gpio_dev->base + offset * 4); |
111 | if (value) | |
112 | pin_reg |= BIT(OUTPUT_VALUE_OFF); | |
113 | else | |
114 | pin_reg &= ~BIT(OUTPUT_VALUE_OFF); | |
115 | writel(pin_reg, gpio_dev->base + offset * 4); | |
229710fe | 116 | raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); |
dbad75dd KX |
117 | } |
118 | ||
119 | static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset, | |
120 | unsigned debounce) | |
121 | { | |
dbad75dd | 122 | u32 time; |
25a853d0 KX |
123 | u32 pin_reg; |
124 | int ret = 0; | |
dbad75dd | 125 | unsigned long flags; |
04d36723 | 126 | struct amd_gpio *gpio_dev = gpiochip_get_data(gc); |
dbad75dd | 127 | |
229710fe | 128 | raw_spin_lock_irqsave(&gpio_dev->lock, flags); |
dbad75dd KX |
129 | pin_reg = readl(gpio_dev->base + offset * 4); |
130 | ||
131 | if (debounce) { | |
132 | pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; | |
133 | pin_reg &= ~DB_TMR_OUT_MASK; | |
134 | /* | |
135 | Debounce Debounce Timer Max | |
136 | TmrLarge TmrOutUnit Unit Debounce | |
137 | Time | |
138 | 0 0 61 usec (2 RtcClk) 976 usec | |
139 | 0 1 244 usec (8 RtcClk) 3.9 msec | |
140 | 1 0 15.6 msec (512 RtcClk) 250 msec | |
141 | 1 1 62.5 msec (2048 RtcClk) 1 sec | |
142 | */ | |
143 | ||
144 | if (debounce < 61) { | |
145 | pin_reg |= 1; | |
146 | pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); | |
147 | pin_reg &= ~BIT(DB_TMR_LARGE_OFF); | |
148 | } else if (debounce < 976) { | |
149 | time = debounce / 61; | |
150 | pin_reg |= time & DB_TMR_OUT_MASK; | |
151 | pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); | |
152 | pin_reg &= ~BIT(DB_TMR_LARGE_OFF); | |
153 | } else if (debounce < 3900) { | |
154 | time = debounce / 244; | |
155 | pin_reg |= time & DB_TMR_OUT_MASK; | |
156 | pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); | |
157 | pin_reg &= ~BIT(DB_TMR_LARGE_OFF); | |
158 | } else if (debounce < 250000) { | |
c64a6a0d | 159 | time = debounce / 15625; |
dbad75dd KX |
160 | pin_reg |= time & DB_TMR_OUT_MASK; |
161 | pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); | |
162 | pin_reg |= BIT(DB_TMR_LARGE_OFF); | |
163 | } else if (debounce < 1000000) { | |
164 | time = debounce / 62500; | |
165 | pin_reg |= time & DB_TMR_OUT_MASK; | |
166 | pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); | |
167 | pin_reg |= BIT(DB_TMR_LARGE_OFF); | |
168 | } else { | |
06abe829 | 169 | pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); |
25a853d0 | 170 | ret = -EINVAL; |
dbad75dd KX |
171 | } |
172 | } else { | |
173 | pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); | |
174 | pin_reg &= ~BIT(DB_TMR_LARGE_OFF); | |
175 | pin_reg &= ~DB_TMR_OUT_MASK; | |
06abe829 | 176 | pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); |
dbad75dd KX |
177 | } |
178 | writel(pin_reg, gpio_dev->base + offset * 4); | |
229710fe | 179 | raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); |
dbad75dd | 180 | |
25a853d0 | 181 | return ret; |
dbad75dd KX |
182 | } |
183 | ||
2956b5d9 MW |
184 | static int amd_gpio_set_config(struct gpio_chip *gc, unsigned offset, |
185 | unsigned long config) | |
186 | { | |
187 | u32 debounce; | |
188 | ||
189 | if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE) | |
190 | return -ENOTSUPP; | |
191 | ||
192 | debounce = pinconf_to_config_argument(config); | |
193 | return amd_gpio_set_debounce(gc, offset, debounce); | |
194 | } | |
195 | ||
dbad75dd KX |
196 | #ifdef CONFIG_DEBUG_FS |
197 | static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc) | |
198 | { | |
199 | u32 pin_reg; | |
39cc1d33 | 200 | u32 db_cntrl; |
dbad75dd KX |
201 | unsigned long flags; |
202 | unsigned int bank, i, pin_num; | |
04d36723 | 203 | struct amd_gpio *gpio_dev = gpiochip_get_data(gc); |
dbad75dd | 204 | |
39cc1d33 CX |
205 | bool tmr_out_unit; |
206 | unsigned int time; | |
207 | unsigned int unit; | |
208 | bool tmr_large; | |
209 | ||
dbad75dd KX |
210 | char *level_trig; |
211 | char *active_level; | |
212 | char *interrupt_enable; | |
213 | char *interrupt_mask; | |
214 | char *wake_cntrl0; | |
215 | char *wake_cntrl1; | |
216 | char *wake_cntrl2; | |
217 | char *pin_sts; | |
218 | char *pull_up_sel; | |
219 | char *pull_up_enable; | |
220 | char *pull_down_enable; | |
221 | char *output_value; | |
222 | char *output_enable; | |
39cc1d33 CX |
223 | char debounce_value[40]; |
224 | char *debounce_enable; | |
dbad75dd | 225 | |
3bfd4430 | 226 | for (bank = 0; bank < gpio_dev->hwbank_num; bank++) { |
dbad75dd KX |
227 | seq_printf(s, "GPIO bank%d\t", bank); |
228 | ||
229 | switch (bank) { | |
230 | case 0: | |
231 | i = 0; | |
232 | pin_num = AMD_GPIO_PINS_BANK0; | |
233 | break; | |
234 | case 1: | |
235 | i = 64; | |
236 | pin_num = AMD_GPIO_PINS_BANK1 + i; | |
237 | break; | |
238 | case 2: | |
239 | i = 128; | |
240 | pin_num = AMD_GPIO_PINS_BANK2 + i; | |
241 | break; | |
3bfd4430 SN |
242 | case 3: |
243 | i = 192; | |
244 | pin_num = AMD_GPIO_PINS_BANK3 + i; | |
245 | break; | |
6ac4c1ad LW |
246 | default: |
247 | /* Illegal bank number, ignore */ | |
248 | continue; | |
dbad75dd | 249 | } |
dbad75dd KX |
250 | for (; i < pin_num; i++) { |
251 | seq_printf(s, "pin%d\t", i); | |
229710fe | 252 | raw_spin_lock_irqsave(&gpio_dev->lock, flags); |
dbad75dd | 253 | pin_reg = readl(gpio_dev->base + i * 4); |
229710fe | 254 | raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); |
dbad75dd KX |
255 | |
256 | if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) { | |
1766e4b7 DK |
257 | u8 level = (pin_reg >> ACTIVE_LEVEL_OFF) & |
258 | ACTIVE_LEVEL_MASK; | |
dbad75dd KX |
259 | interrupt_enable = "interrupt is enabled|"; |
260 | ||
1766e4b7 | 261 | if (level == ACTIVE_LEVEL_HIGH) |
dbad75dd | 262 | active_level = "Active high|"; |
1766e4b7 DK |
263 | else if (level == ACTIVE_LEVEL_LOW) |
264 | active_level = "Active low|"; | |
265 | else if (!(pin_reg & BIT(LEVEL_TRIG_OFF)) && | |
266 | level == ACTIVE_LEVEL_BOTH) | |
dbad75dd KX |
267 | active_level = "Active on both|"; |
268 | else | |
0a95160e | 269 | active_level = "Unknown Active level|"; |
dbad75dd KX |
270 | |
271 | if (pin_reg & BIT(LEVEL_TRIG_OFF)) | |
272 | level_trig = "Level trigger|"; | |
273 | else | |
274 | level_trig = "Edge trigger|"; | |
275 | ||
276 | } else { | |
277 | interrupt_enable = | |
278 | "interrupt is disabled|"; | |
279 | active_level = " "; | |
280 | level_trig = " "; | |
281 | } | |
282 | ||
283 | if (pin_reg & BIT(INTERRUPT_MASK_OFF)) | |
284 | interrupt_mask = | |
285 | "interrupt is unmasked|"; | |
286 | else | |
287 | interrupt_mask = | |
288 | "interrupt is masked|"; | |
289 | ||
3bfd4430 | 290 | if (pin_reg & BIT(WAKE_CNTRL_OFF_S0I3)) |
dbad75dd KX |
291 | wake_cntrl0 = "enable wakeup in S0i3 state|"; |
292 | else | |
293 | wake_cntrl0 = "disable wakeup in S0i3 state|"; | |
294 | ||
3bfd4430 | 295 | if (pin_reg & BIT(WAKE_CNTRL_OFF_S3)) |
dbad75dd KX |
296 | wake_cntrl1 = "enable wakeup in S3 state|"; |
297 | else | |
298 | wake_cntrl1 = "disable wakeup in S3 state|"; | |
299 | ||
3bfd4430 | 300 | if (pin_reg & BIT(WAKE_CNTRL_OFF_S4)) |
dbad75dd KX |
301 | wake_cntrl2 = "enable wakeup in S4/S5 state|"; |
302 | else | |
303 | wake_cntrl2 = "disable wakeup in S4/S5 state|"; | |
304 | ||
305 | if (pin_reg & BIT(PULL_UP_ENABLE_OFF)) { | |
306 | pull_up_enable = "pull-up is enabled|"; | |
307 | if (pin_reg & BIT(PULL_UP_SEL_OFF)) | |
308 | pull_up_sel = "8k pull-up|"; | |
309 | else | |
310 | pull_up_sel = "4k pull-up|"; | |
311 | } else { | |
312 | pull_up_enable = "pull-up is disabled|"; | |
313 | pull_up_sel = " "; | |
314 | } | |
315 | ||
316 | if (pin_reg & BIT(PULL_DOWN_ENABLE_OFF)) | |
317 | pull_down_enable = "pull-down is enabled|"; | |
318 | else | |
319 | pull_down_enable = "Pull-down is disabled|"; | |
320 | ||
321 | if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) { | |
322 | pin_sts = " "; | |
323 | output_enable = "output is enabled|"; | |
324 | if (pin_reg & BIT(OUTPUT_VALUE_OFF)) | |
325 | output_value = "output is high|"; | |
326 | else | |
327 | output_value = "output is low|"; | |
328 | } else { | |
329 | output_enable = "output is disabled|"; | |
330 | output_value = " "; | |
331 | ||
332 | if (pin_reg & BIT(PIN_STS_OFF)) | |
333 | pin_sts = "input is high|"; | |
334 | else | |
335 | pin_sts = "input is low|"; | |
336 | } | |
337 | ||
39cc1d33 CX |
338 | db_cntrl = (DB_CNTRl_MASK << DB_CNTRL_OFF) & pin_reg; |
339 | if (db_cntrl) { | |
340 | tmr_out_unit = pin_reg & BIT(DB_TMR_OUT_UNIT_OFF); | |
341 | tmr_large = pin_reg & BIT(DB_TMR_LARGE_OFF); | |
342 | time = pin_reg & DB_TMR_OUT_MASK; | |
343 | if (tmr_large) { | |
344 | if (tmr_out_unit) | |
345 | unit = 62500; | |
346 | else | |
347 | unit = 15625; | |
348 | } else { | |
349 | if (tmr_out_unit) | |
350 | unit = 244; | |
351 | else | |
352 | unit = 61; | |
353 | } | |
354 | if ((DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF) == db_cntrl) | |
355 | debounce_enable = "debouncing filter (high and low) enabled|"; | |
356 | else if ((DB_TYPE_PRESERVE_LOW_GLITCH << DB_CNTRL_OFF) == db_cntrl) | |
357 | debounce_enable = "debouncing filter (low) enabled|"; | |
358 | else | |
359 | debounce_enable = "debouncing filter (high) enabled|"; | |
360 | ||
361 | snprintf(debounce_value, sizeof(debounce_value), | |
362 | "debouncing timeout is %u (us)|", time * unit); | |
363 | } else { | |
364 | debounce_enable = "debouncing filter disabled|"; | |
365 | snprintf(debounce_value, sizeof(debounce_value), " "); | |
366 | } | |
367 | ||
dbad75dd | 368 | seq_printf(s, "%s %s %s %s %s %s\n" |
39cc1d33 | 369 | " %s %s %s %s %s %s %s %s %s 0x%x\n", |
dbad75dd KX |
370 | level_trig, active_level, interrupt_enable, |
371 | interrupt_mask, wake_cntrl0, wake_cntrl1, | |
372 | wake_cntrl2, pin_sts, pull_up_sel, | |
373 | pull_up_enable, pull_down_enable, | |
39cc1d33 CX |
374 | output_value, output_enable, |
375 | debounce_enable, debounce_value, pin_reg); | |
dbad75dd KX |
376 | } |
377 | } | |
378 | } | |
379 | #else | |
380 | #define amd_gpio_dbg_show NULL | |
381 | #endif | |
382 | ||
383 | static void amd_gpio_irq_enable(struct irq_data *d) | |
384 | { | |
385 | u32 pin_reg; | |
386 | unsigned long flags; | |
387 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); | |
04d36723 | 388 | struct amd_gpio *gpio_dev = gpiochip_get_data(gc); |
dbad75dd | 389 | |
229710fe | 390 | raw_spin_lock_irqsave(&gpio_dev->lock, flags); |
dbad75dd | 391 | pin_reg = readl(gpio_dev->base + (d->hwirq)*4); |
dbad75dd KX |
392 | pin_reg |= BIT(INTERRUPT_ENABLE_OFF); |
393 | pin_reg |= BIT(INTERRUPT_MASK_OFF); | |
394 | writel(pin_reg, gpio_dev->base + (d->hwirq)*4); | |
229710fe | 395 | raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); |
dbad75dd KX |
396 | } |
397 | ||
398 | static void amd_gpio_irq_disable(struct irq_data *d) | |
399 | { | |
400 | u32 pin_reg; | |
401 | unsigned long flags; | |
402 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); | |
04d36723 | 403 | struct amd_gpio *gpio_dev = gpiochip_get_data(gc); |
dbad75dd | 404 | |
229710fe | 405 | raw_spin_lock_irqsave(&gpio_dev->lock, flags); |
dbad75dd KX |
406 | pin_reg = readl(gpio_dev->base + (d->hwirq)*4); |
407 | pin_reg &= ~BIT(INTERRUPT_ENABLE_OFF); | |
408 | pin_reg &= ~BIT(INTERRUPT_MASK_OFF); | |
409 | writel(pin_reg, gpio_dev->base + (d->hwirq)*4); | |
229710fe | 410 | raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); |
dbad75dd KX |
411 | } |
412 | ||
413 | static void amd_gpio_irq_mask(struct irq_data *d) | |
414 | { | |
415 | u32 pin_reg; | |
416 | unsigned long flags; | |
417 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); | |
04d36723 | 418 | struct amd_gpio *gpio_dev = gpiochip_get_data(gc); |
dbad75dd | 419 | |
229710fe | 420 | raw_spin_lock_irqsave(&gpio_dev->lock, flags); |
dbad75dd KX |
421 | pin_reg = readl(gpio_dev->base + (d->hwirq)*4); |
422 | pin_reg &= ~BIT(INTERRUPT_MASK_OFF); | |
423 | writel(pin_reg, gpio_dev->base + (d->hwirq)*4); | |
229710fe | 424 | raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); |
dbad75dd KX |
425 | } |
426 | ||
427 | static void amd_gpio_irq_unmask(struct irq_data *d) | |
428 | { | |
429 | u32 pin_reg; | |
430 | unsigned long flags; | |
431 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); | |
04d36723 | 432 | struct amd_gpio *gpio_dev = gpiochip_get_data(gc); |
dbad75dd | 433 | |
229710fe | 434 | raw_spin_lock_irqsave(&gpio_dev->lock, flags); |
dbad75dd KX |
435 | pin_reg = readl(gpio_dev->base + (d->hwirq)*4); |
436 | pin_reg |= BIT(INTERRUPT_MASK_OFF); | |
437 | writel(pin_reg, gpio_dev->base + (d->hwirq)*4); | |
229710fe | 438 | raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); |
dbad75dd KX |
439 | } |
440 | ||
d62bd5ce RR |
441 | static int amd_gpio_irq_set_wake(struct irq_data *d, unsigned int on) |
442 | { | |
443 | u32 pin_reg; | |
444 | unsigned long flags; | |
445 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); | |
446 | struct amd_gpio *gpio_dev = gpiochip_get_data(gc); | |
c4b68e51 | 447 | u32 wake_mask = BIT(WAKE_CNTRL_OFF_S0I3) | BIT(WAKE_CNTRL_OFF_S3); |
acd47b9f | 448 | int err; |
d62bd5ce RR |
449 | |
450 | raw_spin_lock_irqsave(&gpio_dev->lock, flags); | |
451 | pin_reg = readl(gpio_dev->base + (d->hwirq)*4); | |
452 | ||
453 | if (on) | |
454 | pin_reg |= wake_mask; | |
455 | else | |
456 | pin_reg &= ~wake_mask; | |
457 | ||
458 | writel(pin_reg, gpio_dev->base + (d->hwirq)*4); | |
459 | raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); | |
460 | ||
acd47b9f BN |
461 | if (on) |
462 | err = enable_irq_wake(gpio_dev->irq); | |
463 | else | |
464 | err = disable_irq_wake(gpio_dev->irq); | |
465 | ||
466 | if (err) | |
467 | dev_err(&gpio_dev->pdev->dev, "failed to %s wake-up interrupt\n", | |
468 | on ? "enable" : "disable"); | |
469 | ||
d62bd5ce RR |
470 | return 0; |
471 | } | |
472 | ||
dbad75dd KX |
473 | static void amd_gpio_irq_eoi(struct irq_data *d) |
474 | { | |
475 | u32 reg; | |
476 | unsigned long flags; | |
477 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); | |
04d36723 | 478 | struct amd_gpio *gpio_dev = gpiochip_get_data(gc); |
dbad75dd | 479 | |
229710fe | 480 | raw_spin_lock_irqsave(&gpio_dev->lock, flags); |
dbad75dd KX |
481 | reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG); |
482 | reg |= EOI_MASK; | |
483 | writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG); | |
229710fe | 484 | raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); |
dbad75dd KX |
485 | } |
486 | ||
487 | static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type) | |
488 | { | |
489 | int ret = 0; | |
b85bfa24 | 490 | u32 pin_reg, pin_reg_irq_en, mask; |
5f4962dd | 491 | unsigned long flags; |
dbad75dd | 492 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
04d36723 | 493 | struct amd_gpio *gpio_dev = gpiochip_get_data(gc); |
dbad75dd | 494 | |
229710fe | 495 | raw_spin_lock_irqsave(&gpio_dev->lock, flags); |
dbad75dd KX |
496 | pin_reg = readl(gpio_dev->base + (d->hwirq)*4); |
497 | ||
498 | switch (type & IRQ_TYPE_SENSE_MASK) { | |
499 | case IRQ_TYPE_EDGE_RISING: | |
500 | pin_reg &= ~BIT(LEVEL_TRIG_OFF); | |
501 | pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); | |
502 | pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF; | |
9d829314 | 503 | irq_set_handler_locked(d, handle_edge_irq); |
dbad75dd KX |
504 | break; |
505 | ||
506 | case IRQ_TYPE_EDGE_FALLING: | |
507 | pin_reg &= ~BIT(LEVEL_TRIG_OFF); | |
508 | pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); | |
509 | pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF; | |
9d829314 | 510 | irq_set_handler_locked(d, handle_edge_irq); |
dbad75dd KX |
511 | break; |
512 | ||
513 | case IRQ_TYPE_EDGE_BOTH: | |
514 | pin_reg &= ~BIT(LEVEL_TRIG_OFF); | |
515 | pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); | |
516 | pin_reg |= BOTH_EADGE << ACTIVE_LEVEL_OFF; | |
9d829314 | 517 | irq_set_handler_locked(d, handle_edge_irq); |
dbad75dd KX |
518 | break; |
519 | ||
520 | case IRQ_TYPE_LEVEL_HIGH: | |
521 | pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF; | |
522 | pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); | |
523 | pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF; | |
9d829314 | 524 | irq_set_handler_locked(d, handle_level_irq); |
dbad75dd KX |
525 | break; |
526 | ||
527 | case IRQ_TYPE_LEVEL_LOW: | |
528 | pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF; | |
529 | pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); | |
530 | pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF; | |
9d829314 | 531 | irq_set_handler_locked(d, handle_level_irq); |
dbad75dd KX |
532 | break; |
533 | ||
534 | case IRQ_TYPE_NONE: | |
535 | break; | |
536 | ||
537 | default: | |
538 | dev_err(&gpio_dev->pdev->dev, "Invalid type value\n"); | |
539 | ret = -EINVAL; | |
dbad75dd KX |
540 | } |
541 | ||
542 | pin_reg |= CLR_INTR_STAT << INTERRUPT_STS_OFF; | |
b85bfa24 DK |
543 | /* |
544 | * If WAKE_INT_MASTER_REG.MaskStsEn is set, a software write to the | |
545 | * debounce registers of any GPIO will block wake/interrupt status | |
48c67f1f | 546 | * generation for *all* GPIOs for a length of time that depends on |
b85bfa24 DK |
547 | * WAKE_INT_MASTER_REG.MaskStsLength[11:0]. During this period the |
548 | * INTERRUPT_ENABLE bit will read as 0. | |
549 | * | |
550 | * We temporarily enable irq for the GPIO whose configuration is | |
551 | * changing, and then wait for it to read back as 1 to know when | |
552 | * debounce has settled and then disable the irq again. | |
553 | * We do this polling with the spinlock held to ensure other GPIO | |
554 | * access routines do not read an incorrect value for the irq enable | |
555 | * bit of other GPIOs. We keep the GPIO masked while polling to avoid | |
556 | * spurious irqs, and disable the irq again after polling. | |
557 | */ | |
558 | mask = BIT(INTERRUPT_ENABLE_OFF); | |
559 | pin_reg_irq_en = pin_reg; | |
560 | pin_reg_irq_en |= mask; | |
561 | pin_reg_irq_en &= ~BIT(INTERRUPT_MASK_OFF); | |
562 | writel(pin_reg_irq_en, gpio_dev->base + (d->hwirq)*4); | |
563 | while ((readl(gpio_dev->base + (d->hwirq)*4) & mask) != mask) | |
564 | continue; | |
dbad75dd | 565 | writel(pin_reg, gpio_dev->base + (d->hwirq)*4); |
229710fe | 566 | raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); |
dbad75dd | 567 | |
dbad75dd KX |
568 | return ret; |
569 | } | |
570 | ||
571 | static void amd_irq_ack(struct irq_data *d) | |
572 | { | |
573 | /* | |
574 | * based on HW design,there is no need to ack HW | |
575 | * before handle current irq. But this routine is | |
576 | * necessary for handle_edge_irq | |
577 | */ | |
578 | } | |
579 | ||
580 | static struct irq_chip amd_gpio_irqchip = { | |
581 | .name = "amd_gpio", | |
582 | .irq_ack = amd_irq_ack, | |
583 | .irq_enable = amd_gpio_irq_enable, | |
584 | .irq_disable = amd_gpio_irq_disable, | |
585 | .irq_mask = amd_gpio_irq_mask, | |
586 | .irq_unmask = amd_gpio_irq_unmask, | |
d62bd5ce | 587 | .irq_set_wake = amd_gpio_irq_set_wake, |
dbad75dd KX |
588 | .irq_eoi = amd_gpio_irq_eoi, |
589 | .irq_set_type = amd_gpio_irq_set_type, | |
d62bd5ce RR |
590 | /* |
591 | * We need to set IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND so that a wake event | |
592 | * also generates an IRQ. We need the IRQ so the irq_handler can clear | |
593 | * the wake event. Otherwise the wake event will never clear and | |
594 | * prevent the system from suspending. | |
595 | */ | |
596 | .flags = IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND, | |
dbad75dd KX |
597 | }; |
598 | ||
ba714a9c TG |
599 | #define PIN_IRQ_PENDING (BIT(INTERRUPT_STS_OFF) | BIT(WAKE_STS_OFF)) |
600 | ||
601 | static irqreturn_t amd_gpio_irq_handler(int irq, void *dev_id) | |
dbad75dd | 602 | { |
ba714a9c TG |
603 | struct amd_gpio *gpio_dev = dev_id; |
604 | struct gpio_chip *gc = &gpio_dev->gc; | |
605 | irqreturn_t ret = IRQ_NONE; | |
606 | unsigned int i, irqnr; | |
dbad75dd | 607 | unsigned long flags; |
10ff58aa BDC |
608 | u32 __iomem *regs; |
609 | u32 regval; | |
ba714a9c | 610 | u64 status, mask; |
dbad75dd | 611 | |
ba714a9c | 612 | /* Read the wake status */ |
229710fe | 613 | raw_spin_lock_irqsave(&gpio_dev->lock, flags); |
ba714a9c TG |
614 | status = readl(gpio_dev->base + WAKE_INT_STATUS_REG1); |
615 | status <<= 32; | |
616 | status |= readl(gpio_dev->base + WAKE_INT_STATUS_REG0); | |
229710fe | 617 | raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); |
dbad75dd | 618 | |
ba714a9c TG |
619 | /* Bit 0-45 contain the relevant status bits */ |
620 | status &= (1ULL << 46) - 1; | |
621 | regs = gpio_dev->base; | |
622 | for (mask = 1, irqnr = 0; status; mask <<= 1, regs += 4, irqnr += 4) { | |
623 | if (!(status & mask)) | |
624 | continue; | |
625 | status &= ~mask; | |
626 | ||
627 | /* Each status bit covers four pins */ | |
628 | for (i = 0; i < 4; i++) { | |
629 | regval = readl(regs + i); | |
8bbed1ee DK |
630 | if (!(regval & PIN_IRQ_PENDING) || |
631 | !(regval & BIT(INTERRUPT_MASK_OFF))) | |
ba714a9c | 632 | continue; |
a9cb09b7 | 633 | generic_handle_domain_irq(gc->irq.domain, irqnr + i); |
6afb1026 DD |
634 | |
635 | /* Clear interrupt. | |
636 | * We must read the pin register again, in case the | |
637 | * value was changed while executing | |
a9cb09b7 | 638 | * generic_handle_domain_irq() above. |
d21b8adb DD |
639 | * If we didn't find a mapping for the interrupt, |
640 | * disable it in order to avoid a system hang caused | |
641 | * by an interrupt storm. | |
6afb1026 DD |
642 | */ |
643 | raw_spin_lock_irqsave(&gpio_dev->lock, flags); | |
644 | regval = readl(regs + i); | |
d21b8adb DD |
645 | if (irq == 0) { |
646 | regval &= ~BIT(INTERRUPT_ENABLE_OFF); | |
647 | dev_dbg(&gpio_dev->pdev->dev, | |
648 | "Disabling spurious GPIO IRQ %d\n", | |
649 | irqnr + i); | |
650 | } | |
ba714a9c | 651 | writel(regval, regs + i); |
6afb1026 | 652 | raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); |
ba714a9c | 653 | ret = IRQ_HANDLED; |
dbad75dd KX |
654 | } |
655 | } | |
656 | ||
ba714a9c | 657 | /* Signal EOI to the GPIO unit */ |
229710fe | 658 | raw_spin_lock_irqsave(&gpio_dev->lock, flags); |
ba714a9c TG |
659 | regval = readl(gpio_dev->base + WAKE_INT_MASTER_REG); |
660 | regval |= EOI_MASK; | |
661 | writel(regval, gpio_dev->base + WAKE_INT_MASTER_REG); | |
229710fe | 662 | raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); |
dbad75dd | 663 | |
ba714a9c | 664 | return ret; |
dbad75dd KX |
665 | } |
666 | ||
667 | static int amd_get_groups_count(struct pinctrl_dev *pctldev) | |
668 | { | |
669 | struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); | |
670 | ||
671 | return gpio_dev->ngroups; | |
672 | } | |
673 | ||
674 | static const char *amd_get_group_name(struct pinctrl_dev *pctldev, | |
675 | unsigned group) | |
676 | { | |
677 | struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); | |
678 | ||
679 | return gpio_dev->groups[group].name; | |
680 | } | |
681 | ||
682 | static int amd_get_group_pins(struct pinctrl_dev *pctldev, | |
683 | unsigned group, | |
684 | const unsigned **pins, | |
685 | unsigned *num_pins) | |
686 | { | |
687 | struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); | |
688 | ||
689 | *pins = gpio_dev->groups[group].pins; | |
690 | *num_pins = gpio_dev->groups[group].npins; | |
691 | return 0; | |
692 | } | |
693 | ||
694 | static const struct pinctrl_ops amd_pinctrl_ops = { | |
695 | .get_groups_count = amd_get_groups_count, | |
696 | .get_group_name = amd_get_group_name, | |
697 | .get_group_pins = amd_get_group_pins, | |
698 | #ifdef CONFIG_OF | |
699 | .dt_node_to_map = pinconf_generic_dt_node_to_map_group, | |
d32f7fd3 | 700 | .dt_free_map = pinctrl_utils_free_map, |
dbad75dd KX |
701 | #endif |
702 | }; | |
703 | ||
704 | static int amd_pinconf_get(struct pinctrl_dev *pctldev, | |
705 | unsigned int pin, | |
706 | unsigned long *config) | |
707 | { | |
708 | u32 pin_reg; | |
709 | unsigned arg; | |
710 | unsigned long flags; | |
711 | struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); | |
712 | enum pin_config_param param = pinconf_to_config_param(*config); | |
713 | ||
229710fe | 714 | raw_spin_lock_irqsave(&gpio_dev->lock, flags); |
dbad75dd | 715 | pin_reg = readl(gpio_dev->base + pin*4); |
229710fe | 716 | raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); |
dbad75dd KX |
717 | switch (param) { |
718 | case PIN_CONFIG_INPUT_DEBOUNCE: | |
719 | arg = pin_reg & DB_TMR_OUT_MASK; | |
720 | break; | |
721 | ||
722 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
723 | arg = (pin_reg >> PULL_DOWN_ENABLE_OFF) & BIT(0); | |
724 | break; | |
725 | ||
726 | case PIN_CONFIG_BIAS_PULL_UP: | |
727 | arg = (pin_reg >> PULL_UP_SEL_OFF) & (BIT(0) | BIT(1)); | |
728 | break; | |
729 | ||
730 | case PIN_CONFIG_DRIVE_STRENGTH: | |
731 | arg = (pin_reg >> DRV_STRENGTH_SEL_OFF) & DRV_STRENGTH_SEL_MASK; | |
732 | break; | |
733 | ||
734 | default: | |
735 | dev_err(&gpio_dev->pdev->dev, "Invalid config param %04x\n", | |
736 | param); | |
737 | return -ENOTSUPP; | |
738 | } | |
739 | ||
740 | *config = pinconf_to_config_packed(param, arg); | |
741 | ||
742 | return 0; | |
743 | } | |
744 | ||
745 | static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, | |
746 | unsigned long *configs, unsigned num_configs) | |
747 | { | |
748 | int i; | |
dbad75dd | 749 | u32 arg; |
25a853d0 KX |
750 | int ret = 0; |
751 | u32 pin_reg; | |
dbad75dd KX |
752 | unsigned long flags; |
753 | enum pin_config_param param; | |
754 | struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); | |
755 | ||
229710fe | 756 | raw_spin_lock_irqsave(&gpio_dev->lock, flags); |
dbad75dd KX |
757 | for (i = 0; i < num_configs; i++) { |
758 | param = pinconf_to_config_param(configs[i]); | |
759 | arg = pinconf_to_config_argument(configs[i]); | |
760 | pin_reg = readl(gpio_dev->base + pin*4); | |
761 | ||
762 | switch (param) { | |
763 | case PIN_CONFIG_INPUT_DEBOUNCE: | |
764 | pin_reg &= ~DB_TMR_OUT_MASK; | |
765 | pin_reg |= arg & DB_TMR_OUT_MASK; | |
766 | break; | |
767 | ||
768 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
769 | pin_reg &= ~BIT(PULL_DOWN_ENABLE_OFF); | |
770 | pin_reg |= (arg & BIT(0)) << PULL_DOWN_ENABLE_OFF; | |
771 | break; | |
772 | ||
773 | case PIN_CONFIG_BIAS_PULL_UP: | |
774 | pin_reg &= ~BIT(PULL_UP_SEL_OFF); | |
775 | pin_reg |= (arg & BIT(0)) << PULL_UP_SEL_OFF; | |
776 | pin_reg &= ~BIT(PULL_UP_ENABLE_OFF); | |
777 | pin_reg |= ((arg>>1) & BIT(0)) << PULL_UP_ENABLE_OFF; | |
778 | break; | |
779 | ||
780 | case PIN_CONFIG_DRIVE_STRENGTH: | |
781 | pin_reg &= ~(DRV_STRENGTH_SEL_MASK | |
782 | << DRV_STRENGTH_SEL_OFF); | |
783 | pin_reg |= (arg & DRV_STRENGTH_SEL_MASK) | |
784 | << DRV_STRENGTH_SEL_OFF; | |
785 | break; | |
786 | ||
787 | default: | |
788 | dev_err(&gpio_dev->pdev->dev, | |
789 | "Invalid config param %04x\n", param); | |
25a853d0 | 790 | ret = -ENOTSUPP; |
dbad75dd KX |
791 | } |
792 | ||
793 | writel(pin_reg, gpio_dev->base + pin*4); | |
794 | } | |
229710fe | 795 | raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); |
dbad75dd | 796 | |
25a853d0 | 797 | return ret; |
dbad75dd KX |
798 | } |
799 | ||
800 | static int amd_pinconf_group_get(struct pinctrl_dev *pctldev, | |
801 | unsigned int group, | |
802 | unsigned long *config) | |
803 | { | |
804 | const unsigned *pins; | |
805 | unsigned npins; | |
806 | int ret; | |
807 | ||
808 | ret = amd_get_group_pins(pctldev, group, &pins, &npins); | |
809 | if (ret) | |
810 | return ret; | |
811 | ||
812 | if (amd_pinconf_get(pctldev, pins[0], config)) | |
813 | return -ENOTSUPP; | |
814 | ||
815 | return 0; | |
816 | } | |
817 | ||
818 | static int amd_pinconf_group_set(struct pinctrl_dev *pctldev, | |
819 | unsigned group, unsigned long *configs, | |
820 | unsigned num_configs) | |
821 | { | |
822 | const unsigned *pins; | |
823 | unsigned npins; | |
824 | int i, ret; | |
825 | ||
826 | ret = amd_get_group_pins(pctldev, group, &pins, &npins); | |
827 | if (ret) | |
828 | return ret; | |
829 | for (i = 0; i < npins; i++) { | |
830 | if (amd_pinconf_set(pctldev, pins[i], configs, num_configs)) | |
831 | return -ENOTSUPP; | |
832 | } | |
833 | return 0; | |
834 | } | |
835 | ||
836 | static const struct pinconf_ops amd_pinconf_ops = { | |
837 | .pin_config_get = amd_pinconf_get, | |
838 | .pin_config_set = amd_pinconf_set, | |
839 | .pin_config_group_get = amd_pinconf_group_get, | |
840 | .pin_config_group_set = amd_pinconf_group_set, | |
841 | }; | |
842 | ||
4e5a04be SK |
843 | static void amd_gpio_irq_init(struct amd_gpio *gpio_dev) |
844 | { | |
845 | struct pinctrl_desc *desc = gpio_dev->pctrl->desc; | |
846 | unsigned long flags; | |
847 | u32 pin_reg, mask; | |
848 | int i; | |
849 | ||
850 | mask = BIT(WAKE_CNTRL_OFF_S0I3) | BIT(WAKE_CNTRL_OFF_S3) | | |
851 | BIT(INTERRUPT_MASK_OFF) | BIT(INTERRUPT_ENABLE_OFF) | | |
852 | BIT(WAKE_CNTRL_OFF_S4); | |
853 | ||
854 | for (i = 0; i < desc->npins; i++) { | |
855 | int pin = desc->pins[i].number; | |
856 | const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin); | |
857 | ||
858 | if (!pd) | |
859 | continue; | |
860 | ||
861 | raw_spin_lock_irqsave(&gpio_dev->lock, flags); | |
862 | ||
863 | pin_reg = readl(gpio_dev->base + i * 4); | |
864 | pin_reg &= ~mask; | |
865 | writel(pin_reg, gpio_dev->base + i * 4); | |
866 | ||
867 | raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); | |
868 | } | |
869 | } | |
870 | ||
79d2c8be DD |
871 | #ifdef CONFIG_PM_SLEEP |
872 | static bool amd_gpio_should_save(struct amd_gpio *gpio_dev, unsigned int pin) | |
873 | { | |
874 | const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin); | |
875 | ||
876 | if (!pd) | |
877 | return false; | |
878 | ||
879 | /* | |
880 | * Only restore the pin if it is actually in use by the kernel (or | |
881 | * by userspace). | |
882 | */ | |
883 | if (pd->mux_owner || pd->gpio_owner || | |
884 | gpiochip_line_is_irq(&gpio_dev->gc, pin)) | |
885 | return true; | |
886 | ||
887 | return false; | |
888 | } | |
889 | ||
2d71dfa2 | 890 | static int amd_gpio_suspend(struct device *dev) |
79d2c8be | 891 | { |
9f540c3e | 892 | struct amd_gpio *gpio_dev = dev_get_drvdata(dev); |
79d2c8be DD |
893 | struct pinctrl_desc *desc = gpio_dev->pctrl->desc; |
894 | int i; | |
895 | ||
896 | for (i = 0; i < desc->npins; i++) { | |
897 | int pin = desc->pins[i].number; | |
898 | ||
899 | if (!amd_gpio_should_save(gpio_dev, pin)) | |
900 | continue; | |
901 | ||
902 | gpio_dev->saved_regs[i] = readl(gpio_dev->base + pin*4); | |
903 | } | |
904 | ||
905 | return 0; | |
906 | } | |
907 | ||
2d71dfa2 | 908 | static int amd_gpio_resume(struct device *dev) |
79d2c8be | 909 | { |
9f540c3e | 910 | struct amd_gpio *gpio_dev = dev_get_drvdata(dev); |
79d2c8be DD |
911 | struct pinctrl_desc *desc = gpio_dev->pctrl->desc; |
912 | int i; | |
913 | ||
914 | for (i = 0; i < desc->npins; i++) { | |
915 | int pin = desc->pins[i].number; | |
916 | ||
917 | if (!amd_gpio_should_save(gpio_dev, pin)) | |
918 | continue; | |
919 | ||
920 | writel(gpio_dev->saved_regs[i], gpio_dev->base + pin*4); | |
921 | } | |
922 | ||
923 | return 0; | |
924 | } | |
925 | ||
926 | static const struct dev_pm_ops amd_gpio_pm_ops = { | |
927 | SET_LATE_SYSTEM_SLEEP_PM_OPS(amd_gpio_suspend, | |
928 | amd_gpio_resume) | |
929 | }; | |
930 | #endif | |
931 | ||
dbad75dd KX |
932 | static struct pinctrl_desc amd_pinctrl_desc = { |
933 | .pins = kerncz_pins, | |
934 | .npins = ARRAY_SIZE(kerncz_pins), | |
935 | .pctlops = &amd_pinctrl_ops, | |
936 | .confops = &amd_pinconf_ops, | |
937 | .owner = THIS_MODULE, | |
938 | }; | |
939 | ||
940 | static int amd_gpio_probe(struct platform_device *pdev) | |
941 | { | |
942 | int ret = 0; | |
dbad75dd KX |
943 | struct resource *res; |
944 | struct amd_gpio *gpio_dev; | |
e81376eb | 945 | struct gpio_irq_chip *girq; |
dbad75dd KX |
946 | |
947 | gpio_dev = devm_kzalloc(&pdev->dev, | |
948 | sizeof(struct amd_gpio), GFP_KERNEL); | |
949 | if (!gpio_dev) | |
950 | return -ENOMEM; | |
951 | ||
229710fe | 952 | raw_spin_lock_init(&gpio_dev->lock); |
dbad75dd KX |
953 | |
954 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
955 | if (!res) { | |
956 | dev_err(&pdev->dev, "Failed to get gpio io resource.\n"); | |
957 | return -EINVAL; | |
958 | } | |
959 | ||
4bdc0d67 | 960 | gpio_dev->base = devm_ioremap(&pdev->dev, res->start, |
dbad75dd | 961 | resource_size(res)); |
424a6c60 WY |
962 | if (!gpio_dev->base) |
963 | return -ENOMEM; | |
dbad75dd | 964 | |
7e6f8d6f BN |
965 | gpio_dev->irq = platform_get_irq(pdev, 0); |
966 | if (gpio_dev->irq < 0) | |
967 | return gpio_dev->irq; | |
dbad75dd | 968 | |
79d2c8be DD |
969 | #ifdef CONFIG_PM_SLEEP |
970 | gpio_dev->saved_regs = devm_kcalloc(&pdev->dev, amd_pinctrl_desc.npins, | |
971 | sizeof(*gpio_dev->saved_regs), | |
972 | GFP_KERNEL); | |
973 | if (!gpio_dev->saved_regs) | |
974 | return -ENOMEM; | |
975 | #endif | |
976 | ||
dbad75dd | 977 | gpio_dev->pdev = pdev; |
12b10f47 | 978 | gpio_dev->gc.get_direction = amd_gpio_get_direction; |
dbad75dd KX |
979 | gpio_dev->gc.direction_input = amd_gpio_direction_input; |
980 | gpio_dev->gc.direction_output = amd_gpio_direction_output; | |
981 | gpio_dev->gc.get = amd_gpio_get_value; | |
982 | gpio_dev->gc.set = amd_gpio_set_value; | |
2956b5d9 | 983 | gpio_dev->gc.set_config = amd_gpio_set_config; |
dbad75dd KX |
984 | gpio_dev->gc.dbg_show = amd_gpio_dbg_show; |
985 | ||
3bfd4430 | 986 | gpio_dev->gc.base = -1; |
dbad75dd KX |
987 | gpio_dev->gc.label = pdev->name; |
988 | gpio_dev->gc.owner = THIS_MODULE; | |
58383c78 | 989 | gpio_dev->gc.parent = &pdev->dev; |
3bfd4430 | 990 | gpio_dev->gc.ngpio = resource_size(res) / 4; |
dbad75dd KX |
991 | #if defined(CONFIG_OF_GPIO) |
992 | gpio_dev->gc.of_node = pdev->dev.of_node; | |
993 | #endif | |
994 | ||
3bfd4430 | 995 | gpio_dev->hwbank_num = gpio_dev->gc.ngpio / 64; |
dbad75dd KX |
996 | gpio_dev->groups = kerncz_groups; |
997 | gpio_dev->ngroups = ARRAY_SIZE(kerncz_groups); | |
998 | ||
999 | amd_pinctrl_desc.name = dev_name(&pdev->dev); | |
251e22ab LD |
1000 | gpio_dev->pctrl = devm_pinctrl_register(&pdev->dev, &amd_pinctrl_desc, |
1001 | gpio_dev); | |
323de9ef | 1002 | if (IS_ERR(gpio_dev->pctrl)) { |
dbad75dd | 1003 | dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); |
323de9ef | 1004 | return PTR_ERR(gpio_dev->pctrl); |
dbad75dd KX |
1005 | } |
1006 | ||
4e5a04be SK |
1007 | /* Disable and mask interrupts */ |
1008 | amd_gpio_irq_init(gpio_dev); | |
1009 | ||
e81376eb LW |
1010 | girq = &gpio_dev->gc.irq; |
1011 | girq->chip = &amd_gpio_irqchip; | |
1012 | /* This will let us handle the parent IRQ in the driver */ | |
1013 | girq->parent_handler = NULL; | |
1014 | girq->num_parents = 0; | |
1015 | girq->parents = NULL; | |
1016 | girq->default_type = IRQ_TYPE_NONE; | |
1017 | girq->handler = handle_simple_irq; | |
1018 | ||
04d36723 | 1019 | ret = gpiochip_add_data(&gpio_dev->gc, gpio_dev); |
dbad75dd | 1020 | if (ret) |
251e22ab | 1021 | return ret; |
dbad75dd KX |
1022 | |
1023 | ret = gpiochip_add_pin_range(&gpio_dev->gc, dev_name(&pdev->dev), | |
3bfd4430 | 1024 | 0, 0, gpio_dev->gc.ngpio); |
dbad75dd KX |
1025 | if (ret) { |
1026 | dev_err(&pdev->dev, "Failed to add pin range\n"); | |
1027 | goto out2; | |
1028 | } | |
1029 | ||
7e6f8d6f | 1030 | ret = devm_request_irq(&pdev->dev, gpio_dev->irq, amd_gpio_irq_handler, |
279ffafa | 1031 | IRQF_SHARED, KBUILD_MODNAME, gpio_dev); |
ba714a9c TG |
1032 | if (ret) |
1033 | goto out2; | |
1034 | ||
dbad75dd KX |
1035 | platform_set_drvdata(pdev, gpio_dev); |
1036 | ||
1037 | dev_dbg(&pdev->dev, "amd gpio driver loaded\n"); | |
1038 | return ret; | |
1039 | ||
1040 | out2: | |
1041 | gpiochip_remove(&gpio_dev->gc); | |
1042 | ||
dbad75dd KX |
1043 | return ret; |
1044 | } | |
1045 | ||
1046 | static int amd_gpio_remove(struct platform_device *pdev) | |
1047 | { | |
1048 | struct amd_gpio *gpio_dev; | |
1049 | ||
1050 | gpio_dev = platform_get_drvdata(pdev); | |
1051 | ||
1052 | gpiochip_remove(&gpio_dev->gc); | |
dbad75dd KX |
1053 | |
1054 | return 0; | |
1055 | } | |
1056 | ||
de4334f7 | 1057 | #ifdef CONFIG_ACPI |
dbad75dd KX |
1058 | static const struct acpi_device_id amd_gpio_acpi_match[] = { |
1059 | { "AMD0030", 0 }, | |
42a44402 | 1060 | { "AMDI0030", 0}, |
1ca46d3e | 1061 | { "AMDI0031", 0}, |
dbad75dd KX |
1062 | { }, |
1063 | }; | |
1064 | MODULE_DEVICE_TABLE(acpi, amd_gpio_acpi_match); | |
de4334f7 | 1065 | #endif |
dbad75dd KX |
1066 | |
1067 | static struct platform_driver amd_gpio_driver = { | |
1068 | .driver = { | |
1069 | .name = "amd_gpio", | |
dbad75dd | 1070 | .acpi_match_table = ACPI_PTR(amd_gpio_acpi_match), |
79d2c8be DD |
1071 | #ifdef CONFIG_PM_SLEEP |
1072 | .pm = &amd_gpio_pm_ops, | |
1073 | #endif | |
dbad75dd KX |
1074 | }, |
1075 | .probe = amd_gpio_probe, | |
1076 | .remove = amd_gpio_remove, | |
1077 | }; | |
1078 | ||
1079 | module_platform_driver(amd_gpio_driver); | |
1080 | ||
1081 | MODULE_LICENSE("GPL v2"); | |
1082 | MODULE_AUTHOR("Ken Xue <Ken.Xue@amd.com>, Jeff Wu <Jeff.Wu@amd.com>"); | |
1083 | MODULE_DESCRIPTION("AMD GPIO pinctrl driver"); |