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6732ae5c JCPV |
1 | /* |
2 | * at91 pinctrl driver based on at91 pinmux core | |
3 | * | |
4 | * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | |
5 | * | |
6 | * Under GPLv2 only | |
7 | */ | |
8 | ||
9 | #include <linux/clk.h> | |
10 | #include <linux/err.h> | |
11 | #include <linux/init.h> | |
12 | #include <linux/module.h> | |
13 | #include <linux/of.h> | |
14 | #include <linux/of_device.h> | |
15 | #include <linux/of_address.h> | |
16 | #include <linux/of_irq.h> | |
17 | #include <linux/slab.h> | |
18 | #include <linux/interrupt.h> | |
6732ae5c JCPV |
19 | #include <linux/io.h> |
20 | #include <linux/gpio.h> | |
6732ae5c JCPV |
21 | #include <linux/pinctrl/machine.h> |
22 | #include <linux/pinctrl/pinconf.h> | |
23 | #include <linux/pinctrl/pinctrl.h> | |
24 | #include <linux/pinctrl/pinmux.h> | |
25 | /* Since we request GPIOs from ourself */ | |
26 | #include <linux/pinctrl/consumer.h> | |
27 | ||
6732ae5c JCPV |
28 | #include <mach/hardware.h> |
29 | #include <mach/at91_pio.h> | |
30 | ||
31 | #include "core.h" | |
32 | ||
94daf85e | 33 | #define MAX_GPIO_BANKS 5 |
6732ae5c JCPV |
34 | #define MAX_NB_GPIO_PER_BANK 32 |
35 | ||
36 | struct at91_pinctrl_mux_ops; | |
37 | ||
38 | struct at91_gpio_chip { | |
39 | struct gpio_chip chip; | |
40 | struct pinctrl_gpio_range range; | |
41 | struct at91_gpio_chip *next; /* Bank sharing same clock */ | |
42 | int pioc_hwirq; /* PIO bank interrupt identifier on AIC */ | |
43 | int pioc_virq; /* PIO bank Linux virtual interrupt */ | |
44 | int pioc_idx; /* PIO bank index */ | |
45 | void __iomem *regbase; /* PIO bank virtual address */ | |
46 | struct clk *clock; /* associated clock */ | |
6732ae5c JCPV |
47 | struct at91_pinctrl_mux_ops *ops; /* ops */ |
48 | }; | |
49 | ||
50 | #define to_at91_gpio_chip(c) container_of(c, struct at91_gpio_chip, chip) | |
51 | ||
52 | static struct at91_gpio_chip *gpio_chips[MAX_GPIO_BANKS]; | |
53 | ||
54 | static int gpio_banks; | |
55 | ||
525fae21 | 56 | #define PULL_UP (1 << 0) |
6732ae5c | 57 | #define MULTI_DRIVE (1 << 1) |
7ebd7a3a JCPV |
58 | #define DEGLITCH (1 << 2) |
59 | #define PULL_DOWN (1 << 3) | |
60 | #define DIS_SCHMIT (1 << 4) | |
61 | #define DEBOUNCE (1 << 16) | |
62 | #define DEBOUNCE_VAL_SHIFT 17 | |
63 | #define DEBOUNCE_VAL (0x3fff << DEBOUNCE_VAL_SHIFT) | |
6732ae5c JCPV |
64 | |
65 | /** | |
66 | * struct at91_pmx_func - describes AT91 pinmux functions | |
67 | * @name: the name of this specific function | |
68 | * @groups: corresponding pin groups | |
69 | * @ngroups: the number of groups | |
70 | */ | |
71 | struct at91_pmx_func { | |
72 | const char *name; | |
73 | const char **groups; | |
74 | unsigned ngroups; | |
75 | }; | |
76 | ||
77 | enum at91_mux { | |
78 | AT91_MUX_GPIO = 0, | |
79 | AT91_MUX_PERIPH_A = 1, | |
80 | AT91_MUX_PERIPH_B = 2, | |
81 | AT91_MUX_PERIPH_C = 3, | |
82 | AT91_MUX_PERIPH_D = 4, | |
83 | }; | |
84 | ||
85 | /** | |
86 | * struct at91_pmx_pin - describes an At91 pin mux | |
87 | * @bank: the bank of the pin | |
88 | * @pin: the pin number in the @bank | |
89 | * @mux: the mux mode : gpio or periph_x of the pin i.e. alternate function. | |
90 | * @conf: the configuration of the pin: PULL_UP, MULTIDRIVE etc... | |
91 | */ | |
92 | struct at91_pmx_pin { | |
93 | uint32_t bank; | |
94 | uint32_t pin; | |
95 | enum at91_mux mux; | |
96 | unsigned long conf; | |
97 | }; | |
98 | ||
99 | /** | |
100 | * struct at91_pin_group - describes an At91 pin group | |
101 | * @name: the name of this specific pin group | |
102 | * @pins_conf: the mux mode for each pin in this group. The size of this | |
103 | * array is the same as pins. | |
104 | * @pins: an array of discrete physical pins used in this group, taken | |
105 | * from the driver-local pin enumeration space | |
106 | * @npins: the number of pins in this group array, i.e. the number of | |
107 | * elements in .pins so we can iterate over that array | |
108 | */ | |
109 | struct at91_pin_group { | |
110 | const char *name; | |
111 | struct at91_pmx_pin *pins_conf; | |
112 | unsigned int *pins; | |
113 | unsigned npins; | |
114 | }; | |
115 | ||
116 | /** | |
c2eb9e7f | 117 | * struct at91_pinctrl_mux_ops - describes an AT91 mux ops group |
6732ae5c JCPV |
118 | * on new IP with support for periph C and D the way to mux in |
119 | * periph A and B has changed | |
120 | * So provide the right call back | |
121 | * if not present means the IP does not support it | |
122 | * @get_periph: return the periph mode configured | |
123 | * @mux_A_periph: mux as periph A | |
124 | * @mux_B_periph: mux as periph B | |
125 | * @mux_C_periph: mux as periph C | |
126 | * @mux_D_periph: mux as periph D | |
7ebd7a3a JCPV |
127 | * @get_deglitch: get deglitch status |
128 | * @set_deglitch: enable/disable deglitch | |
129 | * @get_debounce: get debounce status | |
130 | * @set_debounce: enable/disable debounce | |
131 | * @get_pulldown: get pulldown status | |
132 | * @set_pulldown: enable/disable pulldown | |
133 | * @get_schmitt_trig: get schmitt trigger status | |
134 | * @disable_schmitt_trig: disable schmitt trigger | |
6732ae5c JCPV |
135 | * @irq_type: return irq type |
136 | */ | |
137 | struct at91_pinctrl_mux_ops { | |
138 | enum at91_mux (*get_periph)(void __iomem *pio, unsigned mask); | |
139 | void (*mux_A_periph)(void __iomem *pio, unsigned mask); | |
140 | void (*mux_B_periph)(void __iomem *pio, unsigned mask); | |
141 | void (*mux_C_periph)(void __iomem *pio, unsigned mask); | |
142 | void (*mux_D_periph)(void __iomem *pio, unsigned mask); | |
7ebd7a3a | 143 | bool (*get_deglitch)(void __iomem *pio, unsigned pin); |
77966ad7 | 144 | void (*set_deglitch)(void __iomem *pio, unsigned mask, bool is_on); |
7ebd7a3a | 145 | bool (*get_debounce)(void __iomem *pio, unsigned pin, u32 *div); |
77966ad7 | 146 | void (*set_debounce)(void __iomem *pio, unsigned mask, bool is_on, u32 div); |
7ebd7a3a | 147 | bool (*get_pulldown)(void __iomem *pio, unsigned pin); |
77966ad7 | 148 | void (*set_pulldown)(void __iomem *pio, unsigned mask, bool is_on); |
7ebd7a3a JCPV |
149 | bool (*get_schmitt_trig)(void __iomem *pio, unsigned pin); |
150 | void (*disable_schmitt_trig)(void __iomem *pio, unsigned mask); | |
6732ae5c JCPV |
151 | /* irq */ |
152 | int (*irq_type)(struct irq_data *d, unsigned type); | |
153 | }; | |
154 | ||
155 | static int gpio_irq_type(struct irq_data *d, unsigned type); | |
156 | static int alt_gpio_irq_type(struct irq_data *d, unsigned type); | |
157 | ||
158 | struct at91_pinctrl { | |
159 | struct device *dev; | |
160 | struct pinctrl_dev *pctl; | |
161 | ||
162 | int nbanks; | |
163 | ||
164 | uint32_t *mux_mask; | |
165 | int nmux; | |
166 | ||
167 | struct at91_pmx_func *functions; | |
168 | int nfunctions; | |
169 | ||
170 | struct at91_pin_group *groups; | |
171 | int ngroups; | |
172 | ||
173 | struct at91_pinctrl_mux_ops *ops; | |
174 | }; | |
175 | ||
176 | static const inline struct at91_pin_group *at91_pinctrl_find_group_by_name( | |
177 | const struct at91_pinctrl *info, | |
178 | const char *name) | |
179 | { | |
180 | const struct at91_pin_group *grp = NULL; | |
181 | int i; | |
182 | ||
183 | for (i = 0; i < info->ngroups; i++) { | |
184 | if (strcmp(info->groups[i].name, name)) | |
185 | continue; | |
186 | ||
187 | grp = &info->groups[i]; | |
188 | dev_dbg(info->dev, "%s: %d 0:%d\n", name, grp->npins, grp->pins[0]); | |
189 | break; | |
190 | } | |
191 | ||
192 | return grp; | |
193 | } | |
194 | ||
195 | static int at91_get_groups_count(struct pinctrl_dev *pctldev) | |
196 | { | |
197 | struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
198 | ||
199 | return info->ngroups; | |
200 | } | |
201 | ||
202 | static const char *at91_get_group_name(struct pinctrl_dev *pctldev, | |
203 | unsigned selector) | |
204 | { | |
205 | struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
206 | ||
207 | return info->groups[selector].name; | |
208 | } | |
209 | ||
210 | static int at91_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, | |
211 | const unsigned **pins, | |
212 | unsigned *npins) | |
213 | { | |
214 | struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
215 | ||
216 | if (selector >= info->ngroups) | |
217 | return -EINVAL; | |
218 | ||
219 | *pins = info->groups[selector].pins; | |
220 | *npins = info->groups[selector].npins; | |
221 | ||
222 | return 0; | |
223 | } | |
224 | ||
225 | static void at91_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, | |
226 | unsigned offset) | |
227 | { | |
228 | seq_printf(s, "%s", dev_name(pctldev->dev)); | |
229 | } | |
230 | ||
231 | static int at91_dt_node_to_map(struct pinctrl_dev *pctldev, | |
232 | struct device_node *np, | |
233 | struct pinctrl_map **map, unsigned *num_maps) | |
234 | { | |
235 | struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
236 | const struct at91_pin_group *grp; | |
237 | struct pinctrl_map *new_map; | |
238 | struct device_node *parent; | |
239 | int map_num = 1; | |
240 | int i; | |
6732ae5c JCPV |
241 | |
242 | /* | |
61e310a1 | 243 | * first find the group of this node and check if we need to create |
6732ae5c JCPV |
244 | * config maps for pins |
245 | */ | |
246 | grp = at91_pinctrl_find_group_by_name(info, np->name); | |
247 | if (!grp) { | |
248 | dev_err(info->dev, "unable to find group for node %s\n", | |
249 | np->name); | |
250 | return -EINVAL; | |
251 | } | |
252 | ||
253 | map_num += grp->npins; | |
254 | new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num, GFP_KERNEL); | |
255 | if (!new_map) | |
256 | return -ENOMEM; | |
257 | ||
258 | *map = new_map; | |
259 | *num_maps = map_num; | |
260 | ||
261 | /* create mux map */ | |
262 | parent = of_get_parent(np); | |
263 | if (!parent) { | |
c62b2b34 | 264 | devm_kfree(pctldev->dev, new_map); |
6732ae5c JCPV |
265 | return -EINVAL; |
266 | } | |
267 | new_map[0].type = PIN_MAP_TYPE_MUX_GROUP; | |
268 | new_map[0].data.mux.function = parent->name; | |
269 | new_map[0].data.mux.group = np->name; | |
270 | of_node_put(parent); | |
271 | ||
272 | /* create config map */ | |
273 | new_map++; | |
274 | for (i = 0; i < grp->npins; i++) { | |
6732ae5c JCPV |
275 | new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN; |
276 | new_map[i].data.configs.group_or_pin = | |
277 | pin_get_name(pctldev, grp->pins[i]); | |
278 | new_map[i].data.configs.configs = &grp->pins_conf[i].conf; | |
279 | new_map[i].data.configs.num_configs = 1; | |
280 | } | |
281 | ||
282 | dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n", | |
283 | (*map)->data.mux.function, (*map)->data.mux.group, map_num); | |
284 | ||
285 | return 0; | |
286 | } | |
287 | ||
288 | static void at91_dt_free_map(struct pinctrl_dev *pctldev, | |
289 | struct pinctrl_map *map, unsigned num_maps) | |
290 | { | |
291 | } | |
292 | ||
022ab148 | 293 | static const struct pinctrl_ops at91_pctrl_ops = { |
6732ae5c JCPV |
294 | .get_groups_count = at91_get_groups_count, |
295 | .get_group_name = at91_get_group_name, | |
296 | .get_group_pins = at91_get_group_pins, | |
297 | .pin_dbg_show = at91_pin_dbg_show, | |
298 | .dt_node_to_map = at91_dt_node_to_map, | |
299 | .dt_free_map = at91_dt_free_map, | |
300 | }; | |
301 | ||
3c93600d | 302 | static void __iomem *pin_to_controller(struct at91_pinctrl *info, |
6732ae5c JCPV |
303 | unsigned int bank) |
304 | { | |
305 | return gpio_chips[bank]->regbase; | |
306 | } | |
307 | ||
308 | static inline int pin_to_bank(unsigned pin) | |
309 | { | |
310 | return pin /= MAX_NB_GPIO_PER_BANK; | |
311 | } | |
312 | ||
313 | static unsigned pin_to_mask(unsigned int pin) | |
314 | { | |
315 | return 1 << pin; | |
316 | } | |
317 | ||
318 | static void at91_mux_disable_interrupt(void __iomem *pio, unsigned mask) | |
319 | { | |
320 | writel_relaxed(mask, pio + PIO_IDR); | |
321 | } | |
322 | ||
323 | static unsigned at91_mux_get_pullup(void __iomem *pio, unsigned pin) | |
324 | { | |
05d3534a | 325 | return !((readl_relaxed(pio + PIO_PUSR) >> pin) & 0x1); |
6732ae5c JCPV |
326 | } |
327 | ||
328 | static void at91_mux_set_pullup(void __iomem *pio, unsigned mask, bool on) | |
329 | { | |
330 | writel_relaxed(mask, pio + (on ? PIO_PUER : PIO_PUDR)); | |
331 | } | |
332 | ||
333 | static unsigned at91_mux_get_multidrive(void __iomem *pio, unsigned pin) | |
334 | { | |
335 | return (readl_relaxed(pio + PIO_MDSR) >> pin) & 0x1; | |
336 | } | |
337 | ||
338 | static void at91_mux_set_multidrive(void __iomem *pio, unsigned mask, bool on) | |
339 | { | |
340 | writel_relaxed(mask, pio + (on ? PIO_MDER : PIO_MDDR)); | |
341 | } | |
342 | ||
343 | static void at91_mux_set_A_periph(void __iomem *pio, unsigned mask) | |
344 | { | |
345 | writel_relaxed(mask, pio + PIO_ASR); | |
346 | } | |
347 | ||
348 | static void at91_mux_set_B_periph(void __iomem *pio, unsigned mask) | |
349 | { | |
350 | writel_relaxed(mask, pio + PIO_BSR); | |
351 | } | |
352 | ||
353 | static void at91_mux_pio3_set_A_periph(void __iomem *pio, unsigned mask) | |
354 | { | |
355 | ||
356 | writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask, | |
357 | pio + PIO_ABCDSR1); | |
358 | writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask, | |
359 | pio + PIO_ABCDSR2); | |
360 | } | |
361 | ||
362 | static void at91_mux_pio3_set_B_periph(void __iomem *pio, unsigned mask) | |
363 | { | |
364 | writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask, | |
365 | pio + PIO_ABCDSR1); | |
366 | writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask, | |
367 | pio + PIO_ABCDSR2); | |
368 | } | |
369 | ||
370 | static void at91_mux_pio3_set_C_periph(void __iomem *pio, unsigned mask) | |
371 | { | |
372 | writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask, pio + PIO_ABCDSR1); | |
373 | writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2); | |
374 | } | |
375 | ||
376 | static void at91_mux_pio3_set_D_periph(void __iomem *pio, unsigned mask) | |
377 | { | |
378 | writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask, pio + PIO_ABCDSR1); | |
379 | writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2); | |
380 | } | |
381 | ||
382 | static enum at91_mux at91_mux_pio3_get_periph(void __iomem *pio, unsigned mask) | |
383 | { | |
384 | unsigned select; | |
385 | ||
386 | if (readl_relaxed(pio + PIO_PSR) & mask) | |
387 | return AT91_MUX_GPIO; | |
388 | ||
389 | select = !!(readl_relaxed(pio + PIO_ABCDSR1) & mask); | |
390 | select |= (!!(readl_relaxed(pio + PIO_ABCDSR2) & mask) << 1); | |
391 | ||
392 | return select + 1; | |
393 | } | |
394 | ||
395 | static enum at91_mux at91_mux_get_periph(void __iomem *pio, unsigned mask) | |
396 | { | |
397 | unsigned select; | |
398 | ||
399 | if (readl_relaxed(pio + PIO_PSR) & mask) | |
400 | return AT91_MUX_GPIO; | |
401 | ||
402 | select = readl_relaxed(pio + PIO_ABSR) & mask; | |
403 | ||
404 | return select + 1; | |
405 | } | |
406 | ||
7ebd7a3a JCPV |
407 | static bool at91_mux_get_deglitch(void __iomem *pio, unsigned pin) |
408 | { | |
409 | return (__raw_readl(pio + PIO_IFSR) >> pin) & 0x1; | |
410 | } | |
411 | ||
412 | static void at91_mux_set_deglitch(void __iomem *pio, unsigned mask, bool is_on) | |
413 | { | |
414 | __raw_writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR)); | |
415 | } | |
416 | ||
c8dba02e BB |
417 | static bool at91_mux_pio3_get_deglitch(void __iomem *pio, unsigned pin) |
418 | { | |
419 | if ((__raw_readl(pio + PIO_IFSR) >> pin) & 0x1) | |
420 | return !((__raw_readl(pio + PIO_IFSCSR) >> pin) & 0x1); | |
421 | ||
422 | return false; | |
423 | } | |
424 | ||
7ebd7a3a JCPV |
425 | static void at91_mux_pio3_set_deglitch(void __iomem *pio, unsigned mask, bool is_on) |
426 | { | |
427 | if (is_on) | |
428 | __raw_writel(mask, pio + PIO_IFSCDR); | |
429 | at91_mux_set_deglitch(pio, mask, is_on); | |
430 | } | |
431 | ||
432 | static bool at91_mux_pio3_get_debounce(void __iomem *pio, unsigned pin, u32 *div) | |
433 | { | |
434 | *div = __raw_readl(pio + PIO_SCDR); | |
435 | ||
c8dba02e BB |
436 | return ((__raw_readl(pio + PIO_IFSR) >> pin) & 0x1) && |
437 | ((__raw_readl(pio + PIO_IFSCSR) >> pin) & 0x1); | |
7ebd7a3a JCPV |
438 | } |
439 | ||
440 | static void at91_mux_pio3_set_debounce(void __iomem *pio, unsigned mask, | |
441 | bool is_on, u32 div) | |
442 | { | |
443 | if (is_on) { | |
444 | __raw_writel(mask, pio + PIO_IFSCER); | |
445 | __raw_writel(div & PIO_SCDR_DIV, pio + PIO_SCDR); | |
446 | __raw_writel(mask, pio + PIO_IFER); | |
c8dba02e BB |
447 | } else |
448 | __raw_writel(mask, pio + PIO_IFSCDR); | |
7ebd7a3a JCPV |
449 | } |
450 | ||
451 | static bool at91_mux_pio3_get_pulldown(void __iomem *pio, unsigned pin) | |
452 | { | |
05d3534a | 453 | return !((__raw_readl(pio + PIO_PPDSR) >> pin) & 0x1); |
7ebd7a3a JCPV |
454 | } |
455 | ||
456 | static void at91_mux_pio3_set_pulldown(void __iomem *pio, unsigned mask, bool is_on) | |
457 | { | |
458 | __raw_writel(mask, pio + (is_on ? PIO_PPDER : PIO_PPDDR)); | |
459 | } | |
460 | ||
461 | static void at91_mux_pio3_disable_schmitt_trig(void __iomem *pio, unsigned mask) | |
462 | { | |
463 | __raw_writel(__raw_readl(pio + PIO_SCHMITT) | mask, pio + PIO_SCHMITT); | |
464 | } | |
465 | ||
466 | static bool at91_mux_pio3_get_schmitt_trig(void __iomem *pio, unsigned pin) | |
467 | { | |
468 | return (__raw_readl(pio + PIO_SCHMITT) >> pin) & 0x1; | |
469 | } | |
470 | ||
6732ae5c JCPV |
471 | static struct at91_pinctrl_mux_ops at91rm9200_ops = { |
472 | .get_periph = at91_mux_get_periph, | |
473 | .mux_A_periph = at91_mux_set_A_periph, | |
474 | .mux_B_periph = at91_mux_set_B_periph, | |
7ebd7a3a JCPV |
475 | .get_deglitch = at91_mux_get_deglitch, |
476 | .set_deglitch = at91_mux_set_deglitch, | |
6732ae5c JCPV |
477 | .irq_type = gpio_irq_type, |
478 | }; | |
479 | ||
480 | static struct at91_pinctrl_mux_ops at91sam9x5_ops = { | |
481 | .get_periph = at91_mux_pio3_get_periph, | |
482 | .mux_A_periph = at91_mux_pio3_set_A_periph, | |
483 | .mux_B_periph = at91_mux_pio3_set_B_periph, | |
484 | .mux_C_periph = at91_mux_pio3_set_C_periph, | |
485 | .mux_D_periph = at91_mux_pio3_set_D_periph, | |
c8dba02e | 486 | .get_deglitch = at91_mux_pio3_get_deglitch, |
7ebd7a3a JCPV |
487 | .set_deglitch = at91_mux_pio3_set_deglitch, |
488 | .get_debounce = at91_mux_pio3_get_debounce, | |
489 | .set_debounce = at91_mux_pio3_set_debounce, | |
490 | .get_pulldown = at91_mux_pio3_get_pulldown, | |
491 | .set_pulldown = at91_mux_pio3_set_pulldown, | |
492 | .get_schmitt_trig = at91_mux_pio3_get_schmitt_trig, | |
493 | .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig, | |
6732ae5c JCPV |
494 | .irq_type = alt_gpio_irq_type, |
495 | }; | |
496 | ||
497 | static void at91_pin_dbg(const struct device *dev, const struct at91_pmx_pin *pin) | |
498 | { | |
499 | if (pin->mux) { | |
500 | dev_dbg(dev, "pio%c%d configured as periph%c with conf = 0x%lu\n", | |
501 | pin->bank + 'A', pin->pin, pin->mux - 1 + 'A', pin->conf); | |
502 | } else { | |
503 | dev_dbg(dev, "pio%c%d configured as gpio with conf = 0x%lu\n", | |
504 | pin->bank + 'A', pin->pin, pin->conf); | |
505 | } | |
506 | } | |
507 | ||
3c93600d | 508 | static int pin_check_config(struct at91_pinctrl *info, const char *name, |
6732ae5c JCPV |
509 | int index, const struct at91_pmx_pin *pin) |
510 | { | |
511 | int mux; | |
512 | ||
513 | /* check if it's a valid config */ | |
514 | if (pin->bank >= info->nbanks) { | |
515 | dev_err(info->dev, "%s: pin conf %d bank_id %d >= nbanks %d\n", | |
516 | name, index, pin->bank, info->nbanks); | |
517 | return -EINVAL; | |
518 | } | |
519 | ||
520 | if (pin->pin >= MAX_NB_GPIO_PER_BANK) { | |
521 | dev_err(info->dev, "%s: pin conf %d pin_bank_id %d >= %d\n", | |
522 | name, index, pin->pin, MAX_NB_GPIO_PER_BANK); | |
523 | return -EINVAL; | |
524 | } | |
525 | ||
526 | if (!pin->mux) | |
527 | return 0; | |
528 | ||
529 | mux = pin->mux - 1; | |
530 | ||
531 | if (mux >= info->nmux) { | |
532 | dev_err(info->dev, "%s: pin conf %d mux_id %d >= nmux %d\n", | |
533 | name, index, mux, info->nmux); | |
534 | return -EINVAL; | |
535 | } | |
536 | ||
537 | if (!(info->mux_mask[pin->bank * info->nmux + mux] & 1 << pin->pin)) { | |
538 | dev_err(info->dev, "%s: pin conf %d mux_id %d not supported for pio%c%d\n", | |
539 | name, index, mux, pin->bank + 'A', pin->pin); | |
540 | return -EINVAL; | |
541 | } | |
542 | ||
543 | return 0; | |
544 | } | |
545 | ||
546 | static void at91_mux_gpio_disable(void __iomem *pio, unsigned mask) | |
547 | { | |
548 | writel_relaxed(mask, pio + PIO_PDR); | |
549 | } | |
550 | ||
551 | static void at91_mux_gpio_enable(void __iomem *pio, unsigned mask, bool input) | |
552 | { | |
553 | writel_relaxed(mask, pio + PIO_PER); | |
554 | writel_relaxed(mask, pio + (input ? PIO_ODR : PIO_OER)); | |
555 | } | |
556 | ||
557 | static int at91_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector, | |
558 | unsigned group) | |
559 | { | |
560 | struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
561 | const struct at91_pmx_pin *pins_conf = info->groups[group].pins_conf; | |
562 | const struct at91_pmx_pin *pin; | |
563 | uint32_t npins = info->groups[group].npins; | |
564 | int i, ret; | |
565 | unsigned mask; | |
566 | void __iomem *pio; | |
567 | ||
568 | dev_dbg(info->dev, "enable function %s group %s\n", | |
569 | info->functions[selector].name, info->groups[group].name); | |
570 | ||
571 | /* first check that all the pins of the group are valid with a valid | |
61e310a1 | 572 | * parameter */ |
6732ae5c JCPV |
573 | for (i = 0; i < npins; i++) { |
574 | pin = &pins_conf[i]; | |
575 | ret = pin_check_config(info, info->groups[group].name, i, pin); | |
576 | if (ret) | |
577 | return ret; | |
578 | } | |
579 | ||
580 | for (i = 0; i < npins; i++) { | |
581 | pin = &pins_conf[i]; | |
582 | at91_pin_dbg(info->dev, pin); | |
583 | pio = pin_to_controller(info, pin->bank); | |
584 | mask = pin_to_mask(pin->pin); | |
585 | at91_mux_disable_interrupt(pio, mask); | |
3c93600d | 586 | switch (pin->mux) { |
6732ae5c JCPV |
587 | case AT91_MUX_GPIO: |
588 | at91_mux_gpio_enable(pio, mask, 1); | |
589 | break; | |
590 | case AT91_MUX_PERIPH_A: | |
591 | info->ops->mux_A_periph(pio, mask); | |
592 | break; | |
593 | case AT91_MUX_PERIPH_B: | |
594 | info->ops->mux_B_periph(pio, mask); | |
595 | break; | |
596 | case AT91_MUX_PERIPH_C: | |
597 | if (!info->ops->mux_C_periph) | |
598 | return -EINVAL; | |
599 | info->ops->mux_C_periph(pio, mask); | |
600 | break; | |
601 | case AT91_MUX_PERIPH_D: | |
602 | if (!info->ops->mux_D_periph) | |
603 | return -EINVAL; | |
604 | info->ops->mux_D_periph(pio, mask); | |
605 | break; | |
606 | } | |
607 | if (pin->mux) | |
608 | at91_mux_gpio_disable(pio, mask); | |
609 | } | |
610 | ||
611 | return 0; | |
612 | } | |
613 | ||
614 | static void at91_pmx_disable(struct pinctrl_dev *pctldev, unsigned selector, | |
615 | unsigned group) | |
616 | { | |
617 | struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
618 | const struct at91_pmx_pin *pins_conf = info->groups[group].pins_conf; | |
619 | const struct at91_pmx_pin *pin; | |
620 | uint32_t npins = info->groups[group].npins; | |
621 | int i; | |
622 | unsigned mask; | |
623 | void __iomem *pio; | |
624 | ||
625 | for (i = 0; i < npins; i++) { | |
626 | pin = &pins_conf[i]; | |
627 | at91_pin_dbg(info->dev, pin); | |
628 | pio = pin_to_controller(info, pin->bank); | |
629 | mask = pin_to_mask(pin->pin); | |
630 | at91_mux_gpio_enable(pio, mask, 1); | |
631 | } | |
632 | } | |
633 | ||
634 | static int at91_pmx_get_funcs_count(struct pinctrl_dev *pctldev) | |
635 | { | |
636 | struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
637 | ||
638 | return info->nfunctions; | |
639 | } | |
640 | ||
641 | static const char *at91_pmx_get_func_name(struct pinctrl_dev *pctldev, | |
642 | unsigned selector) | |
643 | { | |
644 | struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
645 | ||
646 | return info->functions[selector].name; | |
647 | } | |
648 | ||
649 | static int at91_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector, | |
650 | const char * const **groups, | |
651 | unsigned * const num_groups) | |
652 | { | |
653 | struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
654 | ||
655 | *groups = info->functions[selector].groups; | |
656 | *num_groups = info->functions[selector].ngroups; | |
657 | ||
658 | return 0; | |
659 | } | |
660 | ||
f6f94f66 AL |
661 | static int at91_gpio_request_enable(struct pinctrl_dev *pctldev, |
662 | struct pinctrl_gpio_range *range, | |
663 | unsigned offset) | |
6732ae5c JCPV |
664 | { |
665 | struct at91_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
666 | struct at91_gpio_chip *at91_chip; | |
667 | struct gpio_chip *chip; | |
668 | unsigned mask; | |
669 | ||
670 | if (!range) { | |
671 | dev_err(npct->dev, "invalid range\n"); | |
672 | return -EINVAL; | |
673 | } | |
674 | if (!range->gc) { | |
675 | dev_err(npct->dev, "missing GPIO chip in range\n"); | |
676 | return -EINVAL; | |
677 | } | |
678 | chip = range->gc; | |
679 | at91_chip = container_of(chip, struct at91_gpio_chip, chip); | |
680 | ||
681 | dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset); | |
682 | ||
683 | mask = 1 << (offset - chip->base); | |
684 | ||
685 | dev_dbg(npct->dev, "enable pin %u as PIO%c%d 0x%x\n", | |
686 | offset, 'A' + range->id, offset - chip->base, mask); | |
687 | ||
688 | writel_relaxed(mask, at91_chip->regbase + PIO_PER); | |
689 | ||
690 | return 0; | |
691 | } | |
692 | ||
f6f94f66 AL |
693 | static void at91_gpio_disable_free(struct pinctrl_dev *pctldev, |
694 | struct pinctrl_gpio_range *range, | |
695 | unsigned offset) | |
6732ae5c JCPV |
696 | { |
697 | struct at91_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
698 | ||
699 | dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset); | |
700 | /* Set the pin to some default state, GPIO is usually default */ | |
701 | } | |
702 | ||
022ab148 | 703 | static const struct pinmux_ops at91_pmx_ops = { |
6732ae5c JCPV |
704 | .get_functions_count = at91_pmx_get_funcs_count, |
705 | .get_function_name = at91_pmx_get_func_name, | |
706 | .get_function_groups = at91_pmx_get_groups, | |
707 | .enable = at91_pmx_enable, | |
708 | .disable = at91_pmx_disable, | |
709 | .gpio_request_enable = at91_gpio_request_enable, | |
710 | .gpio_disable_free = at91_gpio_disable_free, | |
711 | }; | |
712 | ||
713 | static int at91_pinconf_get(struct pinctrl_dev *pctldev, | |
714 | unsigned pin_id, unsigned long *config) | |
715 | { | |
716 | struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
717 | void __iomem *pio; | |
718 | unsigned pin; | |
7ebd7a3a | 719 | int div; |
6732ae5c | 720 | |
1292e693 AB |
721 | *config = 0; |
722 | dev_dbg(info->dev, "%s:%d, pin_id=%d", __func__, __LINE__, pin_id); | |
6732ae5c JCPV |
723 | pio = pin_to_controller(info, pin_to_bank(pin_id)); |
724 | pin = pin_id % MAX_NB_GPIO_PER_BANK; | |
725 | ||
726 | if (at91_mux_get_multidrive(pio, pin)) | |
727 | *config |= MULTI_DRIVE; | |
728 | ||
729 | if (at91_mux_get_pullup(pio, pin)) | |
730 | *config |= PULL_UP; | |
731 | ||
7ebd7a3a JCPV |
732 | if (info->ops->get_deglitch && info->ops->get_deglitch(pio, pin)) |
733 | *config |= DEGLITCH; | |
734 | if (info->ops->get_debounce && info->ops->get_debounce(pio, pin, &div)) | |
735 | *config |= DEBOUNCE | (div << DEBOUNCE_VAL_SHIFT); | |
736 | if (info->ops->get_pulldown && info->ops->get_pulldown(pio, pin)) | |
737 | *config |= PULL_DOWN; | |
738 | if (info->ops->get_schmitt_trig && info->ops->get_schmitt_trig(pio, pin)) | |
739 | *config |= DIS_SCHMIT; | |
740 | ||
6732ae5c JCPV |
741 | return 0; |
742 | } | |
743 | ||
744 | static int at91_pinconf_set(struct pinctrl_dev *pctldev, | |
03b054e9 SY |
745 | unsigned pin_id, unsigned long *configs, |
746 | unsigned num_configs) | |
6732ae5c JCPV |
747 | { |
748 | struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
749 | unsigned mask; | |
750 | void __iomem *pio; | |
03b054e9 SY |
751 | int i; |
752 | unsigned long config; | |
753 | ||
754 | for (i = 0; i < num_configs; i++) { | |
755 | config = configs[i]; | |
756 | ||
757 | dev_dbg(info->dev, | |
758 | "%s:%d, pin_id=%d, config=0x%lx", | |
759 | __func__, __LINE__, pin_id, config); | |
760 | pio = pin_to_controller(info, pin_to_bank(pin_id)); | |
761 | mask = pin_to_mask(pin_id % MAX_NB_GPIO_PER_BANK); | |
762 | ||
763 | if (config & PULL_UP && config & PULL_DOWN) | |
764 | return -EINVAL; | |
765 | ||
766 | at91_mux_set_pullup(pio, mask, config & PULL_UP); | |
767 | at91_mux_set_multidrive(pio, mask, config & MULTI_DRIVE); | |
768 | if (info->ops->set_deglitch) | |
769 | info->ops->set_deglitch(pio, mask, config & DEGLITCH); | |
770 | if (info->ops->set_debounce) | |
771 | info->ops->set_debounce(pio, mask, config & DEBOUNCE, | |
7ebd7a3a | 772 | (config & DEBOUNCE_VAL) >> DEBOUNCE_VAL_SHIFT); |
03b054e9 SY |
773 | if (info->ops->set_pulldown) |
774 | info->ops->set_pulldown(pio, mask, config & PULL_DOWN); | |
775 | if (info->ops->disable_schmitt_trig && config & DIS_SCHMIT) | |
776 | info->ops->disable_schmitt_trig(pio, mask); | |
777 | ||
778 | } /* for each config */ | |
7ebd7a3a | 779 | |
6732ae5c JCPV |
780 | return 0; |
781 | } | |
782 | ||
4d9b8a8e AB |
783 | #define DBG_SHOW_FLAG(flag) do { \ |
784 | if (config & flag) { \ | |
785 | if (num_conf) \ | |
786 | seq_puts(s, "|"); \ | |
787 | seq_puts(s, #flag); \ | |
788 | num_conf++; \ | |
789 | } \ | |
790 | } while (0) | |
791 | ||
6732ae5c JCPV |
792 | static void at91_pinconf_dbg_show(struct pinctrl_dev *pctldev, |
793 | struct seq_file *s, unsigned pin_id) | |
794 | { | |
4d9b8a8e AB |
795 | unsigned long config; |
796 | int ret, val, num_conf = 0; | |
797 | ||
798 | ret = at91_pinconf_get(pctldev, pin_id, &config); | |
799 | ||
800 | DBG_SHOW_FLAG(MULTI_DRIVE); | |
801 | DBG_SHOW_FLAG(PULL_UP); | |
802 | DBG_SHOW_FLAG(PULL_DOWN); | |
803 | DBG_SHOW_FLAG(DIS_SCHMIT); | |
804 | DBG_SHOW_FLAG(DEGLITCH); | |
805 | DBG_SHOW_FLAG(DEBOUNCE); | |
806 | if (config & DEBOUNCE) { | |
807 | val = config >> DEBOUNCE_VAL_SHIFT; | |
808 | seq_printf(s, "(%d)", val); | |
809 | } | |
6732ae5c | 810 | |
4d9b8a8e | 811 | return; |
6732ae5c JCPV |
812 | } |
813 | ||
814 | static void at91_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, | |
815 | struct seq_file *s, unsigned group) | |
816 | { | |
817 | } | |
818 | ||
022ab148 | 819 | static const struct pinconf_ops at91_pinconf_ops = { |
6732ae5c JCPV |
820 | .pin_config_get = at91_pinconf_get, |
821 | .pin_config_set = at91_pinconf_set, | |
822 | .pin_config_dbg_show = at91_pinconf_dbg_show, | |
823 | .pin_config_group_dbg_show = at91_pinconf_group_dbg_show, | |
824 | }; | |
825 | ||
826 | static struct pinctrl_desc at91_pinctrl_desc = { | |
827 | .pctlops = &at91_pctrl_ops, | |
828 | .pmxops = &at91_pmx_ops, | |
829 | .confops = &at91_pinconf_ops, | |
830 | .owner = THIS_MODULE, | |
831 | }; | |
832 | ||
833 | static const char *gpio_compat = "atmel,at91rm9200-gpio"; | |
834 | ||
150632b0 GKH |
835 | static void at91_pinctrl_child_count(struct at91_pinctrl *info, |
836 | struct device_node *np) | |
6732ae5c JCPV |
837 | { |
838 | struct device_node *child; | |
839 | ||
840 | for_each_child_of_node(np, child) { | |
841 | if (of_device_is_compatible(child, gpio_compat)) { | |
842 | info->nbanks++; | |
843 | } else { | |
844 | info->nfunctions++; | |
845 | info->ngroups += of_get_child_count(child); | |
846 | } | |
847 | } | |
848 | } | |
849 | ||
150632b0 GKH |
850 | static int at91_pinctrl_mux_mask(struct at91_pinctrl *info, |
851 | struct device_node *np) | |
6732ae5c JCPV |
852 | { |
853 | int ret = 0; | |
854 | int size; | |
1164d73a | 855 | const __be32 *list; |
6732ae5c JCPV |
856 | |
857 | list = of_get_property(np, "atmel,mux-mask", &size); | |
858 | if (!list) { | |
859 | dev_err(info->dev, "can not read the mux-mask of %d\n", size); | |
860 | return -EINVAL; | |
861 | } | |
862 | ||
863 | size /= sizeof(*list); | |
864 | if (!size || size % info->nbanks) { | |
865 | dev_err(info->dev, "wrong mux mask array should be by %d\n", info->nbanks); | |
866 | return -EINVAL; | |
867 | } | |
868 | info->nmux = size / info->nbanks; | |
869 | ||
870 | info->mux_mask = devm_kzalloc(info->dev, sizeof(u32) * size, GFP_KERNEL); | |
871 | if (!info->mux_mask) { | |
872 | dev_err(info->dev, "could not alloc mux_mask\n"); | |
873 | return -ENOMEM; | |
874 | } | |
875 | ||
876 | ret = of_property_read_u32_array(np, "atmel,mux-mask", | |
877 | info->mux_mask, size); | |
878 | if (ret) | |
879 | dev_err(info->dev, "can not read the mux-mask of %d\n", size); | |
880 | return ret; | |
881 | } | |
882 | ||
150632b0 GKH |
883 | static int at91_pinctrl_parse_groups(struct device_node *np, |
884 | struct at91_pin_group *grp, | |
885 | struct at91_pinctrl *info, u32 index) | |
6732ae5c JCPV |
886 | { |
887 | struct at91_pmx_pin *pin; | |
888 | int size; | |
1164d73a | 889 | const __be32 *list; |
6732ae5c JCPV |
890 | int i, j; |
891 | ||
892 | dev_dbg(info->dev, "group(%d): %s\n", index, np->name); | |
893 | ||
894 | /* Initialise group */ | |
895 | grp->name = np->name; | |
896 | ||
897 | /* | |
898 | * the binding format is atmel,pins = <bank pin mux CONFIG ...>, | |
899 | * do sanity check and calculate pins number | |
900 | */ | |
901 | list = of_get_property(np, "atmel,pins", &size); | |
902 | /* we do not check return since it's safe node passed down */ | |
903 | size /= sizeof(*list); | |
904 | if (!size || size % 4) { | |
905 | dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n"); | |
906 | return -EINVAL; | |
907 | } | |
908 | ||
909 | grp->npins = size / 4; | |
910 | pin = grp->pins_conf = devm_kzalloc(info->dev, grp->npins * sizeof(struct at91_pmx_pin), | |
911 | GFP_KERNEL); | |
912 | grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int), | |
913 | GFP_KERNEL); | |
914 | if (!grp->pins_conf || !grp->pins) | |
915 | return -ENOMEM; | |
916 | ||
917 | for (i = 0, j = 0; i < size; i += 4, j++) { | |
918 | pin->bank = be32_to_cpu(*list++); | |
919 | pin->pin = be32_to_cpu(*list++); | |
920 | grp->pins[j] = pin->bank * MAX_NB_GPIO_PER_BANK + pin->pin; | |
921 | pin->mux = be32_to_cpu(*list++); | |
922 | pin->conf = be32_to_cpu(*list++); | |
923 | ||
924 | at91_pin_dbg(info->dev, pin); | |
925 | pin++; | |
926 | } | |
927 | ||
928 | return 0; | |
929 | } | |
930 | ||
150632b0 GKH |
931 | static int at91_pinctrl_parse_functions(struct device_node *np, |
932 | struct at91_pinctrl *info, u32 index) | |
6732ae5c JCPV |
933 | { |
934 | struct device_node *child; | |
935 | struct at91_pmx_func *func; | |
936 | struct at91_pin_group *grp; | |
937 | int ret; | |
938 | static u32 grp_index; | |
939 | u32 i = 0; | |
940 | ||
941 | dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name); | |
942 | ||
943 | func = &info->functions[index]; | |
944 | ||
945 | /* Initialise function */ | |
946 | func->name = np->name; | |
947 | func->ngroups = of_get_child_count(np); | |
948 | if (func->ngroups <= 0) { | |
949 | dev_err(info->dev, "no groups defined\n"); | |
950 | return -EINVAL; | |
951 | } | |
952 | func->groups = devm_kzalloc(info->dev, | |
953 | func->ngroups * sizeof(char *), GFP_KERNEL); | |
954 | if (!func->groups) | |
955 | return -ENOMEM; | |
956 | ||
957 | for_each_child_of_node(np, child) { | |
958 | func->groups[i] = child->name; | |
959 | grp = &info->groups[grp_index++]; | |
960 | ret = at91_pinctrl_parse_groups(child, grp, info, i++); | |
961 | if (ret) | |
962 | return ret; | |
963 | } | |
964 | ||
965 | return 0; | |
966 | } | |
967 | ||
150632b0 | 968 | static struct of_device_id at91_pinctrl_of_match[] = { |
6732ae5c JCPV |
969 | { .compatible = "atmel,at91sam9x5-pinctrl", .data = &at91sam9x5_ops }, |
970 | { .compatible = "atmel,at91rm9200-pinctrl", .data = &at91rm9200_ops }, | |
971 | { /* sentinel */ } | |
972 | }; | |
973 | ||
150632b0 GKH |
974 | static int at91_pinctrl_probe_dt(struct platform_device *pdev, |
975 | struct at91_pinctrl *info) | |
6732ae5c JCPV |
976 | { |
977 | int ret = 0; | |
978 | int i, j; | |
979 | uint32_t *tmp; | |
980 | struct device_node *np = pdev->dev.of_node; | |
981 | struct device_node *child; | |
982 | ||
983 | if (!np) | |
984 | return -ENODEV; | |
985 | ||
986 | info->dev = &pdev->dev; | |
3c93600d | 987 | info->ops = (struct at91_pinctrl_mux_ops *) |
6732ae5c JCPV |
988 | of_match_device(at91_pinctrl_of_match, &pdev->dev)->data; |
989 | at91_pinctrl_child_count(info, np); | |
990 | ||
991 | if (info->nbanks < 1) { | |
61e310a1 | 992 | dev_err(&pdev->dev, "you need to specify at least one gpio-controller\n"); |
6732ae5c JCPV |
993 | return -EINVAL; |
994 | } | |
995 | ||
996 | ret = at91_pinctrl_mux_mask(info, np); | |
997 | if (ret) | |
998 | return ret; | |
999 | ||
1000 | dev_dbg(&pdev->dev, "nmux = %d\n", info->nmux); | |
1001 | ||
1002 | dev_dbg(&pdev->dev, "mux-mask\n"); | |
1003 | tmp = info->mux_mask; | |
1004 | for (i = 0; i < info->nbanks; i++) { | |
1005 | for (j = 0; j < info->nmux; j++, tmp++) { | |
1006 | dev_dbg(&pdev->dev, "%d:%d\t0x%x\n", i, j, tmp[0]); | |
1007 | } | |
1008 | } | |
1009 | ||
1010 | dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions); | |
1011 | dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups); | |
1012 | info->functions = devm_kzalloc(&pdev->dev, info->nfunctions * sizeof(struct at91_pmx_func), | |
1013 | GFP_KERNEL); | |
1014 | if (!info->functions) | |
1015 | return -ENOMEM; | |
1016 | ||
1017 | info->groups = devm_kzalloc(&pdev->dev, info->ngroups * sizeof(struct at91_pin_group), | |
1018 | GFP_KERNEL); | |
1019 | if (!info->groups) | |
1020 | return -ENOMEM; | |
1021 | ||
1022 | dev_dbg(&pdev->dev, "nbanks = %d\n", info->nbanks); | |
1023 | dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions); | |
1024 | dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups); | |
1025 | ||
1026 | i = 0; | |
1027 | ||
1028 | for_each_child_of_node(np, child) { | |
1029 | if (of_device_is_compatible(child, gpio_compat)) | |
1030 | continue; | |
1031 | ret = at91_pinctrl_parse_functions(child, info, i++); | |
1032 | if (ret) { | |
1033 | dev_err(&pdev->dev, "failed to parse function\n"); | |
1034 | return ret; | |
1035 | } | |
1036 | } | |
1037 | ||
1038 | return 0; | |
1039 | } | |
1040 | ||
150632b0 | 1041 | static int at91_pinctrl_probe(struct platform_device *pdev) |
6732ae5c JCPV |
1042 | { |
1043 | struct at91_pinctrl *info; | |
1044 | struct pinctrl_pin_desc *pdesc; | |
3c93600d | 1045 | int ret, i, j, k; |
6732ae5c JCPV |
1046 | |
1047 | info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL); | |
1048 | if (!info) | |
1049 | return -ENOMEM; | |
1050 | ||
1051 | ret = at91_pinctrl_probe_dt(pdev, info); | |
1052 | if (ret) | |
1053 | return ret; | |
1054 | ||
1055 | /* | |
1056 | * We need all the GPIO drivers to probe FIRST, or we will not be able | |
1057 | * to obtain references to the struct gpio_chip * for them, and we | |
1058 | * need this to proceed. | |
1059 | */ | |
1060 | for (i = 0; i < info->nbanks; i++) { | |
1061 | if (!gpio_chips[i]) { | |
1062 | dev_warn(&pdev->dev, "GPIO chip %d not registered yet\n", i); | |
1063 | devm_kfree(&pdev->dev, info); | |
1064 | return -EPROBE_DEFER; | |
1065 | } | |
1066 | } | |
1067 | ||
1068 | at91_pinctrl_desc.name = dev_name(&pdev->dev); | |
1069 | at91_pinctrl_desc.npins = info->nbanks * MAX_NB_GPIO_PER_BANK; | |
1070 | at91_pinctrl_desc.pins = pdesc = | |
1071 | devm_kzalloc(&pdev->dev, sizeof(*pdesc) * at91_pinctrl_desc.npins, GFP_KERNEL); | |
1072 | ||
1073 | if (!at91_pinctrl_desc.pins) | |
1074 | return -ENOMEM; | |
1075 | ||
1076 | for (i = 0 , k = 0; i < info->nbanks; i++) { | |
1077 | for (j = 0; j < MAX_NB_GPIO_PER_BANK; j++, k++) { | |
1078 | pdesc->number = k; | |
1079 | pdesc->name = kasprintf(GFP_KERNEL, "pio%c%d", i + 'A', j); | |
1080 | pdesc++; | |
1081 | } | |
1082 | } | |
1083 | ||
1084 | platform_set_drvdata(pdev, info); | |
1085 | info->pctl = pinctrl_register(&at91_pinctrl_desc, &pdev->dev, info); | |
1086 | ||
1087 | if (!info->pctl) { | |
1088 | dev_err(&pdev->dev, "could not register AT91 pinctrl driver\n"); | |
1089 | ret = -EINVAL; | |
1090 | goto err; | |
1091 | } | |
1092 | ||
1093 | /* We will handle a range of GPIO pins */ | |
1094 | for (i = 0; i < info->nbanks; i++) | |
1095 | pinctrl_add_gpio_range(info->pctl, &gpio_chips[i]->range); | |
1096 | ||
1097 | dev_info(&pdev->dev, "initialized AT91 pinctrl driver\n"); | |
1098 | ||
1099 | return 0; | |
1100 | ||
1101 | err: | |
1102 | return ret; | |
1103 | } | |
1104 | ||
150632b0 | 1105 | static int at91_pinctrl_remove(struct platform_device *pdev) |
6732ae5c JCPV |
1106 | { |
1107 | struct at91_pinctrl *info = platform_get_drvdata(pdev); | |
1108 | ||
1109 | pinctrl_unregister(info->pctl); | |
1110 | ||
1111 | return 0; | |
1112 | } | |
1113 | ||
1114 | static int at91_gpio_request(struct gpio_chip *chip, unsigned offset) | |
1115 | { | |
1116 | /* | |
1117 | * Map back to global GPIO space and request muxing, the direction | |
1118 | * parameter does not matter for this controller. | |
1119 | */ | |
1120 | int gpio = chip->base + offset; | |
1121 | int bank = chip->base / chip->ngpio; | |
1122 | ||
1123 | dev_dbg(chip->dev, "%s:%d pio%c%d(%d)\n", __func__, __LINE__, | |
1124 | 'A' + bank, offset, gpio); | |
1125 | ||
1126 | return pinctrl_request_gpio(gpio); | |
1127 | } | |
1128 | ||
1129 | static void at91_gpio_free(struct gpio_chip *chip, unsigned offset) | |
1130 | { | |
1131 | int gpio = chip->base + offset; | |
1132 | ||
1133 | pinctrl_free_gpio(gpio); | |
1134 | } | |
1135 | ||
8af584b8 RG |
1136 | static int at91_gpio_get_direction(struct gpio_chip *chip, unsigned offset) |
1137 | { | |
1138 | struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); | |
1139 | void __iomem *pio = at91_gpio->regbase; | |
1140 | unsigned mask = 1 << offset; | |
1141 | u32 osr; | |
1142 | ||
1143 | osr = readl_relaxed(pio + PIO_OSR); | |
1144 | return !(osr & mask); | |
1145 | } | |
1146 | ||
6732ae5c JCPV |
1147 | static int at91_gpio_direction_input(struct gpio_chip *chip, unsigned offset) |
1148 | { | |
1149 | struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); | |
1150 | void __iomem *pio = at91_gpio->regbase; | |
1151 | unsigned mask = 1 << offset; | |
1152 | ||
1153 | writel_relaxed(mask, pio + PIO_ODR); | |
1154 | return 0; | |
1155 | } | |
1156 | ||
1157 | static int at91_gpio_get(struct gpio_chip *chip, unsigned offset) | |
1158 | { | |
1159 | struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); | |
1160 | void __iomem *pio = at91_gpio->regbase; | |
1161 | unsigned mask = 1 << offset; | |
1162 | u32 pdsr; | |
1163 | ||
1164 | pdsr = readl_relaxed(pio + PIO_PDSR); | |
1165 | return (pdsr & mask) != 0; | |
1166 | } | |
1167 | ||
1168 | static void at91_gpio_set(struct gpio_chip *chip, unsigned offset, | |
1169 | int val) | |
1170 | { | |
1171 | struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); | |
1172 | void __iomem *pio = at91_gpio->regbase; | |
1173 | unsigned mask = 1 << offset; | |
1174 | ||
1175 | writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR)); | |
1176 | } | |
1177 | ||
1178 | static int at91_gpio_direction_output(struct gpio_chip *chip, unsigned offset, | |
1179 | int val) | |
1180 | { | |
1181 | struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); | |
1182 | void __iomem *pio = at91_gpio->regbase; | |
1183 | unsigned mask = 1 << offset; | |
1184 | ||
1185 | writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR)); | |
1186 | writel_relaxed(mask, pio + PIO_OER); | |
1187 | ||
1188 | return 0; | |
1189 | } | |
1190 | ||
6732ae5c JCPV |
1191 | #ifdef CONFIG_DEBUG_FS |
1192 | static void at91_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) | |
1193 | { | |
1194 | enum at91_mux mode; | |
1195 | int i; | |
1196 | struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); | |
1197 | void __iomem *pio = at91_gpio->regbase; | |
1198 | ||
1199 | for (i = 0; i < chip->ngpio; i++) { | |
1200 | unsigned pin = chip->base + i; | |
1201 | unsigned mask = pin_to_mask(pin); | |
1202 | const char *gpio_label; | |
1203 | u32 pdsr; | |
1204 | ||
1205 | gpio_label = gpiochip_is_requested(chip, i); | |
1206 | if (!gpio_label) | |
1207 | continue; | |
1208 | mode = at91_gpio->ops->get_periph(pio, mask); | |
1209 | seq_printf(s, "[%s] GPIO%s%d: ", | |
1210 | gpio_label, chip->label, i); | |
1211 | if (mode == AT91_MUX_GPIO) { | |
1212 | pdsr = readl_relaxed(pio + PIO_PDSR); | |
1213 | ||
1214 | seq_printf(s, "[gpio] %s\n", | |
1215 | pdsr & mask ? | |
1216 | "set" : "clear"); | |
1217 | } else { | |
1218 | seq_printf(s, "[periph %c]\n", | |
1219 | mode + 'A' - 1); | |
1220 | } | |
1221 | } | |
1222 | } | |
1223 | #else | |
1224 | #define at91_gpio_dbg_show NULL | |
1225 | #endif | |
1226 | ||
1227 | /* Several AIC controller irqs are dispatched through this GPIO handler. | |
1228 | * To use any AT91_PIN_* as an externally triggered IRQ, first call | |
1229 | * at91_set_gpio_input() then maybe enable its glitch filter. | |
1230 | * Then just request_irq() with the pin ID; it works like any ARM IRQ | |
1231 | * handler. | |
1232 | * First implementation always triggers on rising and falling edges | |
1233 | * whereas the newer PIO3 can be additionally configured to trigger on | |
1234 | * level, edge with any polarity. | |
1235 | * | |
1236 | * Alternatively, certain pins may be used directly as IRQ0..IRQ6 after | |
1237 | * configuring them with at91_set_a_periph() or at91_set_b_periph(). | |
1238 | * IRQ0..IRQ6 should be configurable, e.g. level vs edge triggering. | |
1239 | */ | |
1240 | ||
1241 | static void gpio_irq_mask(struct irq_data *d) | |
1242 | { | |
1243 | struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d); | |
1244 | void __iomem *pio = at91_gpio->regbase; | |
1245 | unsigned mask = 1 << d->hwirq; | |
1246 | ||
1247 | if (pio) | |
1248 | writel_relaxed(mask, pio + PIO_IDR); | |
1249 | } | |
1250 | ||
1251 | static void gpio_irq_unmask(struct irq_data *d) | |
1252 | { | |
1253 | struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d); | |
1254 | void __iomem *pio = at91_gpio->regbase; | |
1255 | unsigned mask = 1 << d->hwirq; | |
1256 | ||
1257 | if (pio) | |
1258 | writel_relaxed(mask, pio + PIO_IER); | |
1259 | } | |
1260 | ||
1261 | static int gpio_irq_type(struct irq_data *d, unsigned type) | |
1262 | { | |
1263 | switch (type) { | |
1264 | case IRQ_TYPE_NONE: | |
1265 | case IRQ_TYPE_EDGE_BOTH: | |
1266 | return 0; | |
1267 | default: | |
1268 | return -EINVAL; | |
1269 | } | |
1270 | } | |
1271 | ||
1272 | /* Alternate irq type for PIO3 support */ | |
1273 | static int alt_gpio_irq_type(struct irq_data *d, unsigned type) | |
1274 | { | |
1275 | struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d); | |
1276 | void __iomem *pio = at91_gpio->regbase; | |
1277 | unsigned mask = 1 << d->hwirq; | |
1278 | ||
1279 | switch (type) { | |
1280 | case IRQ_TYPE_EDGE_RISING: | |
b0dcfd87 | 1281 | __irq_set_handler_locked(d->irq, handle_simple_irq); |
6732ae5c JCPV |
1282 | writel_relaxed(mask, pio + PIO_ESR); |
1283 | writel_relaxed(mask, pio + PIO_REHLSR); | |
1284 | break; | |
1285 | case IRQ_TYPE_EDGE_FALLING: | |
b0dcfd87 | 1286 | __irq_set_handler_locked(d->irq, handle_simple_irq); |
6732ae5c JCPV |
1287 | writel_relaxed(mask, pio + PIO_ESR); |
1288 | writel_relaxed(mask, pio + PIO_FELLSR); | |
1289 | break; | |
1290 | case IRQ_TYPE_LEVEL_LOW: | |
b0dcfd87 | 1291 | __irq_set_handler_locked(d->irq, handle_level_irq); |
6732ae5c JCPV |
1292 | writel_relaxed(mask, pio + PIO_LSR); |
1293 | writel_relaxed(mask, pio + PIO_FELLSR); | |
1294 | break; | |
1295 | case IRQ_TYPE_LEVEL_HIGH: | |
b0dcfd87 | 1296 | __irq_set_handler_locked(d->irq, handle_level_irq); |
6732ae5c JCPV |
1297 | writel_relaxed(mask, pio + PIO_LSR); |
1298 | writel_relaxed(mask, pio + PIO_REHLSR); | |
1299 | break; | |
1300 | case IRQ_TYPE_EDGE_BOTH: | |
1301 | /* | |
1302 | * disable additional interrupt modes: | |
1303 | * fall back to default behavior | |
1304 | */ | |
b0dcfd87 | 1305 | __irq_set_handler_locked(d->irq, handle_simple_irq); |
6732ae5c JCPV |
1306 | writel_relaxed(mask, pio + PIO_AIMDR); |
1307 | return 0; | |
1308 | case IRQ_TYPE_NONE: | |
1309 | default: | |
1310 | pr_warn("AT91: No type for irq %d\n", gpio_to_irq(d->irq)); | |
1311 | return -EINVAL; | |
1312 | } | |
1313 | ||
1314 | /* enable additional interrupt modes */ | |
1315 | writel_relaxed(mask, pio + PIO_AIMER); | |
1316 | ||
1317 | return 0; | |
1318 | } | |
1319 | ||
80cc3732 AS |
1320 | static void gpio_irq_ack(struct irq_data *d) |
1321 | { | |
1322 | /* the interrupt is already cleared before by reading ISR */ | |
1323 | } | |
1324 | ||
94e69207 JJH |
1325 | static unsigned int gpio_irq_startup(struct irq_data *d) |
1326 | { | |
1327 | struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d); | |
1328 | unsigned pin = d->hwirq; | |
1329 | int ret; | |
1330 | ||
1331 | ret = gpio_lock_as_irq(&at91_gpio->chip, pin); | |
1332 | if (ret) { | |
1333 | dev_err(at91_gpio->chip.dev, "unable to lock pind %lu IRQ\n", | |
1334 | d->hwirq); | |
1335 | return ret; | |
1336 | } | |
1337 | gpio_irq_unmask(d); | |
1338 | return 0; | |
1339 | } | |
1340 | ||
1341 | static void gpio_irq_shutdown(struct irq_data *d) | |
1342 | { | |
1343 | struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d); | |
1344 | unsigned pin = d->hwirq; | |
1345 | ||
1346 | gpio_irq_mask(d); | |
1347 | gpio_unlock_as_irq(&at91_gpio->chip, pin); | |
1348 | } | |
1349 | ||
6732ae5c | 1350 | #ifdef CONFIG_PM |
647f8d94 LD |
1351 | |
1352 | static u32 wakeups[MAX_GPIO_BANKS]; | |
1353 | static u32 backups[MAX_GPIO_BANKS]; | |
1354 | ||
6732ae5c JCPV |
1355 | static int gpio_irq_set_wake(struct irq_data *d, unsigned state) |
1356 | { | |
1357 | struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d); | |
1358 | unsigned bank = at91_gpio->pioc_idx; | |
647f8d94 | 1359 | unsigned mask = 1 << d->hwirq; |
6732ae5c JCPV |
1360 | |
1361 | if (unlikely(bank >= MAX_GPIO_BANKS)) | |
1362 | return -EINVAL; | |
1363 | ||
647f8d94 LD |
1364 | if (state) |
1365 | wakeups[bank] |= mask; | |
1366 | else | |
1367 | wakeups[bank] &= ~mask; | |
1368 | ||
6732ae5c JCPV |
1369 | irq_set_irq_wake(at91_gpio->pioc_virq, state); |
1370 | ||
1371 | return 0; | |
1372 | } | |
647f8d94 LD |
1373 | |
1374 | void at91_pinctrl_gpio_suspend(void) | |
1375 | { | |
1376 | int i; | |
1377 | ||
1378 | for (i = 0; i < gpio_banks; i++) { | |
1379 | void __iomem *pio; | |
1380 | ||
1381 | if (!gpio_chips[i]) | |
1382 | continue; | |
1383 | ||
1384 | pio = gpio_chips[i]->regbase; | |
1385 | ||
1386 | backups[i] = __raw_readl(pio + PIO_IMR); | |
1387 | __raw_writel(backups[i], pio + PIO_IDR); | |
1388 | __raw_writel(wakeups[i], pio + PIO_IER); | |
1389 | ||
795f9953 BB |
1390 | if (!wakeups[i]) |
1391 | clk_disable_unprepare(gpio_chips[i]->clock); | |
1392 | else | |
647f8d94 LD |
1393 | printk(KERN_DEBUG "GPIO-%c may wake for %08x\n", |
1394 | 'A'+i, wakeups[i]); | |
647f8d94 LD |
1395 | } |
1396 | } | |
1397 | ||
1398 | void at91_pinctrl_gpio_resume(void) | |
1399 | { | |
1400 | int i; | |
1401 | ||
1402 | for (i = 0; i < gpio_banks; i++) { | |
1403 | void __iomem *pio; | |
1404 | ||
1405 | if (!gpio_chips[i]) | |
1406 | continue; | |
1407 | ||
1408 | pio = gpio_chips[i]->regbase; | |
1409 | ||
37ef1d92 BB |
1410 | if (!wakeups[i]) |
1411 | clk_prepare_enable(gpio_chips[i]->clock); | |
647f8d94 LD |
1412 | |
1413 | __raw_writel(wakeups[i], pio + PIO_IDR); | |
1414 | __raw_writel(backups[i], pio + PIO_IER); | |
1415 | } | |
1416 | } | |
1417 | ||
6732ae5c JCPV |
1418 | #else |
1419 | #define gpio_irq_set_wake NULL | |
647f8d94 | 1420 | #endif /* CONFIG_PM */ |
6732ae5c JCPV |
1421 | |
1422 | static struct irq_chip gpio_irqchip = { | |
1423 | .name = "GPIO", | |
80cc3732 | 1424 | .irq_ack = gpio_irq_ack, |
94e69207 JJH |
1425 | .irq_startup = gpio_irq_startup, |
1426 | .irq_shutdown = gpio_irq_shutdown, | |
6732ae5c JCPV |
1427 | .irq_disable = gpio_irq_mask, |
1428 | .irq_mask = gpio_irq_mask, | |
1429 | .irq_unmask = gpio_irq_unmask, | |
1430 | /* .irq_set_type is set dynamically */ | |
1431 | .irq_set_wake = gpio_irq_set_wake, | |
1432 | }; | |
1433 | ||
1434 | static void gpio_irq_handler(unsigned irq, struct irq_desc *desc) | |
1435 | { | |
80cc3732 AS |
1436 | struct irq_chip *chip = irq_get_chip(irq); |
1437 | struct gpio_chip *gpio_chip = irq_desc_get_handler_data(desc); | |
1438 | struct at91_gpio_chip *at91_gpio = container_of(gpio_chip, | |
1439 | struct at91_gpio_chip, chip); | |
1440 | ||
6732ae5c JCPV |
1441 | void __iomem *pio = at91_gpio->regbase; |
1442 | unsigned long isr; | |
1443 | int n; | |
1444 | ||
1445 | chained_irq_enter(chip, desc); | |
1446 | for (;;) { | |
1447 | /* Reading ISR acks pending (edge triggered) GPIO interrupts. | |
c2eb9e7f | 1448 | * When there are none pending, we're finished unless we need |
6732ae5c JCPV |
1449 | * to process multiple banks (like ID_PIOCDE on sam9263). |
1450 | */ | |
1451 | isr = readl_relaxed(pio + PIO_ISR) & readl_relaxed(pio + PIO_IMR); | |
1452 | if (!isr) { | |
1453 | if (!at91_gpio->next) | |
1454 | break; | |
1455 | at91_gpio = at91_gpio->next; | |
1456 | pio = at91_gpio->regbase; | |
1457 | continue; | |
1458 | } | |
1459 | ||
05daa16a | 1460 | for_each_set_bit(n, &isr, BITS_PER_LONG) { |
80cc3732 AS |
1461 | generic_handle_irq(irq_find_mapping( |
1462 | gpio_chip->irqdomain, n)); | |
6732ae5c JCPV |
1463 | } |
1464 | } | |
1465 | chained_irq_exit(chip, desc); | |
1466 | /* now it may re-trigger */ | |
1467 | } | |
1468 | ||
6732ae5c JCPV |
1469 | static int at91_gpio_of_irq_setup(struct device_node *node, |
1470 | struct at91_gpio_chip *at91_gpio) | |
1471 | { | |
6732ae5c | 1472 | struct irq_data *d = irq_get_irq_data(at91_gpio->pioc_virq); |
80cc3732 | 1473 | int ret; |
6732ae5c JCPV |
1474 | |
1475 | at91_gpio->pioc_hwirq = irqd_to_hwirq(d); | |
1476 | ||
1477 | /* Setup proper .irq_set_type function */ | |
1478 | gpio_irqchip.irq_set_type = at91_gpio->ops->irq_type; | |
1479 | ||
1480 | /* Disable irqs of this PIO controller */ | |
1481 | writel_relaxed(~0, at91_gpio->regbase + PIO_IDR); | |
1482 | ||
80cc3732 AS |
1483 | /* |
1484 | * Let the generic code handle this edge IRQ, the the chained | |
1485 | * handler will perform the actual work of handling the parent | |
1486 | * interrupt. | |
1487 | */ | |
1488 | ret = gpiochip_irqchip_add(&at91_gpio->chip, | |
1489 | &gpio_irqchip, | |
1490 | 0, | |
1491 | handle_edge_irq, | |
1492 | IRQ_TYPE_EDGE_BOTH); | |
1493 | if (ret) | |
6732ae5c JCPV |
1494 | panic("at91_gpio.%d: couldn't allocate irq domain (DT).\n", |
1495 | at91_gpio->pioc_idx); | |
1496 | ||
80cc3732 AS |
1497 | /* Then register the chain on the parent IRQ */ |
1498 | gpiochip_set_chained_irqchip(&at91_gpio->chip, | |
1499 | &gpio_irqchip, | |
1500 | at91_gpio->pioc_virq, | |
1501 | gpio_irq_handler); | |
6732ae5c JCPV |
1502 | |
1503 | return 0; | |
1504 | } | |
1505 | ||
1506 | /* This structure is replicated for each GPIO block allocated at probe time */ | |
1507 | static struct gpio_chip at91_gpio_template = { | |
1508 | .request = at91_gpio_request, | |
1509 | .free = at91_gpio_free, | |
8af584b8 | 1510 | .get_direction = at91_gpio_get_direction, |
6732ae5c JCPV |
1511 | .direction_input = at91_gpio_direction_input, |
1512 | .get = at91_gpio_get, | |
1513 | .direction_output = at91_gpio_direction_output, | |
1514 | .set = at91_gpio_set, | |
6732ae5c | 1515 | .dbg_show = at91_gpio_dbg_show, |
9fb1f39e | 1516 | .can_sleep = false, |
6732ae5c JCPV |
1517 | .ngpio = MAX_NB_GPIO_PER_BANK, |
1518 | }; | |
1519 | ||
150632b0 | 1520 | static void at91_gpio_probe_fixup(void) |
6732ae5c JCPV |
1521 | { |
1522 | unsigned i; | |
1523 | struct at91_gpio_chip *at91_gpio, *last = NULL; | |
1524 | ||
1525 | for (i = 0; i < gpio_banks; i++) { | |
1526 | at91_gpio = gpio_chips[i]; | |
1527 | ||
1528 | /* | |
1529 | * GPIO controller are grouped on some SoC: | |
1530 | * PIOC, PIOD and PIOE can share the same IRQ line | |
1531 | */ | |
1532 | if (last && last->pioc_virq == at91_gpio->pioc_virq) | |
1533 | last->next = at91_gpio; | |
1534 | last = at91_gpio; | |
1535 | } | |
1536 | } | |
1537 | ||
150632b0 | 1538 | static struct of_device_id at91_gpio_of_match[] = { |
6732ae5c JCPV |
1539 | { .compatible = "atmel,at91sam9x5-gpio", .data = &at91sam9x5_ops, }, |
1540 | { .compatible = "atmel,at91rm9200-gpio", .data = &at91rm9200_ops }, | |
1541 | { /* sentinel */ } | |
1542 | }; | |
1543 | ||
150632b0 | 1544 | static int at91_gpio_probe(struct platform_device *pdev) |
6732ae5c JCPV |
1545 | { |
1546 | struct device_node *np = pdev->dev.of_node; | |
1547 | struct resource *res; | |
1548 | struct at91_gpio_chip *at91_chip = NULL; | |
1549 | struct gpio_chip *chip; | |
1550 | struct pinctrl_gpio_range *range; | |
1551 | int ret = 0; | |
32b01a36 | 1552 | int irq, i; |
6732ae5c JCPV |
1553 | int alias_idx = of_alias_get_id(np, "gpio"); |
1554 | uint32_t ngpio; | |
32b01a36 | 1555 | char **names; |
6732ae5c JCPV |
1556 | |
1557 | BUG_ON(alias_idx >= ARRAY_SIZE(gpio_chips)); | |
1558 | if (gpio_chips[alias_idx]) { | |
1559 | ret = -EBUSY; | |
1560 | goto err; | |
1561 | } | |
1562 | ||
6732ae5c JCPV |
1563 | irq = platform_get_irq(pdev, 0); |
1564 | if (irq < 0) { | |
1565 | ret = irq; | |
1566 | goto err; | |
1567 | } | |
1568 | ||
1569 | at91_chip = devm_kzalloc(&pdev->dev, sizeof(*at91_chip), GFP_KERNEL); | |
1570 | if (!at91_chip) { | |
1571 | ret = -ENOMEM; | |
1572 | goto err; | |
1573 | } | |
1574 | ||
f50b9e12 | 1575 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
9e0c1fb2 TR |
1576 | at91_chip->regbase = devm_ioremap_resource(&pdev->dev, res); |
1577 | if (IS_ERR(at91_chip->regbase)) { | |
1578 | ret = PTR_ERR(at91_chip->regbase); | |
6732ae5c JCPV |
1579 | goto err; |
1580 | } | |
1581 | ||
3c93600d | 1582 | at91_chip->ops = (struct at91_pinctrl_mux_ops *) |
6732ae5c JCPV |
1583 | of_match_device(at91_gpio_of_match, &pdev->dev)->data; |
1584 | at91_chip->pioc_virq = irq; | |
1585 | at91_chip->pioc_idx = alias_idx; | |
1586 | ||
1587 | at91_chip->clock = clk_get(&pdev->dev, NULL); | |
1588 | if (IS_ERR(at91_chip->clock)) { | |
1589 | dev_err(&pdev->dev, "failed to get clock, ignoring.\n"); | |
1590 | goto err; | |
1591 | } | |
1592 | ||
1593 | if (clk_prepare(at91_chip->clock)) | |
1594 | goto clk_prep_err; | |
1595 | ||
1596 | /* enable PIO controller's clock */ | |
1597 | if (clk_enable(at91_chip->clock)) { | |
1598 | dev_err(&pdev->dev, "failed to enable clock, ignoring.\n"); | |
1599 | goto clk_err; | |
1600 | } | |
1601 | ||
1602 | at91_chip->chip = at91_gpio_template; | |
1603 | ||
1604 | chip = &at91_chip->chip; | |
1605 | chip->of_node = np; | |
1606 | chip->label = dev_name(&pdev->dev); | |
1607 | chip->dev = &pdev->dev; | |
1608 | chip->owner = THIS_MODULE; | |
1609 | chip->base = alias_idx * MAX_NB_GPIO_PER_BANK; | |
1610 | ||
1611 | if (!of_property_read_u32(np, "#gpio-lines", &ngpio)) { | |
1612 | if (ngpio >= MAX_NB_GPIO_PER_BANK) | |
1613 | pr_err("at91_gpio.%d, gpio-nb >= %d failback to %d\n", | |
1614 | alias_idx, MAX_NB_GPIO_PER_BANK, MAX_NB_GPIO_PER_BANK); | |
1615 | else | |
1616 | chip->ngpio = ngpio; | |
1617 | } | |
1618 | ||
3c93600d SK |
1619 | names = devm_kzalloc(&pdev->dev, sizeof(char *) * chip->ngpio, |
1620 | GFP_KERNEL); | |
32b01a36 JCPV |
1621 | |
1622 | if (!names) { | |
1623 | ret = -ENOMEM; | |
1624 | goto clk_err; | |
1625 | } | |
1626 | ||
1627 | for (i = 0; i < chip->ngpio; i++) | |
1628 | names[i] = kasprintf(GFP_KERNEL, "pio%c%d", alias_idx + 'A', i); | |
1629 | ||
3c93600d | 1630 | chip->names = (const char *const *)names; |
32b01a36 | 1631 | |
6732ae5c JCPV |
1632 | range = &at91_chip->range; |
1633 | range->name = chip->label; | |
1634 | range->id = alias_idx; | |
1635 | range->pin_base = range->base = range->id * MAX_NB_GPIO_PER_BANK; | |
1636 | ||
1637 | range->npins = chip->ngpio; | |
1638 | range->gc = chip; | |
1639 | ||
1640 | ret = gpiochip_add(chip); | |
1641 | if (ret) | |
1642 | goto clk_err; | |
1643 | ||
1644 | gpio_chips[alias_idx] = at91_chip; | |
1645 | gpio_banks = max(gpio_banks, alias_idx + 1); | |
1646 | ||
1647 | at91_gpio_probe_fixup(); | |
1648 | ||
1649 | at91_gpio_of_irq_setup(np, at91_chip); | |
1650 | ||
1651 | dev_info(&pdev->dev, "at address %p\n", at91_chip->regbase); | |
1652 | ||
1653 | return 0; | |
1654 | ||
1655 | clk_err: | |
1656 | clk_unprepare(at91_chip->clock); | |
1657 | clk_prep_err: | |
1658 | clk_put(at91_chip->clock); | |
1659 | err: | |
1660 | dev_err(&pdev->dev, "Failure %i for GPIO %i\n", ret, alias_idx); | |
1661 | ||
1662 | return ret; | |
1663 | } | |
1664 | ||
1665 | static struct platform_driver at91_gpio_driver = { | |
1666 | .driver = { | |
1667 | .name = "gpio-at91", | |
1668 | .owner = THIS_MODULE, | |
606fca94 | 1669 | .of_match_table = at91_gpio_of_match, |
6732ae5c JCPV |
1670 | }, |
1671 | .probe = at91_gpio_probe, | |
1672 | }; | |
1673 | ||
1674 | static struct platform_driver at91_pinctrl_driver = { | |
1675 | .driver = { | |
1676 | .name = "pinctrl-at91", | |
1677 | .owner = THIS_MODULE, | |
606fca94 | 1678 | .of_match_table = at91_pinctrl_of_match, |
6732ae5c JCPV |
1679 | }, |
1680 | .probe = at91_pinctrl_probe, | |
150632b0 | 1681 | .remove = at91_pinctrl_remove, |
6732ae5c JCPV |
1682 | }; |
1683 | ||
1684 | static int __init at91_pinctrl_init(void) | |
1685 | { | |
1686 | int ret; | |
1687 | ||
1688 | ret = platform_driver_register(&at91_gpio_driver); | |
1689 | if (ret) | |
1690 | return ret; | |
1691 | return platform_driver_register(&at91_pinctrl_driver); | |
1692 | } | |
1693 | arch_initcall(at91_pinctrl_init); | |
1694 | ||
1695 | static void __exit at91_pinctrl_exit(void) | |
1696 | { | |
1697 | platform_driver_unregister(&at91_pinctrl_driver); | |
1698 | } | |
1699 | ||
1700 | module_exit(at91_pinctrl_exit); | |
1701 | MODULE_AUTHOR("Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>"); | |
1702 | MODULE_DESCRIPTION("Atmel AT91 pinctrl driver"); | |
1703 | MODULE_LICENSE("GPL v2"); |