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Merge branch 'pinmux/next' of git://linuxtv.org/pinchartl/fbdev into devel
[mirror_ubuntu-artful-kernel.git] / drivers / pinctrl / pinctrl-at91.c
CommitLineData
6732ae5c
JCPV		 1/*
2 * at91 pinctrl driver based on at91 pinmux core
3 *
4 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 *
6 * Under GPLv2 only
7 */
8
9#include <linux/clk.h>
10#include <linux/err.h>
11#include <linux/init.h>
12#include <linux/module.h>
13#include <linux/of.h>
14#include <linux/of_device.h>
15#include <linux/of_address.h>
16#include <linux/of_irq.h>
17#include <linux/slab.h>
18#include <linux/interrupt.h>
19#include <linux/irq.h>
20#include <linux/irqdomain.h>
de88cbb7 21#include <linux/irqchip/chained_irq.h>
6732ae5c
JCPV		 22#include <linux/io.h>
23#include <linux/gpio.h>
6732ae5c
JCPV		 24#include <linux/pinctrl/machine.h>
25#include <linux/pinctrl/pinconf.h>
26#include <linux/pinctrl/pinctrl.h>
27#include <linux/pinctrl/pinmux.h>
28/* Since we request GPIOs from ourself */
29#include <linux/pinctrl/consumer.h>
30
6732ae5c
JCPV		 31#include <mach/hardware.h>
32#include <mach/at91_pio.h>
33
34#include "core.h"
35
36#define MAX_NB_GPIO_PER_BANK 32
37
38struct at91_pinctrl_mux_ops;
39
40struct at91_gpio_chip {
41 struct gpio_chip chip;
42 struct pinctrl_gpio_range range;
43 struct at91_gpio_chip *next; /* Bank sharing same clock */
44 int pioc_hwirq; /* PIO bank interrupt identifier on AIC */
45 int pioc_virq; /* PIO bank Linux virtual interrupt */
46 int pioc_idx; /* PIO bank index */
47 void __iomem *regbase; /* PIO bank virtual address */
48 struct clk *clock; /* associated clock */
49 struct irq_domain *domain; /* associated irq domain */
50 struct at91_pinctrl_mux_ops *ops; /* ops */
51};
52
53#define to_at91_gpio_chip(c) container_of(c, struct at91_gpio_chip, chip)
54
55static struct at91_gpio_chip *gpio_chips[MAX_GPIO_BANKS];
56
57static int gpio_banks;
58
525fae21 59#define PULL_UP (1 << 0)
6732ae5c 60#define MULTI_DRIVE (1 << 1)
7ebd7a3a
JCPV		 61#define DEGLITCH (1 << 2)
62#define PULL_DOWN (1 << 3)
63#define DIS_SCHMIT (1 << 4)
64#define DEBOUNCE (1 << 16)
65#define DEBOUNCE_VAL_SHIFT 17
66#define DEBOUNCE_VAL (0x3fff << DEBOUNCE_VAL_SHIFT)
6732ae5c
JCPV		 67
68/**
69 * struct at91_pmx_func - describes AT91 pinmux functions
70 * @name: the name of this specific function
71 * @groups: corresponding pin groups
72 * @ngroups: the number of groups
73 */
74struct at91_pmx_func {
75 const char *name;
76 const char **groups;
77 unsigned ngroups;
78};
79
80enum at91_mux {
81 AT91_MUX_GPIO = 0,
82 AT91_MUX_PERIPH_A = 1,
83 AT91_MUX_PERIPH_B = 2,
84 AT91_MUX_PERIPH_C = 3,
85 AT91_MUX_PERIPH_D = 4,
86};
87
88/**
89 * struct at91_pmx_pin - describes an At91 pin mux
90 * @bank: the bank of the pin
91 * @pin: the pin number in the @bank
92 * @mux: the mux mode : gpio or periph_x of the pin i.e. alternate function.
93 * @conf: the configuration of the pin: PULL_UP, MULTIDRIVE etc...
94 */
95struct at91_pmx_pin {
96 uint32_t bank;
97 uint32_t pin;
98 enum at91_mux mux;
99 unsigned long conf;
100};
101
102/**
103 * struct at91_pin_group - describes an At91 pin group
104 * @name: the name of this specific pin group
105 * @pins_conf: the mux mode for each pin in this group. The size of this
106 * array is the same as pins.
107 * @pins: an array of discrete physical pins used in this group, taken
108 * from the driver-local pin enumeration space
109 * @npins: the number of pins in this group array, i.e. the number of
110 * elements in .pins so we can iterate over that array
111 */
112struct at91_pin_group {
113 const char *name;
114 struct at91_pmx_pin *pins_conf;
115 unsigned int *pins;
116 unsigned npins;
117};
118
119/**
120 * struct at91_pinctrl_mux_ops - describes an At91 mux ops group
121 * on new IP with support for periph C and D the way to mux in
122 * periph A and B has changed
123 * So provide the right call back
124 * if not present means the IP does not support it
125 * @get_periph: return the periph mode configured
126 * @mux_A_periph: mux as periph A
127 * @mux_B_periph: mux as periph B
128 * @mux_C_periph: mux as periph C
129 * @mux_D_periph: mux as periph D
7ebd7a3a
JCPV		 130 * @get_deglitch: get deglitch status
131 * @set_deglitch: enable/disable deglitch
132 * @get_debounce: get debounce status
133 * @set_debounce: enable/disable debounce
134 * @get_pulldown: get pulldown status
135 * @set_pulldown: enable/disable pulldown
136 * @get_schmitt_trig: get schmitt trigger status
137 * @disable_schmitt_trig: disable schmitt trigger
6732ae5c
JCPV		 138 * @irq_type: return irq type
139 */
140struct at91_pinctrl_mux_ops {
141 enum at91_mux (*get_periph)(void __iomem *pio, unsigned mask);
142 void (*mux_A_periph)(void __iomem *pio, unsigned mask);
143 void (*mux_B_periph)(void __iomem *pio, unsigned mask);
144 void (*mux_C_periph)(void __iomem *pio, unsigned mask);
145 void (*mux_D_periph)(void __iomem *pio, unsigned mask);
7ebd7a3a 146 bool (*get_deglitch)(void __iomem *pio, unsigned pin);
77966ad7 147 void (*set_deglitch)(void __iomem *pio, unsigned mask, bool is_on);
7ebd7a3a 148 bool (*get_debounce)(void __iomem *pio, unsigned pin, u32 *div);
77966ad7 149 void (*set_debounce)(void __iomem *pio, unsigned mask, bool is_on, u32 div);
7ebd7a3a 150 bool (*get_pulldown)(void __iomem *pio, unsigned pin);
77966ad7 151 void (*set_pulldown)(void __iomem *pio, unsigned mask, bool is_on);
7ebd7a3a
JCPV		 152 bool (*get_schmitt_trig)(void __iomem *pio, unsigned pin);
153 void (*disable_schmitt_trig)(void __iomem *pio, unsigned mask);
6732ae5c
JCPV		 154 /* irq */
155 int (*irq_type)(struct irq_data *d, unsigned type);
156};
157
158static int gpio_irq_type(struct irq_data *d, unsigned type);
159static int alt_gpio_irq_type(struct irq_data *d, unsigned type);
160
161struct at91_pinctrl {
162 struct device *dev;
163 struct pinctrl_dev *pctl;
164
165 int nbanks;
166
167 uint32_t *mux_mask;
168 int nmux;
169
170 struct at91_pmx_func *functions;
171 int nfunctions;
172
173 struct at91_pin_group *groups;
174 int ngroups;
175
176 struct at91_pinctrl_mux_ops *ops;
177};
178
179static const inline struct at91_pin_group *at91_pinctrl_find_group_by_name(
180 const struct at91_pinctrl *info,
181 const char *name)
182{
183 const struct at91_pin_group *grp = NULL;
184 int i;
185
186 for (i = 0; i < info->ngroups; i++) {
187 if (strcmp(info->groups[i].name, name))
188 continue;
189
190 grp = &info->groups[i];
191 dev_dbg(info->dev, "%s: %d 0:%d\n", name, grp->npins, grp->pins[0]);
192 break;
193 }
194
195 return grp;
196}
197
198static int at91_get_groups_count(struct pinctrl_dev *pctldev)
199{
200 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
201
202 return info->ngroups;
203}
204
205static const char *at91_get_group_name(struct pinctrl_dev *pctldev,
206 unsigned selector)
207{
208 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
209
210 return info->groups[selector].name;
211}
212
213static int at91_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
214 const unsigned **pins,
215 unsigned *npins)
216{
217 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
218
219 if (selector >= info->ngroups)
220 return -EINVAL;
221
222 *pins = info->groups[selector].pins;
223 *npins = info->groups[selector].npins;
224
225 return 0;
226}
227
228static void at91_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
229 unsigned offset)
230{
231 seq_printf(s, "%s", dev_name(pctldev->dev));
232}
233
234static int at91_dt_node_to_map(struct pinctrl_dev *pctldev,
235 struct device_node *np,
236 struct pinctrl_map **map, unsigned *num_maps)
237{
238 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
239 const struct at91_pin_group *grp;
240 struct pinctrl_map *new_map;
241 struct device_node *parent;
242 int map_num = 1;
243 int i;
6732ae5c
JCPV		 244
245 /*
246 * first find the group of this node and check if we need create
247 * config maps for pins
248 */
249 grp = at91_pinctrl_find_group_by_name(info, np->name);
250 if (!grp) {
251 dev_err(info->dev, "unable to find group for node %s\n",
252 np->name);
253 return -EINVAL;
254 }
255
256 map_num += grp->npins;
257 new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num, GFP_KERNEL);
258 if (!new_map)
259 return -ENOMEM;
260
261 *map = new_map;
262 *num_maps = map_num;
263
264 /* create mux map */
265 parent = of_get_parent(np);
266 if (!parent) {
c62b2b34 267 devm_kfree(pctldev->dev, new_map);
6732ae5c
JCPV		 268 return -EINVAL;
269 }
270 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
271 new_map[0].data.mux.function = parent->name;
272 new_map[0].data.mux.group = np->name;
273 of_node_put(parent);
274
275 /* create config map */
276 new_map++;
277 for (i = 0; i < grp->npins; i++) {
6732ae5c
JCPV		 278 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
279 new_map[i].data.configs.group_or_pin =
280 pin_get_name(pctldev, grp->pins[i]);
281 new_map[i].data.configs.configs = &grp->pins_conf[i].conf;
282 new_map[i].data.configs.num_configs = 1;
283 }
284
285 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
286 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
287
288 return 0;
289}
290
291static void at91_dt_free_map(struct pinctrl_dev *pctldev,
292 struct pinctrl_map *map, unsigned num_maps)
293{
294}
295
022ab148 296static const struct pinctrl_ops at91_pctrl_ops = {
6732ae5c
JCPV		 297 .get_groups_count = at91_get_groups_count,
298 .get_group_name = at91_get_group_name,
299 .get_group_pins = at91_get_group_pins,
300 .pin_dbg_show = at91_pin_dbg_show,
301 .dt_node_to_map = at91_dt_node_to_map,
302 .dt_free_map = at91_dt_free_map,
303};
304
3c93600d 305static void __iomem *pin_to_controller(struct at91_pinctrl *info,
6732ae5c
JCPV		 306 unsigned int bank)
307{
308 return gpio_chips[bank]->regbase;
309}
310
311static inline int pin_to_bank(unsigned pin)
312{
313 return pin /= MAX_NB_GPIO_PER_BANK;
314}
315
316static unsigned pin_to_mask(unsigned int pin)
317{
318 return 1 << pin;
319}
320
321static void at91_mux_disable_interrupt(void __iomem *pio, unsigned mask)
322{
323 writel_relaxed(mask, pio + PIO_IDR);
324}
325
326static unsigned at91_mux_get_pullup(void __iomem *pio, unsigned pin)
327{
05d3534a 328 return !((readl_relaxed(pio + PIO_PUSR) >> pin) & 0x1);
6732ae5c
JCPV		 329}
330
331static void at91_mux_set_pullup(void __iomem *pio, unsigned mask, bool on)
332{
333 writel_relaxed(mask, pio + (on ? PIO_PUER : PIO_PUDR));
334}
335
336static unsigned at91_mux_get_multidrive(void __iomem *pio, unsigned pin)
337{
338 return (readl_relaxed(pio + PIO_MDSR) >> pin) & 0x1;
339}
340
341static void at91_mux_set_multidrive(void __iomem *pio, unsigned mask, bool on)
342{
343 writel_relaxed(mask, pio + (on ? PIO_MDER : PIO_MDDR));
344}
345
346static void at91_mux_set_A_periph(void __iomem *pio, unsigned mask)
347{
348 writel_relaxed(mask, pio + PIO_ASR);
349}
350
351static void at91_mux_set_B_periph(void __iomem *pio, unsigned mask)
352{
353 writel_relaxed(mask, pio + PIO_BSR);
354}
355
356static void at91_mux_pio3_set_A_periph(void __iomem *pio, unsigned mask)
357{
358
359 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask,
360 pio + PIO_ABCDSR1);
361 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask,
362 pio + PIO_ABCDSR2);
363}
364
365static void at91_mux_pio3_set_B_periph(void __iomem *pio, unsigned mask)
366{
367 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask,
368 pio + PIO_ABCDSR1);
369 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask,
370 pio + PIO_ABCDSR2);
371}
372
373static void at91_mux_pio3_set_C_periph(void __iomem *pio, unsigned mask)
374{
375 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask, pio + PIO_ABCDSR1);
376 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
377}
378
379static void at91_mux_pio3_set_D_periph(void __iomem *pio, unsigned mask)
380{
381 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask, pio + PIO_ABCDSR1);
382 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
383}
384
385static enum at91_mux at91_mux_pio3_get_periph(void __iomem *pio, unsigned mask)
386{
387 unsigned select;
388
389 if (readl_relaxed(pio + PIO_PSR) & mask)
390 return AT91_MUX_GPIO;
391
392 select = !!(readl_relaxed(pio + PIO_ABCDSR1) & mask);
393 select |= (!!(readl_relaxed(pio + PIO_ABCDSR2) & mask) << 1);
394
395 return select + 1;
396}
397
398static enum at91_mux at91_mux_get_periph(void __iomem *pio, unsigned mask)
399{
400 unsigned select;
401
402 if (readl_relaxed(pio + PIO_PSR) & mask)
403 return AT91_MUX_GPIO;
404
405 select = readl_relaxed(pio + PIO_ABSR) & mask;
406
407 return select + 1;
408}
409
7ebd7a3a
JCPV		 410static bool at91_mux_get_deglitch(void __iomem *pio, unsigned pin)
411{
412 return (__raw_readl(pio + PIO_IFSR) >> pin) & 0x1;
413}
414
415static void at91_mux_set_deglitch(void __iomem *pio, unsigned mask, bool is_on)
416{
417 __raw_writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR));
418}
419
c8dba02e
BB		 420static bool at91_mux_pio3_get_deglitch(void __iomem *pio, unsigned pin)
421{
422 if ((__raw_readl(pio + PIO_IFSR) >> pin) & 0x1)
423 return !((__raw_readl(pio + PIO_IFSCSR) >> pin) & 0x1);
424
425 return false;
426}
427
7ebd7a3a
JCPV		 428static void at91_mux_pio3_set_deglitch(void __iomem *pio, unsigned mask, bool is_on)
429{
430 if (is_on)
431 __raw_writel(mask, pio + PIO_IFSCDR);
432 at91_mux_set_deglitch(pio, mask, is_on);
433}
434
435static bool at91_mux_pio3_get_debounce(void __iomem *pio, unsigned pin, u32 *div)
436{
437 *div = __raw_readl(pio + PIO_SCDR);
438
c8dba02e
BB		 439 return ((__raw_readl(pio + PIO_IFSR) >> pin) & 0x1) &&
440 ((__raw_readl(pio + PIO_IFSCSR) >> pin) & 0x1);
7ebd7a3a
JCPV		 441}
442
443static void at91_mux_pio3_set_debounce(void __iomem *pio, unsigned mask,
444 bool is_on, u32 div)
445{
446 if (is_on) {
447 __raw_writel(mask, pio + PIO_IFSCER);
448 __raw_writel(div & PIO_SCDR_DIV, pio + PIO_SCDR);
449 __raw_writel(mask, pio + PIO_IFER);
c8dba02e
BB		 450 } else
451 __raw_writel(mask, pio + PIO_IFSCDR);
7ebd7a3a
JCPV		 452}
453
454static bool at91_mux_pio3_get_pulldown(void __iomem *pio, unsigned pin)
455{
05d3534a 456 return !((__raw_readl(pio + PIO_PPDSR) >> pin) & 0x1);
7ebd7a3a
JCPV		 457}
458
459static void at91_mux_pio3_set_pulldown(void __iomem *pio, unsigned mask, bool is_on)
460{
461 __raw_writel(mask, pio + (is_on ? PIO_PPDER : PIO_PPDDR));
462}
463
464static void at91_mux_pio3_disable_schmitt_trig(void __iomem *pio, unsigned mask)
465{
466 __raw_writel(__raw_readl(pio + PIO_SCHMITT) | mask, pio + PIO_SCHMITT);
467}
468
469static bool at91_mux_pio3_get_schmitt_trig(void __iomem *pio, unsigned pin)
470{
471 return (__raw_readl(pio + PIO_SCHMITT) >> pin) & 0x1;
472}
473
6732ae5c
JCPV		 474static struct at91_pinctrl_mux_ops at91rm9200_ops = {
475 .get_periph = at91_mux_get_periph,
476 .mux_A_periph = at91_mux_set_A_periph,
477 .mux_B_periph = at91_mux_set_B_periph,
7ebd7a3a
JCPV		 478 .get_deglitch = at91_mux_get_deglitch,
479 .set_deglitch = at91_mux_set_deglitch,
6732ae5c
JCPV		 480 .irq_type = gpio_irq_type,
481};
482
483static struct at91_pinctrl_mux_ops at91sam9x5_ops = {
484 .get_periph = at91_mux_pio3_get_periph,
485 .mux_A_periph = at91_mux_pio3_set_A_periph,
486 .mux_B_periph = at91_mux_pio3_set_B_periph,
487 .mux_C_periph = at91_mux_pio3_set_C_periph,
488 .mux_D_periph = at91_mux_pio3_set_D_periph,
c8dba02e 489 .get_deglitch = at91_mux_pio3_get_deglitch,
7ebd7a3a
JCPV		 490 .set_deglitch = at91_mux_pio3_set_deglitch,
491 .get_debounce = at91_mux_pio3_get_debounce,
492 .set_debounce = at91_mux_pio3_set_debounce,
493 .get_pulldown = at91_mux_pio3_get_pulldown,
494 .set_pulldown = at91_mux_pio3_set_pulldown,
495 .get_schmitt_trig = at91_mux_pio3_get_schmitt_trig,
496 .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
6732ae5c
JCPV		 497 .irq_type = alt_gpio_irq_type,
498};
499
500static void at91_pin_dbg(const struct device *dev, const struct at91_pmx_pin *pin)
501{
502 if (pin->mux) {
503 dev_dbg(dev, "pio%c%d configured as periph%c with conf = 0x%lu\n",
504 pin->bank + 'A', pin->pin, pin->mux - 1 + 'A', pin->conf);
505 } else {
506 dev_dbg(dev, "pio%c%d configured as gpio with conf = 0x%lu\n",
507 pin->bank + 'A', pin->pin, pin->conf);
508 }
509}
510
3c93600d 511static int pin_check_config(struct at91_pinctrl *info, const char *name,
6732ae5c
JCPV		 512 int index, const struct at91_pmx_pin *pin)
513{
514 int mux;
515
516 /* check if it's a valid config */
517 if (pin->bank >= info->nbanks) {
518 dev_err(info->dev, "%s: pin conf %d bank_id %d >= nbanks %d\n",
519 name, index, pin->bank, info->nbanks);
520 return -EINVAL;
521 }
522
523 if (pin->pin >= MAX_NB_GPIO_PER_BANK) {
524 dev_err(info->dev, "%s: pin conf %d pin_bank_id %d >= %d\n",
525 name, index, pin->pin, MAX_NB_GPIO_PER_BANK);
526 return -EINVAL;
527 }
528
529 if (!pin->mux)
530 return 0;
531
532 mux = pin->mux - 1;
533
534 if (mux >= info->nmux) {
535 dev_err(info->dev, "%s: pin conf %d mux_id %d >= nmux %d\n",
536 name, index, mux, info->nmux);
537 return -EINVAL;
538 }
539
540 if (!(info->mux_mask[pin->bank * info->nmux + mux] & 1 << pin->pin)) {
541 dev_err(info->dev, "%s: pin conf %d mux_id %d not supported for pio%c%d\n",
542 name, index, mux, pin->bank + 'A', pin->pin);
543 return -EINVAL;
544 }
545
546 return 0;
547}
548
549static void at91_mux_gpio_disable(void __iomem *pio, unsigned mask)
550{
551 writel_relaxed(mask, pio + PIO_PDR);
552}
553
554static void at91_mux_gpio_enable(void __iomem *pio, unsigned mask, bool input)
555{
556 writel_relaxed(mask, pio + PIO_PER);
557 writel_relaxed(mask, pio + (input ? PIO_ODR : PIO_OER));
558}
559
560static int at91_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
561 unsigned group)
562{
563 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
564 const struct at91_pmx_pin *pins_conf = info->groups[group].pins_conf;
565 const struct at91_pmx_pin *pin;
566 uint32_t npins = info->groups[group].npins;
567 int i, ret;
568 unsigned mask;
569 void __iomem *pio;
570
571 dev_dbg(info->dev, "enable function %s group %s\n",
572 info->functions[selector].name, info->groups[group].name);
573
574 /* first check that all the pins of the group are valid with a valid
575 * paramter */
576 for (i = 0; i < npins; i++) {
577 pin = &pins_conf[i];
578 ret = pin_check_config(info, info->groups[group].name, i, pin);
579 if (ret)
580 return ret;
581 }
582
583 for (i = 0; i < npins; i++) {
584 pin = &pins_conf[i];
585 at91_pin_dbg(info->dev, pin);
586 pio = pin_to_controller(info, pin->bank);
587 mask = pin_to_mask(pin->pin);
588 at91_mux_disable_interrupt(pio, mask);
3c93600d 589 switch (pin->mux) {
6732ae5c
JCPV		 590 case AT91_MUX_GPIO:
591 at91_mux_gpio_enable(pio, mask, 1);
592 break;
593 case AT91_MUX_PERIPH_A:
594 info->ops->mux_A_periph(pio, mask);
595 break;
596 case AT91_MUX_PERIPH_B:
597 info->ops->mux_B_periph(pio, mask);
598 break;
599 case AT91_MUX_PERIPH_C:
600 if (!info->ops->mux_C_periph)
601 return -EINVAL;
602 info->ops->mux_C_periph(pio, mask);
603 break;
604 case AT91_MUX_PERIPH_D:
605 if (!info->ops->mux_D_periph)
606 return -EINVAL;
607 info->ops->mux_D_periph(pio, mask);
608 break;
609 }
610 if (pin->mux)
611 at91_mux_gpio_disable(pio, mask);
612 }
613
614 return 0;
615}
616
617static void at91_pmx_disable(struct pinctrl_dev *pctldev, unsigned selector,
618 unsigned group)
619{
620 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
621 const struct at91_pmx_pin *pins_conf = info->groups[group].pins_conf;
622 const struct at91_pmx_pin *pin;
623 uint32_t npins = info->groups[group].npins;
624 int i;
625 unsigned mask;
626 void __iomem *pio;
627
628 for (i = 0; i < npins; i++) {
629 pin = &pins_conf[i];
630 at91_pin_dbg(info->dev, pin);
631 pio = pin_to_controller(info, pin->bank);
632 mask = pin_to_mask(pin->pin);
633 at91_mux_gpio_enable(pio, mask, 1);
634 }
635}
636
637static int at91_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
638{
639 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
640
641 return info->nfunctions;
642}
643
644static const char *at91_pmx_get_func_name(struct pinctrl_dev *pctldev,
645 unsigned selector)
646{
647 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
648
649 return info->functions[selector].name;
650}
651
652static int at91_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
653 const char * const **groups,
654 unsigned * const num_groups)
655{
656 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
657
658 *groups = info->functions[selector].groups;
659 *num_groups = info->functions[selector].ngroups;
660
661 return 0;
662}
663
f6f94f66
AL		 664static int at91_gpio_request_enable(struct pinctrl_dev *pctldev,
665 struct pinctrl_gpio_range *range,
666 unsigned offset)
6732ae5c
JCPV		 667{
668 struct at91_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
669 struct at91_gpio_chip *at91_chip;
670 struct gpio_chip *chip;
671 unsigned mask;
672
673 if (!range) {
674 dev_err(npct->dev, "invalid range\n");
675 return -EINVAL;
676 }
677 if (!range->gc) {
678 dev_err(npct->dev, "missing GPIO chip in range\n");
679 return -EINVAL;
680 }
681 chip = range->gc;
682 at91_chip = container_of(chip, struct at91_gpio_chip, chip);
683
684 dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset);
685
686 mask = 1 << (offset - chip->base);
687
688 dev_dbg(npct->dev, "enable pin %u as PIO%c%d 0x%x\n",
689 offset, 'A' + range->id, offset - chip->base, mask);
690
691 writel_relaxed(mask, at91_chip->regbase + PIO_PER);
692
693 return 0;
694}
695
f6f94f66
AL		 696static void at91_gpio_disable_free(struct pinctrl_dev *pctldev,
697 struct pinctrl_gpio_range *range,
698 unsigned offset)
6732ae5c
JCPV		 699{
700 struct at91_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
701
702 dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset);
703 /* Set the pin to some default state, GPIO is usually default */
704}
705
022ab148 706static const struct pinmux_ops at91_pmx_ops = {
6732ae5c
JCPV		 707 .get_functions_count = at91_pmx_get_funcs_count,
708 .get_function_name = at91_pmx_get_func_name,
709 .get_function_groups = at91_pmx_get_groups,
710 .enable = at91_pmx_enable,
711 .disable = at91_pmx_disable,
712 .gpio_request_enable = at91_gpio_request_enable,
713 .gpio_disable_free = at91_gpio_disable_free,
714};
715
716static int at91_pinconf_get(struct pinctrl_dev *pctldev,
717 unsigned pin_id, unsigned long *config)
718{
719 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
720 void __iomem *pio;
721 unsigned pin;
7ebd7a3a 722 int div;
6732ae5c
JCPV		 723
724 dev_dbg(info->dev, "%s:%d, pin_id=%d, config=0x%lx", __func__, __LINE__, pin_id, *config);
725 pio = pin_to_controller(info, pin_to_bank(pin_id));
726 pin = pin_id % MAX_NB_GPIO_PER_BANK;
727
728 if (at91_mux_get_multidrive(pio, pin))
729 *config |= MULTI_DRIVE;
730
731 if (at91_mux_get_pullup(pio, pin))
732 *config |= PULL_UP;
733
7ebd7a3a
JCPV		 734 if (info->ops->get_deglitch && info->ops->get_deglitch(pio, pin))
735 *config |= DEGLITCH;
736 if (info->ops->get_debounce && info->ops->get_debounce(pio, pin, &div))
737 *config |= DEBOUNCE | (div << DEBOUNCE_VAL_SHIFT);
738 if (info->ops->get_pulldown && info->ops->get_pulldown(pio, pin))
739 *config |= PULL_DOWN;
740 if (info->ops->get_schmitt_trig && info->ops->get_schmitt_trig(pio, pin))
741 *config |= DIS_SCHMIT;
742
6732ae5c
JCPV		 743 return 0;
744}
745
746static int at91_pinconf_set(struct pinctrl_dev *pctldev,
03b054e9
SY		 747 unsigned pin_id, unsigned long *configs,
748 unsigned num_configs)
6732ae5c
JCPV		 749{
750 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
751 unsigned mask;
752 void __iomem *pio;
03b054e9
SY		 753 int i;
754 unsigned long config;
755
756 for (i = 0; i < num_configs; i++) {
757 config = configs[i];
758
759 dev_dbg(info->dev,
760 "%s:%d, pin_id=%d, config=0x%lx",
761 __func__, __LINE__, pin_id, config);
762 pio = pin_to_controller(info, pin_to_bank(pin_id));
763 mask = pin_to_mask(pin_id % MAX_NB_GPIO_PER_BANK);
764
765 if (config & PULL_UP && config & PULL_DOWN)
766 return -EINVAL;
767
768 at91_mux_set_pullup(pio, mask, config & PULL_UP);
769 at91_mux_set_multidrive(pio, mask, config & MULTI_DRIVE);
770 if (info->ops->set_deglitch)
771 info->ops->set_deglitch(pio, mask, config & DEGLITCH);
772 if (info->ops->set_debounce)
773 info->ops->set_debounce(pio, mask, config & DEBOUNCE,
7ebd7a3a 774 (config & DEBOUNCE_VAL) >> DEBOUNCE_VAL_SHIFT);
03b054e9
SY		 775 if (info->ops->set_pulldown)
776 info->ops->set_pulldown(pio, mask, config & PULL_DOWN);
777 if (info->ops->disable_schmitt_trig && config & DIS_SCHMIT)
778 info->ops->disable_schmitt_trig(pio, mask);
779
780 } /* for each config */
7ebd7a3a 781
6732ae5c
JCPV		 782 return 0;
783}
784
785static void at91_pinconf_dbg_show(struct pinctrl_dev *pctldev,
786 struct seq_file *s, unsigned pin_id)
787{
788
789}
790
791static void at91_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
792 struct seq_file *s, unsigned group)
793{
794}
795
022ab148 796static const struct pinconf_ops at91_pinconf_ops = {
6732ae5c
JCPV		 797 .pin_config_get = at91_pinconf_get,
798 .pin_config_set = at91_pinconf_set,
799 .pin_config_dbg_show = at91_pinconf_dbg_show,
800 .pin_config_group_dbg_show = at91_pinconf_group_dbg_show,
801};
802
803static struct pinctrl_desc at91_pinctrl_desc = {
804 .pctlops = &at91_pctrl_ops,
805 .pmxops = &at91_pmx_ops,
806 .confops = &at91_pinconf_ops,
807 .owner = THIS_MODULE,
808};
809
810static const char *gpio_compat = "atmel,at91rm9200-gpio";
811
150632b0
GKH		 812static void at91_pinctrl_child_count(struct at91_pinctrl *info,
813 struct device_node *np)
6732ae5c
JCPV		 814{
815 struct device_node *child;
816
817 for_each_child_of_node(np, child) {
818 if (of_device_is_compatible(child, gpio_compat)) {
819 info->nbanks++;
820 } else {
821 info->nfunctions++;
822 info->ngroups += of_get_child_count(child);
823 }
824 }
825}
826
150632b0
GKH		 827static int at91_pinctrl_mux_mask(struct at91_pinctrl *info,
828 struct device_node *np)
6732ae5c
JCPV		 829{
830 int ret = 0;
831 int size;
1164d73a 832 const __be32 *list;
6732ae5c
JCPV		 833
834 list = of_get_property(np, "atmel,mux-mask", &size);
835 if (!list) {
836 dev_err(info->dev, "can not read the mux-mask of %d\n", size);
837 return -EINVAL;
838 }
839
840 size /= sizeof(*list);
841 if (!size || size % info->nbanks) {
842 dev_err(info->dev, "wrong mux mask array should be by %d\n", info->nbanks);
843 return -EINVAL;
844 }
845 info->nmux = size / info->nbanks;
846
847 info->mux_mask = devm_kzalloc(info->dev, sizeof(u32) * size, GFP_KERNEL);
848 if (!info->mux_mask) {
849 dev_err(info->dev, "could not alloc mux_mask\n");
850 return -ENOMEM;
851 }
852
853 ret = of_property_read_u32_array(np, "atmel,mux-mask",
854 info->mux_mask, size);
855 if (ret)
856 dev_err(info->dev, "can not read the mux-mask of %d\n", size);
857 return ret;
858}
859
150632b0
GKH		 860static int at91_pinctrl_parse_groups(struct device_node *np,
861 struct at91_pin_group *grp,
862 struct at91_pinctrl *info, u32 index)
6732ae5c
JCPV		 863{
864 struct at91_pmx_pin *pin;
865 int size;
1164d73a 866 const __be32 *list;
6732ae5c
JCPV		 867 int i, j;
868
869 dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
870
871 /* Initialise group */
872 grp->name = np->name;
873
874 /*
875 * the binding format is atmel,pins = <bank pin mux CONFIG ...>,
876 * do sanity check and calculate pins number
877 */
878 list = of_get_property(np, "atmel,pins", &size);
879 /* we do not check return since it's safe node passed down */
880 size /= sizeof(*list);
881 if (!size || size % 4) {
882 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
883 return -EINVAL;
884 }
885
886 grp->npins = size / 4;
887 pin = grp->pins_conf = devm_kzalloc(info->dev, grp->npins * sizeof(struct at91_pmx_pin),
888 GFP_KERNEL);
889 grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
890 GFP_KERNEL);
891 if (!grp->pins_conf || !grp->pins)
892 return -ENOMEM;
893
894 for (i = 0, j = 0; i < size; i += 4, j++) {
895 pin->bank = be32_to_cpu(*list++);
896 pin->pin = be32_to_cpu(*list++);
897 grp->pins[j] = pin->bank * MAX_NB_GPIO_PER_BANK + pin->pin;
898 pin->mux = be32_to_cpu(*list++);
899 pin->conf = be32_to_cpu(*list++);
900
901 at91_pin_dbg(info->dev, pin);
902 pin++;
903 }
904
905 return 0;
906}
907
150632b0
GKH		 908static int at91_pinctrl_parse_functions(struct device_node *np,
909 struct at91_pinctrl *info, u32 index)
6732ae5c
JCPV		 910{
911 struct device_node *child;
912 struct at91_pmx_func *func;
913 struct at91_pin_group *grp;
914 int ret;
915 static u32 grp_index;
916 u32 i = 0;
917
918 dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
919
920 func = &info->functions[index];
921
922 /* Initialise function */
923 func->name = np->name;
924 func->ngroups = of_get_child_count(np);
925 if (func->ngroups <= 0) {
926 dev_err(info->dev, "no groups defined\n");
927 return -EINVAL;
928 }
929 func->groups = devm_kzalloc(info->dev,
930 func->ngroups * sizeof(char *), GFP_KERNEL);
931 if (!func->groups)
932 return -ENOMEM;
933
934 for_each_child_of_node(np, child) {
935 func->groups[i] = child->name;
936 grp = &info->groups[grp_index++];
937 ret = at91_pinctrl_parse_groups(child, grp, info, i++);
938 if (ret)
939 return ret;
940 }
941
942 return 0;
943}
944
150632b0 945static struct of_device_id at91_pinctrl_of_match[] = {
6732ae5c
JCPV		 946 { .compatible = "atmel,at91sam9x5-pinctrl", .data = &at91sam9x5_ops },
947 { .compatible = "atmel,at91rm9200-pinctrl", .data = &at91rm9200_ops },
948 { /* sentinel */ }
949};
950
150632b0
GKH		 951static int at91_pinctrl_probe_dt(struct platform_device *pdev,
952 struct at91_pinctrl *info)
6732ae5c
JCPV		 953{
954 int ret = 0;
955 int i, j;
956 uint32_t *tmp;
957 struct device_node *np = pdev->dev.of_node;
958 struct device_node *child;
959
960 if (!np)
961 return -ENODEV;
962
963 info->dev = &pdev->dev;
3c93600d 964 info->ops = (struct at91_pinctrl_mux_ops *)
6732ae5c
JCPV		 965 of_match_device(at91_pinctrl_of_match, &pdev->dev)->data;
966 at91_pinctrl_child_count(info, np);
967
968 if (info->nbanks < 1) {
969 dev_err(&pdev->dev, "you need to specify atleast one gpio-controller\n");
970 return -EINVAL;
971 }
972
973 ret = at91_pinctrl_mux_mask(info, np);
974 if (ret)
975 return ret;
976
977 dev_dbg(&pdev->dev, "nmux = %d\n", info->nmux);
978
979 dev_dbg(&pdev->dev, "mux-mask\n");
980 tmp = info->mux_mask;
981 for (i = 0; i < info->nbanks; i++) {
982 for (j = 0; j < info->nmux; j++, tmp++) {
983 dev_dbg(&pdev->dev, "%d:%d\t0x%x\n", i, j, tmp[0]);
984 }
985 }
986
987 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
988 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
989 info->functions = devm_kzalloc(&pdev->dev, info->nfunctions * sizeof(struct at91_pmx_func),
990 GFP_KERNEL);
991 if (!info->functions)
992 return -ENOMEM;
993
994 info->groups = devm_kzalloc(&pdev->dev, info->ngroups * sizeof(struct at91_pin_group),
995 GFP_KERNEL);
996 if (!info->groups)
997 return -ENOMEM;
998
999 dev_dbg(&pdev->dev, "nbanks = %d\n", info->nbanks);
1000 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
1001 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
1002
1003 i = 0;
1004
1005 for_each_child_of_node(np, child) {
1006 if (of_device_is_compatible(child, gpio_compat))
1007 continue;
1008 ret = at91_pinctrl_parse_functions(child, info, i++);
1009 if (ret) {
1010 dev_err(&pdev->dev, "failed to parse function\n");
1011 return ret;
1012 }
1013 }
1014
1015 return 0;
1016}
1017
150632b0 1018static int at91_pinctrl_probe(struct platform_device *pdev)
6732ae5c
JCPV		 1019{
1020 struct at91_pinctrl *info;
1021 struct pinctrl_pin_desc *pdesc;
3c93600d 1022 int ret, i, j, k;
6732ae5c
JCPV		 1023
1024 info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
1025 if (!info)
1026 return -ENOMEM;
1027
1028 ret = at91_pinctrl_probe_dt(pdev, info);
1029 if (ret)
1030 return ret;
1031
1032 /*
1033 * We need all the GPIO drivers to probe FIRST, or we will not be able
1034 * to obtain references to the struct gpio_chip * for them, and we
1035 * need this to proceed.
1036 */
1037 for (i = 0; i < info->nbanks; i++) {
1038 if (!gpio_chips[i]) {
1039 dev_warn(&pdev->dev, "GPIO chip %d not registered yet\n", i);
1040 devm_kfree(&pdev->dev, info);
1041 return -EPROBE_DEFER;
1042 }
1043 }
1044
1045 at91_pinctrl_desc.name = dev_name(&pdev->dev);
1046 at91_pinctrl_desc.npins = info->nbanks * MAX_NB_GPIO_PER_BANK;
1047 at91_pinctrl_desc.pins = pdesc =
1048 devm_kzalloc(&pdev->dev, sizeof(*pdesc) * at91_pinctrl_desc.npins, GFP_KERNEL);
1049
1050 if (!at91_pinctrl_desc.pins)
1051 return -ENOMEM;
1052
1053 for (i = 0 , k = 0; i < info->nbanks; i++) {
1054 for (j = 0; j < MAX_NB_GPIO_PER_BANK; j++, k++) {
1055 pdesc->number = k;
1056 pdesc->name = kasprintf(GFP_KERNEL, "pio%c%d", i + 'A', j);
1057 pdesc++;
1058 }
1059 }
1060
1061 platform_set_drvdata(pdev, info);
1062 info->pctl = pinctrl_register(&at91_pinctrl_desc, &pdev->dev, info);
1063
1064 if (!info->pctl) {
1065 dev_err(&pdev->dev, "could not register AT91 pinctrl driver\n");
1066 ret = -EINVAL;
1067 goto err;
1068 }
1069
1070 /* We will handle a range of GPIO pins */
1071 for (i = 0; i < info->nbanks; i++)
1072 pinctrl_add_gpio_range(info->pctl, &gpio_chips[i]->range);
1073
1074 dev_info(&pdev->dev, "initialized AT91 pinctrl driver\n");
1075
1076 return 0;
1077
1078err:
1079 return ret;
1080}
1081
150632b0 1082static int at91_pinctrl_remove(struct platform_device *pdev)
6732ae5c
JCPV		 1083{
1084 struct at91_pinctrl *info = platform_get_drvdata(pdev);
1085
1086 pinctrl_unregister(info->pctl);
1087
1088 return 0;
1089}
1090
1091static int at91_gpio_request(struct gpio_chip *chip, unsigned offset)
1092{
1093 /*
1094 * Map back to global GPIO space and request muxing, the direction
1095 * parameter does not matter for this controller.
1096 */
1097 int gpio = chip->base + offset;
1098 int bank = chip->base / chip->ngpio;
1099
1100 dev_dbg(chip->dev, "%s:%d pio%c%d(%d)\n", __func__, __LINE__,
1101 'A' + bank, offset, gpio);
1102
1103 return pinctrl_request_gpio(gpio);
1104}
1105
1106static void at91_gpio_free(struct gpio_chip *chip, unsigned offset)
1107{
1108 int gpio = chip->base + offset;
1109
1110 pinctrl_free_gpio(gpio);
1111}
1112
1113static int at91_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
1114{
1115 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
1116 void __iomem *pio = at91_gpio->regbase;
1117 unsigned mask = 1 << offset;
1118
1119 writel_relaxed(mask, pio + PIO_ODR);
1120 return 0;
1121}
1122
1123static int at91_gpio_get(struct gpio_chip *chip, unsigned offset)
1124{
1125 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
1126 void __iomem *pio = at91_gpio->regbase;
1127 unsigned mask = 1 << offset;
1128 u32 pdsr;
1129
1130 pdsr = readl_relaxed(pio + PIO_PDSR);
1131 return (pdsr & mask) != 0;
1132}
1133
1134static void at91_gpio_set(struct gpio_chip *chip, unsigned offset,
1135 int val)
1136{
1137 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
1138 void __iomem *pio = at91_gpio->regbase;
1139 unsigned mask = 1 << offset;
1140
1141 writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR));
1142}
1143
1144static int at91_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
1145 int val)
1146{
1147 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
1148 void __iomem *pio = at91_gpio->regbase;
1149 unsigned mask = 1 << offset;
1150
1151 writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR));
1152 writel_relaxed(mask, pio + PIO_OER);
1153
1154 return 0;
1155}
1156
1157static int at91_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
1158{
1159 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
1160 int virq;
1161
1162 if (offset < chip->ngpio)
1163 virq = irq_create_mapping(at91_gpio->domain, offset);
1164 else
1165 virq = -ENXIO;
1166
1167 dev_dbg(chip->dev, "%s: request IRQ for GPIO %d, return %d\n",
1168 chip->label, offset + chip->base, virq);
1169 return virq;
1170}
1171
1172#ifdef CONFIG_DEBUG_FS
1173static void at91_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
1174{
1175 enum at91_mux mode;
1176 int i;
1177 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
1178 void __iomem *pio = at91_gpio->regbase;
1179
1180 for (i = 0; i < chip->ngpio; i++) {
1181 unsigned pin = chip->base + i;
1182 unsigned mask = pin_to_mask(pin);
1183 const char *gpio_label;
1184 u32 pdsr;
1185
1186 gpio_label = gpiochip_is_requested(chip, i);
1187 if (!gpio_label)
1188 continue;
1189 mode = at91_gpio->ops->get_periph(pio, mask);
1190 seq_printf(s, "[%s] GPIO%s%d: ",
1191 gpio_label, chip->label, i);
1192 if (mode == AT91_MUX_GPIO) {
1193 pdsr = readl_relaxed(pio + PIO_PDSR);
1194
1195 seq_printf(s, "[gpio] %s\n",
1196 pdsr & mask ?
1197 "set" : "clear");
1198 } else {
1199 seq_printf(s, "[periph %c]\n",
1200 mode + 'A' - 1);
1201 }
1202 }
1203}
1204#else
1205#define at91_gpio_dbg_show NULL
1206#endif
1207
1208/* Several AIC controller irqs are dispatched through this GPIO handler.
1209 * To use any AT91_PIN_* as an externally triggered IRQ, first call
1210 * at91_set_gpio_input() then maybe enable its glitch filter.
1211 * Then just request_irq() with the pin ID; it works like any ARM IRQ
1212 * handler.
1213 * First implementation always triggers on rising and falling edges
1214 * whereas the newer PIO3 can be additionally configured to trigger on
1215 * level, edge with any polarity.
1216 *
1217 * Alternatively, certain pins may be used directly as IRQ0..IRQ6 after
1218 * configuring them with at91_set_a_periph() or at91_set_b_periph().
1219 * IRQ0..IRQ6 should be configurable, e.g. level vs edge triggering.
1220 */
1221
1222static void gpio_irq_mask(struct irq_data *d)
1223{
1224 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1225 void __iomem *pio = at91_gpio->regbase;
1226 unsigned mask = 1 << d->hwirq;
1227
1228 if (pio)
1229 writel_relaxed(mask, pio + PIO_IDR);
1230}
1231
1232static void gpio_irq_unmask(struct irq_data *d)
1233{
1234 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1235 void __iomem *pio = at91_gpio->regbase;
1236 unsigned mask = 1 << d->hwirq;
1237
1238 if (pio)
1239 writel_relaxed(mask, pio + PIO_IER);
1240}
1241
1242static int gpio_irq_type(struct irq_data *d, unsigned type)
1243{
1244 switch (type) {
1245 case IRQ_TYPE_NONE:
1246 case IRQ_TYPE_EDGE_BOTH:
1247 return 0;
1248 default:
1249 return -EINVAL;
1250 }
1251}
1252
1253/* Alternate irq type for PIO3 support */
1254static int alt_gpio_irq_type(struct irq_data *d, unsigned type)
1255{
1256 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1257 void __iomem *pio = at91_gpio->regbase;
1258 unsigned mask = 1 << d->hwirq;
1259
1260 switch (type) {
1261 case IRQ_TYPE_EDGE_RISING:
99fce029 1262 irq_set_handler(d->irq, handle_simple_irq);
6732ae5c
JCPV		 1263 writel_relaxed(mask, pio + PIO_ESR);
1264 writel_relaxed(mask, pio + PIO_REHLSR);
1265 break;
1266 case IRQ_TYPE_EDGE_FALLING:
99fce029 1267 irq_set_handler(d->irq, handle_simple_irq);
6732ae5c
JCPV		 1268 writel_relaxed(mask, pio + PIO_ESR);
1269 writel_relaxed(mask, pio + PIO_FELLSR);
1270 break;
1271 case IRQ_TYPE_LEVEL_LOW:
99fce029 1272 irq_set_handler(d->irq, handle_level_irq);
6732ae5c
JCPV		 1273 writel_relaxed(mask, pio + PIO_LSR);
1274 writel_relaxed(mask, pio + PIO_FELLSR);
1275 break;
1276 case IRQ_TYPE_LEVEL_HIGH:
99fce029 1277 irq_set_handler(d->irq, handle_level_irq);
6732ae5c
JCPV		 1278 writel_relaxed(mask, pio + PIO_LSR);
1279 writel_relaxed(mask, pio + PIO_REHLSR);
1280 break;
1281 case IRQ_TYPE_EDGE_BOTH:
1282 /*
1283 * disable additional interrupt modes:
1284 * fall back to default behavior
1285 */
99fce029 1286 irq_set_handler(d->irq, handle_simple_irq);
6732ae5c
JCPV		 1287 writel_relaxed(mask, pio + PIO_AIMDR);
1288 return 0;
1289 case IRQ_TYPE_NONE:
1290 default:
1291 pr_warn("AT91: No type for irq %d\n", gpio_to_irq(d->irq));
1292 return -EINVAL;
1293 }
1294
1295 /* enable additional interrupt modes */
1296 writel_relaxed(mask, pio + PIO_AIMER);
1297
1298 return 0;
1299}
1300
1301#ifdef CONFIG_PM
647f8d94
LD		 1302
1303static u32 wakeups[MAX_GPIO_BANKS];
1304static u32 backups[MAX_GPIO_BANKS];
1305
6732ae5c
JCPV		 1306static int gpio_irq_set_wake(struct irq_data *d, unsigned state)
1307{
1308 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1309 unsigned bank = at91_gpio->pioc_idx;
647f8d94 1310 unsigned mask = 1 << d->hwirq;
6732ae5c
JCPV		 1311
1312 if (unlikely(bank >= MAX_GPIO_BANKS))
1313 return -EINVAL;
1314
647f8d94
LD		 1315 if (state)
1316 wakeups[bank] |= mask;
1317 else
1318 wakeups[bank] &= ~mask;
1319
6732ae5c
JCPV		 1320 irq_set_irq_wake(at91_gpio->pioc_virq, state);
1321
1322 return 0;
1323}
647f8d94
LD		 1324
1325void at91_pinctrl_gpio_suspend(void)
1326{
1327 int i;
1328
1329 for (i = 0; i < gpio_banks; i++) {
1330 void __iomem *pio;
1331
1332 if (!gpio_chips[i])
1333 continue;
1334
1335 pio = gpio_chips[i]->regbase;
1336
1337 backups[i] = __raw_readl(pio + PIO_IMR);
1338 __raw_writel(backups[i], pio + PIO_IDR);
1339 __raw_writel(wakeups[i], pio + PIO_IER);
1340
1341 if (!wakeups[i]) {
1342 clk_unprepare(gpio_chips[i]->clock);
1343 clk_disable(gpio_chips[i]->clock);
1344 } else {
1345 printk(KERN_DEBUG "GPIO-%c may wake for %08x\n",
1346 'A'+i, wakeups[i]);
1347 }
1348 }
1349}
1350
1351void at91_pinctrl_gpio_resume(void)
1352{
1353 int i;
1354
1355 for (i = 0; i < gpio_banks; i++) {
1356 void __iomem *pio;
1357
1358 if (!gpio_chips[i])
1359 continue;
1360
1361 pio = gpio_chips[i]->regbase;
1362
1363 if (!wakeups[i]) {
1364 if (clk_prepare(gpio_chips[i]->clock) == 0)
1365 clk_enable(gpio_chips[i]->clock);
1366 }
1367
1368 __raw_writel(wakeups[i], pio + PIO_IDR);
1369 __raw_writel(backups[i], pio + PIO_IER);
1370 }
1371}
1372
6732ae5c
JCPV		 1373#else
1374#define gpio_irq_set_wake NULL
647f8d94 1375#endif /* CONFIG_PM */
6732ae5c
JCPV		 1376
1377static struct irq_chip gpio_irqchip = {
1378 .name = "GPIO",
1379 .irq_disable = gpio_irq_mask,
1380 .irq_mask = gpio_irq_mask,
1381 .irq_unmask = gpio_irq_unmask,
1382 /* .irq_set_type is set dynamically */
1383 .irq_set_wake = gpio_irq_set_wake,
1384};
1385
1386static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
1387{
1388 struct irq_chip *chip = irq_desc_get_chip(desc);
1389 struct irq_data *idata = irq_desc_get_irq_data(desc);
1390 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(idata);
1391 void __iomem *pio = at91_gpio->regbase;
1392 unsigned long isr;
1393 int n;
1394
1395 chained_irq_enter(chip, desc);
1396 for (;;) {
1397 /* Reading ISR acks pending (edge triggered) GPIO interrupts.
1398 * When there none are pending, we're finished unless we need
1399 * to process multiple banks (like ID_PIOCDE on sam9263).
1400 */
1401 isr = readl_relaxed(pio + PIO_ISR) & readl_relaxed(pio + PIO_IMR);
1402 if (!isr) {
1403 if (!at91_gpio->next)
1404 break;
1405 at91_gpio = at91_gpio->next;
1406 pio = at91_gpio->regbase;
1407 continue;
1408 }
1409
05daa16a 1410 for_each_set_bit(n, &isr, BITS_PER_LONG) {
6732ae5c 1411 generic_handle_irq(irq_find_mapping(at91_gpio->domain, n));
6732ae5c
JCPV		 1412 }
1413 }
1414 chained_irq_exit(chip, desc);
1415 /* now it may re-trigger */
1416}
1417
1418/*
1419 * This lock class tells lockdep that GPIO irqs are in a different
1420 * category than their parents, so it won't report false recursion.
1421 */
1422static struct lock_class_key gpio_lock_class;
1423
1424static int at91_gpio_irq_map(struct irq_domain *h, unsigned int virq,
1425 irq_hw_number_t hw)
1426{
1427 struct at91_gpio_chip *at91_gpio = h->host_data;
99fce029
BB		 1428 void __iomem *pio = at91_gpio->regbase;
1429 u32 mask = 1 << hw;
6732ae5c
JCPV		 1430
1431 irq_set_lockdep_class(virq, &gpio_lock_class);
1432
1433 /*
1434 * Can use the "simple" and not "edge" handler since it's
1435 * shorter, and the AIC handles interrupts sanely.
1436 */
99fce029
BB		 1437 irq_set_chip(virq, &gpio_irqchip);
1438 if ((at91_gpio->ops == &at91sam9x5_ops) &&
1439 (readl_relaxed(pio + PIO_AIMMR) & mask) &&
1440 (readl_relaxed(pio + PIO_ELSR) & mask))
1441 irq_set_handler(virq, handle_level_irq);
1442 else
1443 irq_set_handler(virq, handle_simple_irq);
6732ae5c
JCPV		 1444 set_irq_flags(virq, IRQF_VALID);
1445 irq_set_chip_data(virq, at91_gpio);
1446
1447 return 0;
1448}
1449
f6f94f66
AL		 1450static int at91_gpio_irq_domain_xlate(struct irq_domain *d,
1451 struct device_node *ctrlr,
1452 const u32 *intspec, unsigned int intsize,
1453 irq_hw_number_t *out_hwirq,
1454 unsigned int *out_type)
a728c7cd
JCPV		 1455{
1456 struct at91_gpio_chip *at91_gpio = d->host_data;
1457 int ret;
1458 int pin = at91_gpio->chip.base + intspec[0];
1459
1460 if (WARN_ON(intsize < 2))
1461 return -EINVAL;
1462 *out_hwirq = intspec[0];
1463 *out_type = intspec[1] & IRQ_TYPE_SENSE_MASK;
1464
1465 ret = gpio_request(pin, ctrlr->full_name);
1466 if (ret)
1467 return ret;
1468
1469 ret = gpio_direction_input(pin);
1470 if (ret)
1471 return ret;
1472
1473 return 0;
1474}
1475
6732ae5c
JCPV		 1476static struct irq_domain_ops at91_gpio_ops = {
1477 .map = at91_gpio_irq_map,
a728c7cd 1478 .xlate = at91_gpio_irq_domain_xlate,
6732ae5c
JCPV		 1479};
1480
1481static int at91_gpio_of_irq_setup(struct device_node *node,
1482 struct at91_gpio_chip *at91_gpio)
1483{
1484 struct at91_gpio_chip *prev = NULL;
1485 struct irq_data *d = irq_get_irq_data(at91_gpio->pioc_virq);
1486
1487 at91_gpio->pioc_hwirq = irqd_to_hwirq(d);
1488
1489 /* Setup proper .irq_set_type function */
1490 gpio_irqchip.irq_set_type = at91_gpio->ops->irq_type;
1491
1492 /* Disable irqs of this PIO controller */
1493 writel_relaxed(~0, at91_gpio->regbase + PIO_IDR);
1494
1495 /* Setup irq domain */
1496 at91_gpio->domain = irq_domain_add_linear(node, at91_gpio->chip.ngpio,
1497 &at91_gpio_ops, at91_gpio);
1498 if (!at91_gpio->domain)
1499 panic("at91_gpio.%d: couldn't allocate irq domain (DT).\n",
1500 at91_gpio->pioc_idx);
1501
1502 /* Setup chained handler */
1503 if (at91_gpio->pioc_idx)
1504 prev = gpio_chips[at91_gpio->pioc_idx - 1];
1505
1506 /* The toplevel handler handles one bank of GPIOs, except
1507 * on some SoC it can handles up to three...
1508 * We only set up the handler for the first of the list.
1509 */
1510 if (prev && prev->next == at91_gpio)
1511 return 0;
1512
1513 irq_set_chip_data(at91_gpio->pioc_virq, at91_gpio);
1514 irq_set_chained_handler(at91_gpio->pioc_virq, gpio_irq_handler);
1515
1516 return 0;
1517}
1518
1519/* This structure is replicated for each GPIO block allocated at probe time */
1520static struct gpio_chip at91_gpio_template = {
1521 .request = at91_gpio_request,
1522 .free = at91_gpio_free,
1523 .direction_input = at91_gpio_direction_input,
1524 .get = at91_gpio_get,
1525 .direction_output = at91_gpio_direction_output,
1526 .set = at91_gpio_set,
1527 .to_irq = at91_gpio_to_irq,
1528 .dbg_show = at91_gpio_dbg_show,
1529 .can_sleep = 0,
1530 .ngpio = MAX_NB_GPIO_PER_BANK,
1531};
1532
150632b0 1533static void at91_gpio_probe_fixup(void)
6732ae5c
JCPV		 1534{
1535 unsigned i;
1536 struct at91_gpio_chip *at91_gpio, *last = NULL;
1537
1538 for (i = 0; i < gpio_banks; i++) {
1539 at91_gpio = gpio_chips[i];
1540
1541 /*
1542 * GPIO controller are grouped on some SoC:
1543 * PIOC, PIOD and PIOE can share the same IRQ line
1544 */
1545 if (last && last->pioc_virq == at91_gpio->pioc_virq)
1546 last->next = at91_gpio;
1547 last = at91_gpio;
1548 }
1549}
1550
150632b0 1551static struct of_device_id at91_gpio_of_match[] = {
6732ae5c
JCPV		 1552 { .compatible = "atmel,at91sam9x5-gpio", .data = &at91sam9x5_ops, },
1553 { .compatible = "atmel,at91rm9200-gpio", .data = &at91rm9200_ops },
1554 { /* sentinel */ }
1555};
1556
150632b0 1557static int at91_gpio_probe(struct platform_device *pdev)
6732ae5c
JCPV		 1558{
1559 struct device_node *np = pdev->dev.of_node;
1560 struct resource *res;
1561 struct at91_gpio_chip *at91_chip = NULL;
1562 struct gpio_chip *chip;
1563 struct pinctrl_gpio_range *range;
1564 int ret = 0;
32b01a36 1565 int irq, i;
6732ae5c
JCPV		 1566 int alias_idx = of_alias_get_id(np, "gpio");
1567 uint32_t ngpio;
32b01a36 1568 char **names;
6732ae5c
JCPV		 1569
1570 BUG_ON(alias_idx >= ARRAY_SIZE(gpio_chips));
1571 if (gpio_chips[alias_idx]) {
1572 ret = -EBUSY;
1573 goto err;
1574 }
1575
6732ae5c
JCPV		 1576 irq = platform_get_irq(pdev, 0);
1577 if (irq < 0) {
1578 ret = irq;
1579 goto err;
1580 }
1581
1582 at91_chip = devm_kzalloc(&pdev->dev, sizeof(*at91_chip), GFP_KERNEL);
1583 if (!at91_chip) {
1584 ret = -ENOMEM;
1585 goto err;
1586 }
1587
f50b9e12 1588 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
9e0c1fb2
TR		 1589 at91_chip->regbase = devm_ioremap_resource(&pdev->dev, res);
1590 if (IS_ERR(at91_chip->regbase)) {
1591 ret = PTR_ERR(at91_chip->regbase);
6732ae5c
JCPV		 1592 goto err;
1593 }
1594
3c93600d 1595 at91_chip->ops = (struct at91_pinctrl_mux_ops *)
6732ae5c
JCPV		 1596 of_match_device(at91_gpio_of_match, &pdev->dev)->data;
1597 at91_chip->pioc_virq = irq;
1598 at91_chip->pioc_idx = alias_idx;
1599
1600 at91_chip->clock = clk_get(&pdev->dev, NULL);
1601 if (IS_ERR(at91_chip->clock)) {
1602 dev_err(&pdev->dev, "failed to get clock, ignoring.\n");
1603 goto err;
1604 }
1605
1606 if (clk_prepare(at91_chip->clock))
1607 goto clk_prep_err;
1608
1609 /* enable PIO controller's clock */
1610 if (clk_enable(at91_chip->clock)) {
1611 dev_err(&pdev->dev, "failed to enable clock, ignoring.\n");
1612 goto clk_err;
1613 }
1614
1615 at91_chip->chip = at91_gpio_template;
1616
1617 chip = &at91_chip->chip;
1618 chip->of_node = np;
1619 chip->label = dev_name(&pdev->dev);
1620 chip->dev = &pdev->dev;
1621 chip->owner = THIS_MODULE;
1622 chip->base = alias_idx * MAX_NB_GPIO_PER_BANK;
1623
1624 if (!of_property_read_u32(np, "#gpio-lines", &ngpio)) {
1625 if (ngpio >= MAX_NB_GPIO_PER_BANK)
1626 pr_err("at91_gpio.%d, gpio-nb >= %d failback to %d\n",
1627 alias_idx, MAX_NB_GPIO_PER_BANK, MAX_NB_GPIO_PER_BANK);
1628 else
1629 chip->ngpio = ngpio;
1630 }
1631
3c93600d
SK		 1632 names = devm_kzalloc(&pdev->dev, sizeof(char *) * chip->ngpio,
1633 GFP_KERNEL);
32b01a36
JCPV		 1634
1635 if (!names) {
1636 ret = -ENOMEM;
1637 goto clk_err;
1638 }
1639
1640 for (i = 0; i < chip->ngpio; i++)
1641 names[i] = kasprintf(GFP_KERNEL, "pio%c%d", alias_idx + 'A', i);
1642
3c93600d 1643 chip->names = (const char *const *)names;
32b01a36 1644
6732ae5c
JCPV		 1645 range = &at91_chip->range;
1646 range->name = chip->label;
1647 range->id = alias_idx;
1648 range->pin_base = range->base = range->id * MAX_NB_GPIO_PER_BANK;
1649
1650 range->npins = chip->ngpio;
1651 range->gc = chip;
1652
1653 ret = gpiochip_add(chip);
1654 if (ret)
1655 goto clk_err;
1656
1657 gpio_chips[alias_idx] = at91_chip;
1658 gpio_banks = max(gpio_banks, alias_idx + 1);
1659
1660 at91_gpio_probe_fixup();
1661
1662 at91_gpio_of_irq_setup(np, at91_chip);
1663
1664 dev_info(&pdev->dev, "at address %p\n", at91_chip->regbase);
1665
1666 return 0;
1667
1668clk_err:
1669 clk_unprepare(at91_chip->clock);
1670clk_prep_err:
1671 clk_put(at91_chip->clock);
1672err:
1673 dev_err(&pdev->dev, "Failure %i for GPIO %i\n", ret, alias_idx);
1674
1675 return ret;
1676}
1677
1678static struct platform_driver at91_gpio_driver = {
1679 .driver = {
1680 .name = "gpio-at91",
1681 .owner = THIS_MODULE,
1682 .of_match_table = of_match_ptr(at91_gpio_of_match),
1683 },
1684 .probe = at91_gpio_probe,
1685};
1686
1687static struct platform_driver at91_pinctrl_driver = {
1688 .driver = {
1689 .name = "pinctrl-at91",
1690 .owner = THIS_MODULE,
1691 .of_match_table = of_match_ptr(at91_pinctrl_of_match),
1692 },
1693 .probe = at91_pinctrl_probe,
150632b0 1694 .remove = at91_pinctrl_remove,
6732ae5c
JCPV		 1695};
1696
1697static int __init at91_pinctrl_init(void)
1698{
1699 int ret;
1700
1701 ret = platform_driver_register(&at91_gpio_driver);
1702 if (ret)
1703 return ret;
1704 return platform_driver_register(&at91_pinctrl_driver);
1705}
1706arch_initcall(at91_pinctrl_init);
1707
1708static void __exit at91_pinctrl_exit(void)
1709{
1710 platform_driver_unregister(&at91_pinctrl_driver);
1711}
1712
1713module_exit(at91_pinctrl_exit);
1714MODULE_AUTHOR("Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>");
1715MODULE_DESCRIPTION("Atmel AT91 pinctrl driver");
1716MODULE_LICENSE("GPL v2");
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