[mirror_ubuntu-jammy-kernel.git] / drivers / pinctrl / pinctrl-axp209.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * AXP20x pinctrl and GPIO driver
 *
 * Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
 * Copyright (C) 2017 Quentin Schulz <quentin.schulz@free-electrons.com>
 */

#include <linux/bitops.h>
#include <linux/device.h>
#include <linux/gpio/driver.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/mfd/axp20x.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/slab.h>

#define AXP20X_GPIO_FUNCTIONS		0x7
#define AXP20X_GPIO_FUNCTION_OUT_LOW	0
#define AXP20X_GPIO_FUNCTION_OUT_HIGH	1
#define AXP20X_GPIO_FUNCTION_INPUT	2

#define AXP20X_FUNC_GPIO_OUT		0
#define AXP20X_FUNC_GPIO_IN		1
#define AXP20X_FUNC_LDO			2
#define AXP20X_FUNC_ADC			3
#define AXP20X_FUNCS_NB			4

#define AXP20X_MUX_GPIO_OUT		0
#define AXP20X_MUX_GPIO_IN		BIT(1)
#define AXP20X_MUX_ADC			BIT(2)

#define AXP813_MUX_ADC			(BIT(2) | BIT(0))

struct axp20x_pctrl_desc {
	const struct pinctrl_pin_desc	*pins;
	unsigned int			npins;
	/* Stores the pins supporting LDO function. Bit offset is pin number. */
	u8				ldo_mask;
	/* Stores the pins supporting ADC function. Bit offset is pin number. */
	u8				adc_mask;
	u8				gpio_status_offset;
	u8				adc_mux;
};

struct axp20x_pinctrl_function {
	const char	*name;
	unsigned int	muxval;
	const char	**groups;
	unsigned int	ngroups;
};

struct axp20x_pctl {
	struct gpio_chip	chip;
	struct regmap		*regmap;
	struct pinctrl_dev			*pctl_dev;
	struct device				*dev;
	const struct axp20x_pctrl_desc		*desc;
	struct axp20x_pinctrl_function		funcs[AXP20X_FUNCS_NB];
};

static const struct pinctrl_pin_desc axp209_pins[] = {
	PINCTRL_PIN(0, "GPIO0"),
	PINCTRL_PIN(1, "GPIO1"),
	PINCTRL_PIN(2, "GPIO2"),
};

static const struct pinctrl_pin_desc axp813_pins[] = {
	PINCTRL_PIN(0, "GPIO0"),
	PINCTRL_PIN(1, "GPIO1"),
};

static const struct axp20x_pctrl_desc axp20x_data = {
	.pins	= axp209_pins,
	.npins	= ARRAY_SIZE(axp209_pins),
	.ldo_mask = BIT(0) | BIT(1),
	.adc_mask = BIT(0) | BIT(1),
	.gpio_status_offset = 4,
	.adc_mux = AXP20X_MUX_ADC,
};

static const struct axp20x_pctrl_desc axp813_data = {
	.pins	= axp813_pins,
	.npins	= ARRAY_SIZE(axp813_pins),
	.ldo_mask = BIT(0) | BIT(1),
	.adc_mask = BIT(0),
	.gpio_status_offset = 0,
	.adc_mux = AXP813_MUX_ADC,
};

static int axp20x_gpio_get_reg(unsigned int offset)
{
	switch (offset) {
	case 0:
		return AXP20X_GPIO0_CTRL;
	case 1:
		return AXP20X_GPIO1_CTRL;
	case 2:
		return AXP20X_GPIO2_CTRL;
	}

	return -EINVAL;
}

static int axp20x_gpio_input(struct gpio_chip *chip, unsigned int offset)
{
	return pinctrl_gpio_direction_input(chip->base + offset);
}

static int axp20x_gpio_get(struct gpio_chip *chip, unsigned int offset)
{
	struct axp20x_pctl *pctl = gpiochip_get_data(chip);
	unsigned int val;
	int ret;

	ret = regmap_read(pctl->regmap, AXP20X_GPIO20_SS, &val);
	if (ret)
		return ret;

	return !!(val & BIT(offset + pctl->desc->gpio_status_offset));
}

static int axp20x_gpio_get_direction(struct gpio_chip *chip,
				     unsigned int offset)
{
	struct axp20x_pctl *pctl = gpiochip_get_data(chip);
	unsigned int val;
	int reg, ret;

	reg = axp20x_gpio_get_reg(offset);
	if (reg < 0)
		return reg;

	ret = regmap_read(pctl->regmap, reg, &val);
	if (ret)
		return ret;

	/*
	 * This shouldn't really happen if the pin is in use already,
	 * or if it's not in use yet, it doesn't matter since we're
	 * going to change the value soon anyway. Default to output.
	 */
	if ((val & AXP20X_GPIO_FUNCTIONS) > 2)
		return GPIO_LINE_DIRECTION_OUT;

	/*
	 * The GPIO directions are the three lowest values.
	 * 2 is input, 0 and 1 are output
	 */
	if (val & 2)
		return GPIO_LINE_DIRECTION_IN;

	return GPIO_LINE_DIRECTION_OUT;
}

static int axp20x_gpio_output(struct gpio_chip *chip, unsigned int offset,
			      int value)
{
	chip->set(chip, offset, value);

	return 0;
}

static void axp20x_gpio_set(struct gpio_chip *chip, unsigned int offset,
			    int value)
{
	struct axp20x_pctl *pctl = gpiochip_get_data(chip);
	int reg;

	reg = axp20x_gpio_get_reg(offset);
	if (reg < 0)
		return;

	regmap_update_bits(pctl->regmap, reg,
			   AXP20X_GPIO_FUNCTIONS,
			   value ? AXP20X_GPIO_FUNCTION_OUT_HIGH :
			   AXP20X_GPIO_FUNCTION_OUT_LOW);
}

static int axp20x_pmx_set(struct pinctrl_dev *pctldev, unsigned int offset,
			  u8 config)
{
	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
	int reg;

	reg = axp20x_gpio_get_reg(offset);
	if (reg < 0)
		return reg;

	return regmap_update_bits(pctl->regmap, reg, AXP20X_GPIO_FUNCTIONS,
				  config);
}

static int axp20x_pmx_func_cnt(struct pinctrl_dev *pctldev)
{
	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);

	return ARRAY_SIZE(pctl->funcs);
}

static const char *axp20x_pmx_func_name(struct pinctrl_dev *pctldev,
					unsigned int selector)
{
	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);

	return pctl->funcs[selector].name;
}

static int axp20x_pmx_func_groups(struct pinctrl_dev *pctldev,
				  unsigned int selector,
				  const char * const **groups,
				  unsigned int *num_groups)
{
	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);

	*groups = pctl->funcs[selector].groups;
	*num_groups = pctl->funcs[selector].ngroups;

	return 0;
}

static int axp20x_pmx_set_mux(struct pinctrl_dev *pctldev,
			      unsigned int function, unsigned int group)
{
	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
	unsigned int mask;

	/* Every pin supports GPIO_OUT and GPIO_IN functions */
	if (function <= AXP20X_FUNC_GPIO_IN)
		return axp20x_pmx_set(pctldev, group,
				      pctl->funcs[function].muxval);

	if (function == AXP20X_FUNC_LDO)
		mask = pctl->desc->ldo_mask;
	else
		mask = pctl->desc->adc_mask;

	if (!(BIT(group) & mask))
		return -EINVAL;

	/*
	 * We let the regulator framework handle the LDO muxing as muxing bits
	 * are basically also regulators on/off bits. It's better not to enforce
	 * any state of the regulator when selecting LDO mux so that we don't
	 * interfere with the regulator driver.
	 */
	if (function == AXP20X_FUNC_LDO)
		return 0;

	return axp20x_pmx_set(pctldev, group, pctl->funcs[function].muxval);
}

static int axp20x_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
					 struct pinctrl_gpio_range *range,
					 unsigned int offset, bool input)
{
	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);

	if (input)
		return axp20x_pmx_set(pctldev, offset,
				      pctl->funcs[AXP20X_FUNC_GPIO_IN].muxval);

	return axp20x_pmx_set(pctldev, offset,
			      pctl->funcs[AXP20X_FUNC_GPIO_OUT].muxval);
}

static const struct pinmux_ops axp20x_pmx_ops = {
	.get_functions_count	= axp20x_pmx_func_cnt,
	.get_function_name	= axp20x_pmx_func_name,
	.get_function_groups	= axp20x_pmx_func_groups,
	.set_mux		= axp20x_pmx_set_mux,
	.gpio_set_direction	= axp20x_pmx_gpio_set_direction,
	.strict			= true,
};

static int axp20x_groups_cnt(struct pinctrl_dev *pctldev)
{
	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);

	return pctl->desc->npins;
}

static int axp20x_group_pins(struct pinctrl_dev *pctldev, unsigned int selector,
			     const unsigned int **pins, unsigned int *num_pins)
{
	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);

	*pins = (unsigned int *)&pctl->desc->pins[selector];
	*num_pins = 1;

	return 0;
}

static const char *axp20x_group_name(struct pinctrl_dev *pctldev,
				     unsigned int selector)
{
	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);

	return pctl->desc->pins[selector].name;
}

static const struct pinctrl_ops axp20x_pctrl_ops = {
	.dt_node_to_map		= pinconf_generic_dt_node_to_map_group,
	.dt_free_map		= pinconf_generic_dt_free_map,
	.get_groups_count	= axp20x_groups_cnt,
	.get_group_name		= axp20x_group_name,
	.get_group_pins		= axp20x_group_pins,
};

static int axp20x_funcs_groups_from_mask(struct device *dev, unsigned int mask,
					  unsigned int mask_len,
					  struct axp20x_pinctrl_function *func,
					  const struct pinctrl_pin_desc *pins)
{
	unsigned long int mask_cpy = mask;
	const char **group;
	unsigned int ngroups = hweight8(mask);
	int bit;

	func->ngroups = ngroups;
	if (func->ngroups > 0) {
		func->groups = devm_kcalloc(dev,
					    ngroups, sizeof(const char *),
					    GFP_KERNEL);
		if (!func->groups)
			return -ENOMEM;
		group = func->groups;
		for_each_set_bit(bit, &mask_cpy, mask_len) {
			*group = pins[bit].name;
			group++;
		}
	}

	return 0;
}

static int axp20x_build_funcs_groups(struct platform_device *pdev)
{
	struct axp20x_pctl *pctl = platform_get_drvdata(pdev);
	int i, ret, pin, npins = pctl->desc->npins;

	pctl->funcs[AXP20X_FUNC_GPIO_OUT].name = "gpio_out";
	pctl->funcs[AXP20X_FUNC_GPIO_OUT].muxval = AXP20X_MUX_GPIO_OUT;
	pctl->funcs[AXP20X_FUNC_GPIO_IN].name = "gpio_in";
	pctl->funcs[AXP20X_FUNC_GPIO_IN].muxval = AXP20X_MUX_GPIO_IN;
	pctl->funcs[AXP20X_FUNC_LDO].name = "ldo";
	/*
	 * Muxval for LDO is useless as we won't use it.
	 * See comment in axp20x_pmx_set_mux.
	 */
	pctl->funcs[AXP20X_FUNC_ADC].name = "adc";
	pctl->funcs[AXP20X_FUNC_ADC].muxval = pctl->desc->adc_mux;

	/* Every pin supports GPIO_OUT and GPIO_IN functions */
	for (i = 0; i <= AXP20X_FUNC_GPIO_IN; i++) {
		pctl->funcs[i].ngroups = npins;
		pctl->funcs[i].groups = devm_kcalloc(&pdev->dev,
						     npins, sizeof(char *),
						     GFP_KERNEL);
		if (!pctl->funcs[i].groups)
			return -ENOMEM;
		for (pin = 0; pin < npins; pin++)
			pctl->funcs[i].groups[pin] = pctl->desc->pins[pin].name;
	}

	ret = axp20x_funcs_groups_from_mask(&pdev->dev, pctl->desc->ldo_mask,
				      npins, &pctl->funcs[AXP20X_FUNC_LDO],
				      pctl->desc->pins);
	if (ret)
		return ret;

	ret = axp20x_funcs_groups_from_mask(&pdev->dev, pctl->desc->adc_mask,
				      npins, &pctl->funcs[AXP20X_FUNC_ADC],
				      pctl->desc->pins);
	if (ret)
		return ret;

	return 0;
}

static const struct of_device_id axp20x_pctl_match[] = {
	{ .compatible = "x-powers,axp209-gpio", .data = &axp20x_data, },
	{ .compatible = "x-powers,axp813-gpio", .data = &axp813_data, },
	{ }
};
MODULE_DEVICE_TABLE(of, axp20x_pctl_match);

static int axp20x_pctl_probe(struct platform_device *pdev)
{
	struct axp20x_dev *axp20x = dev_get_drvdata(pdev->dev.parent);
	struct axp20x_pctl *pctl;
	struct device *dev = &pdev->dev;
	struct pinctrl_desc *pctrl_desc;
	int ret;

	if (!of_device_is_available(pdev->dev.of_node))
		return -ENODEV;

	if (!axp20x) {
		dev_err(&pdev->dev, "Parent drvdata not set\n");
		return -EINVAL;
	}

	pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
	if (!pctl)
		return -ENOMEM;

	pctl->chip.base			= -1;
	pctl->chip.can_sleep		= true;
	pctl->chip.request		= gpiochip_generic_request;
	pctl->chip.free			= gpiochip_generic_free;
	pctl->chip.parent		= &pdev->dev;
	pctl->chip.label		= dev_name(&pdev->dev);
	pctl->chip.owner		= THIS_MODULE;
	pctl->chip.get			= axp20x_gpio_get;
	pctl->chip.get_direction	= axp20x_gpio_get_direction;
	pctl->chip.set			= axp20x_gpio_set;
	pctl->chip.direction_input	= axp20x_gpio_input;
	pctl->chip.direction_output	= axp20x_gpio_output;

	pctl->desc = of_device_get_match_data(dev);

	pctl->chip.ngpio		= pctl->desc->npins;

	pctl->regmap = axp20x->regmap;
	pctl->dev = &pdev->dev;

	platform_set_drvdata(pdev, pctl);

	ret = axp20x_build_funcs_groups(pdev);
	if (ret) {
		dev_err(&pdev->dev, "failed to build groups\n");
		return ret;
	}

	pctrl_desc = devm_kzalloc(&pdev->dev, sizeof(*pctrl_desc), GFP_KERNEL);
	if (!pctrl_desc)
		return -ENOMEM;

	pctrl_desc->name = dev_name(&pdev->dev);
	pctrl_desc->owner = THIS_MODULE;
	pctrl_desc->pins = pctl->desc->pins;
	pctrl_desc->npins = pctl->desc->npins;
	pctrl_desc->pctlops = &axp20x_pctrl_ops;
	pctrl_desc->pmxops = &axp20x_pmx_ops;

	pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, pctrl_desc, pctl);
	if (IS_ERR(pctl->pctl_dev)) {
		dev_err(&pdev->dev, "couldn't register pinctrl driver\n");
		return PTR_ERR(pctl->pctl_dev);
	}

	ret = devm_gpiochip_add_data(&pdev->dev, &pctl->chip, pctl);
	if (ret) {
		dev_err(&pdev->dev, "Failed to register GPIO chip\n");
		return ret;
	}

	ret = gpiochip_add_pin_range(&pctl->chip, dev_name(&pdev->dev),
				     pctl->desc->pins->number,
				     pctl->desc->pins->number,
				     pctl->desc->npins);
	if (ret) {
		dev_err(&pdev->dev, "failed to add pin range\n");
		return ret;
	}

	dev_info(&pdev->dev, "AXP209 pinctrl and GPIO driver loaded\n");

	return 0;
}

static struct platform_driver axp20x_pctl_driver = {
	.probe		= axp20x_pctl_probe,
	.driver = {
		.name		= "axp20x-gpio",
		.of_match_table	= axp20x_pctl_match,
	},
};

module_platform_driver(axp20x_pctl_driver);

MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
MODULE_AUTHOR("Quentin Schulz <quentin.schulz@free-electrons.com>");
MODULE_DESCRIPTION("AXP20x PMIC pinctrl and GPIO driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
2874c5fd	1	// SPDX-License-Identifier: GPL-2.0-or-later
f72f4b44	2	/*
23f75d7d	3	* AXP20x pinctrl and GPIO driver
f72f4b44 MR	4	*
f72f4b44 MR	5	* Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
23f75d7d	6	* Copyright (C) 2017 Quentin Schulz <quentin.schulz@free-electrons.com>
f72f4b44 MR	7	*/
	8
	9	#include <linux/bitops.h>
	10	#include <linux/device.h>
	11	#include <linux/gpio/driver.h>
	12	#include <linux/init.h>
	13	#include <linux/interrupt.h>
	14	#include <linux/kernel.h>
	15	#include <linux/mfd/axp20x.h>
	16	#include <linux/module.h>
	17	#include <linux/of.h>
e1190083	18	#include <linux/of_device.h>
23f75d7d QS	19	#include <linux/pinctrl/pinconf-generic.h>
	20	#include <linux/pinctrl/pinctrl.h>
	21	#include <linux/pinctrl/pinmux.h>
f72f4b44 MR	22	#include <linux/platform_device.h>
	23	#include <linux/regmap.h>
	24	#include <linux/slab.h>
	25
	26	#define AXP20X_GPIO_FUNCTIONS 0x7
	27	#define AXP20X_GPIO_FUNCTION_OUT_LOW 0
	28	#define AXP20X_GPIO_FUNCTION_OUT_HIGH 1
	29	#define AXP20X_GPIO_FUNCTION_INPUT 2
	30
23f75d7d QS	31	#define AXP20X_FUNC_GPIO_OUT 0
	32	#define AXP20X_FUNC_GPIO_IN 1
	33	#define AXP20X_FUNC_LDO 2
	34	#define AXP20X_FUNC_ADC 3
	35	#define AXP20X_FUNCS_NB 4
	36
	37	#define AXP20X_MUX_GPIO_OUT 0
	38	#define AXP20X_MUX_GPIO_IN BIT(1)
	39	#define AXP20X_MUX_ADC BIT(2)
	40
e1190083 QS	41	#define AXP813_MUX_ADC (BIT(2) \| BIT(0))
e1190083 QS	42
23f75d7d QS	43	struct axp20x_pctrl_desc {
	44	const struct pinctrl_pin_desc *pins;
	45	unsigned int npins;
	46	/* Stores the pins supporting LDO function. Bit offset is pin number. */
	47	u8 ldo_mask;
	48	/* Stores the pins supporting ADC function. Bit offset is pin number. */
	49	u8 adc_mask;
48e706fb	50	u8 gpio_status_offset;
a0a4b4c2	51	u8 adc_mux;
23f75d7d QS	52	};
	53
	54	struct axp20x_pinctrl_function {
	55	const char *name;
	56	unsigned int muxval;
	57	const char **groups;
	58	unsigned int ngroups;
	59	};
	60
d242e60c	61	struct axp20x_pctl {
f72f4b44 MR	62	struct gpio_chip chip;
f72f4b44 MR	63	struct regmap *regmap;
23f75d7d QS	64	struct pinctrl_dev *pctl_dev;
	65	struct device *dev;
	66	const struct axp20x_pctrl_desc *desc;
	67	struct axp20x_pinctrl_function funcs[AXP20X_FUNCS_NB];
	68	};
	69
	70	static const struct pinctrl_pin_desc axp209_pins[] = {
	71	PINCTRL_PIN(0, "GPIO0"),
	72	PINCTRL_PIN(1, "GPIO1"),
	73	PINCTRL_PIN(2, "GPIO2"),
	74	};
	75
e1190083 QS	76	static const struct pinctrl_pin_desc axp813_pins[] = {
	77	PINCTRL_PIN(0, "GPIO0"),
	78	PINCTRL_PIN(1, "GPIO1"),
	79	};
	80
23f75d7d QS	81	static const struct axp20x_pctrl_desc axp20x_data = {
	82	.pins = axp209_pins,
	83	.npins = ARRAY_SIZE(axp209_pins),
	84	.ldo_mask = BIT(0) \| BIT(1),
	85	.adc_mask = BIT(0) \| BIT(1),
48e706fb	86	.gpio_status_offset = 4,
a0a4b4c2	87	.adc_mux = AXP20X_MUX_ADC,
f72f4b44 MR	88	};
f72f4b44 MR	89
e1190083 QS	90	static const struct axp20x_pctrl_desc axp813_data = {
	91	.pins = axp813_pins,
	92	.npins = ARRAY_SIZE(axp813_pins),
	93	.ldo_mask = BIT(0) \| BIT(1),
	94	.adc_mask = BIT(0),
	95	.gpio_status_offset = 0,
	96	.adc_mux = AXP813_MUX_ADC,
	97	};
	98
3cac991e	99	static int axp20x_gpio_get_reg(unsigned int offset)
f72f4b44 MR	100	{
	101	switch (offset) {
	102	case 0:
	103	return AXP20X_GPIO0_CTRL;
	104	case 1:
	105	return AXP20X_GPIO1_CTRL;
	106	case 2:
	107	return AXP20X_GPIO2_CTRL;
	108	}
	109
	110	return -EINVAL;
	111	}
	112
3cac991e	113	static int axp20x_gpio_input(struct gpio_chip *chip, unsigned int offset)
f72f4b44	114	{
23f75d7d	115	return pinctrl_gpio_direction_input(chip->base + offset);
f72f4b44 MR	116	}
f72f4b44 MR	117
3cac991e	118	static int axp20x_gpio_get(struct gpio_chip *chip, unsigned int offset)
f72f4b44	119	{
d242e60c	120	struct axp20x_pctl *pctl = gpiochip_get_data(chip);
f72f4b44	121	unsigned int val;
1d2b2ac0	122	int ret;
f72f4b44	123
d242e60c	124	ret = regmap_read(pctl->regmap, AXP20X_GPIO20_SS, &val);
f72f4b44 MR	125	if (ret)
	126	return ret;
	127
48e706fb	128	return !!(val & BIT(offset + pctl->desc->gpio_status_offset));
f72f4b44 MR	129	}
f72f4b44 MR	130
3cac991e QS	131	static int axp20x_gpio_get_direction(struct gpio_chip *chip,
3cac991e QS	132	unsigned int offset)
81d3753d	133	{
d242e60c	134	struct axp20x_pctl *pctl = gpiochip_get_data(chip);
81d3753d MR	135	unsigned int val;
	136	int reg, ret;
	137
	138	reg = axp20x_gpio_get_reg(offset);
	139	if (reg < 0)
	140	return reg;
	141
d242e60c	142	ret = regmap_read(pctl->regmap, reg, &val);
81d3753d MR	143	if (ret)
	144	return ret;
	145
	146	/*
	147	* This shouldn't really happen if the pin is in use already,
	148	* or if it's not in use yet, it doesn't matter since we're
	149	* going to change the value soon anyway. Default to output.
	150	*/
	151	if ((val & AXP20X_GPIO_FUNCTIONS) > 2)
3c827873	152	return GPIO_LINE_DIRECTION_OUT;
81d3753d MR	153
	154	/*
	155	* The GPIO directions are the three lowest values.
	156	* 2 is input, 0 and 1 are output
	157	*/
3c827873 MV	158	if (val & 2)
	159	return GPIO_LINE_DIRECTION_IN;
	160
	161	return GPIO_LINE_DIRECTION_OUT;
81d3753d MR	162	}
81d3753d MR	163
3cac991e	164	static int axp20x_gpio_output(struct gpio_chip *chip, unsigned int offset,
f72f4b44	165	int value)
23f75d7d QS	166	{
	167	chip->set(chip, offset, value);
	168
	169	return 0;
	170	}
	171
	172	static void axp20x_gpio_set(struct gpio_chip *chip, unsigned int offset,
	173	int value)
f72f4b44	174	{
d242e60c	175	struct axp20x_pctl *pctl = gpiochip_get_data(chip);
f72f4b44 MR	176	int reg;
f72f4b44 MR	177
23f75d7d QS	178	reg = axp20x_gpio_get_reg(offset);
	179	if (reg < 0)
	180	return;
	181
d242e60c	182	regmap_update_bits(pctl->regmap, reg,
23f75d7d QS	183	AXP20X_GPIO_FUNCTIONS,
	184	value ? AXP20X_GPIO_FUNCTION_OUT_HIGH :
	185	AXP20X_GPIO_FUNCTION_OUT_LOW);
	186	}
	187
	188	static int axp20x_pmx_set(struct pinctrl_dev *pctldev, unsigned int offset,
	189	u8 config)
	190	{
d242e60c	191	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
23f75d7d QS	192	int reg;
23f75d7d QS	193
f72f4b44 MR	194	reg = axp20x_gpio_get_reg(offset);
	195	if (reg < 0)
	196	return reg;
	197
d242e60c	198	return regmap_update_bits(pctl->regmap, reg, AXP20X_GPIO_FUNCTIONS,
23f75d7d	199	config);
f72f4b44 MR	200	}
f72f4b44 MR	201
23f75d7d QS	202	static int axp20x_pmx_func_cnt(struct pinctrl_dev *pctldev)
23f75d7d QS	203	{
d242e60c	204	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
23f75d7d	205
d242e60c	206	return ARRAY_SIZE(pctl->funcs);
23f75d7d QS	207	}
	208
	209	static const char axp20x_pmx_func_name(struct pinctrl_dev pctldev,
	210	unsigned int selector)
	211	{
d242e60c	212	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
23f75d7d	213
d242e60c	214	return pctl->funcs[selector].name;
23f75d7d QS	215	}
	216
	217	static int axp20x_pmx_func_groups(struct pinctrl_dev *pctldev,
	218	unsigned int selector,
	219	const char * const **groups,
	220	unsigned int *num_groups)
	221	{
d242e60c	222	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
23f75d7d	223
d242e60c QS	224	*groups = pctl->funcs[selector].groups;
d242e60c QS	225	*num_groups = pctl->funcs[selector].ngroups;
23f75d7d QS	226
	227	return 0;
	228	}
	229
	230	static int axp20x_pmx_set_mux(struct pinctrl_dev *pctldev,
	231	unsigned int function, unsigned int group)
	232	{
d242e60c	233	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
23f75d7d QS	234	unsigned int mask;
	235
	236	/* Every pin supports GPIO_OUT and GPIO_IN functions */
	237	if (function <= AXP20X_FUNC_GPIO_IN)
	238	return axp20x_pmx_set(pctldev, group,
d242e60c	239	pctl->funcs[function].muxval);
23f75d7d QS	240
23f75d7d QS	241	if (function == AXP20X_FUNC_LDO)
d242e60c	242	mask = pctl->desc->ldo_mask;
23f75d7d	243	else
d242e60c	244	mask = pctl->desc->adc_mask;
23f75d7d QS	245
	246	if (!(BIT(group) & mask))
	247	return -EINVAL;
	248
	249	/*
	250	* We let the regulator framework handle the LDO muxing as muxing bits
	251	* are basically also regulators on/off bits. It's better not to enforce
	252	* any state of the regulator when selecting LDO mux so that we don't
	253	* interfere with the regulator driver.
	254	*/
	255	if (function == AXP20X_FUNC_LDO)
	256	return 0;
	257
d242e60c	258	return axp20x_pmx_set(pctldev, group, pctl->funcs[function].muxval);
23f75d7d QS	259	}
	260
	261	static int axp20x_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
	262	struct pinctrl_gpio_range *range,
	263	unsigned int offset, bool input)
	264	{
d242e60c	265	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
23f75d7d QS	266
	267	if (input)
	268	return axp20x_pmx_set(pctldev, offset,
d242e60c	269	pctl->funcs[AXP20X_FUNC_GPIO_IN].muxval);
23f75d7d QS	270
23f75d7d QS	271	return axp20x_pmx_set(pctldev, offset,
d242e60c	272	pctl->funcs[AXP20X_FUNC_GPIO_OUT].muxval);
23f75d7d QS	273	}
	274
	275	static const struct pinmux_ops axp20x_pmx_ops = {
	276	.get_functions_count = axp20x_pmx_func_cnt,
	277	.get_function_name = axp20x_pmx_func_name,
	278	.get_function_groups = axp20x_pmx_func_groups,
	279	.set_mux = axp20x_pmx_set_mux,
	280	.gpio_set_direction = axp20x_pmx_gpio_set_direction,
	281	.strict = true,
	282	};
	283
	284	static int axp20x_groups_cnt(struct pinctrl_dev *pctldev)
	285	{
d242e60c	286	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
23f75d7d	287
d242e60c	288	return pctl->desc->npins;
23f75d7d QS	289	}
	290
	291	static int axp20x_group_pins(struct pinctrl_dev *pctldev, unsigned int selector,
	292	const unsigned int *pins, unsigned int num_pins)
	293	{
d242e60c	294	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
23f75d7d	295
d242e60c	296	pins = (unsigned int )&pctl->desc->pins[selector];
23f75d7d QS	297	*num_pins = 1;
	298
	299	return 0;
	300	}
	301
	302	static const char axp20x_group_name(struct pinctrl_dev pctldev,
	303	unsigned int selector)
f72f4b44	304	{
d242e60c	305	struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
23f75d7d	306
d242e60c	307	return pctl->desc->pins[selector].name;
23f75d7d QS	308	}
	309
	310	static const struct pinctrl_ops axp20x_pctrl_ops = {
	311	.dt_node_to_map = pinconf_generic_dt_node_to_map_group,
	312	.dt_free_map = pinconf_generic_dt_free_map,
	313	.get_groups_count = axp20x_groups_cnt,
	314	.get_group_name = axp20x_group_name,
	315	.get_group_pins = axp20x_group_pins,
	316	};
	317
504c7697	318	static int axp20x_funcs_groups_from_mask(struct device *dev, unsigned int mask,
23f75d7d QS	319	unsigned int mask_len,
	320	struct axp20x_pinctrl_function *func,
	321	const struct pinctrl_pin_desc *pins)
	322	{
	323	unsigned long int mask_cpy = mask;
	324	const char **group;
	325	unsigned int ngroups = hweight8(mask);
	326	int bit;
	327
	328	func->ngroups = ngroups;
	329	if (func->ngroups > 0) {
a86854d0 KC	330	func->groups = devm_kcalloc(dev,
a86854d0 KC	331	ngroups, sizeof(const char *),
23f75d7d	332	GFP_KERNEL);
504c7697 AV	333	if (!func->groups)
504c7697 AV	334	return -ENOMEM;
23f75d7d QS	335	group = func->groups;
	336	for_each_set_bit(bit, &mask_cpy, mask_len) {
	337	*group = pins[bit].name;
	338	group++;
	339	}
	340	}
504c7697 AV	341
504c7697 AV	342	return 0;
23f75d7d QS	343	}
23f75d7d QS	344
504c7697	345	static int axp20x_build_funcs_groups(struct platform_device *pdev)
23f75d7d	346	{
d242e60c	347	struct axp20x_pctl *pctl = platform_get_drvdata(pdev);
504c7697	348	int i, ret, pin, npins = pctl->desc->npins;
d242e60c QS	349
	350	pctl->funcs[AXP20X_FUNC_GPIO_OUT].name = "gpio_out";
	351	pctl->funcs[AXP20X_FUNC_GPIO_OUT].muxval = AXP20X_MUX_GPIO_OUT;
	352	pctl->funcs[AXP20X_FUNC_GPIO_IN].name = "gpio_in";
	353	pctl->funcs[AXP20X_FUNC_GPIO_IN].muxval = AXP20X_MUX_GPIO_IN;
	354	pctl->funcs[AXP20X_FUNC_LDO].name = "ldo";
23f75d7d QS	355	/*
	356	* Muxval for LDO is useless as we won't use it.
	357	* See comment in axp20x_pmx_set_mux.
	358	*/
d242e60c	359	pctl->funcs[AXP20X_FUNC_ADC].name = "adc";
a0a4b4c2	360	pctl->funcs[AXP20X_FUNC_ADC].muxval = pctl->desc->adc_mux;
23f75d7d QS	361
	362	/* Every pin supports GPIO_OUT and GPIO_IN functions */
	363	for (i = 0; i <= AXP20X_FUNC_GPIO_IN; i++) {
d242e60c	364	pctl->funcs[i].ngroups = npins;
a86854d0 KC	365	pctl->funcs[i].groups = devm_kcalloc(&pdev->dev,
a86854d0 KC	366	npins, sizeof(char *),
23f75d7d	367	GFP_KERNEL);
1adc90c7 AP	368	if (!pctl->funcs[i].groups)
1adc90c7 AP	369	return -ENOMEM;
23f75d7d	370	for (pin = 0; pin < npins; pin++)
d242e60c	371	pctl->funcs[i].groups[pin] = pctl->desc->pins[pin].name;
23f75d7d QS	372	}
23f75d7d QS	373
504c7697	374	ret = axp20x_funcs_groups_from_mask(&pdev->dev, pctl->desc->ldo_mask,
d242e60c QS	375	npins, &pctl->funcs[AXP20X_FUNC_LDO],
d242e60c QS	376	pctl->desc->pins);
504c7697 AV	377	if (ret)
504c7697 AV	378	return ret;
23f75d7d	379
504c7697	380	ret = axp20x_funcs_groups_from_mask(&pdev->dev, pctl->desc->adc_mask,
d242e60c QS	381	npins, &pctl->funcs[AXP20X_FUNC_ADC],
d242e60c QS	382	pctl->desc->pins);
504c7697 AV	383	if (ret)
	384	return ret;
	385
	386	return 0;
f72f4b44 MR	387	}
f72f4b44 MR	388
e1190083 QS	389	static const struct of_device_id axp20x_pctl_match[] = {
	390	{ .compatible = "x-powers,axp209-gpio", .data = &axp20x_data, },
	391	{ .compatible = "x-powers,axp813-gpio", .data = &axp813_data, },
	392	{ }
	393	};
	394	MODULE_DEVICE_TABLE(of, axp20x_pctl_match);
	395
d242e60c	396	static int axp20x_pctl_probe(struct platform_device *pdev)
f72f4b44 MR	397	{
f72f4b44 MR	398	struct axp20x_dev *axp20x = dev_get_drvdata(pdev->dev.parent);
d242e60c	399	struct axp20x_pctl *pctl;
e1190083	400	struct device *dev = &pdev->dev;
23f75d7d	401	struct pinctrl_desc *pctrl_desc;
f72f4b44 MR	402	int ret;
	403
	404	if (!of_device_is_available(pdev->dev.of_node))
	405	return -ENODEV;
	406
	407	if (!axp20x) {
	408	dev_err(&pdev->dev, "Parent drvdata not set\n");
	409	return -EINVAL;
	410	}
	411
d242e60c QS	412	pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
d242e60c QS	413	if (!pctl)
f72f4b44 MR	414	return -ENOMEM;
f72f4b44 MR	415
d242e60c QS	416	pctl->chip.base = -1;
	417	pctl->chip.can_sleep = true;
	418	pctl->chip.request = gpiochip_generic_request;
	419	pctl->chip.free = gpiochip_generic_free;
	420	pctl->chip.parent = &pdev->dev;
	421	pctl->chip.label = dev_name(&pdev->dev);
	422	pctl->chip.owner = THIS_MODULE;
	423	pctl->chip.get = axp20x_gpio_get;
	424	pctl->chip.get_direction = axp20x_gpio_get_direction;
	425	pctl->chip.set = axp20x_gpio_set;
	426	pctl->chip.direction_input = axp20x_gpio_input;
	427	pctl->chip.direction_output = axp20x_gpio_output;
d242e60c	428
9b8ee3c0	429	pctl->desc = of_device_get_match_data(dev);
a0498152 QS	430
	431	pctl->chip.ngpio = pctl->desc->npins;
	432
d242e60c QS	433	pctl->regmap = axp20x->regmap;
	434	pctl->dev = &pdev->dev;
	435
	436	platform_set_drvdata(pdev, pctl);
23f75d7d	437
504c7697 AV	438	ret = axp20x_build_funcs_groups(pdev);
	439	if (ret) {
	440	dev_err(&pdev->dev, "failed to build groups\n");
	441	return ret;
	442	}
23f75d7d QS	443
	444	pctrl_desc = devm_kzalloc(&pdev->dev, sizeof(*pctrl_desc), GFP_KERNEL);
	445	if (!pctrl_desc)
	446	return -ENOMEM;
	447
	448	pctrl_desc->name = dev_name(&pdev->dev);
	449	pctrl_desc->owner = THIS_MODULE;
d242e60c QS	450	pctrl_desc->pins = pctl->desc->pins;
d242e60c QS	451	pctrl_desc->npins = pctl->desc->npins;
23f75d7d QS	452	pctrl_desc->pctlops = &axp20x_pctrl_ops;
	453	pctrl_desc->pmxops = &axp20x_pmx_ops;
	454
d242e60c QS	455	pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, pctrl_desc, pctl);
d242e60c QS	456	if (IS_ERR(pctl->pctl_dev)) {
23f75d7d	457	dev_err(&pdev->dev, "couldn't register pinctrl driver\n");
d242e60c	458	return PTR_ERR(pctl->pctl_dev);
23f75d7d	459	}
f72f4b44	460
d242e60c	461	ret = devm_gpiochip_add_data(&pdev->dev, &pctl->chip, pctl);
f72f4b44 MR	462	if (ret) {
	463	dev_err(&pdev->dev, "Failed to register GPIO chip\n");
	464	return ret;
	465	}
	466
d242e60c QS	467	ret = gpiochip_add_pin_range(&pctl->chip, dev_name(&pdev->dev),
	468	pctl->desc->pins->number,
	469	pctl->desc->pins->number,
	470	pctl->desc->npins);
23f75d7d QS	471	if (ret) {
	472	dev_err(&pdev->dev, "failed to add pin range\n");
	473	return ret;
	474	}
	475
	476	dev_info(&pdev->dev, "AXP209 pinctrl and GPIO driver loaded\n");
f72f4b44 MR	477
	478	return 0;
	479	}
	480
d242e60c QS	481	static struct platform_driver axp20x_pctl_driver = {
d242e60c QS	482	.probe = axp20x_pctl_probe,
f72f4b44 MR	483	.driver = {
f72f4b44 MR	484	.name = "axp20x-gpio",
d242e60c	485	.of_match_table = axp20x_pctl_match,
f72f4b44 MR	486	},
	487	};
	488
d242e60c	489	module_platform_driver(axp20x_pctl_driver);
f72f4b44 MR	490
f72f4b44 MR	491	MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
23f75d7d QS	492	MODULE_AUTHOR("Quentin Schulz <quentin.schulz@free-electrons.com>");
23f75d7d QS	493	MODULE_DESCRIPTION("AXP20x PMIC pinctrl and GPIO driver");
f72f4b44	494	MODULE_LICENSE("GPL");