[mirror_ubuntu-bionic-kernel.git] / drivers / pinctrl / pinctrl-baytrail.c

/*
 * Pinctrl GPIO driver for Intel Baytrail
 * Copyright (c) 2012-2013, Intel Corporation.
 *
 * Author: Mathias Nyman <mathias.nyman@linux.intel.com>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program; if not, write to the Free Software Foundation, Inc.,
 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
 *
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/types.h>
#include <linux/bitops.h>
#include <linux/interrupt.h>
#include <linux/gpio.h>
#include <linux/acpi.h>
#include <linux/platform_device.h>
#include <linux/seq_file.h>
#include <linux/io.h>
#include <linux/pm_runtime.h>
#include <linux/pinctrl/pinctrl.h>

/* memory mapped register offsets */
#define BYT_CONF0_REG		0x000
#define BYT_CONF1_REG		0x004
#define BYT_VAL_REG		0x008
#define BYT_DFT_REG		0x00c
#define BYT_INT_STAT_REG	0x800

/* BYT_CONF0_REG register bits */
#define BYT_IODEN		BIT(31)
#define BYT_DIRECT_IRQ_EN	BIT(27)
#define BYT_TRIG_NEG		BIT(26)
#define BYT_TRIG_POS		BIT(25)
#define BYT_TRIG_LVL		BIT(24)
#define BYT_PULL_STR_SHIFT	9
#define BYT_PULL_STR_MASK	(3 << BYT_PULL_STR_SHIFT)
#define BYT_PULL_STR_2K		(0 << BYT_PULL_STR_SHIFT)
#define BYT_PULL_STR_10K	(1 << BYT_PULL_STR_SHIFT)
#define BYT_PULL_STR_20K	(2 << BYT_PULL_STR_SHIFT)
#define BYT_PULL_STR_40K	(3 << BYT_PULL_STR_SHIFT)
#define BYT_PULL_ASSIGN_SHIFT	7
#define BYT_PULL_ASSIGN_MASK	(3 << BYT_PULL_ASSIGN_SHIFT)
#define BYT_PULL_ASSIGN_UP	(1 << BYT_PULL_ASSIGN_SHIFT)
#define BYT_PULL_ASSIGN_DOWN	(2 << BYT_PULL_ASSIGN_SHIFT)
#define BYT_PIN_MUX		0x07

/* BYT_VAL_REG register bits */
#define BYT_INPUT_EN		BIT(2)  /* 0: input enabled (active low)*/
#define BYT_OUTPUT_EN		BIT(1)  /* 0: output enabled (active low)*/
#define BYT_LEVEL		BIT(0)

#define BYT_DIR_MASK		(BIT(1) | BIT(2))
#define BYT_TRIG_MASK		(BIT(26) | BIT(25) | BIT(24))

#define BYT_NGPIO_SCORE		102
#define BYT_NGPIO_NCORE		28
#define BYT_NGPIO_SUS		44

#define BYT_SCORE_ACPI_UID	"1"
#define BYT_NCORE_ACPI_UID	"2"
#define BYT_SUS_ACPI_UID	"3"

/*
 * Baytrail gpio controller consist of three separate sub-controllers called
 * SCORE, NCORE and SUS. The sub-controllers are identified by their acpi UID.
 *
 * GPIO numbering is _not_ ordered meaning that gpio # 0 in ACPI namespace does
 * _not_ correspond to the first gpio register at controller's gpio base.
 * There is no logic or pattern in mapping gpio numbers to registers (pads) so
 * each sub-controller needs to have its own mapping table
 */

/* score_pins[gpio_nr] = pad_nr */

static unsigned const score_pins[BYT_NGPIO_SCORE] = {
	85, 89, 93, 96, 99, 102, 98, 101, 34, 37,
	36, 38, 39, 35, 40, 84, 62, 61, 64, 59,
	54, 56, 60, 55, 63, 57, 51, 50, 53, 47,
	52, 49, 48, 43, 46, 41, 45, 42, 58, 44,
	95, 105, 70, 68, 67, 66, 69, 71, 65, 72,
	86, 90, 88, 92, 103, 77, 79, 83, 78, 81,
	80, 82, 13, 12, 15, 14, 17, 18, 19, 16,
	2, 1, 0, 4, 6, 7, 9, 8, 33, 32,
	31, 30, 29, 27, 25, 28, 26, 23, 21, 20,
	24, 22, 5, 3, 10, 11, 106, 87, 91, 104,
	97, 100,
};

static unsigned const ncore_pins[BYT_NGPIO_NCORE] = {
	19, 18, 17, 20, 21, 22, 24, 25, 23, 16,
	14, 15, 12, 26, 27, 1, 4, 8, 11, 0,
	3, 6, 10, 13, 2, 5, 9, 7,
};

static unsigned const sus_pins[BYT_NGPIO_SUS] = {
	29, 33, 30, 31, 32, 34, 36, 35, 38, 37,
	18, 7, 11, 20, 17, 1, 8, 10, 19, 12,
	0, 2, 23, 39, 28, 27, 22, 21, 24, 25,
	26, 51, 56, 54, 49, 55, 48, 57, 50, 58,
	52, 53, 59, 40,
};

static struct pinctrl_gpio_range byt_ranges[] = {
	{
		.name = BYT_SCORE_ACPI_UID, /* match with acpi _UID in probe */
		.npins = BYT_NGPIO_SCORE,
		.pins = score_pins,
	},
	{
		.name = BYT_NCORE_ACPI_UID,
		.npins = BYT_NGPIO_NCORE,
		.pins = ncore_pins,
	},
	{
		.name = BYT_SUS_ACPI_UID,
		.npins = BYT_NGPIO_SUS,
		.pins = sus_pins,
	},
	{
	},
};

struct byt_gpio {
	struct gpio_chip		chip;
	struct platform_device		*pdev;
	spinlock_t			lock;
	void __iomem			*reg_base;
	struct pinctrl_gpio_range	*range;
};

#define to_byt_gpio(c)	container_of(c, struct byt_gpio, chip)

static void __iomem *byt_gpio_reg(struct gpio_chip *chip, unsigned offset,
				 int reg)
{
	struct byt_gpio *vg = to_byt_gpio(chip);
	u32 reg_offset;

	if (reg == BYT_INT_STAT_REG)
		reg_offset = (offset / 32) * 4;
	else
		reg_offset = vg->range->pins[offset] * 16;

	return vg->reg_base + reg_offset + reg;
}

static bool is_special_pin(struct byt_gpio *vg, unsigned offset)
{
	/* SCORE pin 92-93 */
	if (!strcmp(vg->range->name, BYT_SCORE_ACPI_UID) &&
		offset >= 92 && offset <= 93)
		return true;

	/* SUS pin 11-21 */
	if (!strcmp(vg->range->name, BYT_SUS_ACPI_UID) &&
		offset >= 11 && offset <= 21)
		return true;

	return false;
}

static int byt_gpio_request(struct gpio_chip *chip, unsigned offset)
{
	struct byt_gpio *vg = to_byt_gpio(chip);
	void __iomem *reg = byt_gpio_reg(chip, offset, BYT_CONF0_REG);
	u32 value;
	bool special;

	/*
	 * In most cases, func pin mux 000 means GPIO function.
	 * But, some pins may have func pin mux 001 represents
	 * GPIO function. Only allow user to export pin with
	 * func pin mux preset as GPIO function by BIOS/FW.
	 */
	value = readl(reg) & BYT_PIN_MUX;
	special = is_special_pin(vg, offset);
	if ((special && value != 1) || (!special && value)) {
		dev_err(&vg->pdev->dev,
			"pin %u cannot be used as GPIO.\n", offset);
		return -EINVAL;
	}

	pm_runtime_get(&vg->pdev->dev);

	return 0;
}

static void byt_gpio_free(struct gpio_chip *chip, unsigned offset)
{
	struct byt_gpio *vg = to_byt_gpio(chip);
	void __iomem *reg = byt_gpio_reg(&vg->chip, offset, BYT_CONF0_REG);
	u32 value;

	/* clear interrupt triggering */
	value = readl(reg);
	value &= ~(BYT_TRIG_POS | BYT_TRIG_NEG | BYT_TRIG_LVL);
	writel(value, reg);

	pm_runtime_put(&vg->pdev->dev);
}

static int byt_irq_type(struct irq_data *d, unsigned type)
{
	struct byt_gpio *vg = to_byt_gpio(irq_data_get_irq_chip_data(d));
	u32 offset = irqd_to_hwirq(d);
	u32 value;
	unsigned long flags;
	void __iomem *reg = byt_gpio_reg(&vg->chip, offset, BYT_CONF0_REG);

	if (offset >= vg->chip.ngpio)
		return -EINVAL;

	spin_lock_irqsave(&vg->lock, flags);
	value = readl(reg);

	WARN(value & BYT_DIRECT_IRQ_EN,
		"Bad pad config for io mode, force direct_irq_en bit clearing");

	/* For level trigges the BYT_TRIG_POS and BYT_TRIG_NEG bits
	 * are used to indicate high and low level triggering
	 */
	value &= ~(BYT_DIRECT_IRQ_EN | BYT_TRIG_POS | BYT_TRIG_NEG |
		   BYT_TRIG_LVL);

	switch (type) {
	case IRQ_TYPE_LEVEL_HIGH:
		value |= BYT_TRIG_LVL;
	case IRQ_TYPE_EDGE_RISING:
		value |= BYT_TRIG_POS;
		break;
	case IRQ_TYPE_LEVEL_LOW:
		value |= BYT_TRIG_LVL;
	case IRQ_TYPE_EDGE_FALLING:
		value |= BYT_TRIG_NEG;
		break;
	case IRQ_TYPE_EDGE_BOTH:
		value |= (BYT_TRIG_NEG | BYT_TRIG_POS);
		break;
	}
	writel(value, reg);

	spin_unlock_irqrestore(&vg->lock, flags);

	return 0;
}

static int byt_gpio_get(struct gpio_chip *chip, unsigned offset)
{
	void __iomem *reg = byt_gpio_reg(chip, offset, BYT_VAL_REG);
	return readl(reg) & BYT_LEVEL;
}

static void byt_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
	struct byt_gpio *vg = to_byt_gpio(chip);
	void __iomem *reg = byt_gpio_reg(chip, offset, BYT_VAL_REG);
	unsigned long flags;
	u32 old_val;

	spin_lock_irqsave(&vg->lock, flags);

	old_val = readl(reg);

	if (value)
		writel(old_val | BYT_LEVEL, reg);
	else
		writel(old_val & ~BYT_LEVEL, reg);

	spin_unlock_irqrestore(&vg->lock, flags);
}

static int byt_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
{
	struct byt_gpio *vg = to_byt_gpio(chip);
	void __iomem *reg = byt_gpio_reg(chip, offset, BYT_VAL_REG);
	unsigned long flags;
	u32 value;

	spin_lock_irqsave(&vg->lock, flags);

	value = readl(reg) | BYT_DIR_MASK;
	value &= ~BYT_INPUT_EN;		/* active low */
	writel(value, reg);

	spin_unlock_irqrestore(&vg->lock, flags);

	return 0;
}

static int byt_gpio_direction_output(struct gpio_chip *chip,
				     unsigned gpio, int value)
{
	struct byt_gpio *vg = to_byt_gpio(chip);
	void __iomem *conf_reg = byt_gpio_reg(chip, gpio, BYT_CONF0_REG);
	void __iomem *reg = byt_gpio_reg(chip, gpio, BYT_VAL_REG);
	unsigned long flags;
	u32 reg_val;

	spin_lock_irqsave(&vg->lock, flags);

	/*
	 * Before making any direction modifications, do a check if gpio
	 * is set for direct IRQ.  On baytrail, setting GPIO to output does
	 * not make sense, so let's at least warn the caller before they shoot
	 * themselves in the foot.
	 */
	WARN(readl(conf_reg) & BYT_DIRECT_IRQ_EN,
		"Potential Error: Setting GPIO with direct_irq_en to output");

	reg_val = readl(reg) | BYT_DIR_MASK;
	reg_val &= ~(BYT_OUTPUT_EN | BYT_INPUT_EN);

	if (value)
		writel(reg_val | BYT_LEVEL, reg);
	else
		writel(reg_val & ~BYT_LEVEL, reg);

	spin_unlock_irqrestore(&vg->lock, flags);

	return 0;
}

static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
{
	struct byt_gpio *vg = to_byt_gpio(chip);
	int i;
	unsigned long flags;
	u32 conf0, val, offs;

	spin_lock_irqsave(&vg->lock, flags);

	for (i = 0; i < vg->chip.ngpio; i++) {
		const char *pull_str = NULL;
		const char *pull = NULL;
		const char *label;
		offs = vg->range->pins[i] * 16;
		conf0 = readl(vg->reg_base + offs + BYT_CONF0_REG);
		val = readl(vg->reg_base + offs + BYT_VAL_REG);

		label = gpiochip_is_requested(chip, i);
		if (!label)
			label = "Unrequested";

		switch (conf0 & BYT_PULL_ASSIGN_MASK) {
		case BYT_PULL_ASSIGN_UP:
			pull = "up";
			break;
		case BYT_PULL_ASSIGN_DOWN:
			pull = "down";
			break;
		}

		switch (conf0 & BYT_PULL_STR_MASK) {
		case BYT_PULL_STR_2K:
			pull_str = "2k";
			break;
		case BYT_PULL_STR_10K:
			pull_str = "10k";
			break;
		case BYT_PULL_STR_20K:
			pull_str = "20k";
			break;
		case BYT_PULL_STR_40K:
			pull_str = "40k";
			break;
		}

		seq_printf(s,
			   " gpio-%-3d (%-20.20s) %s %s %s pad-%-3d offset:0x%03x mux:%d %s%s%s",
			   i,
			   label,
			   val & BYT_INPUT_EN ? "  " : "in",
			   val & BYT_OUTPUT_EN ? "   " : "out",
			   val & BYT_LEVEL ? "hi" : "lo",
			   vg->range->pins[i], offs,
			   conf0 & 0x7,
			   conf0 & BYT_TRIG_NEG ? " fall" : "     ",
			   conf0 & BYT_TRIG_POS ? " rise" : "     ",
			   conf0 & BYT_TRIG_LVL ? " level" : "      ");

		if (pull && pull_str)
			seq_printf(s, " %-4s %-3s", pull, pull_str);
		else
			seq_puts(s, "          ");

		if (conf0 & BYT_IODEN)
			seq_puts(s, " open-drain");

		seq_puts(s, "\n");
	}
	spin_unlock_irqrestore(&vg->lock, flags);
}

static void byt_gpio_irq_handler(unsigned irq, struct irq_desc *desc)
{
	struct irq_data *data = irq_desc_get_irq_data(desc);
	struct byt_gpio *vg = to_byt_gpio(irq_desc_get_handler_data(desc));
	struct irq_chip *chip = irq_data_get_irq_chip(data);
	u32 base, pin, mask;
	void __iomem *reg;
	u32 pending;
	unsigned virq;
	int looplimit = 0;

	/* check from GPIO controller which pin triggered the interrupt */
	for (base = 0; base < vg->chip.ngpio; base += 32) {

		reg = byt_gpio_reg(&vg->chip, base, BYT_INT_STAT_REG);

		while ((pending = readl(reg))) {
			pin = __ffs(pending);
			mask = BIT(pin);
			/* Clear before handling so we can't lose an edge */
			writel(mask, reg);

			virq = irq_find_mapping(vg->chip.irqdomain, base + pin);
			generic_handle_irq(virq);

			/* In case bios or user sets triggering incorretly a pin
			 * might remain in "interrupt triggered" state.
			 */
			if (looplimit++ > 32) {
				dev_err(&vg->pdev->dev,
					"Gpio %d interrupt flood, disabling\n",
					base + pin);

				reg = byt_gpio_reg(&vg->chip, base + pin,
						   BYT_CONF0_REG);
				mask = readl(reg);
				mask &= ~(BYT_TRIG_NEG | BYT_TRIG_POS |
					  BYT_TRIG_LVL);
				writel(mask, reg);
				mask = readl(reg); /* flush */
				break;
			}
		}
	}
	chip->irq_eoi(data);
}

static void byt_irq_unmask(struct irq_data *d)
{
}

static void byt_irq_mask(struct irq_data *d)
{
}

static struct irq_chip byt_irqchip = {
	.name = "BYT-GPIO",
	.irq_mask = byt_irq_mask,
	.irq_unmask = byt_irq_unmask,
	.irq_set_type = byt_irq_type,
	.flags = IRQCHIP_SKIP_SET_WAKE,
};

static void byt_gpio_irq_init_hw(struct byt_gpio *vg)
{
	void __iomem *reg;
	u32 base, value;

	/* clear interrupt status trigger registers */
	for (base = 0; base < vg->chip.ngpio; base += 32) {
		reg = byt_gpio_reg(&vg->chip, base, BYT_INT_STAT_REG);
		writel(0xffffffff, reg);
		/* make sure trigger bits are cleared, if not then a pin
		   might be misconfigured in bios */
		value = readl(reg);
		if (value)
			dev_err(&vg->pdev->dev,
				"GPIO interrupt error, pins misconfigured\n");
	}
}

static int byt_gpio_probe(struct platform_device *pdev)
{
	struct byt_gpio *vg;
	struct gpio_chip *gc;
	struct resource *mem_rc, *irq_rc;
	struct device *dev = &pdev->dev;
	struct acpi_device *acpi_dev;
	struct pinctrl_gpio_range *range;
	acpi_handle handle = ACPI_HANDLE(dev);
	int ret;

	if (acpi_bus_get_device(handle, &acpi_dev))
		return -ENODEV;

	vg = devm_kzalloc(dev, sizeof(struct byt_gpio), GFP_KERNEL);
	if (!vg) {
		dev_err(&pdev->dev, "can't allocate byt_gpio chip data\n");
		return -ENOMEM;
	}

	for (range = byt_ranges; range->name; range++) {
		if (!strcmp(acpi_dev->pnp.unique_id, range->name)) {
			vg->chip.ngpio = range->npins;
			vg->range = range;
			break;
		}
	}

	if (!vg->chip.ngpio || !vg->range)
		return -ENODEV;

	vg->pdev = pdev;
	platform_set_drvdata(pdev, vg);

	mem_rc = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	vg->reg_base = devm_ioremap_resource(dev, mem_rc);
	if (IS_ERR(vg->reg_base))
		return PTR_ERR(vg->reg_base);

	spin_lock_init(&vg->lock);

	gc = &vg->chip;
	gc->label = dev_name(&pdev->dev);
	gc->owner = THIS_MODULE;
	gc->request = byt_gpio_request;
	gc->free = byt_gpio_free;
	gc->direction_input = byt_gpio_direction_input;
	gc->direction_output = byt_gpio_direction_output;
	gc->get = byt_gpio_get;
	gc->set = byt_gpio_set;
	gc->dbg_show = byt_gpio_dbg_show;
	gc->base = -1;
	gc->can_sleep = false;
	gc->dev = dev;

	ret = gpiochip_add(gc);
	if (ret) {
		dev_err(&pdev->dev, "failed adding byt-gpio chip\n");
		return ret;
	}

	/* set up interrupts  */
	irq_rc = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
	if (irq_rc && irq_rc->start) {
		byt_gpio_irq_init_hw(vg);
		ret = gpiochip_irqchip_add(gc, &byt_irqchip, 0,
					   handle_simple_irq, IRQ_TYPE_NONE);
		if (ret) {
			dev_err(dev, "failed to add irqchip\n");
			gpiochip_remove(gc);
			return ret;
		}

		gpiochip_set_chained_irqchip(gc, &byt_irqchip,
					     (unsigned)irq_rc->start,
					     byt_gpio_irq_handler);
	}

	pm_runtime_enable(dev);

	return 0;
}

static int byt_gpio_runtime_suspend(struct device *dev)
{
	return 0;
}

static int byt_gpio_runtime_resume(struct device *dev)
{
	return 0;
}

static const struct dev_pm_ops byt_gpio_pm_ops = {
	.runtime_suspend = byt_gpio_runtime_suspend,
	.runtime_resume = byt_gpio_runtime_resume,
};

static const struct acpi_device_id byt_gpio_acpi_match[] = {
	{ "INT33B2", 0 },
	{ "INT33FC", 0 },
	{ }
};
MODULE_DEVICE_TABLE(acpi, byt_gpio_acpi_match);

static int byt_gpio_remove(struct platform_device *pdev)
{
	struct byt_gpio *vg = platform_get_drvdata(pdev);

	pm_runtime_disable(&pdev->dev);
	gpiochip_remove(&vg->chip);

	return 0;
}

static struct platform_driver byt_gpio_driver = {
	.probe          = byt_gpio_probe,
	.remove         = byt_gpio_remove,
	.driver         = {
		.name   = "byt_gpio",
		.owner  = THIS_MODULE,
		.pm	= &byt_gpio_pm_ops,
		.acpi_match_table = ACPI_PTR(byt_gpio_acpi_match),
	},
};

static int __init byt_gpio_init(void)
{
	return platform_driver_register(&byt_gpio_driver);
}

subsys_initcall(byt_gpio_init);
Commit	Line	Data
a5d811bb MN	1	/*
	2	* Pinctrl GPIO driver for Intel Baytrail
	3	* Copyright (c) 2012-2013, Intel Corporation.
	4	*
	5	* Author: Mathias Nyman <mathias.nyman@linux.intel.com>
	6	*
	7	* This program is free software; you can redistribute it and/or modify it
	8	* under the terms and conditions of the GNU General Public License,
	9	* version 2, as published by the Free Software Foundation.
	10	*
	11	* This program is distributed in the hope it will be useful, but WITHOUT
	12	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	13	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	14	* more details.
	15	*
	16	* You should have received a copy of the GNU General Public License along with
	17	* this program; if not, write to the Free Software Foundation, Inc.,
	18	* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
	19	*
	20	*/
	21
	22	#include <linux/kernel.h>
	23	#include <linux/module.h>
	24	#include <linux/init.h>
	25	#include <linux/types.h>
	26	#include <linux/bitops.h>
	27	#include <linux/interrupt.h>
a5d811bb	28	#include <linux/gpio.h>
a5d811bb	29	#include <linux/acpi.h>
a5d811bb MN	30	#include <linux/platform_device.h>
	31	#include <linux/seq_file.h>
	32	#include <linux/io.h>
	33	#include <linux/pm_runtime.h>
	34	#include <linux/pinctrl/pinctrl.h>
	35
	36	/* memory mapped register offsets */
	37	#define BYT_CONF0_REG 0x000
	38	#define BYT_CONF1_REG 0x004
	39	#define BYT_VAL_REG 0x008
	40	#define BYT_DFT_REG 0x00c
	41	#define BYT_INT_STAT_REG 0x800
	42
	43	/* BYT_CONF0_REG register bits */
3ff95885	44	#define BYT_IODEN BIT(31)
ff998356	45	#define BYT_DIRECT_IRQ_EN BIT(27)
a5d811bb MN	46	#define BYT_TRIG_NEG BIT(26)
	47	#define BYT_TRIG_POS BIT(25)
	48	#define BYT_TRIG_LVL BIT(24)
3ff95885 MW	49	#define BYT_PULL_STR_SHIFT 9
	50	#define BYT_PULL_STR_MASK (3 << BYT_PULL_STR_SHIFT)
	51	#define BYT_PULL_STR_2K (0 << BYT_PULL_STR_SHIFT)
	52	#define BYT_PULL_STR_10K (1 << BYT_PULL_STR_SHIFT)
	53	#define BYT_PULL_STR_20K (2 << BYT_PULL_STR_SHIFT)
	54	#define BYT_PULL_STR_40K (3 << BYT_PULL_STR_SHIFT)
	55	#define BYT_PULL_ASSIGN_SHIFT 7
	56	#define BYT_PULL_ASSIGN_MASK (3 << BYT_PULL_ASSIGN_SHIFT)
	57	#define BYT_PULL_ASSIGN_UP (1 << BYT_PULL_ASSIGN_SHIFT)
	58	#define BYT_PULL_ASSIGN_DOWN (2 << BYT_PULL_ASSIGN_SHIFT)
a5d811bb MN	59	#define BYT_PIN_MUX 0x07
	60
	61	/* BYT_VAL_REG register bits */
	62	#define BYT_INPUT_EN BIT(2) /* 0: input enabled (active low)*/
	63	#define BYT_OUTPUT_EN BIT(1) /* 0: output enabled (active low)*/
	64	#define BYT_LEVEL BIT(0)
	65
	66	#define BYT_DIR_MASK (BIT(1) \| BIT(2))
	67	#define BYT_TRIG_MASK (BIT(26) \| BIT(25) \| BIT(24))
	68
	69	#define BYT_NGPIO_SCORE 102
	70	#define BYT_NGPIO_NCORE 28
	71	#define BYT_NGPIO_SUS 44
	72
42bd0070 CKH	73	#define BYT_SCORE_ACPI_UID "1"
	74	#define BYT_NCORE_ACPI_UID "2"
	75	#define BYT_SUS_ACPI_UID "3"
	76
a5d811bb MN	77	/*
	78	* Baytrail gpio controller consist of three separate sub-controllers called
	79	* SCORE, NCORE and SUS. The sub-controllers are identified by their acpi UID.
	80	*
	81	* GPIO numbering is _not_ ordered meaning that gpio # 0 in ACPI namespace does
	82	* _not_ correspond to the first gpio register at controller's gpio base.
	83	* There is no logic or pattern in mapping gpio numbers to registers (pads) so
	84	* each sub-controller needs to have its own mapping table
	85	*/
	86
	87	/* score_pins[gpio_nr] = pad_nr */
	88
	89	static unsigned const score_pins[BYT_NGPIO_SCORE] = {
	90	85, 89, 93, 96, 99, 102, 98, 101, 34, 37,
	91	36, 38, 39, 35, 40, 84, 62, 61, 64, 59,
	92	54, 56, 60, 55, 63, 57, 51, 50, 53, 47,
	93	52, 49, 48, 43, 46, 41, 45, 42, 58, 44,
	94	95, 105, 70, 68, 67, 66, 69, 71, 65, 72,
	95	86, 90, 88, 92, 103, 77, 79, 83, 78, 81,
	96	80, 82, 13, 12, 15, 14, 17, 18, 19, 16,
	97	2, 1, 0, 4, 6, 7, 9, 8, 33, 32,
	98	31, 30, 29, 27, 25, 28, 26, 23, 21, 20,
	99	24, 22, 5, 3, 10, 11, 106, 87, 91, 104,
	100	97, 100,
	101	};
	102
	103	static unsigned const ncore_pins[BYT_NGPIO_NCORE] = {
	104	19, 18, 17, 20, 21, 22, 24, 25, 23, 16,
	105	14, 15, 12, 26, 27, 1, 4, 8, 11, 0,
	106	3, 6, 10, 13, 2, 5, 9, 7,
	107	};
	108
	109	static unsigned const sus_pins[BYT_NGPIO_SUS] = {
	110	29, 33, 30, 31, 32, 34, 36, 35, 38, 37,
	111	18, 7, 11, 20, 17, 1, 8, 10, 19, 12,
	112	0, 2, 23, 39, 28, 27, 22, 21, 24, 25,
	113	26, 51, 56, 54, 49, 55, 48, 57, 50, 58,
	114	52, 53, 59, 40,
	115	};
	116
	117	static struct pinctrl_gpio_range byt_ranges[] = {
	118	{
42bd0070	119	.name = BYT_SCORE_ACPI_UID, /* match with acpi _UID in probe */
a5d811bb MN	120	.npins = BYT_NGPIO_SCORE,
	121	.pins = score_pins,
	122	},
	123	{
42bd0070	124	.name = BYT_NCORE_ACPI_UID,
a5d811bb MN	125	.npins = BYT_NGPIO_NCORE,
	126	.pins = ncore_pins,
	127	},
	128	{
42bd0070	129	.name = BYT_SUS_ACPI_UID,
a5d811bb MN	130	.npins = BYT_NGPIO_SUS,
	131	.pins = sus_pins,
	132	},
	133	{
	134	},
	135	};
	136
	137	struct byt_gpio {
	138	struct gpio_chip chip;
a5d811bb MN	139	struct platform_device *pdev;
	140	spinlock_t lock;
	141	void __iomem *reg_base;
	142	struct pinctrl_gpio_range *range;
	143	};
	144
17e52464 AS	145	#define to_byt_gpio(c) container_of(c, struct byt_gpio, chip)
17e52464 AS	146
a5d811bb MN	147	static void __iomem byt_gpio_reg(struct gpio_chip chip, unsigned offset,
	148	int reg)
	149	{
17e52464	150	struct byt_gpio *vg = to_byt_gpio(chip);
a5d811bb	151	u32 reg_offset;
a5d811bb MN	152
	153	if (reg == BYT_INT_STAT_REG)
	154	reg_offset = (offset / 32) * 4;
	155	else
	156	reg_offset = vg->range->pins[offset] * 16;
	157
9c5b6557	158	return vg->reg_base + reg_offset + reg;
a5d811bb MN	159	}
a5d811bb MN	160
42bd0070 CKH	161	static bool is_special_pin(struct byt_gpio *vg, unsigned offset)
	162	{
	163	/* SCORE pin 92-93 */
	164	if (!strcmp(vg->range->name, BYT_SCORE_ACPI_UID) &&
	165	offset >= 92 && offset <= 93)
	166	return true;
	167
	168	/* SUS pin 11-21 */
	169	if (!strcmp(vg->range->name, BYT_SUS_ACPI_UID) &&
	170	offset >= 11 && offset <= 21)
	171	return true;
	172
	173	return false;
	174	}
	175
a5d811bb MN	176	static int byt_gpio_request(struct gpio_chip *chip, unsigned offset)
a5d811bb MN	177	{
17e52464	178	struct byt_gpio *vg = to_byt_gpio(chip);
42bd0070 CKH	179	void __iomem *reg = byt_gpio_reg(chip, offset, BYT_CONF0_REG);
	180	u32 value;
	181	bool special;
	182
	183	/*
	184	* In most cases, func pin mux 000 means GPIO function.
	185	* But, some pins may have func pin mux 001 represents
	186	* GPIO function. Only allow user to export pin with
	187	* func pin mux preset as GPIO function by BIOS/FW.
	188	*/
	189	value = readl(reg) & BYT_PIN_MUX;
	190	special = is_special_pin(vg, offset);
	191	if ((special && value != 1) \|\| (!special && value)) {
	192	dev_err(&vg->pdev->dev,
	193	"pin %u cannot be used as GPIO.\n", offset);
	194	return -EINVAL;
	195	}
a5d811bb MN	196
	197	pm_runtime_get(&vg->pdev->dev);
	198
	199	return 0;
	200	}
	201
	202	static void byt_gpio_free(struct gpio_chip *chip, unsigned offset)
	203	{
17e52464	204	struct byt_gpio *vg = to_byt_gpio(chip);
a5d811bb MN	205	void __iomem *reg = byt_gpio_reg(&vg->chip, offset, BYT_CONF0_REG);
	206	u32 value;
	207
	208	/* clear interrupt triggering */
	209	value = readl(reg);
	210	value &= ~(BYT_TRIG_POS \| BYT_TRIG_NEG \| BYT_TRIG_LVL);
	211	writel(value, reg);
	212
	213	pm_runtime_put(&vg->pdev->dev);
	214	}
	215
	216	static int byt_irq_type(struct irq_data *d, unsigned type)
	217	{
e1ee5c57	218	struct byt_gpio *vg = to_byt_gpio(irq_data_get_irq_chip_data(d));
a5d811bb MN	219	u32 offset = irqd_to_hwirq(d);
	220	u32 value;
	221	unsigned long flags;
	222	void __iomem *reg = byt_gpio_reg(&vg->chip, offset, BYT_CONF0_REG);
	223
	224	if (offset >= vg->chip.ngpio)
	225	return -EINVAL;
	226
	227	spin_lock_irqsave(&vg->lock, flags);
	228	value = readl(reg);
	229
3a71c05e LP	230	WARN(value & BYT_DIRECT_IRQ_EN,
	231	"Bad pad config for io mode, force direct_irq_en bit clearing");
	232
a5d811bb MN	233	/* For level trigges the BYT_TRIG_POS and BYT_TRIG_NEG bits
	234	* are used to indicate high and low level triggering
	235	*/
3a71c05e LP	236	value &= ~(BYT_DIRECT_IRQ_EN \| BYT_TRIG_POS \| BYT_TRIG_NEG \|
3a71c05e LP	237	BYT_TRIG_LVL);
a5d811bb MN	238
	239	switch (type) {
	240	case IRQ_TYPE_LEVEL_HIGH:
	241	value \|= BYT_TRIG_LVL;
	242	case IRQ_TYPE_EDGE_RISING:
	243	value \|= BYT_TRIG_POS;
	244	break;
	245	case IRQ_TYPE_LEVEL_LOW:
	246	value \|= BYT_TRIG_LVL;
	247	case IRQ_TYPE_EDGE_FALLING:
	248	value \|= BYT_TRIG_NEG;
	249	break;
	250	case IRQ_TYPE_EDGE_BOTH:
	251	value \|= (BYT_TRIG_NEG \| BYT_TRIG_POS);
	252	break;
	253	}
	254	writel(value, reg);
	255
	256	spin_unlock_irqrestore(&vg->lock, flags);
	257
	258	return 0;
	259	}
	260
	261	static int byt_gpio_get(struct gpio_chip *chip, unsigned offset)
	262	{
	263	void __iomem *reg = byt_gpio_reg(chip, offset, BYT_VAL_REG);
	264	return readl(reg) & BYT_LEVEL;
	265	}
	266
	267	static void byt_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
	268	{
17e52464	269	struct byt_gpio *vg = to_byt_gpio(chip);
a5d811bb MN	270	void __iomem *reg = byt_gpio_reg(chip, offset, BYT_VAL_REG);
	271	unsigned long flags;
	272	u32 old_val;
	273
	274	spin_lock_irqsave(&vg->lock, flags);
	275
	276	old_val = readl(reg);
	277
	278	if (value)
	279	writel(old_val \| BYT_LEVEL, reg);
	280	else
	281	writel(old_val & ~BYT_LEVEL, reg);
	282
	283	spin_unlock_irqrestore(&vg->lock, flags);
	284	}
	285
	286	static int byt_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
	287	{
17e52464	288	struct byt_gpio *vg = to_byt_gpio(chip);
a5d811bb MN	289	void __iomem *reg = byt_gpio_reg(chip, offset, BYT_VAL_REG);
	290	unsigned long flags;
	291	u32 value;
	292
	293	spin_lock_irqsave(&vg->lock, flags);
	294
	295	value = readl(reg) \| BYT_DIR_MASK;
496940c1	296	value &= ~BYT_INPUT_EN; /* active low */
a5d811bb MN	297	writel(value, reg);
	298
	299	spin_unlock_irqrestore(&vg->lock, flags);
	300
	301	return 0;
	302	}
	303
	304	static int byt_gpio_direction_output(struct gpio_chip *chip,
	305	unsigned gpio, int value)
	306	{
17e52464	307	struct byt_gpio *vg = to_byt_gpio(chip);
ff998356	308	void __iomem *conf_reg = byt_gpio_reg(chip, gpio, BYT_CONF0_REG);
a5d811bb MN	309	void __iomem *reg = byt_gpio_reg(chip, gpio, BYT_VAL_REG);
	310	unsigned long flags;
	311	u32 reg_val;
	312
	313	spin_lock_irqsave(&vg->lock, flags);
	314
ff998356 EE	315	/*
	316	* Before making any direction modifications, do a check if gpio
	317	* is set for direct IRQ. On baytrail, setting GPIO to output does
	318	* not make sense, so let's at least warn the caller before they shoot
	319	* themselves in the foot.
	320	*/
	321	WARN(readl(conf_reg) & BYT_DIRECT_IRQ_EN,
	322	"Potential Error: Setting GPIO with direct_irq_en to output");
	323
496940c1	324	reg_val = readl(reg) \| BYT_DIR_MASK;
d90c3381	325	reg_val &= ~(BYT_OUTPUT_EN \| BYT_INPUT_EN);
496940c1 AS	326
	327	if (value)
	328	writel(reg_val \| BYT_LEVEL, reg);
	329	else
	330	writel(reg_val & ~BYT_LEVEL, reg);
a5d811bb MN	331
	332	spin_unlock_irqrestore(&vg->lock, flags);
	333
	334	return 0;
	335	}
	336
	337	static void byt_gpio_dbg_show(struct seq_file s, struct gpio_chip chip)
	338	{
17e52464	339	struct byt_gpio *vg = to_byt_gpio(chip);
a5d811bb MN	340	int i;
	341	unsigned long flags;
	342	u32 conf0, val, offs;
	343
	344	spin_lock_irqsave(&vg->lock, flags);
	345
	346	for (i = 0; i < vg->chip.ngpio; i++) {
3ff95885 MW	347	const char *pull_str = NULL;
3ff95885 MW	348	const char *pull = NULL;
a4d8d6da	349	const char *label;
a5d811bb MN	350	offs = vg->range->pins[i] * 16;
	351	conf0 = readl(vg->reg_base + offs + BYT_CONF0_REG);
	352	val = readl(vg->reg_base + offs + BYT_VAL_REG);
	353
a4d8d6da MN	354	label = gpiochip_is_requested(chip, i);
	355	if (!label)
	356	label = "Unrequested";
	357
3ff95885 MW	358	switch (conf0 & BYT_PULL_ASSIGN_MASK) {
	359	case BYT_PULL_ASSIGN_UP:
	360	pull = "up";
	361	break;
	362	case BYT_PULL_ASSIGN_DOWN:
	363	pull = "down";
	364	break;
	365	}
	366
	367	switch (conf0 & BYT_PULL_STR_MASK) {
	368	case BYT_PULL_STR_2K:
	369	pull_str = "2k";
	370	break;
	371	case BYT_PULL_STR_10K:
	372	pull_str = "10k";
	373	break;
	374	case BYT_PULL_STR_20K:
	375	pull_str = "20k";
	376	break;
	377	case BYT_PULL_STR_40K:
	378	pull_str = "40k";
	379	break;
	380	}
	381
a5d811bb	382	seq_printf(s,
3ff95885	383	" gpio-%-3d (%-20.20s) %s %s %s pad-%-3d offset:0x%03x mux:%d %s%s%s",
a5d811bb	384	i,
a4d8d6da	385	label,
a5d811bb MN	386	val & BYT_INPUT_EN ? " " : "in",
	387	val & BYT_OUTPUT_EN ? " " : "out",
	388	val & BYT_LEVEL ? "hi" : "lo",
	389	vg->range->pins[i], offs,
	390	conf0 & 0x7,
3ff95885 MW	391	conf0 & BYT_TRIG_NEG ? " fall" : " ",
	392	conf0 & BYT_TRIG_POS ? " rise" : " ",
	393	conf0 & BYT_TRIG_LVL ? " level" : " ");
	394
	395	if (pull && pull_str)
	396	seq_printf(s, " %-4s %-3s", pull, pull_str);
	397	else
	398	seq_puts(s, " ");
	399
	400	if (conf0 & BYT_IODEN)
	401	seq_puts(s, " open-drain");
	402
	403	seq_puts(s, "\n");
a5d811bb MN	404	}
	405	spin_unlock_irqrestore(&vg->lock, flags);
	406	}
	407
a5d811bb MN	408	static void byt_gpio_irq_handler(unsigned irq, struct irq_desc *desc)
	409	{
	410	struct irq_data *data = irq_desc_get_irq_data(desc);
e1ee5c57	411	struct byt_gpio *vg = to_byt_gpio(irq_desc_get_handler_data(desc));
a5d811bb MN	412	struct irq_chip *chip = irq_data_get_irq_chip(data);
	413	u32 base, pin, mask;
	414	void __iomem *reg;
	415	u32 pending;
	416	unsigned virq;
	417	int looplimit = 0;
	418
	419	/* check from GPIO controller which pin triggered the interrupt */
	420	for (base = 0; base < vg->chip.ngpio; base += 32) {
	421
	422	reg = byt_gpio_reg(&vg->chip, base, BYT_INT_STAT_REG);
	423
	424	while ((pending = readl(reg))) {
	425	pin = __ffs(pending);
	426	mask = BIT(pin);
	427	/* Clear before handling so we can't lose an edge */
	428	writel(mask, reg);
	429
e1ee5c57	430	virq = irq_find_mapping(vg->chip.irqdomain, base + pin);
a5d811bb MN	431	generic_handle_irq(virq);
	432
	433	/* In case bios or user sets triggering incorretly a pin
	434	* might remain in "interrupt triggered" state.
	435	*/
	436	if (looplimit++ > 32) {
	437	dev_err(&vg->pdev->dev,
	438	"Gpio %d interrupt flood, disabling\n",
	439	base + pin);
	440
	441	reg = byt_gpio_reg(&vg->chip, base + pin,
	442	BYT_CONF0_REG);
	443	mask = readl(reg);
	444	mask &= ~(BYT_TRIG_NEG \| BYT_TRIG_POS \|
	445	BYT_TRIG_LVL);
	446	writel(mask, reg);
	447	mask = readl(reg); /* flush */
	448	break;
	449	}
	450	}
	451	}
	452	chip->irq_eoi(data);
	453	}
	454
	455	static void byt_irq_unmask(struct irq_data *d)
	456	{
	457	}
	458
	459	static void byt_irq_mask(struct irq_data *d)
	460	{
	461	}
	462
	463	static struct irq_chip byt_irqchip = {
	464	.name = "BYT-GPIO",
	465	.irq_mask = byt_irq_mask,
	466	.irq_unmask = byt_irq_unmask,
	467	.irq_set_type = byt_irq_type,
41939e69	468	.flags = IRQCHIP_SKIP_SET_WAKE,
a5d811bb MN	469	};
	470
	471	static void byt_gpio_irq_init_hw(struct byt_gpio *vg)
	472	{
	473	void __iomem *reg;
	474	u32 base, value;
	475
	476	/* clear interrupt status trigger registers */
	477	for (base = 0; base < vg->chip.ngpio; base += 32) {
	478	reg = byt_gpio_reg(&vg->chip, base, BYT_INT_STAT_REG);
	479	writel(0xffffffff, reg);
	480	/* make sure trigger bits are cleared, if not then a pin
	481	might be misconfigured in bios */
	482	value = readl(reg);
	483	if (value)
	484	dev_err(&vg->pdev->dev,
	485	"GPIO interrupt error, pins misconfigured\n");
	486	}
	487	}
	488
a5d811bb MN	489	static int byt_gpio_probe(struct platform_device *pdev)
	490	{
	491	struct byt_gpio *vg;
	492	struct gpio_chip *gc;
	493	struct resource mem_rc, irq_rc;
	494	struct device *dev = &pdev->dev;
	495	struct acpi_device *acpi_dev;
	496	struct pinctrl_gpio_range *range;
	497	acpi_handle handle = ACPI_HANDLE(dev);
a5d811bb MN	498	int ret;
	499
	500	if (acpi_bus_get_device(handle, &acpi_dev))
	501	return -ENODEV;
	502
	503	vg = devm_kzalloc(dev, sizeof(struct byt_gpio), GFP_KERNEL);
	504	if (!vg) {
	505	dev_err(&pdev->dev, "can't allocate byt_gpio chip data\n");
	506	return -ENOMEM;
	507	}
	508
	509	for (range = byt_ranges; range->name; range++) {
	510	if (!strcmp(acpi_dev->pnp.unique_id, range->name)) {
	511	vg->chip.ngpio = range->npins;
	512	vg->range = range;
	513	break;
	514	}
	515	}
	516
	517	if (!vg->chip.ngpio \|\| !vg->range)
	518	return -ENODEV;
	519
	520	vg->pdev = pdev;
	521	platform_set_drvdata(pdev, vg);
	522
	523	mem_rc = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	524	vg->reg_base = devm_ioremap_resource(dev, mem_rc);
	525	if (IS_ERR(vg->reg_base))
	526	return PTR_ERR(vg->reg_base);
	527
	528	spin_lock_init(&vg->lock);
	529
	530	gc = &vg->chip;
	531	gc->label = dev_name(&pdev->dev);
	532	gc->owner = THIS_MODULE;
	533	gc->request = byt_gpio_request;
	534	gc->free = byt_gpio_free;
	535	gc->direction_input = byt_gpio_direction_input;
	536	gc->direction_output = byt_gpio_direction_output;
	537	gc->get = byt_gpio_get;
	538	gc->set = byt_gpio_set;
	539	gc->dbg_show = byt_gpio_dbg_show;
	540	gc->base = -1;
9fb1f39e	541	gc->can_sleep = false;
a5d811bb MN	542	gc->dev = dev;
a5d811bb MN	543
e1ee5c57 MW	544	ret = gpiochip_add(gc);
	545	if (ret) {
	546	dev_err(&pdev->dev, "failed adding byt-gpio chip\n");
	547	return ret;
	548	}
	549
a5d811bb MN	550	/* set up interrupts */
	551	irq_rc = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
	552	if (irq_rc && irq_rc->start) {
a5d811bb	553	byt_gpio_irq_init_hw(vg);
e1ee5c57 MW	554	ret = gpiochip_irqchip_add(gc, &byt_irqchip, 0,
	555	handle_simple_irq, IRQ_TYPE_NONE);
	556	if (ret) {
	557	dev_err(dev, "failed to add irqchip\n");
	558	gpiochip_remove(gc);
	559	return ret;
	560	}
a5d811bb	561
e1ee5c57 MW	562	gpiochip_set_chained_irqchip(gc, &byt_irqchip,
	563	(unsigned)irq_rc->start,
	564	byt_gpio_irq_handler);
605a7bca JY	565	}
605a7bca JY	566
a5d811bb MN	567	pm_runtime_enable(dev);
	568
	569	return 0;
	570	}
	571
	572	static int byt_gpio_runtime_suspend(struct device *dev)
	573	{
	574	return 0;
	575	}
	576
	577	static int byt_gpio_runtime_resume(struct device *dev)
	578	{
	579	return 0;
	580	}
	581
	582	static const struct dev_pm_ops byt_gpio_pm_ops = {
	583	.runtime_suspend = byt_gpio_runtime_suspend,
	584	.runtime_resume = byt_gpio_runtime_resume,
	585	};
	586
	587	static const struct acpi_device_id byt_gpio_acpi_match[] = {
	588	{ "INT33B2", 0 },
20482d32	589	{ "INT33FC", 0 },
a5d811bb MN	590	{ }
	591	};
	592	MODULE_DEVICE_TABLE(acpi, byt_gpio_acpi_match);
	593
	594	static int byt_gpio_remove(struct platform_device *pdev)
	595	{
	596	struct byt_gpio *vg = platform_get_drvdata(pdev);
ec243320	597
a5d811bb	598	pm_runtime_disable(&pdev->dev);
b4e7c55d	599	gpiochip_remove(&vg->chip);
a5d811bb MN	600
	601	return 0;
	602	}
	603
	604	static struct platform_driver byt_gpio_driver = {
	605	.probe = byt_gpio_probe,
	606	.remove = byt_gpio_remove,
	607	.driver = {
	608	.name = "byt_gpio",
	609	.owner = THIS_MODULE,
	610	.pm = &byt_gpio_pm_ops,
	611	.acpi_match_table = ACPI_PTR(byt_gpio_acpi_match),
	612	},
	613	};
	614
	615	static int __init byt_gpio_init(void)
	616	{
	617	return platform_driver_register(&byt_gpio_driver);
	618	}
	619
	620	subsys_initcall(byt_gpio_init);