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Commit | Line | Data |
---|---|---|
bd41b99d | 1 | /* |
c103de24 | 2 | * U300 GPIO module. |
bd41b99d | 3 | * |
04b13de6 | 4 | * Copyright (C) 2007-2012 ST-Ericsson AB |
bd41b99d | 5 | * License terms: GNU General Public License (GPL) version 2 |
bd41b99d | 6 | * COH 901 571/3 - Used in DB3210 (U365 2.0) and DB3350 (U335 1.0) |
cc890cd7 | 7 | * Author: Linus Walleij <linus.walleij@linaro.org> |
bd41b99d | 8 | * Author: Jonas Aaberg <jonas.aberg@stericsson.com> |
bd41b99d LW |
9 | */ |
10 | #include <linux/module.h> | |
cc890cd7 | 11 | #include <linux/irq.h> |
bd41b99d LW |
12 | #include <linux/interrupt.h> |
13 | #include <linux/delay.h> | |
14 | #include <linux/errno.h> | |
15 | #include <linux/io.h> | |
a6c45b99 | 16 | #include <linux/irqdomain.h> |
bd41b99d LW |
17 | #include <linux/clk.h> |
18 | #include <linux/err.h> | |
19 | #include <linux/platform_device.h> | |
20 | #include <linux/gpio.h> | |
cc890cd7 LW |
21 | #include <linux/list.h> |
22 | #include <linux/slab.h> | |
28a8d14c | 23 | #include <linux/pinctrl/consumer.h> |
dc0b1aa3 | 24 | #include <linux/pinctrl/pinconf-generic.h> |
65172850 | 25 | #include <linux/platform_data/pinctrl-coh901.h> |
dc0b1aa3 | 26 | #include "pinctrl-coh901.h" |
bd41b99d | 27 | |
04b13de6 | 28 | #define U300_GPIO_PORT_STRIDE (0x30) |
cc890cd7 | 29 | /* |
04b13de6 LW |
30 | * Control Register 32bit (R/W) |
31 | * bit 15-9 (mask 0x0000FE00) contains the number of cores. 8*cores | |
32 | * gives the number of GPIO pins. | |
33 | * bit 8-2 (mask 0x000001FC) contains the core version ID. | |
cc890cd7 | 34 | */ |
04b13de6 LW |
35 | #define U300_GPIO_CR (0x00) |
36 | #define U300_GPIO_CR_SYNC_SEL_ENABLE (0x00000002UL) | |
37 | #define U300_GPIO_CR_BLOCK_CLKRQ_ENABLE (0x00000001UL) | |
38 | #define U300_GPIO_PXPDIR (0x04) | |
39 | #define U300_GPIO_PXPDOR (0x08) | |
40 | #define U300_GPIO_PXPCR (0x0C) | |
cc890cd7 LW |
41 | #define U300_GPIO_PXPCR_ALL_PINS_MODE_MASK (0x0000FFFFUL) |
42 | #define U300_GPIO_PXPCR_PIN_MODE_MASK (0x00000003UL) | |
43 | #define U300_GPIO_PXPCR_PIN_MODE_SHIFT (0x00000002UL) | |
44 | #define U300_GPIO_PXPCR_PIN_MODE_INPUT (0x00000000UL) | |
45 | #define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL (0x00000001UL) | |
46 | #define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN (0x00000002UL) | |
47 | #define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE (0x00000003UL) | |
04b13de6 LW |
48 | #define U300_GPIO_PXPER (0x10) |
49 | #define U300_GPIO_PXPER_ALL_PULL_UP_DISABLE_MASK (0x000000FFUL) | |
50 | #define U300_GPIO_PXPER_PULL_UP_DISABLE (0x00000001UL) | |
51 | #define U300_GPIO_PXIEV (0x14) | |
52 | #define U300_GPIO_PXIEN (0x18) | |
53 | #define U300_GPIO_PXIFR (0x1C) | |
54 | #define U300_GPIO_PXICR (0x20) | |
cc890cd7 LW |
55 | #define U300_GPIO_PXICR_ALL_IRQ_CONFIG_MASK (0x000000FFUL) |
56 | #define U300_GPIO_PXICR_IRQ_CONFIG_MASK (0x00000001UL) | |
57 | #define U300_GPIO_PXICR_IRQ_CONFIG_FALLING_EDGE (0x00000000UL) | |
58 | #define U300_GPIO_PXICR_IRQ_CONFIG_RISING_EDGE (0x00000001UL) | |
cc890cd7 LW |
59 | |
60 | /* 8 bits per port, no version has more than 7 ports */ | |
61 | #define U300_GPIO_PINS_PER_PORT 8 | |
62 | #define U300_GPIO_MAX (U300_GPIO_PINS_PER_PORT * 7) | |
63 | ||
64 | struct u300_gpio { | |
65 | struct gpio_chip chip; | |
66 | struct list_head port_list; | |
67 | struct clk *clk; | |
cc890cd7 LW |
68 | void __iomem *base; |
69 | struct device *dev; | |
cc890cd7 LW |
70 | u32 stride; |
71 | /* Register offsets */ | |
72 | u32 pcr; | |
73 | u32 dor; | |
74 | u32 dir; | |
75 | u32 per; | |
76 | u32 icr; | |
77 | u32 ien; | |
78 | u32 iev; | |
79 | }; | |
bd41b99d LW |
80 | |
81 | struct u300_gpio_port { | |
cc890cd7 LW |
82 | struct list_head node; |
83 | struct u300_gpio *gpio; | |
84 | char name[8]; | |
a6c45b99 | 85 | struct irq_domain *domain; |
bd41b99d LW |
86 | int irq; |
87 | int number; | |
cc890cd7 | 88 | u8 toggle_edge_mode; |
bd41b99d LW |
89 | }; |
90 | ||
cc890cd7 LW |
91 | /* |
92 | * Macro to expand to read a specific register found in the "gpio" | |
93 | * struct. It requires the struct u300_gpio *gpio variable to exist in | |
94 | * its context. It calculates the port offset from the given pin | |
95 | * offset, muliplies by the port stride and adds the register offset | |
96 | * so it provides a pointer to the desired register. | |
97 | */ | |
98 | #define U300_PIN_REG(pin, reg) \ | |
99 | (gpio->base + (pin >> 3) * gpio->stride + gpio->reg) | |
bd41b99d | 100 | |
cc890cd7 LW |
101 | /* |
102 | * Provides a bitmask for a specific gpio pin inside an 8-bit GPIO | |
103 | * register. | |
104 | */ | |
105 | #define U300_PIN_BIT(pin) \ | |
106 | (1 << (pin & 0x07)) | |
bd41b99d | 107 | |
cc890cd7 LW |
108 | struct u300_gpio_confdata { |
109 | u16 bias_mode; | |
110 | bool output; | |
111 | int outval; | |
bd41b99d LW |
112 | }; |
113 | ||
cc890cd7 LW |
114 | /* BS335 has seven ports of 8 bits each = GPIO pins 0..55 */ |
115 | #define BS335_GPIO_NUM_PORTS 7 | |
bd41b99d | 116 | |
cc890cd7 | 117 | #define U300_FLOATING_INPUT { \ |
a050b3ee | 118 | .bias_mode = PIN_CONFIG_BIAS_HIGH_IMPEDANCE, \ |
cc890cd7 LW |
119 | .output = false, \ |
120 | } | |
bd41b99d | 121 | |
cc890cd7 | 122 | #define U300_PULL_UP_INPUT { \ |
a050b3ee | 123 | .bias_mode = PIN_CONFIG_BIAS_PULL_UP, \ |
cc890cd7 LW |
124 | .output = false, \ |
125 | } | |
bd41b99d | 126 | |
cc890cd7 LW |
127 | #define U300_OUTPUT_LOW { \ |
128 | .output = true, \ | |
129 | .outval = 0, \ | |
130 | } | |
bd41b99d | 131 | |
cc890cd7 LW |
132 | #define U300_OUTPUT_HIGH { \ |
133 | .output = true, \ | |
134 | .outval = 1, \ | |
135 | } | |
bd41b99d | 136 | |
bd41b99d | 137 | /* Initial configuration */ |
122dbe7e | 138 | static const struct __initconst u300_gpio_confdata |
cc890cd7 | 139 | bs335_gpio_config[BS335_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = { |
bd41b99d LW |
140 | /* Port 0, pins 0-7 */ |
141 | { | |
cc890cd7 LW |
142 | U300_FLOATING_INPUT, |
143 | U300_OUTPUT_HIGH, | |
144 | U300_FLOATING_INPUT, | |
145 | U300_OUTPUT_LOW, | |
146 | U300_OUTPUT_LOW, | |
147 | U300_OUTPUT_LOW, | |
148 | U300_OUTPUT_LOW, | |
149 | U300_OUTPUT_LOW, | |
bd41b99d LW |
150 | }, |
151 | /* Port 1, pins 0-7 */ | |
152 | { | |
cc890cd7 LW |
153 | U300_OUTPUT_LOW, |
154 | U300_OUTPUT_LOW, | |
155 | U300_OUTPUT_LOW, | |
156 | U300_PULL_UP_INPUT, | |
157 | U300_FLOATING_INPUT, | |
158 | U300_OUTPUT_HIGH, | |
159 | U300_OUTPUT_LOW, | |
160 | U300_OUTPUT_LOW, | |
bd41b99d LW |
161 | }, |
162 | /* Port 2, pins 0-7 */ | |
163 | { | |
cc890cd7 LW |
164 | U300_FLOATING_INPUT, |
165 | U300_FLOATING_INPUT, | |
166 | U300_FLOATING_INPUT, | |
167 | U300_FLOATING_INPUT, | |
168 | U300_OUTPUT_LOW, | |
169 | U300_PULL_UP_INPUT, | |
170 | U300_OUTPUT_LOW, | |
171 | U300_PULL_UP_INPUT, | |
bd41b99d LW |
172 | }, |
173 | /* Port 3, pins 0-7 */ | |
174 | { | |
cc890cd7 LW |
175 | U300_PULL_UP_INPUT, |
176 | U300_OUTPUT_LOW, | |
177 | U300_FLOATING_INPUT, | |
178 | U300_FLOATING_INPUT, | |
179 | U300_FLOATING_INPUT, | |
180 | U300_FLOATING_INPUT, | |
181 | U300_FLOATING_INPUT, | |
182 | U300_FLOATING_INPUT, | |
bd41b99d LW |
183 | }, |
184 | /* Port 4, pins 0-7 */ | |
185 | { | |
cc890cd7 LW |
186 | U300_FLOATING_INPUT, |
187 | U300_FLOATING_INPUT, | |
188 | U300_FLOATING_INPUT, | |
189 | U300_FLOATING_INPUT, | |
190 | U300_FLOATING_INPUT, | |
191 | U300_FLOATING_INPUT, | |
192 | U300_FLOATING_INPUT, | |
193 | U300_FLOATING_INPUT, | |
bd41b99d LW |
194 | }, |
195 | /* Port 5, pins 0-7 */ | |
196 | { | |
cc890cd7 LW |
197 | U300_FLOATING_INPUT, |
198 | U300_FLOATING_INPUT, | |
199 | U300_FLOATING_INPUT, | |
200 | U300_FLOATING_INPUT, | |
201 | U300_FLOATING_INPUT, | |
202 | U300_FLOATING_INPUT, | |
203 | U300_FLOATING_INPUT, | |
204 | U300_FLOATING_INPUT, | |
bd41b99d LW |
205 | }, |
206 | /* Port 6, pind 0-7 */ | |
207 | { | |
cc890cd7 LW |
208 | U300_FLOATING_INPUT, |
209 | U300_FLOATING_INPUT, | |
210 | U300_FLOATING_INPUT, | |
211 | U300_FLOATING_INPUT, | |
212 | U300_FLOATING_INPUT, | |
213 | U300_FLOATING_INPUT, | |
214 | U300_FLOATING_INPUT, | |
215 | U300_FLOATING_INPUT, | |
bd41b99d | 216 | } |
cc890cd7 | 217 | }; |
bd41b99d | 218 | |
cc890cd7 LW |
219 | /** |
220 | * to_u300_gpio() - get the pointer to u300_gpio | |
221 | * @chip: the gpio chip member of the structure u300_gpio | |
bd41b99d | 222 | */ |
cc890cd7 | 223 | static inline struct u300_gpio *to_u300_gpio(struct gpio_chip *chip) |
bd41b99d | 224 | { |
cc890cd7 | 225 | return container_of(chip, struct u300_gpio, chip); |
bd41b99d | 226 | } |
bd41b99d | 227 | |
b4e3ac74 LW |
228 | static int u300_gpio_request(struct gpio_chip *chip, unsigned offset) |
229 | { | |
230 | /* | |
231 | * Map back to global GPIO space and request muxing, the direction | |
232 | * parameter does not matter for this controller. | |
233 | */ | |
234 | int gpio = chip->base + offset; | |
235 | ||
e93bcee0 | 236 | return pinctrl_request_gpio(gpio); |
b4e3ac74 LW |
237 | } |
238 | ||
239 | static void u300_gpio_free(struct gpio_chip *chip, unsigned offset) | |
240 | { | |
241 | int gpio = chip->base + offset; | |
242 | ||
e93bcee0 | 243 | pinctrl_free_gpio(gpio); |
b4e3ac74 LW |
244 | } |
245 | ||
cc890cd7 | 246 | static int u300_gpio_get(struct gpio_chip *chip, unsigned offset) |
bd41b99d | 247 | { |
cc890cd7 | 248 | struct u300_gpio *gpio = to_u300_gpio(chip); |
bd41b99d | 249 | |
cc890cd7 | 250 | return readl(U300_PIN_REG(offset, dir)) & U300_PIN_BIT(offset); |
bd41b99d | 251 | } |
bd41b99d | 252 | |
cc890cd7 | 253 | static void u300_gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
ee17962e | 254 | { |
cc890cd7 LW |
255 | struct u300_gpio *gpio = to_u300_gpio(chip); |
256 | unsigned long flags; | |
257 | u32 val; | |
ee17962e | 258 | |
cc890cd7 | 259 | local_irq_save(flags); |
bd41b99d | 260 | |
cc890cd7 LW |
261 | val = readl(U300_PIN_REG(offset, dor)); |
262 | if (value) | |
263 | writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, dor)); | |
264 | else | |
265 | writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, dor)); | |
bd41b99d | 266 | |
cc890cd7 | 267 | local_irq_restore(flags); |
bd41b99d | 268 | } |
bd41b99d | 269 | |
cc890cd7 | 270 | static int u300_gpio_direction_input(struct gpio_chip *chip, unsigned offset) |
bd41b99d | 271 | { |
cc890cd7 LW |
272 | struct u300_gpio *gpio = to_u300_gpio(chip); |
273 | unsigned long flags; | |
274 | u32 val; | |
bd41b99d | 275 | |
cc890cd7 LW |
276 | local_irq_save(flags); |
277 | val = readl(U300_PIN_REG(offset, pcr)); | |
278 | /* Mask out this pin, note 2 bits per setting */ | |
279 | val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK << ((offset & 0x07) << 1)); | |
280 | writel(val, U300_PIN_REG(offset, pcr)); | |
281 | local_irq_restore(flags); | |
282 | return 0; | |
bd41b99d | 283 | } |
bd41b99d | 284 | |
cc890cd7 LW |
285 | static int u300_gpio_direction_output(struct gpio_chip *chip, unsigned offset, |
286 | int value) | |
bd41b99d | 287 | { |
cc890cd7 | 288 | struct u300_gpio *gpio = to_u300_gpio(chip); |
bd41b99d | 289 | unsigned long flags; |
cc890cd7 LW |
290 | u32 oldmode; |
291 | u32 val; | |
bd41b99d LW |
292 | |
293 | local_irq_save(flags); | |
cc890cd7 LW |
294 | val = readl(U300_PIN_REG(offset, pcr)); |
295 | /* | |
296 | * Drive mode must be set by the special mode set function, set | |
297 | * push/pull mode by default if no mode has been selected. | |
298 | */ | |
299 | oldmode = val & (U300_GPIO_PXPCR_PIN_MODE_MASK << | |
300 | ((offset & 0x07) << 1)); | |
301 | /* mode = 0 means input, else some mode is already set */ | |
302 | if (oldmode == 0) { | |
303 | val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK << | |
304 | ((offset & 0x07) << 1)); | |
305 | val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL | |
306 | << ((offset & 0x07) << 1)); | |
307 | writel(val, U300_PIN_REG(offset, pcr)); | |
bd41b99d | 308 | } |
cc890cd7 | 309 | u300_gpio_set(chip, offset, value); |
bd41b99d | 310 | local_irq_restore(flags); |
cc890cd7 | 311 | return 0; |
bd41b99d | 312 | } |
bd41b99d | 313 | |
cc890cd7 | 314 | static int u300_gpio_to_irq(struct gpio_chip *chip, unsigned offset) |
bd41b99d | 315 | { |
cc890cd7 | 316 | struct u300_gpio *gpio = to_u300_gpio(chip); |
a6c45b99 LW |
317 | int portno = offset >> 3; |
318 | struct u300_gpio_port *port = NULL; | |
319 | struct list_head *p; | |
320 | int retirq; | |
28d0c14b | 321 | bool found = false; |
cc890cd7 | 322 | |
a6c45b99 LW |
323 | list_for_each(p, &gpio->port_list) { |
324 | port = list_entry(p, struct u300_gpio_port, node); | |
28d0c14b AL |
325 | if (port->number == portno) { |
326 | found = true; | |
a6c45b99 | 327 | break; |
28d0c14b | 328 | } |
a6c45b99 | 329 | } |
28d0c14b | 330 | if (!found) { |
a6c45b99 LW |
331 | dev_err(gpio->dev, "could not locate port for GPIO %d IRQ\n", |
332 | offset); | |
333 | return -EINVAL; | |
334 | } | |
335 | ||
336 | /* | |
337 | * The local hwirqs on the port are the lower three bits, there | |
338 | * are exactly 8 IRQs per port since they are 8-bit | |
339 | */ | |
340 | retirq = irq_find_mapping(port->domain, (offset & 0x7)); | |
341 | ||
342 | dev_dbg(gpio->dev, "request IRQ for GPIO %d, return %d from port %d\n", | |
343 | offset, retirq, port->number); | |
cc890cd7 LW |
344 | return retirq; |
345 | } | |
346 | ||
dc0b1aa3 LW |
347 | /* Returning -EINVAL means "supported but not available" */ |
348 | int u300_gpio_config_get(struct gpio_chip *chip, | |
349 | unsigned offset, | |
350 | unsigned long *config) | |
351 | { | |
352 | struct u300_gpio *gpio = to_u300_gpio(chip); | |
353 | enum pin_config_param param = (enum pin_config_param) *config; | |
354 | bool biasmode; | |
355 | u32 drmode; | |
356 | ||
357 | /* One bit per pin, clamp to bool range */ | |
358 | biasmode = !!(readl(U300_PIN_REG(offset, per)) & U300_PIN_BIT(offset)); | |
359 | ||
360 | /* Mask out the two bits for this pin and shift to bits 0,1 */ | |
361 | drmode = readl(U300_PIN_REG(offset, pcr)); | |
362 | drmode &= (U300_GPIO_PXPCR_PIN_MODE_MASK << ((offset & 0x07) << 1)); | |
363 | drmode >>= ((offset & 0x07) << 1); | |
364 | ||
8b0ef258 | 365 | switch (param) { |
dc0b1aa3 LW |
366 | case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: |
367 | *config = 0; | |
368 | if (biasmode) | |
369 | return 0; | |
370 | else | |
371 | return -EINVAL; | |
372 | break; | |
373 | case PIN_CONFIG_BIAS_PULL_UP: | |
374 | *config = 0; | |
375 | if (!biasmode) | |
376 | return 0; | |
377 | else | |
378 | return -EINVAL; | |
379 | break; | |
380 | case PIN_CONFIG_DRIVE_PUSH_PULL: | |
381 | *config = 0; | |
382 | if (drmode == U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL) | |
383 | return 0; | |
384 | else | |
385 | return -EINVAL; | |
386 | break; | |
387 | case PIN_CONFIG_DRIVE_OPEN_DRAIN: | |
388 | *config = 0; | |
389 | if (drmode == U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN) | |
390 | return 0; | |
391 | else | |
392 | return -EINVAL; | |
393 | break; | |
394 | case PIN_CONFIG_DRIVE_OPEN_SOURCE: | |
395 | *config = 0; | |
396 | if (drmode == U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE) | |
397 | return 0; | |
398 | else | |
399 | return -EINVAL; | |
400 | break; | |
401 | default: | |
402 | break; | |
403 | } | |
404 | return -ENOTSUPP; | |
405 | } | |
406 | ||
407 | int u300_gpio_config_set(struct gpio_chip *chip, unsigned offset, | |
408 | enum pin_config_param param) | |
cc890cd7 LW |
409 | { |
410 | struct u300_gpio *gpio = to_u300_gpio(chip); | |
bd41b99d LW |
411 | unsigned long flags; |
412 | u32 val; | |
413 | ||
bd41b99d | 414 | local_irq_save(flags); |
cc890cd7 | 415 | switch (param) { |
a050b3ee LW |
416 | case PIN_CONFIG_BIAS_DISABLE: |
417 | case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: | |
cc890cd7 LW |
418 | val = readl(U300_PIN_REG(offset, per)); |
419 | writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, per)); | |
420 | break; | |
a050b3ee | 421 | case PIN_CONFIG_BIAS_PULL_UP: |
cc890cd7 LW |
422 | val = readl(U300_PIN_REG(offset, per)); |
423 | writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, per)); | |
424 | break; | |
a050b3ee | 425 | case PIN_CONFIG_DRIVE_PUSH_PULL: |
cc890cd7 LW |
426 | val = readl(U300_PIN_REG(offset, pcr)); |
427 | val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK | |
428 | << ((offset & 0x07) << 1)); | |
429 | val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL | |
430 | << ((offset & 0x07) << 1)); | |
431 | writel(val, U300_PIN_REG(offset, pcr)); | |
432 | break; | |
a050b3ee | 433 | case PIN_CONFIG_DRIVE_OPEN_DRAIN: |
cc890cd7 LW |
434 | val = readl(U300_PIN_REG(offset, pcr)); |
435 | val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK | |
436 | << ((offset & 0x07) << 1)); | |
437 | val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN | |
438 | << ((offset & 0x07) << 1)); | |
439 | writel(val, U300_PIN_REG(offset, pcr)); | |
440 | break; | |
a050b3ee | 441 | case PIN_CONFIG_DRIVE_OPEN_SOURCE: |
cc890cd7 LW |
442 | val = readl(U300_PIN_REG(offset, pcr)); |
443 | val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK | |
444 | << ((offset & 0x07) << 1)); | |
445 | val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE | |
446 | << ((offset & 0x07) << 1)); | |
447 | writel(val, U300_PIN_REG(offset, pcr)); | |
448 | break; | |
449 | default: | |
450 | local_irq_restore(flags); | |
451 | dev_err(gpio->dev, "illegal configuration requested\n"); | |
452 | return -EINVAL; | |
453 | } | |
bd41b99d LW |
454 | local_irq_restore(flags); |
455 | return 0; | |
456 | } | |
bd41b99d | 457 | |
cc890cd7 LW |
458 | static struct gpio_chip u300_gpio_chip = { |
459 | .label = "u300-gpio-chip", | |
460 | .owner = THIS_MODULE, | |
b4e3ac74 LW |
461 | .request = u300_gpio_request, |
462 | .free = u300_gpio_free, | |
cc890cd7 LW |
463 | .get = u300_gpio_get, |
464 | .set = u300_gpio_set, | |
465 | .direction_input = u300_gpio_direction_input, | |
466 | .direction_output = u300_gpio_direction_output, | |
467 | .to_irq = u300_gpio_to_irq, | |
468 | }; | |
469 | ||
470 | static void u300_toggle_trigger(struct u300_gpio *gpio, unsigned offset) | |
bd41b99d | 471 | { |
bd41b99d LW |
472 | u32 val; |
473 | ||
cc890cd7 LW |
474 | val = readl(U300_PIN_REG(offset, icr)); |
475 | /* Set mode depending on state */ | |
476 | if (u300_gpio_get(&gpio->chip, offset)) { | |
477 | /* High now, let's trigger on falling edge next then */ | |
478 | writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, icr)); | |
479 | dev_dbg(gpio->dev, "next IRQ on falling edge on pin %d\n", | |
480 | offset); | |
481 | } else { | |
482 | /* Low now, let's trigger on rising edge next then */ | |
483 | writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, icr)); | |
484 | dev_dbg(gpio->dev, "next IRQ on rising edge on pin %d\n", | |
485 | offset); | |
486 | } | |
bd41b99d | 487 | } |
bd41b99d | 488 | |
cc890cd7 | 489 | static int u300_gpio_irq_type(struct irq_data *d, unsigned trigger) |
bd41b99d | 490 | { |
cc890cd7 LW |
491 | struct u300_gpio_port *port = irq_data_get_irq_chip_data(d); |
492 | struct u300_gpio *gpio = port->gpio; | |
a6c45b99 | 493 | int offset = (port->number << 3) + d->hwirq; |
bd41b99d | 494 | u32 val; |
bd41b99d | 495 | |
cc890cd7 LW |
496 | if ((trigger & IRQF_TRIGGER_RISING) && |
497 | (trigger & IRQF_TRIGGER_FALLING)) { | |
498 | /* | |
499 | * The GPIO block can only trigger on falling OR rising edges, | |
500 | * not both. So we need to toggle the mode whenever the pin | |
501 | * goes from one state to the other with a special state flag | |
502 | */ | |
503 | dev_dbg(gpio->dev, | |
504 | "trigger on both rising and falling edge on pin %d\n", | |
505 | offset); | |
506 | port->toggle_edge_mode |= U300_PIN_BIT(offset); | |
507 | u300_toggle_trigger(gpio, offset); | |
508 | } else if (trigger & IRQF_TRIGGER_RISING) { | |
509 | dev_dbg(gpio->dev, "trigger on rising edge on pin %d\n", | |
510 | offset); | |
511 | val = readl(U300_PIN_REG(offset, icr)); | |
512 | writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, icr)); | |
513 | port->toggle_edge_mode &= ~U300_PIN_BIT(offset); | |
514 | } else if (trigger & IRQF_TRIGGER_FALLING) { | |
515 | dev_dbg(gpio->dev, "trigger on falling edge on pin %d\n", | |
516 | offset); | |
517 | val = readl(U300_PIN_REG(offset, icr)); | |
518 | writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, icr)); | |
519 | port->toggle_edge_mode &= ~U300_PIN_BIT(offset); | |
520 | } | |
521 | ||
522 | return 0; | |
bd41b99d | 523 | } |
bd41b99d | 524 | |
cc890cd7 | 525 | static void u300_gpio_irq_enable(struct irq_data *d) |
bd41b99d | 526 | { |
cc890cd7 LW |
527 | struct u300_gpio_port *port = irq_data_get_irq_chip_data(d); |
528 | struct u300_gpio *gpio = port->gpio; | |
a6c45b99 | 529 | int offset = (port->number << 3) + d->hwirq; |
bd41b99d LW |
530 | u32 val; |
531 | unsigned long flags; | |
532 | ||
a6c45b99 LW |
533 | dev_dbg(gpio->dev, "enable IRQ for hwirq %lu on port %s, offset %d\n", |
534 | d->hwirq, port->name, offset); | |
bd41b99d | 535 | local_irq_save(flags); |
cc890cd7 LW |
536 | val = readl(U300_PIN_REG(offset, ien)); |
537 | writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, ien)); | |
bd41b99d LW |
538 | local_irq_restore(flags); |
539 | } | |
bd41b99d | 540 | |
cc890cd7 | 541 | static void u300_gpio_irq_disable(struct irq_data *d) |
bd41b99d | 542 | { |
cc890cd7 LW |
543 | struct u300_gpio_port *port = irq_data_get_irq_chip_data(d); |
544 | struct u300_gpio *gpio = port->gpio; | |
a6c45b99 | 545 | int offset = (port->number << 3) + d->hwirq; |
bd41b99d LW |
546 | u32 val; |
547 | unsigned long flags; | |
548 | ||
549 | local_irq_save(flags); | |
cc890cd7 LW |
550 | val = readl(U300_PIN_REG(offset, ien)); |
551 | writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, ien)); | |
bd41b99d LW |
552 | local_irq_restore(flags); |
553 | } | |
bd41b99d | 554 | |
cc890cd7 LW |
555 | static struct irq_chip u300_gpio_irqchip = { |
556 | .name = "u300-gpio-irqchip", | |
557 | .irq_enable = u300_gpio_irq_enable, | |
558 | .irq_disable = u300_gpio_irq_disable, | |
559 | .irq_set_type = u300_gpio_irq_type, | |
560 | ||
561 | }; | |
562 | ||
563 | static void u300_gpio_irq_handler(unsigned irq, struct irq_desc *desc) | |
bd41b99d | 564 | { |
cc890cd7 LW |
565 | struct u300_gpio_port *port = irq_get_handler_data(irq); |
566 | struct u300_gpio *gpio = port->gpio; | |
567 | int pinoffset = port->number << 3; /* get the right stride */ | |
568 | unsigned long val; | |
bd41b99d | 569 | |
cc890cd7 | 570 | desc->irq_data.chip->irq_ack(&desc->irq_data); |
bd41b99d | 571 | /* Read event register */ |
cc890cd7 | 572 | val = readl(U300_PIN_REG(pinoffset, iev)); |
bd41b99d | 573 | /* Mask relevant bits */ |
cc890cd7 | 574 | val &= 0xFFU; /* 8 bits per port */ |
bd41b99d | 575 | /* ACK IRQ (clear event) */ |
cc890cd7 LW |
576 | writel(val, U300_PIN_REG(pinoffset, iev)); |
577 | ||
578 | /* Call IRQ handler */ | |
579 | if (val != 0) { | |
580 | int irqoffset; | |
581 | ||
582 | for_each_set_bit(irqoffset, &val, U300_GPIO_PINS_PER_PORT) { | |
a6c45b99 | 583 | int pin_irq = irq_find_mapping(port->domain, irqoffset); |
cc890cd7 LW |
584 | int offset = pinoffset + irqoffset; |
585 | ||
586 | dev_dbg(gpio->dev, "GPIO IRQ %d on pin %d\n", | |
587 | pin_irq, offset); | |
588 | generic_handle_irq(pin_irq); | |
589 | /* | |
590 | * Triggering IRQ on both rising and falling edge | |
591 | * needs mockery | |
592 | */ | |
593 | if (port->toggle_edge_mode & U300_PIN_BIT(offset)) | |
594 | u300_toggle_trigger(gpio, offset); | |
595 | } | |
bd41b99d | 596 | } |
cc890cd7 LW |
597 | |
598 | desc->irq_data.chip->irq_unmask(&desc->irq_data); | |
bd41b99d LW |
599 | } |
600 | ||
cc890cd7 LW |
601 | static void __init u300_gpio_init_pin(struct u300_gpio *gpio, |
602 | int offset, | |
603 | const struct u300_gpio_confdata *conf) | |
bd41b99d | 604 | { |
cc890cd7 LW |
605 | /* Set mode: input or output */ |
606 | if (conf->output) { | |
607 | u300_gpio_direction_output(&gpio->chip, offset, conf->outval); | |
bd41b99d | 608 | |
cc890cd7 | 609 | /* Deactivate bias mode for output */ |
dc0b1aa3 LW |
610 | u300_gpio_config_set(&gpio->chip, offset, |
611 | PIN_CONFIG_BIAS_HIGH_IMPEDANCE); | |
cc890cd7 LW |
612 | |
613 | /* Set drive mode for output */ | |
dc0b1aa3 LW |
614 | u300_gpio_config_set(&gpio->chip, offset, |
615 | PIN_CONFIG_DRIVE_PUSH_PULL); | |
cc890cd7 LW |
616 | |
617 | dev_dbg(gpio->dev, "set up pin %d as output, value: %d\n", | |
618 | offset, conf->outval); | |
619 | } else { | |
620 | u300_gpio_direction_input(&gpio->chip, offset); | |
621 | ||
622 | /* Always set output low on input pins */ | |
623 | u300_gpio_set(&gpio->chip, offset, 0); | |
624 | ||
625 | /* Set bias mode for input */ | |
dc0b1aa3 | 626 | u300_gpio_config_set(&gpio->chip, offset, conf->bias_mode); |
cc890cd7 LW |
627 | |
628 | dev_dbg(gpio->dev, "set up pin %d as input, bias: %04x\n", | |
629 | offset, conf->bias_mode); | |
bd41b99d | 630 | } |
cc890cd7 | 631 | } |
bd41b99d | 632 | |
cc890cd7 LW |
633 | static void __init u300_gpio_init_coh901571(struct u300_gpio *gpio, |
634 | struct u300_gpio_platform *plat) | |
635 | { | |
636 | int i, j; | |
637 | ||
638 | /* Write default config and values to all pins */ | |
639 | for (i = 0; i < plat->ports; i++) { | |
640 | for (j = 0; j < 8; j++) { | |
641 | const struct u300_gpio_confdata *conf; | |
642 | int offset = (i*8) + j; | |
643 | ||
04b13de6 | 644 | conf = &bs335_gpio_config[i][j]; |
cc890cd7 | 645 | u300_gpio_init_pin(gpio, offset, conf); |
bd41b99d LW |
646 | } |
647 | } | |
cc890cd7 | 648 | } |
bd41b99d | 649 | |
cc890cd7 LW |
650 | static inline void u300_gpio_free_ports(struct u300_gpio *gpio) |
651 | { | |
652 | struct u300_gpio_port *port; | |
653 | struct list_head *p, *n; | |
654 | ||
655 | list_for_each_safe(p, n, &gpio->port_list) { | |
656 | port = list_entry(p, struct u300_gpio_port, node); | |
657 | list_del(&port->node); | |
a6c45b99 LW |
658 | if (port->domain) |
659 | irq_domain_remove(port->domain); | |
cc890cd7 | 660 | kfree(port); |
bd41b99d | 661 | } |
bd41b99d LW |
662 | } |
663 | ||
387923c5 LW |
664 | /* |
665 | * Here we map a GPIO in the local gpio_chip pin space to a pin in | |
666 | * the local pinctrl pin space. The pin controller used is | |
667 | * pinctrl-u300. | |
668 | */ | |
669 | struct coh901_pinpair { | |
670 | unsigned int offset; | |
671 | unsigned int pin_base; | |
672 | }; | |
673 | ||
674 | #define COH901_PINRANGE(a, b) { .offset = a, .pin_base = b } | |
675 | ||
676 | static struct coh901_pinpair coh901_pintable[] = { | |
677 | COH901_PINRANGE(10, 426), | |
678 | COH901_PINRANGE(11, 180), | |
679 | COH901_PINRANGE(12, 165), /* MS/MMC card insertion */ | |
680 | COH901_PINRANGE(13, 179), | |
681 | COH901_PINRANGE(14, 178), | |
682 | COH901_PINRANGE(16, 194), | |
683 | COH901_PINRANGE(17, 193), | |
684 | COH901_PINRANGE(18, 192), | |
685 | COH901_PINRANGE(19, 191), | |
686 | COH901_PINRANGE(20, 186), | |
687 | COH901_PINRANGE(21, 185), | |
688 | COH901_PINRANGE(22, 184), | |
689 | COH901_PINRANGE(23, 183), | |
690 | COH901_PINRANGE(24, 182), | |
691 | COH901_PINRANGE(25, 181), | |
692 | }; | |
693 | ||
cc890cd7 | 694 | static int __init u300_gpio_probe(struct platform_device *pdev) |
bd41b99d | 695 | { |
cc890cd7 LW |
696 | struct u300_gpio_platform *plat = dev_get_platdata(&pdev->dev); |
697 | struct u300_gpio *gpio; | |
585583f5 | 698 | struct resource *memres; |
bd41b99d | 699 | int err = 0; |
cc890cd7 LW |
700 | int portno; |
701 | u32 val; | |
702 | u32 ifr; | |
bd41b99d | 703 | int i; |
bd41b99d | 704 | |
585583f5 LW |
705 | gpio = devm_kzalloc(&pdev->dev, sizeof(struct u300_gpio), GFP_KERNEL); |
706 | if (gpio == NULL) | |
cc890cd7 | 707 | return -ENOMEM; |
cc890cd7 LW |
708 | |
709 | gpio->chip = u300_gpio_chip; | |
710 | gpio->chip.ngpio = plat->ports * U300_GPIO_PINS_PER_PORT; | |
cc890cd7 LW |
711 | gpio->chip.dev = &pdev->dev; |
712 | gpio->chip.base = plat->gpio_base; | |
713 | gpio->dev = &pdev->dev; | |
bd41b99d | 714 | |
585583f5 | 715 | memres = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
9e0c1fb2 TR |
716 | gpio->base = devm_ioremap_resource(&pdev->dev, memres); |
717 | if (IS_ERR(gpio->base)) | |
718 | return PTR_ERR(gpio->base); | |
585583f5 LW |
719 | |
720 | gpio->clk = devm_clk_get(gpio->dev, NULL); | |
cc890cd7 LW |
721 | if (IS_ERR(gpio->clk)) { |
722 | err = PTR_ERR(gpio->clk); | |
723 | dev_err(gpio->dev, "could not get GPIO clock\n"); | |
585583f5 | 724 | return err; |
bd41b99d | 725 | } |
585583f5 | 726 | |
27e8461c | 727 | err = clk_prepare_enable(gpio->clk); |
bd41b99d | 728 | if (err) { |
cc890cd7 | 729 | dev_err(gpio->dev, "could not enable GPIO clock\n"); |
585583f5 | 730 | return err; |
bd41b99d | 731 | } |
cc890cd7 | 732 | |
04b13de6 LW |
733 | dev_info(gpio->dev, |
734 | "initializing GPIO Controller COH 901 571/3\n"); | |
735 | gpio->stride = U300_GPIO_PORT_STRIDE; | |
736 | gpio->pcr = U300_GPIO_PXPCR; | |
737 | gpio->dor = U300_GPIO_PXPDOR; | |
738 | gpio->dir = U300_GPIO_PXPDIR; | |
739 | gpio->per = U300_GPIO_PXPER; | |
740 | gpio->icr = U300_GPIO_PXICR; | |
741 | gpio->ien = U300_GPIO_PXIEN; | |
742 | gpio->iev = U300_GPIO_PXIEV; | |
743 | ifr = U300_GPIO_PXIFR; | |
744 | ||
745 | val = readl(gpio->base + U300_GPIO_CR); | |
746 | dev_info(gpio->dev, "COH901571/3 block version: %d, " \ | |
747 | "number of cores: %d totalling %d pins\n", | |
748 | ((val & 0x000001FC) >> 2), | |
749 | ((val & 0x0000FE00) >> 9), | |
750 | ((val & 0x0000FE00) >> 9) * 8); | |
751 | writel(U300_GPIO_CR_BLOCK_CLKRQ_ENABLE, | |
752 | gpio->base + U300_GPIO_CR); | |
753 | u300_gpio_init_coh901571(gpio, plat); | |
cc890cd7 LW |
754 | |
755 | /* Add each port with its IRQ separately */ | |
756 | INIT_LIST_HEAD(&gpio->port_list); | |
757 | for (portno = 0 ; portno < plat->ports; portno++) { | |
758 | struct u300_gpio_port *port = | |
759 | kmalloc(sizeof(struct u300_gpio_port), GFP_KERNEL); | |
760 | ||
761 | if (!port) { | |
762 | dev_err(gpio->dev, "out of memory\n"); | |
763 | err = -ENOMEM; | |
764 | goto err_no_port; | |
bd41b99d | 765 | } |
cc890cd7 LW |
766 | |
767 | snprintf(port->name, 8, "gpio%d", portno); | |
768 | port->number = portno; | |
769 | port->gpio = gpio; | |
770 | ||
771 | port->irq = platform_get_irq_byname(pdev, | |
772 | port->name); | |
773 | ||
a6c45b99 | 774 | dev_dbg(gpio->dev, "register IRQ %d for port %s\n", port->irq, |
cc890cd7 LW |
775 | port->name); |
776 | ||
a6c45b99 LW |
777 | port->domain = irq_domain_add_linear(pdev->dev.of_node, |
778 | U300_GPIO_PINS_PER_PORT, | |
779 | &irq_domain_simple_ops, | |
780 | port); | |
80357203 AL |
781 | if (!port->domain) { |
782 | err = -ENOMEM; | |
a6c45b99 | 783 | goto err_no_domain; |
80357203 | 784 | } |
a6c45b99 | 785 | |
cc890cd7 LW |
786 | irq_set_chained_handler(port->irq, u300_gpio_irq_handler); |
787 | irq_set_handler_data(port->irq, port); | |
788 | ||
789 | /* For each GPIO pin set the unique IRQ handler */ | |
790 | for (i = 0; i < U300_GPIO_PINS_PER_PORT; i++) { | |
a6c45b99 | 791 | int irqno = irq_create_mapping(port->domain, i); |
cc890cd7 | 792 | |
a6c45b99 LW |
793 | dev_dbg(gpio->dev, "GPIO%d on port %s gets IRQ %d\n", |
794 | gpio->chip.base + (port->number << 3) + i, | |
795 | port->name, irqno); | |
cc890cd7 LW |
796 | irq_set_chip_and_handler(irqno, &u300_gpio_irqchip, |
797 | handle_simple_irq); | |
798 | set_irq_flags(irqno, IRQF_VALID); | |
799 | irq_set_chip_data(irqno, port); | |
800 | } | |
801 | ||
802 | /* Turns off irq force (test register) for this port */ | |
803 | writel(0x0, gpio->base + portno * gpio->stride + ifr); | |
804 | ||
805 | list_add_tail(&port->node, &gpio->port_list); | |
bd41b99d | 806 | } |
cc890cd7 LW |
807 | dev_dbg(gpio->dev, "initialized %d GPIO ports\n", portno); |
808 | ||
809 | err = gpiochip_add(&gpio->chip); | |
810 | if (err) { | |
811 | dev_err(gpio->dev, "unable to add gpiochip: %d\n", err); | |
812 | goto err_no_chip; | |
813 | } | |
814 | ||
387923c5 LW |
815 | /* |
816 | * Add pinctrl pin ranges, the pin controller must be registered | |
817 | * at this point | |
818 | */ | |
819 | for (i = 0; i < ARRAY_SIZE(coh901_pintable); i++) { | |
820 | struct coh901_pinpair *p = &coh901_pintable[i]; | |
821 | ||
822 | err = gpiochip_add_pin_range(&gpio->chip, "pinctrl-u300", | |
823 | p->offset, p->pin_base, 1); | |
824 | if (err) | |
825 | goto err_no_range; | |
826 | } | |
827 | ||
cc890cd7 | 828 | platform_set_drvdata(pdev, gpio); |
bd41b99d LW |
829 | |
830 | return 0; | |
831 | ||
387923c5 | 832 | err_no_range: |
97fc4637 AL |
833 | if (gpiochip_remove(&gpio->chip)) |
834 | dev_err(&pdev->dev, "failed to remove gpio chip\n"); | |
cc890cd7 | 835 | err_no_chip: |
a6c45b99 | 836 | err_no_domain: |
cc890cd7 LW |
837 | err_no_port: |
838 | u300_gpio_free_ports(gpio); | |
27e8461c | 839 | clk_disable_unprepare(gpio->clk); |
80357203 | 840 | dev_err(&pdev->dev, "module ERROR:%d\n", err); |
bd41b99d LW |
841 | return err; |
842 | } | |
843 | ||
cc890cd7 | 844 | static int __exit u300_gpio_remove(struct platform_device *pdev) |
bd41b99d | 845 | { |
cc890cd7 LW |
846 | struct u300_gpio *gpio = platform_get_drvdata(pdev); |
847 | int err; | |
bd41b99d LW |
848 | |
849 | /* Turn off the GPIO block */ | |
04b13de6 | 850 | writel(0x00000000U, gpio->base + U300_GPIO_CR); |
cc890cd7 LW |
851 | |
852 | err = gpiochip_remove(&gpio->chip); | |
853 | if (err < 0) { | |
854 | dev_err(gpio->dev, "unable to remove gpiochip: %d\n", err); | |
855 | return err; | |
856 | } | |
857 | u300_gpio_free_ports(gpio); | |
27e8461c | 858 | clk_disable_unprepare(gpio->clk); |
cc890cd7 | 859 | platform_set_drvdata(pdev, NULL); |
bd41b99d LW |
860 | return 0; |
861 | } | |
862 | ||
cc890cd7 | 863 | static struct platform_driver u300_gpio_driver = { |
bd41b99d LW |
864 | .driver = { |
865 | .name = "u300-gpio", | |
866 | }, | |
cc890cd7 | 867 | .remove = __exit_p(u300_gpio_remove), |
bd41b99d LW |
868 | }; |
869 | ||
bd41b99d LW |
870 | static int __init u300_gpio_init(void) |
871 | { | |
cc890cd7 | 872 | return platform_driver_probe(&u300_gpio_driver, u300_gpio_probe); |
bd41b99d LW |
873 | } |
874 | ||
875 | static void __exit u300_gpio_exit(void) | |
876 | { | |
cc890cd7 | 877 | platform_driver_unregister(&u300_gpio_driver); |
bd41b99d LW |
878 | } |
879 | ||
880 | arch_initcall(u300_gpio_init); | |
881 | module_exit(u300_gpio_exit); | |
882 | ||
883 | MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>"); | |
cc890cd7 | 884 | MODULE_DESCRIPTION("ST-Ericsson AB COH 901 335/COH 901 571/3 GPIO driver"); |
bd41b99d | 885 | MODULE_LICENSE("GPL"); |