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43b169db TA |
1 | /* |
2 | * Exynos specific support for Samsung pinctrl/gpiolib driver with eint support. | |
3 | * | |
4 | * Copyright (c) 2012 Samsung Electronics Co., Ltd. | |
5 | * http://www.samsung.com | |
6 | * Copyright (c) 2012 Linaro Ltd | |
7 | * http://www.linaro.org | |
8 | * | |
9 | * Author: Thomas Abraham <thomas.ab@samsung.com> | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or | |
14 | * (at your option) any later version. | |
15 | * | |
16 | * This file contains the Samsung Exynos specific information required by the | |
17 | * the Samsung pinctrl/gpiolib driver. It also includes the implementation of | |
18 | * external gpio and wakeup interrupt support. | |
19 | */ | |
20 | ||
21 | #include <linux/module.h> | |
22 | #include <linux/device.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/irqdomain.h> | |
25 | #include <linux/irq.h> | |
26 | #include <linux/of_irq.h> | |
27 | #include <linux/io.h> | |
28 | #include <linux/slab.h> | |
29 | #include <linux/err.h> | |
30 | ||
31 | #include <asm/mach/irq.h> | |
32 | ||
33 | #include "pinctrl-samsung.h" | |
34 | #include "pinctrl-exynos.h" | |
35 | ||
36 | /* list of external wakeup controllers supported */ | |
37 | static const struct of_device_id exynos_wkup_irq_ids[] = { | |
38 | { .compatible = "samsung,exynos4210-wakeup-eint", }, | |
39 | }; | |
40 | ||
41 | static void exynos_gpio_irq_unmask(struct irq_data *irqd) | |
42 | { | |
595be726 TF |
43 | struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); |
44 | struct samsung_pinctrl_drv_data *d = bank->drvdata; | |
45 | unsigned long reg_mask = d->ctrl->geint_mask + bank->eint_offset; | |
43b169db TA |
46 | unsigned long mask; |
47 | ||
48 | mask = readl(d->virt_base + reg_mask); | |
595be726 | 49 | mask &= ~(1 << irqd->hwirq); |
43b169db TA |
50 | writel(mask, d->virt_base + reg_mask); |
51 | } | |
52 | ||
53 | static void exynos_gpio_irq_mask(struct irq_data *irqd) | |
54 | { | |
595be726 TF |
55 | struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); |
56 | struct samsung_pinctrl_drv_data *d = bank->drvdata; | |
57 | unsigned long reg_mask = d->ctrl->geint_mask + bank->eint_offset; | |
43b169db TA |
58 | unsigned long mask; |
59 | ||
60 | mask = readl(d->virt_base + reg_mask); | |
595be726 | 61 | mask |= 1 << irqd->hwirq; |
43b169db TA |
62 | writel(mask, d->virt_base + reg_mask); |
63 | } | |
64 | ||
65 | static void exynos_gpio_irq_ack(struct irq_data *irqd) | |
66 | { | |
595be726 TF |
67 | struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); |
68 | struct samsung_pinctrl_drv_data *d = bank->drvdata; | |
69 | unsigned long reg_pend = d->ctrl->geint_pend + bank->eint_offset; | |
43b169db | 70 | |
595be726 | 71 | writel(1 << irqd->hwirq, d->virt_base + reg_pend); |
43b169db TA |
72 | } |
73 | ||
74 | static int exynos_gpio_irq_set_type(struct irq_data *irqd, unsigned int type) | |
75 | { | |
595be726 TF |
76 | struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); |
77 | struct samsung_pinctrl_drv_data *d = bank->drvdata; | |
43b169db | 78 | struct samsung_pin_ctrl *ctrl = d->ctrl; |
595be726 TF |
79 | unsigned int pin = irqd->hwirq; |
80 | unsigned int shift = EXYNOS_EINT_CON_LEN * pin; | |
43b169db | 81 | unsigned int con, trig_type; |
595be726 | 82 | unsigned long reg_con = ctrl->geint_con + bank->eint_offset; |
ee2f573c | 83 | unsigned int mask; |
43b169db TA |
84 | |
85 | switch (type) { | |
86 | case IRQ_TYPE_EDGE_RISING: | |
87 | trig_type = EXYNOS_EINT_EDGE_RISING; | |
88 | break; | |
89 | case IRQ_TYPE_EDGE_FALLING: | |
90 | trig_type = EXYNOS_EINT_EDGE_FALLING; | |
91 | break; | |
92 | case IRQ_TYPE_EDGE_BOTH: | |
93 | trig_type = EXYNOS_EINT_EDGE_BOTH; | |
94 | break; | |
95 | case IRQ_TYPE_LEVEL_HIGH: | |
96 | trig_type = EXYNOS_EINT_LEVEL_HIGH; | |
97 | break; | |
98 | case IRQ_TYPE_LEVEL_LOW: | |
99 | trig_type = EXYNOS_EINT_LEVEL_LOW; | |
100 | break; | |
101 | default: | |
102 | pr_err("unsupported external interrupt type\n"); | |
103 | return -EINVAL; | |
104 | } | |
105 | ||
106 | if (type & IRQ_TYPE_EDGE_BOTH) | |
107 | __irq_set_handler_locked(irqd->irq, handle_edge_irq); | |
108 | else | |
109 | __irq_set_handler_locked(irqd->irq, handle_level_irq); | |
110 | ||
111 | con = readl(d->virt_base + reg_con); | |
112 | con &= ~(EXYNOS_EINT_CON_MASK << shift); | |
113 | con |= trig_type << shift; | |
114 | writel(con, d->virt_base + reg_con); | |
ee2f573c TF |
115 | |
116 | reg_con = bank->pctl_offset; | |
595be726 | 117 | shift = pin * bank->func_width; |
ee2f573c TF |
118 | mask = (1 << bank->func_width) - 1; |
119 | ||
120 | con = readl(d->virt_base + reg_con); | |
121 | con &= ~(mask << shift); | |
122 | con |= EXYNOS_EINT_FUNC << shift; | |
123 | writel(con, d->virt_base + reg_con); | |
124 | ||
43b169db TA |
125 | return 0; |
126 | } | |
127 | ||
128 | /* | |
129 | * irq_chip for gpio interrupts. | |
130 | */ | |
131 | static struct irq_chip exynos_gpio_irq_chip = { | |
132 | .name = "exynos_gpio_irq_chip", | |
133 | .irq_unmask = exynos_gpio_irq_unmask, | |
134 | .irq_mask = exynos_gpio_irq_mask, | |
135 | .irq_ack = exynos_gpio_irq_ack, | |
136 | .irq_set_type = exynos_gpio_irq_set_type, | |
137 | }; | |
138 | ||
43b169db TA |
139 | static int exynos_gpio_irq_map(struct irq_domain *h, unsigned int virq, |
140 | irq_hw_number_t hw) | |
141 | { | |
595be726 | 142 | struct samsung_pin_bank *b = h->host_data; |
43b169db | 143 | |
595be726 | 144 | irq_set_chip_data(virq, b); |
43b169db TA |
145 | irq_set_chip_and_handler(virq, &exynos_gpio_irq_chip, |
146 | handle_level_irq); | |
147 | set_irq_flags(virq, IRQF_VALID); | |
148 | return 0; | |
149 | } | |
150 | ||
43b169db TA |
151 | /* |
152 | * irq domain callbacks for external gpio interrupt controller. | |
153 | */ | |
154 | static const struct irq_domain_ops exynos_gpio_irqd_ops = { | |
155 | .map = exynos_gpio_irq_map, | |
43b169db TA |
156 | .xlate = irq_domain_xlate_twocell, |
157 | }; | |
158 | ||
159 | static irqreturn_t exynos_eint_gpio_irq(int irq, void *data) | |
160 | { | |
161 | struct samsung_pinctrl_drv_data *d = data; | |
162 | struct samsung_pin_ctrl *ctrl = d->ctrl; | |
163 | struct samsung_pin_bank *bank = ctrl->pin_banks; | |
164 | unsigned int svc, group, pin, virq; | |
165 | ||
166 | svc = readl(d->virt_base + ctrl->svc); | |
167 | group = EXYNOS_SVC_GROUP(svc); | |
168 | pin = svc & EXYNOS_SVC_NUM_MASK; | |
169 | ||
170 | if (!group) | |
171 | return IRQ_HANDLED; | |
172 | bank += (group - 1); | |
173 | ||
595be726 | 174 | virq = irq_linear_revmap(bank->irq_domain, pin); |
43b169db TA |
175 | if (!virq) |
176 | return IRQ_NONE; | |
177 | generic_handle_irq(virq); | |
178 | return IRQ_HANDLED; | |
179 | } | |
180 | ||
181 | /* | |
182 | * exynos_eint_gpio_init() - setup handling of external gpio interrupts. | |
183 | * @d: driver data of samsung pinctrl driver. | |
184 | */ | |
185 | static int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d) | |
186 | { | |
595be726 | 187 | struct samsung_pin_bank *bank; |
43b169db TA |
188 | struct device *dev = d->dev; |
189 | unsigned int ret; | |
595be726 | 190 | unsigned int i; |
43b169db TA |
191 | |
192 | if (!d->irq) { | |
193 | dev_err(dev, "irq number not available\n"); | |
194 | return -EINVAL; | |
195 | } | |
196 | ||
197 | ret = devm_request_irq(dev, d->irq, exynos_eint_gpio_irq, | |
198 | 0, dev_name(dev), d); | |
199 | if (ret) { | |
200 | dev_err(dev, "irq request failed\n"); | |
201 | return -ENXIO; | |
202 | } | |
203 | ||
595be726 TF |
204 | bank = d->ctrl->pin_banks; |
205 | for (i = 0; i < d->ctrl->nr_banks; ++i, ++bank) { | |
206 | if (bank->eint_type != EINT_TYPE_GPIO) | |
207 | continue; | |
208 | bank->irq_domain = irq_domain_add_linear(bank->of_node, | |
209 | bank->nr_pins, &exynos_gpio_irqd_ops, bank); | |
210 | if (!bank->irq_domain) { | |
211 | dev_err(dev, "gpio irq domain add failed\n"); | |
212 | return -ENXIO; | |
213 | } | |
43b169db TA |
214 | } |
215 | ||
216 | return 0; | |
217 | } | |
218 | ||
219 | static void exynos_wkup_irq_unmask(struct irq_data *irqd) | |
220 | { | |
221 | struct samsung_pinctrl_drv_data *d = irq_data_get_irq_chip_data(irqd); | |
222 | unsigned int bank = irqd->hwirq / EXYNOS_EINT_MAX_PER_BANK; | |
223 | unsigned int pin = irqd->hwirq & (EXYNOS_EINT_MAX_PER_BANK - 1); | |
224 | unsigned long reg_mask = d->ctrl->weint_mask + (bank << 2); | |
225 | unsigned long mask; | |
226 | ||
227 | mask = readl(d->virt_base + reg_mask); | |
228 | mask &= ~(1 << pin); | |
229 | writel(mask, d->virt_base + reg_mask); | |
230 | } | |
231 | ||
232 | static void exynos_wkup_irq_mask(struct irq_data *irqd) | |
233 | { | |
234 | struct samsung_pinctrl_drv_data *d = irq_data_get_irq_chip_data(irqd); | |
235 | unsigned int bank = irqd->hwirq / EXYNOS_EINT_MAX_PER_BANK; | |
236 | unsigned int pin = irqd->hwirq & (EXYNOS_EINT_MAX_PER_BANK - 1); | |
237 | unsigned long reg_mask = d->ctrl->weint_mask + (bank << 2); | |
238 | unsigned long mask; | |
239 | ||
240 | mask = readl(d->virt_base + reg_mask); | |
3da23f27 | 241 | mask |= 1 << pin; |
43b169db TA |
242 | writel(mask, d->virt_base + reg_mask); |
243 | } | |
244 | ||
245 | static void exynos_wkup_irq_ack(struct irq_data *irqd) | |
246 | { | |
247 | struct samsung_pinctrl_drv_data *d = irq_data_get_irq_chip_data(irqd); | |
248 | unsigned int bank = irqd->hwirq / EXYNOS_EINT_MAX_PER_BANK; | |
249 | unsigned int pin = irqd->hwirq & (EXYNOS_EINT_MAX_PER_BANK - 1); | |
250 | unsigned long pend = d->ctrl->weint_pend + (bank << 2); | |
251 | ||
252 | writel(1 << pin, d->virt_base + pend); | |
253 | } | |
254 | ||
255 | static int exynos_wkup_irq_set_type(struct irq_data *irqd, unsigned int type) | |
256 | { | |
257 | struct samsung_pinctrl_drv_data *d = irq_data_get_irq_chip_data(irqd); | |
258 | unsigned int bank = irqd->hwirq / EXYNOS_EINT_MAX_PER_BANK; | |
259 | unsigned int pin = irqd->hwirq & (EXYNOS_EINT_MAX_PER_BANK - 1); | |
260 | unsigned long reg_con = d->ctrl->weint_con + (bank << 2); | |
261 | unsigned long shift = EXYNOS_EINT_CON_LEN * pin; | |
262 | unsigned long con, trig_type; | |
263 | ||
264 | switch (type) { | |
265 | case IRQ_TYPE_EDGE_RISING: | |
266 | trig_type = EXYNOS_EINT_EDGE_RISING; | |
267 | break; | |
268 | case IRQ_TYPE_EDGE_FALLING: | |
269 | trig_type = EXYNOS_EINT_EDGE_FALLING; | |
270 | break; | |
271 | case IRQ_TYPE_EDGE_BOTH: | |
272 | trig_type = EXYNOS_EINT_EDGE_BOTH; | |
273 | break; | |
274 | case IRQ_TYPE_LEVEL_HIGH: | |
275 | trig_type = EXYNOS_EINT_LEVEL_HIGH; | |
276 | break; | |
277 | case IRQ_TYPE_LEVEL_LOW: | |
278 | trig_type = EXYNOS_EINT_LEVEL_LOW; | |
279 | break; | |
280 | default: | |
281 | pr_err("unsupported external interrupt type\n"); | |
282 | return -EINVAL; | |
283 | } | |
284 | ||
285 | if (type & IRQ_TYPE_EDGE_BOTH) | |
286 | __irq_set_handler_locked(irqd->irq, handle_edge_irq); | |
287 | else | |
288 | __irq_set_handler_locked(irqd->irq, handle_level_irq); | |
289 | ||
290 | con = readl(d->virt_base + reg_con); | |
291 | con &= ~(EXYNOS_EINT_CON_MASK << shift); | |
292 | con |= trig_type << shift; | |
293 | writel(con, d->virt_base + reg_con); | |
294 | return 0; | |
295 | } | |
296 | ||
297 | /* | |
298 | * irq_chip for wakeup interrupts | |
299 | */ | |
300 | static struct irq_chip exynos_wkup_irq_chip = { | |
301 | .name = "exynos_wkup_irq_chip", | |
302 | .irq_unmask = exynos_wkup_irq_unmask, | |
303 | .irq_mask = exynos_wkup_irq_mask, | |
304 | .irq_ack = exynos_wkup_irq_ack, | |
305 | .irq_set_type = exynos_wkup_irq_set_type, | |
306 | }; | |
307 | ||
308 | /* interrupt handler for wakeup interrupts 0..15 */ | |
309 | static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc) | |
310 | { | |
311 | struct exynos_weint_data *eintd = irq_get_handler_data(irq); | |
312 | struct irq_chip *chip = irq_get_chip(irq); | |
313 | int eint_irq; | |
314 | ||
315 | chained_irq_enter(chip, desc); | |
316 | chip->irq_mask(&desc->irq_data); | |
317 | ||
318 | if (chip->irq_ack) | |
319 | chip->irq_ack(&desc->irq_data); | |
320 | ||
321 | eint_irq = irq_linear_revmap(eintd->domain, eintd->irq); | |
322 | generic_handle_irq(eint_irq); | |
323 | chip->irq_unmask(&desc->irq_data); | |
324 | chained_irq_exit(chip, desc); | |
325 | } | |
326 | ||
9759e2eb | 327 | static inline void exynos_irq_demux_eint(int irq_base, unsigned long pend, |
43b169db TA |
328 | struct irq_domain *domain) |
329 | { | |
330 | unsigned int irq; | |
331 | ||
332 | while (pend) { | |
333 | irq = fls(pend) - 1; | |
334 | generic_handle_irq(irq_find_mapping(domain, irq_base + irq)); | |
335 | pend &= ~(1 << irq); | |
336 | } | |
337 | } | |
338 | ||
339 | /* interrupt handler for wakeup interrupt 16 */ | |
340 | static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc) | |
341 | { | |
342 | struct irq_chip *chip = irq_get_chip(irq); | |
343 | struct exynos_weint_data *eintd = irq_get_handler_data(irq); | |
344 | struct samsung_pinctrl_drv_data *d = eintd->domain->host_data; | |
345 | unsigned long pend; | |
de59049b | 346 | unsigned long mask; |
43b169db TA |
347 | |
348 | chained_irq_enter(chip, desc); | |
349 | pend = readl(d->virt_base + d->ctrl->weint_pend + 0x8); | |
de59049b TF |
350 | mask = readl(d->virt_base + d->ctrl->weint_mask + 0x8); |
351 | exynos_irq_demux_eint(16, pend & ~mask, eintd->domain); | |
43b169db | 352 | pend = readl(d->virt_base + d->ctrl->weint_pend + 0xC); |
de59049b TF |
353 | mask = readl(d->virt_base + d->ctrl->weint_mask + 0xC); |
354 | exynos_irq_demux_eint(24, pend & ~mask, eintd->domain); | |
43b169db TA |
355 | chained_irq_exit(chip, desc); |
356 | } | |
357 | ||
358 | static int exynos_wkup_irq_map(struct irq_domain *h, unsigned int virq, | |
359 | irq_hw_number_t hw) | |
360 | { | |
361 | irq_set_chip_and_handler(virq, &exynos_wkup_irq_chip, handle_level_irq); | |
362 | irq_set_chip_data(virq, h->host_data); | |
363 | set_irq_flags(virq, IRQF_VALID); | |
364 | return 0; | |
365 | } | |
366 | ||
367 | /* | |
368 | * irq domain callbacks for external wakeup interrupt controller. | |
369 | */ | |
370 | static const struct irq_domain_ops exynos_wkup_irqd_ops = { | |
371 | .map = exynos_wkup_irq_map, | |
372 | .xlate = irq_domain_xlate_twocell, | |
373 | }; | |
374 | ||
375 | /* | |
376 | * exynos_eint_wkup_init() - setup handling of external wakeup interrupts. | |
377 | * @d: driver data of samsung pinctrl driver. | |
378 | */ | |
379 | static int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d) | |
380 | { | |
381 | struct device *dev = d->dev; | |
c3ad056b TF |
382 | struct device_node *wkup_np = NULL; |
383 | struct device_node *np; | |
43b169db TA |
384 | struct exynos_weint_data *weint_data; |
385 | int idx, irq; | |
386 | ||
c3ad056b TF |
387 | for_each_child_of_node(dev->of_node, np) { |
388 | if (of_match_node(exynos_wkup_irq_ids, np)) { | |
389 | wkup_np = np; | |
390 | break; | |
391 | } | |
43b169db | 392 | } |
c3ad056b TF |
393 | if (!wkup_np) |
394 | return -ENODEV; | |
43b169db TA |
395 | |
396 | d->wkup_irqd = irq_domain_add_linear(wkup_np, d->ctrl->nr_wint, | |
397 | &exynos_wkup_irqd_ops, d); | |
d3c97792 | 398 | if (!d->wkup_irqd) { |
43b169db TA |
399 | dev_err(dev, "wakeup irq domain allocation failed\n"); |
400 | return -ENXIO; | |
401 | } | |
402 | ||
403 | weint_data = devm_kzalloc(dev, sizeof(*weint_data) * 17, GFP_KERNEL); | |
404 | if (!weint_data) { | |
405 | dev_err(dev, "could not allocate memory for weint_data\n"); | |
406 | return -ENOMEM; | |
407 | } | |
408 | ||
409 | irq = irq_of_parse_and_map(wkup_np, 16); | |
410 | if (irq) { | |
411 | weint_data[16].domain = d->wkup_irqd; | |
412 | irq_set_chained_handler(irq, exynos_irq_demux_eint16_31); | |
413 | irq_set_handler_data(irq, &weint_data[16]); | |
414 | } else { | |
415 | dev_err(dev, "irq number for EINT16-32 not found\n"); | |
416 | } | |
417 | ||
418 | for (idx = 0; idx < 16; idx++) { | |
419 | weint_data[idx].domain = d->wkup_irqd; | |
420 | weint_data[idx].irq = idx; | |
421 | ||
422 | irq = irq_of_parse_and_map(wkup_np, idx); | |
423 | if (irq) { | |
424 | irq_set_handler_data(irq, &weint_data[idx]); | |
425 | irq_set_chained_handler(irq, exynos_irq_eint0_15); | |
426 | } else { | |
427 | dev_err(dev, "irq number for eint-%x not found\n", idx); | |
428 | } | |
429 | } | |
430 | return 0; | |
431 | } | |
432 | ||
433 | /* pin banks of exynos4210 pin-controller 0 */ | |
434 | static struct samsung_pin_bank exynos4210_pin_banks0[] = { | |
1b6056d6 TF |
435 | EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), |
436 | EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04), | |
437 | EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08), | |
438 | EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c), | |
439 | EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10), | |
440 | EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14), | |
441 | EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpd1", 0x18), | |
442 | EXYNOS_PIN_BANK_EINTG(5, 0x0E0, "gpe0", 0x1c), | |
443 | EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpe1", 0x20), | |
444 | EXYNOS_PIN_BANK_EINTG(6, 0x120, "gpe2", 0x24), | |
445 | EXYNOS_PIN_BANK_EINTG(8, 0x140, "gpe3", 0x28), | |
446 | EXYNOS_PIN_BANK_EINTG(8, 0x160, "gpe4", 0x2c), | |
447 | EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpf0", 0x30), | |
448 | EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpf1", 0x34), | |
449 | EXYNOS_PIN_BANK_EINTG(8, 0x1C0, "gpf2", 0x38), | |
450 | EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf3", 0x3c), | |
43b169db TA |
451 | }; |
452 | ||
453 | /* pin banks of exynos4210 pin-controller 1 */ | |
454 | static struct samsung_pin_bank exynos4210_pin_banks1[] = { | |
1b6056d6 TF |
455 | EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpj0", 0x00), |
456 | EXYNOS_PIN_BANK_EINTG(5, 0x020, "gpj1", 0x04), | |
457 | EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpk0", 0x08), | |
458 | EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c), | |
459 | EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10), | |
460 | EXYNOS_PIN_BANK_EINTG(7, 0x0A0, "gpk3", 0x14), | |
461 | EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpl0", 0x18), | |
462 | EXYNOS_PIN_BANK_EINTG(3, 0x0E0, "gpl1", 0x1c), | |
463 | EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpl2", 0x20), | |
40ba6227 TF |
464 | EXYNOS_PIN_BANK_EINTN(6, 0x120, "gpy0"), |
465 | EXYNOS_PIN_BANK_EINTN(4, 0x140, "gpy1"), | |
466 | EXYNOS_PIN_BANK_EINTN(6, 0x160, "gpy2"), | |
467 | EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy3"), | |
468 | EXYNOS_PIN_BANK_EINTN(8, 0x1A0, "gpy4"), | |
469 | EXYNOS_PIN_BANK_EINTN(8, 0x1C0, "gpy5"), | |
470 | EXYNOS_PIN_BANK_EINTN(8, 0x1E0, "gpy6"), | |
471 | EXYNOS_PIN_BANK_EINTN(8, 0xC00, "gpx0"), | |
472 | EXYNOS_PIN_BANK_EINTN(8, 0xC20, "gpx1"), | |
473 | EXYNOS_PIN_BANK_EINTN(8, 0xC40, "gpx2"), | |
474 | EXYNOS_PIN_BANK_EINTN(8, 0xC60, "gpx3"), | |
43b169db TA |
475 | }; |
476 | ||
477 | /* pin banks of exynos4210 pin-controller 2 */ | |
478 | static struct samsung_pin_bank exynos4210_pin_banks2[] = { | |
40ba6227 | 479 | EXYNOS_PIN_BANK_EINTN(7, 0x000, "gpz"), |
43b169db TA |
480 | }; |
481 | ||
482 | /* | |
483 | * Samsung pinctrl driver data for Exynos4210 SoC. Exynos4210 SoC includes | |
484 | * three gpio/pin-mux/pinconfig controllers. | |
485 | */ | |
486 | struct samsung_pin_ctrl exynos4210_pin_ctrl[] = { | |
487 | { | |
488 | /* pin-controller instance 0 data */ | |
489 | .pin_banks = exynos4210_pin_banks0, | |
490 | .nr_banks = ARRAY_SIZE(exynos4210_pin_banks0), | |
43b169db TA |
491 | .geint_con = EXYNOS_GPIO_ECON_OFFSET, |
492 | .geint_mask = EXYNOS_GPIO_EMASK_OFFSET, | |
493 | .geint_pend = EXYNOS_GPIO_EPEND_OFFSET, | |
494 | .svc = EXYNOS_SVC_OFFSET, | |
495 | .eint_gpio_init = exynos_eint_gpio_init, | |
496 | .label = "exynos4210-gpio-ctrl0", | |
497 | }, { | |
498 | /* pin-controller instance 1 data */ | |
499 | .pin_banks = exynos4210_pin_banks1, | |
500 | .nr_banks = ARRAY_SIZE(exynos4210_pin_banks1), | |
43b169db TA |
501 | .nr_wint = 32, |
502 | .geint_con = EXYNOS_GPIO_ECON_OFFSET, | |
503 | .geint_mask = EXYNOS_GPIO_EMASK_OFFSET, | |
504 | .geint_pend = EXYNOS_GPIO_EPEND_OFFSET, | |
505 | .weint_con = EXYNOS_WKUP_ECON_OFFSET, | |
506 | .weint_mask = EXYNOS_WKUP_EMASK_OFFSET, | |
507 | .weint_pend = EXYNOS_WKUP_EPEND_OFFSET, | |
508 | .svc = EXYNOS_SVC_OFFSET, | |
509 | .eint_gpio_init = exynos_eint_gpio_init, | |
510 | .eint_wkup_init = exynos_eint_wkup_init, | |
511 | .label = "exynos4210-gpio-ctrl1", | |
512 | }, { | |
513 | /* pin-controller instance 2 data */ | |
514 | .pin_banks = exynos4210_pin_banks2, | |
515 | .nr_banks = ARRAY_SIZE(exynos4210_pin_banks2), | |
43b169db TA |
516 | .label = "exynos4210-gpio-ctrl2", |
517 | }, | |
518 | }; |