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Commit | Line | Data |
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e58b9e27 | 1 | /* |
4e47f91b LP |
2 | * MCP23S08 SPI/I2C GPIO gpio expander driver |
3 | * | |
4 | * The inputs and outputs of the mcp23s08, mcp23s17, mcp23008 and mcp23017 are | |
5 | * supported. | |
6 | * For the I2C versions of the chips (mcp23008 and mcp23017) generation of | |
7 | * interrupts is also supported. | |
8 | * The hardware of the SPI versions of the chips (mcp23s08 and mcp23s17) is | |
9 | * also capable of generating interrupts, but the linux driver does not | |
10 | * support that yet. | |
e58b9e27 DB |
11 | */ |
12 | ||
13 | #include <linux/kernel.h> | |
14 | #include <linux/device.h> | |
e58b9e27 | 15 | #include <linux/mutex.h> |
bb207ef1 | 16 | #include <linux/module.h> |
d120c17f | 17 | #include <linux/gpio.h> |
752ad5e8 | 18 | #include <linux/i2c.h> |
e58b9e27 DB |
19 | #include <linux/spi/spi.h> |
20 | #include <linux/spi/mcp23s08.h> | |
5a0e3ad6 | 21 | #include <linux/slab.h> |
0b7bb77f | 22 | #include <asm/byteorder.h> |
4e47f91b | 23 | #include <linux/interrupt.h> |
97ddb1c8 | 24 | #include <linux/of_device.h> |
3d84fdb3 | 25 | #include <linux/regmap.h> |
82039d24 SR |
26 | #include <linux/pinctrl/pinctrl.h> |
27 | #include <linux/pinctrl/pinconf.h> | |
28 | #include <linux/pinctrl/pinconf-generic.h> | |
e58b9e27 | 29 | |
0b7bb77f PK |
30 | /** |
31 | * MCP types supported by driver | |
32 | */ | |
33 | #define MCP_TYPE_S08 0 | |
34 | #define MCP_TYPE_S17 1 | |
752ad5e8 PK |
35 | #define MCP_TYPE_008 2 |
36 | #define MCP_TYPE_017 3 | |
28c5a41e | 37 | #define MCP_TYPE_S18 4 |
e58b9e27 DB |
38 | |
39 | /* Registers are all 8 bits wide. | |
40 | * | |
41 | * The mcp23s17 has twice as many bits, and can be configured to work | |
42 | * with either 16 bit registers or with two adjacent 8 bit banks. | |
e58b9e27 DB |
43 | */ |
44 | #define MCP_IODIR 0x00 /* init/reset: all ones */ | |
45 | #define MCP_IPOL 0x01 | |
46 | #define MCP_GPINTEN 0x02 | |
47 | #define MCP_DEFVAL 0x03 | |
48 | #define MCP_INTCON 0x04 | |
49 | #define MCP_IOCON 0x05 | |
4e47f91b | 50 | # define IOCON_MIRROR (1 << 6) |
e58b9e27 DB |
51 | # define IOCON_SEQOP (1 << 5) |
52 | # define IOCON_HAEN (1 << 3) | |
53 | # define IOCON_ODR (1 << 2) | |
54 | # define IOCON_INTPOL (1 << 1) | |
3539699c | 55 | # define IOCON_INTCC (1) |
e58b9e27 DB |
56 | #define MCP_GPPU 0x06 |
57 | #define MCP_INTF 0x07 | |
58 | #define MCP_INTCAP 0x08 | |
59 | #define MCP_GPIO 0x09 | |
60 | #define MCP_OLAT 0x0a | |
61 | ||
0b7bb77f PK |
62 | struct mcp23s08; |
63 | ||
e58b9e27 | 64 | struct mcp23s08 { |
e58b9e27 | 65 | u8 addr; |
a4e63554 | 66 | bool irq_active_high; |
3d84fdb3 | 67 | bool reg_shift; |
e58b9e27 | 68 | |
4e47f91b LP |
69 | u16 irq_rise; |
70 | u16 irq_fall; | |
71 | int irq; | |
72 | bool irq_controller; | |
8f38910b SR |
73 | int cached_gpio; |
74 | /* lock protects regmap access with bypass/cache flags */ | |
e58b9e27 | 75 | struct mutex lock; |
e58b9e27 DB |
76 | |
77 | struct gpio_chip chip; | |
78 | ||
3d84fdb3 SR |
79 | struct regmap *regmap; |
80 | struct device *dev; | |
82039d24 SR |
81 | |
82 | struct pinctrl_dev *pctldev; | |
83 | struct pinctrl_desc pinctrl_desc; | |
8f1cc3b1 DB |
84 | }; |
85 | ||
8f38910b SR |
86 | static const struct reg_default mcp23x08_defaults[] = { |
87 | {.reg = MCP_IODIR, .def = 0xff}, | |
88 | {.reg = MCP_IPOL, .def = 0x00}, | |
89 | {.reg = MCP_GPINTEN, .def = 0x00}, | |
90 | {.reg = MCP_DEFVAL, .def = 0x00}, | |
91 | {.reg = MCP_INTCON, .def = 0x00}, | |
92 | {.reg = MCP_IOCON, .def = 0x00}, | |
93 | {.reg = MCP_GPPU, .def = 0x00}, | |
94 | {.reg = MCP_OLAT, .def = 0x00}, | |
95 | }; | |
96 | ||
97 | static const struct regmap_range mcp23x08_volatile_range = { | |
98 | .range_min = MCP_INTF, | |
99 | .range_max = MCP_GPIO, | |
100 | }; | |
101 | ||
102 | static const struct regmap_access_table mcp23x08_volatile_table = { | |
103 | .yes_ranges = &mcp23x08_volatile_range, | |
104 | .n_yes_ranges = 1, | |
105 | }; | |
106 | ||
107 | static const struct regmap_range mcp23x08_precious_range = { | |
108 | .range_min = MCP_GPIO, | |
109 | .range_max = MCP_GPIO, | |
110 | }; | |
111 | ||
112 | static const struct regmap_access_table mcp23x08_precious_table = { | |
113 | .yes_ranges = &mcp23x08_precious_range, | |
114 | .n_yes_ranges = 1, | |
115 | }; | |
116 | ||
3d84fdb3 SR |
117 | static const struct regmap_config mcp23x08_regmap = { |
118 | .reg_bits = 8, | |
119 | .val_bits = 8, | |
752ad5e8 | 120 | |
3d84fdb3 | 121 | .reg_stride = 1, |
8f38910b SR |
122 | .volatile_table = &mcp23x08_volatile_table, |
123 | .precious_table = &mcp23x08_precious_table, | |
124 | .reg_defaults = mcp23x08_defaults, | |
125 | .num_reg_defaults = ARRAY_SIZE(mcp23x08_defaults), | |
126 | .cache_type = REGCACHE_FLAT, | |
3d84fdb3 | 127 | .max_register = MCP_OLAT, |
752ad5e8 PK |
128 | }; |
129 | ||
8f38910b SR |
130 | static const struct reg_default mcp23x16_defaults[] = { |
131 | {.reg = MCP_IODIR << 1, .def = 0xffff}, | |
132 | {.reg = MCP_IPOL << 1, .def = 0x0000}, | |
133 | {.reg = MCP_GPINTEN << 1, .def = 0x0000}, | |
134 | {.reg = MCP_DEFVAL << 1, .def = 0x0000}, | |
135 | {.reg = MCP_INTCON << 1, .def = 0x0000}, | |
136 | {.reg = MCP_IOCON << 1, .def = 0x0000}, | |
137 | {.reg = MCP_GPPU << 1, .def = 0x0000}, | |
138 | {.reg = MCP_OLAT << 1, .def = 0x0000}, | |
139 | }; | |
140 | ||
141 | static const struct regmap_range mcp23x16_volatile_range = { | |
142 | .range_min = MCP_INTF << 1, | |
143 | .range_max = MCP_GPIO << 1, | |
144 | }; | |
145 | ||
146 | static const struct regmap_access_table mcp23x16_volatile_table = { | |
147 | .yes_ranges = &mcp23x16_volatile_range, | |
148 | .n_yes_ranges = 1, | |
149 | }; | |
150 | ||
151 | static const struct regmap_range mcp23x16_precious_range = { | |
152 | .range_min = MCP_GPIO << 1, | |
153 | .range_max = MCP_GPIO << 1, | |
154 | }; | |
155 | ||
156 | static const struct regmap_access_table mcp23x16_precious_table = { | |
157 | .yes_ranges = &mcp23x16_precious_range, | |
158 | .n_yes_ranges = 1, | |
159 | }; | |
160 | ||
3d84fdb3 SR |
161 | static const struct regmap_config mcp23x17_regmap = { |
162 | .reg_bits = 8, | |
163 | .val_bits = 16, | |
752ad5e8 | 164 | |
3d84fdb3 SR |
165 | .reg_stride = 2, |
166 | .max_register = MCP_OLAT << 1, | |
8f38910b SR |
167 | .volatile_table = &mcp23x16_volatile_table, |
168 | .precious_table = &mcp23x16_precious_table, | |
169 | .reg_defaults = mcp23x16_defaults, | |
170 | .num_reg_defaults = ARRAY_SIZE(mcp23x16_defaults), | |
171 | .cache_type = REGCACHE_FLAT, | |
3d84fdb3 SR |
172 | .val_format_endian = REGMAP_ENDIAN_LITTLE, |
173 | }; | |
752ad5e8 | 174 | |
82039d24 SR |
175 | static int mcp_read(struct mcp23s08 *mcp, unsigned int reg, unsigned int *val) |
176 | { | |
177 | return regmap_read(mcp->regmap, reg << mcp->reg_shift, val); | |
178 | } | |
179 | ||
180 | static int mcp_write(struct mcp23s08 *mcp, unsigned int reg, unsigned int val) | |
181 | { | |
182 | return regmap_write(mcp->regmap, reg << mcp->reg_shift, val); | |
183 | } | |
184 | ||
8f38910b SR |
185 | static int mcp_set_mask(struct mcp23s08 *mcp, unsigned int reg, |
186 | unsigned int mask, bool enabled) | |
82039d24 SR |
187 | { |
188 | u16 val = enabled ? 0xffff : 0x0000; | |
82039d24 SR |
189 | return regmap_update_bits(mcp->regmap, reg << mcp->reg_shift, |
190 | mask, val); | |
191 | } | |
192 | ||
8f38910b SR |
193 | static int mcp_set_bit(struct mcp23s08 *mcp, unsigned int reg, |
194 | unsigned int pin, bool enabled) | |
82039d24 | 195 | { |
8f38910b SR |
196 | u16 mask = BIT(pin); |
197 | return mcp_set_mask(mcp, reg, mask, enabled); | |
82039d24 SR |
198 | } |
199 | ||
200 | static const struct pinctrl_pin_desc mcp23x08_pins[] = { | |
201 | PINCTRL_PIN(0, "gpio0"), | |
202 | PINCTRL_PIN(1, "gpio1"), | |
203 | PINCTRL_PIN(2, "gpio2"), | |
204 | PINCTRL_PIN(3, "gpio3"), | |
205 | PINCTRL_PIN(4, "gpio4"), | |
206 | PINCTRL_PIN(5, "gpio5"), | |
207 | PINCTRL_PIN(6, "gpio6"), | |
208 | PINCTRL_PIN(7, "gpio7"), | |
209 | }; | |
210 | ||
211 | static const struct pinctrl_pin_desc mcp23x17_pins[] = { | |
212 | PINCTRL_PIN(0, "gpio0"), | |
213 | PINCTRL_PIN(1, "gpio1"), | |
214 | PINCTRL_PIN(2, "gpio2"), | |
215 | PINCTRL_PIN(3, "gpio3"), | |
216 | PINCTRL_PIN(4, "gpio4"), | |
217 | PINCTRL_PIN(5, "gpio5"), | |
218 | PINCTRL_PIN(6, "gpio6"), | |
219 | PINCTRL_PIN(7, "gpio7"), | |
220 | PINCTRL_PIN(8, "gpio8"), | |
221 | PINCTRL_PIN(9, "gpio9"), | |
222 | PINCTRL_PIN(10, "gpio10"), | |
223 | PINCTRL_PIN(11, "gpio11"), | |
224 | PINCTRL_PIN(12, "gpio12"), | |
225 | PINCTRL_PIN(13, "gpio13"), | |
226 | PINCTRL_PIN(14, "gpio14"), | |
227 | PINCTRL_PIN(15, "gpio15"), | |
228 | }; | |
229 | ||
230 | static int mcp_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) | |
231 | { | |
232 | return 0; | |
233 | } | |
234 | ||
235 | static const char *mcp_pinctrl_get_group_name(struct pinctrl_dev *pctldev, | |
236 | unsigned int group) | |
237 | { | |
238 | return NULL; | |
239 | } | |
240 | ||
241 | static int mcp_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, | |
242 | unsigned int group, | |
243 | const unsigned int **pins, | |
244 | unsigned int *num_pins) | |
245 | { | |
246 | return -ENOTSUPP; | |
247 | } | |
248 | ||
249 | static const struct pinctrl_ops mcp_pinctrl_ops = { | |
250 | .get_groups_count = mcp_pinctrl_get_groups_count, | |
251 | .get_group_name = mcp_pinctrl_get_group_name, | |
252 | .get_group_pins = mcp_pinctrl_get_group_pins, | |
253 | #ifdef CONFIG_OF | |
254 | .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, | |
255 | .dt_free_map = pinconf_generic_dt_free_map, | |
256 | #endif | |
257 | }; | |
258 | ||
259 | static int mcp_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, | |
260 | unsigned long *config) | |
261 | { | |
262 | struct mcp23s08 *mcp = pinctrl_dev_get_drvdata(pctldev); | |
263 | enum pin_config_param param = pinconf_to_config_param(*config); | |
264 | unsigned int data, status; | |
265 | int ret; | |
266 | ||
267 | switch (param) { | |
268 | case PIN_CONFIG_BIAS_PULL_UP: | |
269 | ret = mcp_read(mcp, MCP_GPPU, &data); | |
270 | if (ret < 0) | |
271 | return ret; | |
272 | status = (data & BIT(pin)) ? 1 : 0; | |
273 | break; | |
274 | default: | |
275 | dev_err(mcp->dev, "Invalid config param %04x\n", param); | |
276 | return -ENOTSUPP; | |
277 | } | |
278 | ||
279 | *config = 0; | |
280 | ||
281 | return status ? 0 : -EINVAL; | |
282 | } | |
283 | ||
284 | static int mcp_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, | |
285 | unsigned long *configs, unsigned int num_configs) | |
286 | { | |
287 | struct mcp23s08 *mcp = pinctrl_dev_get_drvdata(pctldev); | |
288 | enum pin_config_param param; | |
289 | u32 arg, mask; | |
290 | u16 val; | |
291 | int ret = 0; | |
292 | int i; | |
293 | ||
294 | for (i = 0; i < num_configs; i++) { | |
295 | param = pinconf_to_config_param(configs[i]); | |
296 | arg = pinconf_to_config_argument(configs[i]); | |
297 | ||
298 | switch (param) { | |
299 | case PIN_CONFIG_BIAS_PULL_UP: | |
300 | val = arg ? 0xFFFF : 0x0000; | |
301 | mask = BIT(pin); | |
302 | ret = mcp_set_bit(mcp, MCP_GPPU, pin, arg); | |
303 | break; | |
304 | default: | |
305 | dev_err(mcp->dev, "Invalid config param %04x\n", param); | |
306 | return -ENOTSUPP; | |
307 | } | |
308 | } | |
309 | ||
310 | return ret; | |
311 | } | |
312 | ||
313 | static const struct pinconf_ops mcp_pinconf_ops = { | |
314 | .pin_config_get = mcp_pinconf_get, | |
315 | .pin_config_set = mcp_pinconf_set, | |
316 | .is_generic = true, | |
317 | }; | |
318 | ||
752ad5e8 PK |
319 | /*----------------------------------------------------------------------*/ |
320 | ||
d62b98f3 PK |
321 | #ifdef CONFIG_SPI_MASTER |
322 | ||
3d84fdb3 | 323 | static int mcp23sxx_spi_write(void *context, const void *data, size_t count) |
e58b9e27 | 324 | { |
3d84fdb3 SR |
325 | struct mcp23s08 *mcp = context; |
326 | struct spi_device *spi = to_spi_device(mcp->dev); | |
327 | struct spi_message m; | |
328 | struct spi_transfer t[2] = { { .tx_buf = &mcp->addr, .len = 1, }, | |
329 | { .tx_buf = data, .len = count, }, }; | |
e58b9e27 | 330 | |
3d84fdb3 SR |
331 | spi_message_init(&m); |
332 | spi_message_add_tail(&t[0], &m); | |
333 | spi_message_add_tail(&t[1], &m); | |
334 | ||
335 | return spi_sync(spi, &m); | |
e58b9e27 DB |
336 | } |
337 | ||
3d84fdb3 SR |
338 | static int mcp23sxx_spi_gather_write(void *context, |
339 | const void *reg, size_t reg_size, | |
340 | const void *val, size_t val_size) | |
e58b9e27 | 341 | { |
3d84fdb3 SR |
342 | struct mcp23s08 *mcp = context; |
343 | struct spi_device *spi = to_spi_device(mcp->dev); | |
344 | struct spi_message m; | |
345 | struct spi_transfer t[3] = { { .tx_buf = &mcp->addr, .len = 1, }, | |
346 | { .tx_buf = reg, .len = reg_size, }, | |
347 | { .tx_buf = val, .len = val_size, }, }; | |
348 | ||
349 | spi_message_init(&m); | |
350 | spi_message_add_tail(&t[0], &m); | |
351 | spi_message_add_tail(&t[1], &m); | |
352 | spi_message_add_tail(&t[2], &m); | |
353 | ||
354 | return spi_sync(spi, &m); | |
e58b9e27 DB |
355 | } |
356 | ||
3d84fdb3 SR |
357 | static int mcp23sxx_spi_read(void *context, const void *reg, size_t reg_size, |
358 | void *val, size_t val_size) | |
e58b9e27 | 359 | { |
3d84fdb3 SR |
360 | struct mcp23s08 *mcp = context; |
361 | struct spi_device *spi = to_spi_device(mcp->dev); | |
362 | u8 tx[2]; | |
e58b9e27 | 363 | |
3d84fdb3 | 364 | if (reg_size != 1) |
e58b9e27 | 365 | return -EINVAL; |
3d84fdb3 | 366 | |
e58b9e27 | 367 | tx[0] = mcp->addr | 0x01; |
3d84fdb3 | 368 | tx[1] = *((u8 *) reg); |
0b7bb77f | 369 | |
3d84fdb3 | 370 | return spi_write_then_read(spi, tx, sizeof(tx), val, val_size); |
0b7bb77f PK |
371 | } |
372 | ||
3d84fdb3 SR |
373 | static const struct regmap_bus mcp23sxx_spi_regmap = { |
374 | .write = mcp23sxx_spi_write, | |
375 | .gather_write = mcp23sxx_spi_gather_write, | |
376 | .read = mcp23sxx_spi_read, | |
377 | }; | |
0b7bb77f | 378 | |
3d84fdb3 | 379 | #endif /* CONFIG_SPI_MASTER */ |
0b7bb77f | 380 | |
3d84fdb3 | 381 | /*----------------------------------------------------------------------*/ |
0b7bb77f | 382 | |
3d84fdb3 SR |
383 | /* A given spi_device can represent up to eight mcp23sxx chips |
384 | * sharing the same chipselect but using different addresses | |
385 | * (e.g. chips #0 and #3 might be populated, but not #1 or $2). | |
386 | * Driver data holds all the per-chip data. | |
387 | */ | |
388 | struct mcp23s08_driver_data { | |
389 | unsigned ngpio; | |
390 | struct mcp23s08 *mcp[8]; | |
391 | struct mcp23s08 chip[]; | |
0b7bb77f PK |
392 | }; |
393 | ||
e58b9e27 DB |
394 | |
395 | static int mcp23s08_direction_input(struct gpio_chip *chip, unsigned offset) | |
396 | { | |
9e03cf0b | 397 | struct mcp23s08 *mcp = gpiochip_get_data(chip); |
e58b9e27 DB |
398 | int status; |
399 | ||
400 | mutex_lock(&mcp->lock); | |
8f38910b | 401 | status = mcp_set_bit(mcp, MCP_IODIR, offset, true); |
e58b9e27 | 402 | mutex_unlock(&mcp->lock); |
8f38910b | 403 | |
e58b9e27 DB |
404 | return status; |
405 | } | |
406 | ||
407 | static int mcp23s08_get(struct gpio_chip *chip, unsigned offset) | |
408 | { | |
9e03cf0b | 409 | struct mcp23s08 *mcp = gpiochip_get_data(chip); |
3d84fdb3 | 410 | int status, ret; |
e58b9e27 DB |
411 | |
412 | mutex_lock(&mcp->lock); | |
413 | ||
414 | /* REVISIT reading this clears any IRQ ... */ | |
3d84fdb3 SR |
415 | ret = mcp_read(mcp, MCP_GPIO, &status); |
416 | if (ret < 0) | |
e58b9e27 | 417 | status = 0; |
8f38910b | 418 | else |
e58b9e27 | 419 | status = !!(status & (1 << offset)); |
8f38910b SR |
420 | |
421 | mcp->cached_gpio = status; | |
422 | ||
e58b9e27 DB |
423 | mutex_unlock(&mcp->lock); |
424 | return status; | |
425 | } | |
426 | ||
8f38910b | 427 | static int __mcp23s08_set(struct mcp23s08 *mcp, unsigned mask, bool value) |
e58b9e27 | 428 | { |
8f38910b | 429 | return mcp_set_mask(mcp, MCP_OLAT, mask, value); |
e58b9e27 DB |
430 | } |
431 | ||
432 | static void mcp23s08_set(struct gpio_chip *chip, unsigned offset, int value) | |
433 | { | |
9e03cf0b | 434 | struct mcp23s08 *mcp = gpiochip_get_data(chip); |
8f38910b | 435 | unsigned mask = BIT(offset); |
e58b9e27 DB |
436 | |
437 | mutex_lock(&mcp->lock); | |
8f38910b | 438 | __mcp23s08_set(mcp, mask, !!value); |
e58b9e27 DB |
439 | mutex_unlock(&mcp->lock); |
440 | } | |
441 | ||
442 | static int | |
443 | mcp23s08_direction_output(struct gpio_chip *chip, unsigned offset, int value) | |
444 | { | |
9e03cf0b | 445 | struct mcp23s08 *mcp = gpiochip_get_data(chip); |
8f38910b | 446 | unsigned mask = BIT(offset); |
e58b9e27 DB |
447 | int status; |
448 | ||
449 | mutex_lock(&mcp->lock); | |
450 | status = __mcp23s08_set(mcp, mask, value); | |
451 | if (status == 0) { | |
8f38910b | 452 | status = mcp_set_mask(mcp, MCP_IODIR, mask, false); |
e58b9e27 DB |
453 | } |
454 | mutex_unlock(&mcp->lock); | |
455 | return status; | |
456 | } | |
457 | ||
4e47f91b LP |
458 | /*----------------------------------------------------------------------*/ |
459 | static irqreturn_t mcp23s08_irq(int irq, void *data) | |
460 | { | |
461 | struct mcp23s08 *mcp = data; | |
8f38910b | 462 | int intcap, intcon, intf, i, gpio, gpio_orig, intcap_mask, defval; |
4e47f91b | 463 | unsigned int child_irq; |
2cd29f23 RM |
464 | bool intf_set, intcap_changed, gpio_bit_changed, |
465 | defval_changed, gpio_set; | |
4e47f91b LP |
466 | |
467 | mutex_lock(&mcp->lock); | |
3d84fdb3 | 468 | if (mcp_read(mcp, MCP_INTF, &intf) < 0) { |
4e47f91b LP |
469 | mutex_unlock(&mcp->lock); |
470 | return IRQ_HANDLED; | |
471 | } | |
472 | ||
3d84fdb3 | 473 | if (mcp_read(mcp, MCP_INTCAP, &intcap) < 0) { |
4e47f91b LP |
474 | mutex_unlock(&mcp->lock); |
475 | return IRQ_HANDLED; | |
476 | } | |
477 | ||
8f38910b SR |
478 | if (mcp_read(mcp, MCP_INTCON, &intcon) < 0) { |
479 | mutex_unlock(&mcp->lock); | |
480 | return IRQ_HANDLED; | |
481 | } | |
482 | ||
483 | if (mcp_read(mcp, MCP_DEFVAL, &defval) < 0) { | |
484 | mutex_unlock(&mcp->lock); | |
485 | return IRQ_HANDLED; | |
486 | } | |
2cd29f23 RM |
487 | |
488 | /* This clears the interrupt(configurable on S18) */ | |
489 | if (mcp_read(mcp, MCP_GPIO, &gpio) < 0) { | |
490 | mutex_unlock(&mcp->lock); | |
491 | return IRQ_HANDLED; | |
492 | } | |
8f38910b SR |
493 | gpio_orig = mcp->cached_gpio; |
494 | mcp->cached_gpio = gpio; | |
4e47f91b LP |
495 | mutex_unlock(&mcp->lock); |
496 | ||
8f38910b | 497 | if (intf == 0) { |
2cd29f23 RM |
498 | /* There is no interrupt pending */ |
499 | return IRQ_HANDLED; | |
500 | } | |
501 | ||
502 | dev_dbg(mcp->chip.parent, | |
503 | "intcap 0x%04X intf 0x%04X gpio_orig 0x%04X gpio 0x%04X\n", | |
504 | intcap, intf, gpio_orig, gpio); | |
4e47f91b LP |
505 | |
506 | for (i = 0; i < mcp->chip.ngpio; i++) { | |
2cd29f23 RM |
507 | /* We must check all of the inputs on the chip, |
508 | * otherwise we may not notice a change on >=2 pins. | |
509 | * | |
510 | * On at least the mcp23s17, INTCAP is only updated | |
511 | * one byte at a time(INTCAPA and INTCAPB are | |
512 | * not written to at the same time - only on a per-bank | |
513 | * basis). | |
514 | * | |
515 | * INTF only contains the single bit that caused the | |
516 | * interrupt per-bank. On the mcp23s17, there is | |
517 | * INTFA and INTFB. If two pins are changed on the A | |
518 | * side at the same time, INTF will only have one bit | |
519 | * set. If one pin on the A side and one pin on the B | |
520 | * side are changed at the same time, INTF will have | |
521 | * two bits set. Thus, INTF can't be the only check | |
522 | * to see if the input has changed. | |
523 | */ | |
524 | ||
8f38910b | 525 | intf_set = intf & BIT(i); |
2cd29f23 RM |
526 | if (i < 8 && intf_set) |
527 | intcap_mask = 0x00FF; | |
528 | else if (i >= 8 && intf_set) | |
529 | intcap_mask = 0xFF00; | |
530 | else | |
531 | intcap_mask = 0x00; | |
532 | ||
533 | intcap_changed = (intcap_mask & | |
8f38910b | 534 | (intcap & BIT(i))) != |
2cd29f23 | 535 | (intcap_mask & (BIT(i) & gpio_orig)); |
8f38910b | 536 | gpio_set = BIT(i) & gpio; |
2cd29f23 | 537 | gpio_bit_changed = (BIT(i) & gpio_orig) != |
8f38910b SR |
538 | (BIT(i) & gpio); |
539 | defval_changed = (BIT(i) & intcon) && | |
540 | ((BIT(i) & gpio) != | |
541 | (BIT(i) & defval)); | |
2cd29f23 RM |
542 | |
543 | if (((gpio_bit_changed || intcap_changed) && | |
544 | (BIT(i) & mcp->irq_rise) && gpio_set) || | |
545 | ((gpio_bit_changed || intcap_changed) && | |
546 | (BIT(i) & mcp->irq_fall) && !gpio_set) || | |
547 | defval_changed) { | |
dad3d272 | 548 | child_irq = irq_find_mapping(mcp->chip.irqdomain, i); |
4e47f91b LP |
549 | handle_nested_irq(child_irq); |
550 | } | |
551 | } | |
552 | ||
553 | return IRQ_HANDLED; | |
554 | } | |
555 | ||
4e47f91b LP |
556 | static void mcp23s08_irq_mask(struct irq_data *data) |
557 | { | |
dad3d272 PR |
558 | struct gpio_chip *gc = irq_data_get_irq_chip_data(data); |
559 | struct mcp23s08 *mcp = gpiochip_get_data(gc); | |
4e47f91b LP |
560 | unsigned int pos = data->hwirq; |
561 | ||
8f38910b | 562 | mcp_set_bit(mcp, MCP_GPINTEN, pos, false); |
4e47f91b LP |
563 | } |
564 | ||
565 | static void mcp23s08_irq_unmask(struct irq_data *data) | |
566 | { | |
dad3d272 PR |
567 | struct gpio_chip *gc = irq_data_get_irq_chip_data(data); |
568 | struct mcp23s08 *mcp = gpiochip_get_data(gc); | |
4e47f91b LP |
569 | unsigned int pos = data->hwirq; |
570 | ||
8f38910b | 571 | mcp_set_bit(mcp, MCP_GPINTEN, pos, true); |
4e47f91b LP |
572 | } |
573 | ||
574 | static int mcp23s08_irq_set_type(struct irq_data *data, unsigned int type) | |
575 | { | |
dad3d272 PR |
576 | struct gpio_chip *gc = irq_data_get_irq_chip_data(data); |
577 | struct mcp23s08 *mcp = gpiochip_get_data(gc); | |
4e47f91b LP |
578 | unsigned int pos = data->hwirq; |
579 | int status = 0; | |
580 | ||
581 | if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) { | |
8f38910b | 582 | mcp_set_bit(mcp, MCP_INTCON, pos, false); |
4e47f91b LP |
583 | mcp->irq_rise |= BIT(pos); |
584 | mcp->irq_fall |= BIT(pos); | |
585 | } else if (type & IRQ_TYPE_EDGE_RISING) { | |
8f38910b | 586 | mcp_set_bit(mcp, MCP_INTCON, pos, false); |
4e47f91b LP |
587 | mcp->irq_rise |= BIT(pos); |
588 | mcp->irq_fall &= ~BIT(pos); | |
589 | } else if (type & IRQ_TYPE_EDGE_FALLING) { | |
8f38910b | 590 | mcp_set_bit(mcp, MCP_INTCON, pos, false); |
4e47f91b LP |
591 | mcp->irq_rise &= ~BIT(pos); |
592 | mcp->irq_fall |= BIT(pos); | |
16fe1ad2 | 593 | } else if (type & IRQ_TYPE_LEVEL_HIGH) { |
8f38910b SR |
594 | mcp_set_bit(mcp, MCP_INTCON, pos, true); |
595 | mcp_set_bit(mcp, MCP_DEFVAL, pos, false); | |
16fe1ad2 | 596 | } else if (type & IRQ_TYPE_LEVEL_LOW) { |
8f38910b SR |
597 | mcp_set_bit(mcp, MCP_INTCON, pos, true); |
598 | mcp_set_bit(mcp, MCP_DEFVAL, pos, true); | |
4e47f91b LP |
599 | } else |
600 | return -EINVAL; | |
601 | ||
602 | return status; | |
603 | } | |
604 | ||
605 | static void mcp23s08_irq_bus_lock(struct irq_data *data) | |
606 | { | |
dad3d272 PR |
607 | struct gpio_chip *gc = irq_data_get_irq_chip_data(data); |
608 | struct mcp23s08 *mcp = gpiochip_get_data(gc); | |
4e47f91b | 609 | |
8f38910b SR |
610 | mutex_lock(&mcp->lock); |
611 | regcache_cache_only(mcp->regmap, true); | |
4e47f91b LP |
612 | } |
613 | ||
614 | static void mcp23s08_irq_bus_unlock(struct irq_data *data) | |
615 | { | |
dad3d272 PR |
616 | struct gpio_chip *gc = irq_data_get_irq_chip_data(data); |
617 | struct mcp23s08 *mcp = gpiochip_get_data(gc); | |
4e47f91b | 618 | |
8f38910b SR |
619 | regcache_cache_only(mcp->regmap, false); |
620 | regcache_sync(mcp->regmap); | |
621 | ||
4e47f91b | 622 | mutex_unlock(&mcp->lock); |
4e47f91b LP |
623 | } |
624 | ||
4e47f91b LP |
625 | static struct irq_chip mcp23s08_irq_chip = { |
626 | .name = "gpio-mcp23xxx", | |
627 | .irq_mask = mcp23s08_irq_mask, | |
628 | .irq_unmask = mcp23s08_irq_unmask, | |
629 | .irq_set_type = mcp23s08_irq_set_type, | |
630 | .irq_bus_lock = mcp23s08_irq_bus_lock, | |
631 | .irq_bus_sync_unlock = mcp23s08_irq_bus_unlock, | |
4e47f91b LP |
632 | }; |
633 | ||
634 | static int mcp23s08_irq_setup(struct mcp23s08 *mcp) | |
635 | { | |
636 | struct gpio_chip *chip = &mcp->chip; | |
dad3d272 | 637 | int err; |
a4e63554 | 638 | unsigned long irqflags = IRQF_ONESHOT | IRQF_SHARED; |
4e47f91b | 639 | |
a4e63554 AS |
640 | if (mcp->irq_active_high) |
641 | irqflags |= IRQF_TRIGGER_HIGH; | |
642 | else | |
643 | irqflags |= IRQF_TRIGGER_LOW; | |
644 | ||
58383c78 LW |
645 | err = devm_request_threaded_irq(chip->parent, mcp->irq, NULL, |
646 | mcp23s08_irq, | |
647 | irqflags, dev_name(chip->parent), mcp); | |
4e47f91b | 648 | if (err != 0) { |
58383c78 | 649 | dev_err(chip->parent, "unable to request IRQ#%d: %d\n", |
4e47f91b LP |
650 | mcp->irq, err); |
651 | return err; | |
652 | } | |
653 | ||
d245b3f9 LW |
654 | err = gpiochip_irqchip_add_nested(chip, |
655 | &mcp23s08_irq_chip, | |
656 | 0, | |
657 | handle_simple_irq, | |
658 | IRQ_TYPE_NONE); | |
dad3d272 PR |
659 | if (err) { |
660 | dev_err(chip->parent, | |
661 | "could not connect irqchip to gpiochip: %d\n", err); | |
662 | return err; | |
4e47f91b | 663 | } |
4e47f91b | 664 | |
d245b3f9 LW |
665 | gpiochip_set_nested_irqchip(chip, |
666 | &mcp23s08_irq_chip, | |
667 | mcp->irq); | |
4e47f91b | 668 | |
dad3d272 | 669 | return 0; |
4e47f91b LP |
670 | } |
671 | ||
e58b9e27 DB |
672 | /*----------------------------------------------------------------------*/ |
673 | ||
674 | #ifdef CONFIG_DEBUG_FS | |
675 | ||
676 | #include <linux/seq_file.h> | |
677 | ||
8f38910b SR |
678 | /* |
679 | * This compares the chip's registers with the register | |
680 | * cache and corrects any incorrectly set register. This | |
681 | * can be used to fix state for MCP23xxx, that temporary | |
682 | * lost its power supply. | |
683 | */ | |
684 | #define MCP23S08_CONFIG_REGS 8 | |
685 | static int __check_mcp23s08_reg_cache(struct mcp23s08 *mcp) | |
686 | { | |
687 | int cached[MCP23S08_CONFIG_REGS]; | |
688 | int err = 0, i; | |
689 | ||
690 | /* read cached config registers */ | |
691 | for (i = 0; i < MCP23S08_CONFIG_REGS; i++) { | |
692 | err = mcp_read(mcp, i, &cached[i]); | |
693 | if (err) | |
694 | goto out; | |
695 | } | |
696 | ||
697 | regcache_cache_bypass(mcp->regmap, true); | |
698 | ||
699 | for (i = 0; i < MCP23S08_CONFIG_REGS; i++) { | |
700 | int uncached; | |
701 | err = mcp_read(mcp, i, &uncached); | |
702 | if (err) | |
703 | goto out; | |
704 | ||
705 | if (uncached != cached[i]) { | |
706 | dev_err(mcp->dev, "restoring reg 0x%02x from 0x%04x to 0x%04x (power-loss?)\n", | |
707 | i, uncached, cached[i]); | |
708 | mcp_write(mcp, i, cached[i]); | |
709 | } | |
710 | } | |
711 | ||
712 | out: | |
713 | if (err) | |
714 | dev_err(mcp->dev, "read error: reg=%02x, err=%d", i, err); | |
715 | regcache_cache_bypass(mcp->regmap, false); | |
716 | return err; | |
717 | } | |
718 | ||
e58b9e27 DB |
719 | /* |
720 | * This shows more info than the generic gpio dump code: | |
721 | * pullups, deglitching, open drain drive. | |
722 | */ | |
723 | static void mcp23s08_dbg_show(struct seq_file *s, struct gpio_chip *chip) | |
724 | { | |
725 | struct mcp23s08 *mcp; | |
726 | char bank; | |
1d1c1d9b | 727 | int t; |
e58b9e27 | 728 | unsigned mask; |
8f38910b | 729 | int iodir, gpio, gppu; |
e58b9e27 | 730 | |
9e03cf0b | 731 | mcp = gpiochip_get_data(chip); |
e58b9e27 DB |
732 | |
733 | /* NOTE: we only handle one bank for now ... */ | |
0b7bb77f | 734 | bank = '0' + ((mcp->addr >> 1) & 0x7); |
e58b9e27 DB |
735 | |
736 | mutex_lock(&mcp->lock); | |
8f38910b SR |
737 | |
738 | t = __check_mcp23s08_reg_cache(mcp); | |
739 | if (t) { | |
740 | seq_printf(s, " I/O Error\n"); | |
741 | goto done; | |
742 | } | |
743 | t = mcp_read(mcp, MCP_IODIR, &iodir); | |
744 | if (t) { | |
745 | seq_printf(s, " I/O Error\n"); | |
746 | goto done; | |
747 | } | |
748 | t = mcp_read(mcp, MCP_GPIO, &gpio); | |
749 | if (t) { | |
750 | seq_printf(s, " I/O Error\n"); | |
751 | goto done; | |
752 | } | |
753 | t = mcp_read(mcp, MCP_GPPU, &gppu); | |
754 | if (t) { | |
755 | seq_printf(s, " I/O Error\n"); | |
e58b9e27 DB |
756 | goto done; |
757 | } | |
758 | ||
8f38910b SR |
759 | for (t = 0, mask = BIT(0); t < chip->ngpio; t++, mask <<= 1) { |
760 | const char *label; | |
e58b9e27 DB |
761 | |
762 | label = gpiochip_is_requested(chip, t); | |
763 | if (!label) | |
764 | continue; | |
765 | ||
766 | seq_printf(s, " gpio-%-3d P%c.%d (%-12s) %s %s %s", | |
767 | chip->base + t, bank, t, label, | |
8f38910b SR |
768 | (iodir & mask) ? "in " : "out", |
769 | (gpio & mask) ? "hi" : "lo", | |
770 | (gppu & mask) ? "up" : " "); | |
e58b9e27 | 771 | /* NOTE: ignoring the irq-related registers */ |
33bc8411 | 772 | seq_puts(s, "\n"); |
e58b9e27 DB |
773 | } |
774 | done: | |
775 | mutex_unlock(&mcp->lock); | |
776 | } | |
777 | ||
778 | #else | |
779 | #define mcp23s08_dbg_show NULL | |
780 | #endif | |
781 | ||
782 | /*----------------------------------------------------------------------*/ | |
783 | ||
d62b98f3 | 784 | static int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev, |
4e47f91b | 785 | void *data, unsigned addr, unsigned type, |
3af0dbd5 | 786 | struct mcp23s08_platform_data *pdata, int cs) |
e58b9e27 | 787 | { |
3d84fdb3 | 788 | int status, ret; |
4e47f91b | 789 | bool mirror = false; |
e58b9e27 | 790 | |
e58b9e27 DB |
791 | mutex_init(&mcp->lock); |
792 | ||
3d84fdb3 | 793 | mcp->dev = dev; |
d62b98f3 | 794 | mcp->addr = addr; |
a4e63554 | 795 | mcp->irq_active_high = false; |
e58b9e27 | 796 | |
e58b9e27 DB |
797 | mcp->chip.direction_input = mcp23s08_direction_input; |
798 | mcp->chip.get = mcp23s08_get; | |
799 | mcp->chip.direction_output = mcp23s08_direction_output; | |
800 | mcp->chip.set = mcp23s08_set; | |
801 | mcp->chip.dbg_show = mcp23s08_dbg_show; | |
60f749f8 | 802 | #ifdef CONFIG_OF_GPIO |
97ddb1c8 LP |
803 | mcp->chip.of_gpio_n_cells = 2; |
804 | mcp->chip.of_node = dev->of_node; | |
805 | #endif | |
e58b9e27 | 806 | |
d62b98f3 PK |
807 | switch (type) { |
808 | #ifdef CONFIG_SPI_MASTER | |
809 | case MCP_TYPE_S08: | |
3d84fdb3 SR |
810 | mcp->regmap = devm_regmap_init(dev, &mcp23sxx_spi_regmap, mcp, |
811 | &mcp23x08_regmap); | |
812 | mcp->reg_shift = 0; | |
0b7bb77f PK |
813 | mcp->chip.ngpio = 8; |
814 | mcp->chip.label = "mcp23s08"; | |
d62b98f3 PK |
815 | break; |
816 | ||
817 | case MCP_TYPE_S17: | |
3d84fdb3 SR |
818 | mcp->regmap = devm_regmap_init(dev, &mcp23sxx_spi_regmap, mcp, |
819 | &mcp23x17_regmap); | |
820 | mcp->reg_shift = 1; | |
d62b98f3 PK |
821 | mcp->chip.ngpio = 16; |
822 | mcp->chip.label = "mcp23s17"; | |
823 | break; | |
28c5a41e PR |
824 | |
825 | case MCP_TYPE_S18: | |
3d84fdb3 SR |
826 | mcp->regmap = devm_regmap_init(dev, &mcp23sxx_spi_regmap, mcp, |
827 | &mcp23x17_regmap); | |
828 | mcp->reg_shift = 1; | |
28c5a41e PR |
829 | mcp->chip.ngpio = 16; |
830 | mcp->chip.label = "mcp23s18"; | |
831 | break; | |
d62b98f3 PK |
832 | #endif /* CONFIG_SPI_MASTER */ |
833 | ||
cbf24fad | 834 | #if IS_ENABLED(CONFIG_I2C) |
752ad5e8 | 835 | case MCP_TYPE_008: |
3d84fdb3 SR |
836 | mcp->regmap = devm_regmap_init_i2c(data, &mcp23x08_regmap); |
837 | mcp->reg_shift = 0; | |
752ad5e8 PK |
838 | mcp->chip.ngpio = 8; |
839 | mcp->chip.label = "mcp23008"; | |
840 | break; | |
841 | ||
842 | case MCP_TYPE_017: | |
3d84fdb3 SR |
843 | mcp->regmap = devm_regmap_init_i2c(data, &mcp23x17_regmap); |
844 | mcp->reg_shift = 1; | |
752ad5e8 PK |
845 | mcp->chip.ngpio = 16; |
846 | mcp->chip.label = "mcp23017"; | |
847 | break; | |
848 | #endif /* CONFIG_I2C */ | |
849 | ||
d62b98f3 PK |
850 | default: |
851 | dev_err(dev, "invalid device type (%d)\n", type); | |
852 | return -EINVAL; | |
0b7bb77f | 853 | } |
d62b98f3 | 854 | |
3d84fdb3 SR |
855 | if (IS_ERR(mcp->regmap)) |
856 | return PTR_ERR(mcp->regmap); | |
857 | ||
3af0dbd5 | 858 | mcp->chip.base = pdata->base; |
9fb1f39e | 859 | mcp->chip.can_sleep = true; |
58383c78 | 860 | mcp->chip.parent = dev; |
d72cbed0 | 861 | mcp->chip.owner = THIS_MODULE; |
e58b9e27 | 862 | |
8f1cc3b1 DB |
863 | /* verify MCP_IOCON.SEQOP = 0, so sequential reads work, |
864 | * and MCP_IOCON.HAEN = 1, so we work with all chips. | |
865 | */ | |
4e47f91b | 866 | |
3d84fdb3 SR |
867 | ret = mcp_read(mcp, MCP_IOCON, &status); |
868 | if (ret < 0) | |
e58b9e27 | 869 | goto fail; |
4e47f91b | 870 | |
3af0dbd5 | 871 | mcp->irq_controller = pdata->irq_controller; |
a4e63554 | 872 | if (mcp->irq && mcp->irq_controller) { |
170680ab | 873 | mcp->irq_active_high = |
58383c78 | 874 | of_property_read_bool(mcp->chip.parent->of_node, |
170680ab | 875 | "microchip,irq-active-high"); |
4e47f91b | 876 | |
28c5a41e | 877 | mirror = pdata->mirror; |
a4e63554 AS |
878 | } |
879 | ||
880 | if ((status & IOCON_SEQOP) || !(status & IOCON_HAEN) || mirror || | |
881 | mcp->irq_active_high) { | |
0b7bb77f PK |
882 | /* mcp23s17 has IOCON twice, make sure they are in sync */ |
883 | status &= ~(IOCON_SEQOP | (IOCON_SEQOP << 8)); | |
884 | status |= IOCON_HAEN | (IOCON_HAEN << 8); | |
a4e63554 AS |
885 | if (mcp->irq_active_high) |
886 | status |= IOCON_INTPOL | (IOCON_INTPOL << 8); | |
887 | else | |
888 | status &= ~(IOCON_INTPOL | (IOCON_INTPOL << 8)); | |
889 | ||
4e47f91b LP |
890 | if (mirror) |
891 | status |= IOCON_MIRROR | (IOCON_MIRROR << 8); | |
892 | ||
3539699c PR |
893 | if (type == MCP_TYPE_S18) |
894 | status |= IOCON_INTCC | (IOCON_INTCC << 8); | |
895 | ||
3d84fdb3 SR |
896 | ret = mcp_write(mcp, MCP_IOCON, status); |
897 | if (ret < 0) | |
e58b9e27 DB |
898 | goto fail; |
899 | } | |
900 | ||
d0e49dab | 901 | ret = devm_gpiochip_add_data(dev, &mcp->chip, mcp); |
3d84fdb3 | 902 | if (ret < 0) |
4e47f91b LP |
903 | goto fail; |
904 | ||
905 | if (mcp->irq && mcp->irq_controller) { | |
3d84fdb3 SR |
906 | ret = mcp23s08_irq_setup(mcp); |
907 | if (ret) | |
4e47f91b | 908 | goto fail; |
4e47f91b | 909 | } |
82039d24 SR |
910 | |
911 | mcp->pinctrl_desc.name = "mcp23xxx-pinctrl"; | |
912 | mcp->pinctrl_desc.pctlops = &mcp_pinctrl_ops; | |
913 | mcp->pinctrl_desc.confops = &mcp_pinconf_ops; | |
914 | mcp->pinctrl_desc.npins = mcp->chip.ngpio; | |
915 | if (mcp->pinctrl_desc.npins == 8) | |
916 | mcp->pinctrl_desc.pins = mcp23x08_pins; | |
917 | else if (mcp->pinctrl_desc.npins == 16) | |
918 | mcp->pinctrl_desc.pins = mcp23x17_pins; | |
919 | mcp->pinctrl_desc.owner = THIS_MODULE; | |
920 | ||
921 | mcp->pctldev = devm_pinctrl_register(dev, &mcp->pinctrl_desc, mcp); | |
922 | if (IS_ERR(mcp->pctldev)) { | |
923 | ret = PTR_ERR(mcp->pctldev); | |
924 | goto fail; | |
925 | } | |
926 | ||
8f1cc3b1 | 927 | fail: |
3d84fdb3 SR |
928 | if (ret < 0) |
929 | dev_dbg(dev, "can't setup chip %d, --> %d\n", addr, ret); | |
930 | return ret; | |
8f1cc3b1 DB |
931 | } |
932 | ||
752ad5e8 PK |
933 | /*----------------------------------------------------------------------*/ |
934 | ||
97ddb1c8 LP |
935 | #ifdef CONFIG_OF |
936 | #ifdef CONFIG_SPI_MASTER | |
ac791804 | 937 | static const struct of_device_id mcp23s08_spi_of_match[] = { |
97ddb1c8 | 938 | { |
45971686 LP |
939 | .compatible = "microchip,mcp23s08", |
940 | .data = (void *) MCP_TYPE_S08, | |
97ddb1c8 LP |
941 | }, |
942 | { | |
45971686 LP |
943 | .compatible = "microchip,mcp23s17", |
944 | .data = (void *) MCP_TYPE_S17, | |
945 | }, | |
28c5a41e PR |
946 | { |
947 | .compatible = "microchip,mcp23s18", | |
948 | .data = (void *) MCP_TYPE_S18, | |
949 | }, | |
45971686 LP |
950 | /* NOTE: The use of the mcp prefix is deprecated and will be removed. */ |
951 | { | |
952 | .compatible = "mcp,mcp23s08", | |
953 | .data = (void *) MCP_TYPE_S08, | |
954 | }, | |
955 | { | |
956 | .compatible = "mcp,mcp23s17", | |
957 | .data = (void *) MCP_TYPE_S17, | |
97ddb1c8 LP |
958 | }, |
959 | { }, | |
960 | }; | |
961 | MODULE_DEVICE_TABLE(of, mcp23s08_spi_of_match); | |
962 | #endif | |
963 | ||
964 | #if IS_ENABLED(CONFIG_I2C) | |
ac791804 | 965 | static const struct of_device_id mcp23s08_i2c_of_match[] = { |
97ddb1c8 | 966 | { |
45971686 LP |
967 | .compatible = "microchip,mcp23008", |
968 | .data = (void *) MCP_TYPE_008, | |
97ddb1c8 LP |
969 | }, |
970 | { | |
45971686 LP |
971 | .compatible = "microchip,mcp23017", |
972 | .data = (void *) MCP_TYPE_017, | |
973 | }, | |
974 | /* NOTE: The use of the mcp prefix is deprecated and will be removed. */ | |
975 | { | |
976 | .compatible = "mcp,mcp23008", | |
977 | .data = (void *) MCP_TYPE_008, | |
978 | }, | |
979 | { | |
980 | .compatible = "mcp,mcp23017", | |
981 | .data = (void *) MCP_TYPE_017, | |
97ddb1c8 LP |
982 | }, |
983 | { }, | |
984 | }; | |
985 | MODULE_DEVICE_TABLE(of, mcp23s08_i2c_of_match); | |
986 | #endif | |
987 | #endif /* CONFIG_OF */ | |
988 | ||
989 | ||
cbf24fad | 990 | #if IS_ENABLED(CONFIG_I2C) |
752ad5e8 | 991 | |
3836309d | 992 | static int mcp230xx_probe(struct i2c_client *client, |
752ad5e8 PK |
993 | const struct i2c_device_id *id) |
994 | { | |
3af0dbd5 | 995 | struct mcp23s08_platform_data *pdata, local_pdata; |
752ad5e8 | 996 | struct mcp23s08 *mcp; |
3af0dbd5 | 997 | int status; |
97ddb1c8 LP |
998 | const struct of_device_id *match; |
999 | ||
1000 | match = of_match_device(of_match_ptr(mcp23s08_i2c_of_match), | |
1001 | &client->dev); | |
3af0dbd5 SZ |
1002 | if (match) { |
1003 | pdata = &local_pdata; | |
1004 | pdata->base = -1; | |
3af0dbd5 SZ |
1005 | pdata->irq_controller = of_property_read_bool( |
1006 | client->dev.of_node, | |
1007 | "interrupt-controller"); | |
1008 | pdata->mirror = of_property_read_bool(client->dev.of_node, | |
1009 | "microchip,irq-mirror"); | |
97ddb1c8 | 1010 | } else { |
3af0dbd5 | 1011 | pdata = dev_get_platdata(&client->dev); |
b184c388 SZ |
1012 | if (!pdata) { |
1013 | pdata = devm_kzalloc(&client->dev, | |
1014 | sizeof(struct mcp23s08_platform_data), | |
1015 | GFP_KERNEL); | |
aaf2b3af IY |
1016 | if (!pdata) |
1017 | return -ENOMEM; | |
b184c388 | 1018 | pdata->base = -1; |
97ddb1c8 | 1019 | } |
752ad5e8 PK |
1020 | } |
1021 | ||
2f98e78b | 1022 | mcp = devm_kzalloc(&client->dev, sizeof(*mcp), GFP_KERNEL); |
752ad5e8 PK |
1023 | if (!mcp) |
1024 | return -ENOMEM; | |
1025 | ||
4e47f91b | 1026 | mcp->irq = client->irq; |
752ad5e8 | 1027 | status = mcp23s08_probe_one(mcp, &client->dev, client, client->addr, |
3af0dbd5 | 1028 | id->driver_data, pdata, 0); |
752ad5e8 | 1029 | if (status) |
2f98e78b | 1030 | return status; |
752ad5e8 PK |
1031 | |
1032 | i2c_set_clientdata(client, mcp); | |
1033 | ||
1034 | return 0; | |
752ad5e8 PK |
1035 | } |
1036 | ||
752ad5e8 PK |
1037 | static const struct i2c_device_id mcp230xx_id[] = { |
1038 | { "mcp23008", MCP_TYPE_008 }, | |
1039 | { "mcp23017", MCP_TYPE_017 }, | |
1040 | { }, | |
1041 | }; | |
1042 | MODULE_DEVICE_TABLE(i2c, mcp230xx_id); | |
1043 | ||
1044 | static struct i2c_driver mcp230xx_driver = { | |
1045 | .driver = { | |
1046 | .name = "mcp230xx", | |
97ddb1c8 | 1047 | .of_match_table = of_match_ptr(mcp23s08_i2c_of_match), |
752ad5e8 PK |
1048 | }, |
1049 | .probe = mcp230xx_probe, | |
752ad5e8 PK |
1050 | .id_table = mcp230xx_id, |
1051 | }; | |
1052 | ||
1053 | static int __init mcp23s08_i2c_init(void) | |
1054 | { | |
1055 | return i2c_add_driver(&mcp230xx_driver); | |
1056 | } | |
1057 | ||
1058 | static void mcp23s08_i2c_exit(void) | |
1059 | { | |
1060 | i2c_del_driver(&mcp230xx_driver); | |
1061 | } | |
1062 | ||
1063 | #else | |
1064 | ||
1065 | static int __init mcp23s08_i2c_init(void) { return 0; } | |
1066 | static void mcp23s08_i2c_exit(void) { } | |
1067 | ||
1068 | #endif /* CONFIG_I2C */ | |
1069 | ||
1070 | /*----------------------------------------------------------------------*/ | |
1071 | ||
d62b98f3 PK |
1072 | #ifdef CONFIG_SPI_MASTER |
1073 | ||
8f1cc3b1 DB |
1074 | static int mcp23s08_probe(struct spi_device *spi) |
1075 | { | |
3af0dbd5 | 1076 | struct mcp23s08_platform_data *pdata, local_pdata; |
8f1cc3b1 | 1077 | unsigned addr; |
596a1c5f | 1078 | int chips = 0; |
8f1cc3b1 | 1079 | struct mcp23s08_driver_data *data; |
0b7bb77f | 1080 | int status, type; |
3af0dbd5 | 1081 | unsigned ngpio = 0; |
97ddb1c8 LP |
1082 | const struct of_device_id *match; |
1083 | u32 spi_present_mask = 0; | |
1084 | ||
1085 | match = of_match_device(of_match_ptr(mcp23s08_spi_of_match), &spi->dev); | |
1086 | if (match) { | |
de755c33 | 1087 | type = (int)(uintptr_t)match->data; |
97ddb1c8 | 1088 | status = of_property_read_u32(spi->dev.of_node, |
45971686 | 1089 | "microchip,spi-present-mask", &spi_present_mask); |
97ddb1c8 | 1090 | if (status) { |
45971686 LP |
1091 | status = of_property_read_u32(spi->dev.of_node, |
1092 | "mcp,spi-present-mask", &spi_present_mask); | |
1093 | if (status) { | |
1094 | dev_err(&spi->dev, | |
1095 | "DT has no spi-present-mask\n"); | |
1096 | return -ENODEV; | |
1097 | } | |
97ddb1c8 LP |
1098 | } |
1099 | if ((spi_present_mask <= 0) || (spi_present_mask >= 256)) { | |
1100 | dev_err(&spi->dev, "invalid spi-present-mask\n"); | |
1101 | return -ENODEV; | |
1102 | } | |
8f1cc3b1 | 1103 | |
3af0dbd5 SZ |
1104 | pdata = &local_pdata; |
1105 | pdata->base = -1; | |
99e4b98d | 1106 | for (addr = 0; addr < ARRAY_SIZE(pdata->chip); addr++) { |
3e3bed91 MS |
1107 | if (spi_present_mask & (1 << addr)) |
1108 | chips++; | |
99e4b98d | 1109 | } |
3af0dbd5 SZ |
1110 | pdata->irq_controller = of_property_read_bool( |
1111 | spi->dev.of_node, | |
1112 | "interrupt-controller"); | |
1113 | pdata->mirror = of_property_read_bool(spi->dev.of_node, | |
1114 | "microchip,irq-mirror"); | |
97ddb1c8 LP |
1115 | } else { |
1116 | type = spi_get_device_id(spi)->driver_data; | |
e56aee18 | 1117 | pdata = dev_get_platdata(&spi->dev); |
b184c388 SZ |
1118 | if (!pdata) { |
1119 | pdata = devm_kzalloc(&spi->dev, | |
1120 | sizeof(struct mcp23s08_platform_data), | |
1121 | GFP_KERNEL); | |
1122 | pdata->base = -1; | |
0b7bb77f | 1123 | } |
97ddb1c8 LP |
1124 | |
1125 | for (addr = 0; addr < ARRAY_SIZE(pdata->chip); addr++) { | |
1126 | if (!pdata->chip[addr].is_present) | |
1127 | continue; | |
1128 | chips++; | |
1129 | if ((type == MCP_TYPE_S08) && (addr > 3)) { | |
1130 | dev_err(&spi->dev, | |
1131 | "mcp23s08 only supports address 0..3\n"); | |
1132 | return -EINVAL; | |
1133 | } | |
1134 | spi_present_mask |= 1 << addr; | |
97ddb1c8 | 1135 | } |
8f1cc3b1 | 1136 | } |
8f1cc3b1 | 1137 | |
99e4b98d MW |
1138 | if (!chips) |
1139 | return -ENODEV; | |
1140 | ||
7898b31e VB |
1141 | data = devm_kzalloc(&spi->dev, |
1142 | sizeof(*data) + chips * sizeof(struct mcp23s08), | |
1143 | GFP_KERNEL); | |
8f1cc3b1 DB |
1144 | if (!data) |
1145 | return -ENOMEM; | |
7898b31e | 1146 | |
8f1cc3b1 DB |
1147 | spi_set_drvdata(spi, data); |
1148 | ||
0b7bb77f | 1149 | for (addr = 0; addr < ARRAY_SIZE(pdata->chip); addr++) { |
97ddb1c8 | 1150 | if (!(spi_present_mask & (1 << addr))) |
8f1cc3b1 DB |
1151 | continue; |
1152 | chips--; | |
1153 | data->mcp[addr] = &data->chip[chips]; | |
a231b88c | 1154 | data->mcp[addr]->irq = spi->irq; |
d62b98f3 | 1155 | status = mcp23s08_probe_one(data->mcp[addr], &spi->dev, spi, |
3af0dbd5 SZ |
1156 | 0x40 | (addr << 1), type, pdata, |
1157 | addr); | |
8f1cc3b1 | 1158 | if (status < 0) |
d0e49dab | 1159 | return status; |
0b7bb77f | 1160 | |
3af0dbd5 | 1161 | if (pdata->base != -1) |
28c5a41e PR |
1162 | pdata->base += data->mcp[addr]->chip.ngpio; |
1163 | ngpio += data->mcp[addr]->chip.ngpio; | |
8f1cc3b1 | 1164 | } |
97ddb1c8 | 1165 | data->ngpio = ngpio; |
e58b9e27 DB |
1166 | |
1167 | /* NOTE: these chips have a relatively sane IRQ framework, with | |
1168 | * per-signal masking and level/edge triggering. It's not yet | |
1169 | * handled here... | |
1170 | */ | |
1171 | ||
e58b9e27 | 1172 | return 0; |
e58b9e27 DB |
1173 | } |
1174 | ||
0b7bb77f PK |
1175 | static const struct spi_device_id mcp23s08_ids[] = { |
1176 | { "mcp23s08", MCP_TYPE_S08 }, | |
1177 | { "mcp23s17", MCP_TYPE_S17 }, | |
28c5a41e | 1178 | { "mcp23s18", MCP_TYPE_S18 }, |
0b7bb77f PK |
1179 | { }, |
1180 | }; | |
1181 | MODULE_DEVICE_TABLE(spi, mcp23s08_ids); | |
1182 | ||
e58b9e27 DB |
1183 | static struct spi_driver mcp23s08_driver = { |
1184 | .probe = mcp23s08_probe, | |
0b7bb77f | 1185 | .id_table = mcp23s08_ids, |
e58b9e27 DB |
1186 | .driver = { |
1187 | .name = "mcp23s08", | |
97ddb1c8 | 1188 | .of_match_table = of_match_ptr(mcp23s08_spi_of_match), |
e58b9e27 DB |
1189 | }, |
1190 | }; | |
1191 | ||
d62b98f3 PK |
1192 | static int __init mcp23s08_spi_init(void) |
1193 | { | |
1194 | return spi_register_driver(&mcp23s08_driver); | |
1195 | } | |
1196 | ||
1197 | static void mcp23s08_spi_exit(void) | |
1198 | { | |
1199 | spi_unregister_driver(&mcp23s08_driver); | |
1200 | } | |
1201 | ||
1202 | #else | |
1203 | ||
1204 | static int __init mcp23s08_spi_init(void) { return 0; } | |
1205 | static void mcp23s08_spi_exit(void) { } | |
1206 | ||
1207 | #endif /* CONFIG_SPI_MASTER */ | |
1208 | ||
e58b9e27 DB |
1209 | /*----------------------------------------------------------------------*/ |
1210 | ||
1211 | static int __init mcp23s08_init(void) | |
1212 | { | |
752ad5e8 PK |
1213 | int ret; |
1214 | ||
1215 | ret = mcp23s08_spi_init(); | |
1216 | if (ret) | |
1217 | goto spi_fail; | |
1218 | ||
1219 | ret = mcp23s08_i2c_init(); | |
1220 | if (ret) | |
1221 | goto i2c_fail; | |
1222 | ||
1223 | return 0; | |
1224 | ||
1225 | i2c_fail: | |
1226 | mcp23s08_spi_exit(); | |
1227 | spi_fail: | |
1228 | return ret; | |
e58b9e27 | 1229 | } |
752ad5e8 | 1230 | /* register after spi/i2c postcore initcall and before |
673c0c00 DB |
1231 | * subsys initcalls that may rely on these GPIOs |
1232 | */ | |
1233 | subsys_initcall(mcp23s08_init); | |
e58b9e27 DB |
1234 | |
1235 | static void __exit mcp23s08_exit(void) | |
1236 | { | |
d62b98f3 | 1237 | mcp23s08_spi_exit(); |
752ad5e8 | 1238 | mcp23s08_i2c_exit(); |
e58b9e27 DB |
1239 | } |
1240 | module_exit(mcp23s08_exit); | |
1241 | ||
1242 | MODULE_LICENSE("GPL"); |