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f365be09 BA |
1 | /* |
2 | * Copyright (c) 2013, Sony Mobile Communications AB. | |
3 | * Copyright (c) 2013, The Linux Foundation. All rights reserved. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 and | |
7 | * only version 2 as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | */ | |
14 | ||
15 | #include <linux/err.h> | |
16 | #include <linux/irqdomain.h> | |
17 | #include <linux/io.h> | |
18 | #include <linux/module.h> | |
19 | #include <linux/of.h> | |
20 | #include <linux/platform_device.h> | |
21 | #include <linux/pinctrl/machine.h> | |
22 | #include <linux/pinctrl/pinctrl.h> | |
23 | #include <linux/pinctrl/pinmux.h> | |
24 | #include <linux/pinctrl/pinconf.h> | |
25 | #include <linux/pinctrl/pinconf-generic.h> | |
26 | #include <linux/slab.h> | |
27 | #include <linux/gpio.h> | |
28 | #include <linux/interrupt.h> | |
29 | #include <linux/irq.h> | |
30 | #include <linux/irqchip/chained_irq.h> | |
f365be09 BA |
31 | #include <linux/spinlock.h> |
32 | ||
33 | #include "core.h" | |
34 | #include "pinconf.h" | |
35 | #include "pinctrl-msm.h" | |
36 | #include "pinctrl-utils.h" | |
37 | ||
408e3c66 BA |
38 | #define MAX_NR_GPIO 300 |
39 | ||
f365be09 BA |
40 | /** |
41 | * struct msm_pinctrl - state for a pinctrl-msm device | |
42 | * @dev: device handle. | |
43 | * @pctrl: pinctrl handle. | |
44 | * @domain: irqdomain handle. | |
45 | * @chip: gpiochip handle. | |
46 | * @irq: parent irq for the TLMM irq_chip. | |
47 | * @lock: Spinlock to protect register resources as well | |
48 | * as msm_pinctrl data structures. | |
49 | * @enabled_irqs: Bitmap of currently enabled irqs. | |
50 | * @dual_edge_irqs: Bitmap of irqs that need sw emulated dual edge | |
51 | * detection. | |
f365be09 BA |
52 | * @soc; Reference to soc_data of platform specific data. |
53 | * @regs: Base address for the TLMM register map. | |
54 | */ | |
55 | struct msm_pinctrl { | |
56 | struct device *dev; | |
57 | struct pinctrl_dev *pctrl; | |
58 | struct irq_domain *domain; | |
59 | struct gpio_chip chip; | |
f393e489 | 60 | int irq; |
f365be09 BA |
61 | |
62 | spinlock_t lock; | |
63 | ||
408e3c66 BA |
64 | DECLARE_BITMAP(dual_edge_irqs, MAX_NR_GPIO); |
65 | DECLARE_BITMAP(enabled_irqs, MAX_NR_GPIO); | |
f365be09 BA |
66 | |
67 | const struct msm_pinctrl_soc_data *soc; | |
68 | void __iomem *regs; | |
69 | }; | |
70 | ||
71 | static int msm_get_groups_count(struct pinctrl_dev *pctldev) | |
72 | { | |
73 | struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
74 | ||
75 | return pctrl->soc->ngroups; | |
76 | } | |
77 | ||
78 | static const char *msm_get_group_name(struct pinctrl_dev *pctldev, | |
79 | unsigned group) | |
80 | { | |
81 | struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
82 | ||
83 | return pctrl->soc->groups[group].name; | |
84 | } | |
85 | ||
86 | static int msm_get_group_pins(struct pinctrl_dev *pctldev, | |
87 | unsigned group, | |
88 | const unsigned **pins, | |
89 | unsigned *num_pins) | |
90 | { | |
91 | struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
92 | ||
93 | *pins = pctrl->soc->groups[group].pins; | |
94 | *num_pins = pctrl->soc->groups[group].npins; | |
95 | return 0; | |
96 | } | |
97 | ||
1f2b2398 | 98 | static const struct pinctrl_ops msm_pinctrl_ops = { |
f365be09 BA |
99 | .get_groups_count = msm_get_groups_count, |
100 | .get_group_name = msm_get_group_name, | |
101 | .get_group_pins = msm_get_group_pins, | |
102 | .dt_node_to_map = pinconf_generic_dt_node_to_map_group, | |
103 | .dt_free_map = pinctrl_utils_dt_free_map, | |
104 | }; | |
105 | ||
106 | static int msm_get_functions_count(struct pinctrl_dev *pctldev) | |
107 | { | |
108 | struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
109 | ||
110 | return pctrl->soc->nfunctions; | |
111 | } | |
112 | ||
113 | static const char *msm_get_function_name(struct pinctrl_dev *pctldev, | |
114 | unsigned function) | |
115 | { | |
116 | struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
117 | ||
118 | return pctrl->soc->functions[function].name; | |
119 | } | |
120 | ||
121 | static int msm_get_function_groups(struct pinctrl_dev *pctldev, | |
122 | unsigned function, | |
123 | const char * const **groups, | |
124 | unsigned * const num_groups) | |
125 | { | |
126 | struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
127 | ||
128 | *groups = pctrl->soc->functions[function].groups; | |
129 | *num_groups = pctrl->soc->functions[function].ngroups; | |
130 | return 0; | |
131 | } | |
132 | ||
133 | static int msm_pinmux_enable(struct pinctrl_dev *pctldev, | |
134 | unsigned function, | |
135 | unsigned group) | |
136 | { | |
137 | struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
138 | const struct msm_pingroup *g; | |
139 | unsigned long flags; | |
140 | u32 val; | |
141 | int i; | |
142 | ||
143 | g = &pctrl->soc->groups[group]; | |
144 | ||
145 | if (WARN_ON(g->mux_bit < 0)) | |
146 | return -EINVAL; | |
147 | ||
148 | for (i = 0; i < ARRAY_SIZE(g->funcs); i++) { | |
149 | if (g->funcs[i] == function) | |
150 | break; | |
151 | } | |
152 | ||
153 | if (WARN_ON(i == ARRAY_SIZE(g->funcs))) | |
154 | return -EINVAL; | |
155 | ||
156 | spin_lock_irqsave(&pctrl->lock, flags); | |
157 | ||
158 | val = readl(pctrl->regs + g->ctl_reg); | |
159 | val &= ~(0x7 << g->mux_bit); | |
160 | val |= i << g->mux_bit; | |
161 | writel(val, pctrl->regs + g->ctl_reg); | |
162 | ||
163 | spin_unlock_irqrestore(&pctrl->lock, flags); | |
164 | ||
165 | return 0; | |
166 | } | |
167 | ||
168 | static void msm_pinmux_disable(struct pinctrl_dev *pctldev, | |
169 | unsigned function, | |
170 | unsigned group) | |
171 | { | |
172 | struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
173 | const struct msm_pingroup *g; | |
174 | unsigned long flags; | |
175 | u32 val; | |
176 | ||
177 | g = &pctrl->soc->groups[group]; | |
178 | ||
179 | if (WARN_ON(g->mux_bit < 0)) | |
180 | return; | |
181 | ||
182 | spin_lock_irqsave(&pctrl->lock, flags); | |
183 | ||
184 | /* Clear the mux bits to select gpio mode */ | |
185 | val = readl(pctrl->regs + g->ctl_reg); | |
186 | val &= ~(0x7 << g->mux_bit); | |
187 | writel(val, pctrl->regs + g->ctl_reg); | |
188 | ||
189 | spin_unlock_irqrestore(&pctrl->lock, flags); | |
190 | } | |
191 | ||
1f2b2398 | 192 | static const struct pinmux_ops msm_pinmux_ops = { |
f365be09 BA |
193 | .get_functions_count = msm_get_functions_count, |
194 | .get_function_name = msm_get_function_name, | |
195 | .get_function_groups = msm_get_function_groups, | |
196 | .enable = msm_pinmux_enable, | |
197 | .disable = msm_pinmux_disable, | |
198 | }; | |
199 | ||
200 | static int msm_config_reg(struct msm_pinctrl *pctrl, | |
201 | const struct msm_pingroup *g, | |
202 | unsigned param, | |
f365be09 BA |
203 | unsigned *mask, |
204 | unsigned *bit) | |
205 | { | |
206 | switch (param) { | |
207 | case PIN_CONFIG_BIAS_DISABLE: | |
f365be09 | 208 | case PIN_CONFIG_BIAS_PULL_DOWN: |
f365be09 | 209 | case PIN_CONFIG_BIAS_PULL_UP: |
f365be09 BA |
210 | *bit = g->pull_bit; |
211 | *mask = 3; | |
212 | break; | |
213 | case PIN_CONFIG_DRIVE_STRENGTH: | |
f365be09 BA |
214 | *bit = g->drv_bit; |
215 | *mask = 7; | |
216 | break; | |
ed118a5f | 217 | case PIN_CONFIG_OUTPUT: |
ed118a5f BA |
218 | *bit = g->oe_bit; |
219 | *mask = 1; | |
220 | break; | |
f365be09 BA |
221 | default: |
222 | dev_err(pctrl->dev, "Invalid config param %04x\n", param); | |
223 | return -ENOTSUPP; | |
224 | } | |
225 | ||
f365be09 BA |
226 | return 0; |
227 | } | |
228 | ||
229 | static int msm_config_get(struct pinctrl_dev *pctldev, | |
230 | unsigned int pin, | |
231 | unsigned long *config) | |
232 | { | |
233 | dev_err(pctldev->dev, "pin_config_set op not supported\n"); | |
234 | return -ENOTSUPP; | |
235 | } | |
236 | ||
237 | static int msm_config_set(struct pinctrl_dev *pctldev, unsigned int pin, | |
238 | unsigned long *configs, unsigned num_configs) | |
239 | { | |
240 | dev_err(pctldev->dev, "pin_config_set op not supported\n"); | |
241 | return -ENOTSUPP; | |
242 | } | |
243 | ||
244 | #define MSM_NO_PULL 0 | |
245 | #define MSM_PULL_DOWN 1 | |
246 | #define MSM_PULL_UP 3 | |
247 | ||
7cc34e2e SB |
248 | static unsigned msm_regval_to_drive(u32 val) |
249 | { | |
250 | return (val + 1) * 2; | |
251 | } | |
f365be09 BA |
252 | |
253 | static int msm_config_group_get(struct pinctrl_dev *pctldev, | |
254 | unsigned int group, | |
255 | unsigned long *config) | |
256 | { | |
257 | const struct msm_pingroup *g; | |
258 | struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
259 | unsigned param = pinconf_to_config_param(*config); | |
260 | unsigned mask; | |
261 | unsigned arg; | |
262 | unsigned bit; | |
f365be09 BA |
263 | int ret; |
264 | u32 val; | |
265 | ||
266 | g = &pctrl->soc->groups[group]; | |
267 | ||
051a58b4 | 268 | ret = msm_config_reg(pctrl, g, param, &mask, &bit); |
f365be09 BA |
269 | if (ret < 0) |
270 | return ret; | |
271 | ||
051a58b4 | 272 | val = readl(pctrl->regs + g->ctl_reg); |
f365be09 BA |
273 | arg = (val >> bit) & mask; |
274 | ||
275 | /* Convert register value to pinconf value */ | |
276 | switch (param) { | |
277 | case PIN_CONFIG_BIAS_DISABLE: | |
278 | arg = arg == MSM_NO_PULL; | |
279 | break; | |
280 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
281 | arg = arg == MSM_PULL_DOWN; | |
282 | break; | |
283 | case PIN_CONFIG_BIAS_PULL_UP: | |
284 | arg = arg == MSM_PULL_UP; | |
285 | break; | |
286 | case PIN_CONFIG_DRIVE_STRENGTH: | |
7cc34e2e | 287 | arg = msm_regval_to_drive(arg); |
f365be09 | 288 | break; |
ed118a5f BA |
289 | case PIN_CONFIG_OUTPUT: |
290 | /* Pin is not output */ | |
291 | if (!arg) | |
292 | return -EINVAL; | |
293 | ||
294 | val = readl(pctrl->regs + g->io_reg); | |
295 | arg = !!(val & BIT(g->in_bit)); | |
296 | break; | |
f365be09 BA |
297 | default: |
298 | dev_err(pctrl->dev, "Unsupported config parameter: %x\n", | |
299 | param); | |
300 | return -EINVAL; | |
301 | } | |
302 | ||
303 | *config = pinconf_to_config_packed(param, arg); | |
304 | ||
305 | return 0; | |
306 | } | |
307 | ||
308 | static int msm_config_group_set(struct pinctrl_dev *pctldev, | |
309 | unsigned group, | |
310 | unsigned long *configs, | |
311 | unsigned num_configs) | |
312 | { | |
313 | const struct msm_pingroup *g; | |
314 | struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
315 | unsigned long flags; | |
316 | unsigned param; | |
317 | unsigned mask; | |
318 | unsigned arg; | |
319 | unsigned bit; | |
f365be09 BA |
320 | int ret; |
321 | u32 val; | |
322 | int i; | |
323 | ||
324 | g = &pctrl->soc->groups[group]; | |
325 | ||
326 | for (i = 0; i < num_configs; i++) { | |
327 | param = pinconf_to_config_param(configs[i]); | |
328 | arg = pinconf_to_config_argument(configs[i]); | |
329 | ||
051a58b4 | 330 | ret = msm_config_reg(pctrl, g, param, &mask, &bit); |
f365be09 BA |
331 | if (ret < 0) |
332 | return ret; | |
333 | ||
334 | /* Convert pinconf values to register values */ | |
335 | switch (param) { | |
336 | case PIN_CONFIG_BIAS_DISABLE: | |
337 | arg = MSM_NO_PULL; | |
338 | break; | |
339 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
340 | arg = MSM_PULL_DOWN; | |
341 | break; | |
342 | case PIN_CONFIG_BIAS_PULL_UP: | |
343 | arg = MSM_PULL_UP; | |
344 | break; | |
345 | case PIN_CONFIG_DRIVE_STRENGTH: | |
346 | /* Check for invalid values */ | |
7cc34e2e | 347 | if (arg > 16 || arg < 2 || (arg % 2) != 0) |
f365be09 BA |
348 | arg = -1; |
349 | else | |
7cc34e2e | 350 | arg = (arg / 2) - 1; |
f365be09 | 351 | break; |
ed118a5f BA |
352 | case PIN_CONFIG_OUTPUT: |
353 | /* set output value */ | |
354 | spin_lock_irqsave(&pctrl->lock, flags); | |
355 | val = readl(pctrl->regs + g->io_reg); | |
356 | if (arg) | |
357 | val |= BIT(g->out_bit); | |
358 | else | |
359 | val &= ~BIT(g->out_bit); | |
360 | writel(val, pctrl->regs + g->io_reg); | |
361 | spin_unlock_irqrestore(&pctrl->lock, flags); | |
362 | ||
363 | /* enable output */ | |
364 | arg = 1; | |
365 | break; | |
f365be09 BA |
366 | default: |
367 | dev_err(pctrl->dev, "Unsupported config parameter: %x\n", | |
368 | param); | |
369 | return -EINVAL; | |
370 | } | |
371 | ||
372 | /* Range-check user-supplied value */ | |
373 | if (arg & ~mask) { | |
374 | dev_err(pctrl->dev, "config %x: %x is invalid\n", param, arg); | |
375 | return -EINVAL; | |
376 | } | |
377 | ||
378 | spin_lock_irqsave(&pctrl->lock, flags); | |
051a58b4 | 379 | val = readl(pctrl->regs + g->ctl_reg); |
f365be09 BA |
380 | val &= ~(mask << bit); |
381 | val |= arg << bit; | |
051a58b4 | 382 | writel(val, pctrl->regs + g->ctl_reg); |
f365be09 BA |
383 | spin_unlock_irqrestore(&pctrl->lock, flags); |
384 | } | |
385 | ||
386 | return 0; | |
387 | } | |
388 | ||
1f2b2398 | 389 | static const struct pinconf_ops msm_pinconf_ops = { |
f365be09 BA |
390 | .pin_config_get = msm_config_get, |
391 | .pin_config_set = msm_config_set, | |
392 | .pin_config_group_get = msm_config_group_get, | |
393 | .pin_config_group_set = msm_config_group_set, | |
394 | }; | |
395 | ||
396 | static struct pinctrl_desc msm_pinctrl_desc = { | |
397 | .pctlops = &msm_pinctrl_ops, | |
398 | .pmxops = &msm_pinmux_ops, | |
399 | .confops = &msm_pinconf_ops, | |
400 | .owner = THIS_MODULE, | |
401 | }; | |
402 | ||
403 | static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset) | |
404 | { | |
405 | const struct msm_pingroup *g; | |
406 | struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip); | |
407 | unsigned long flags; | |
408 | u32 val; | |
409 | ||
f365be09 | 410 | g = &pctrl->soc->groups[offset]; |
f365be09 BA |
411 | |
412 | spin_lock_irqsave(&pctrl->lock, flags); | |
413 | ||
414 | val = readl(pctrl->regs + g->ctl_reg); | |
415 | val &= ~BIT(g->oe_bit); | |
416 | writel(val, pctrl->regs + g->ctl_reg); | |
417 | ||
418 | spin_unlock_irqrestore(&pctrl->lock, flags); | |
419 | ||
420 | return 0; | |
421 | } | |
422 | ||
423 | static int msm_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int value) | |
424 | { | |
425 | const struct msm_pingroup *g; | |
426 | struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip); | |
427 | unsigned long flags; | |
428 | u32 val; | |
429 | ||
f365be09 | 430 | g = &pctrl->soc->groups[offset]; |
f365be09 BA |
431 | |
432 | spin_lock_irqsave(&pctrl->lock, flags); | |
433 | ||
e476e77f AL |
434 | val = readl(pctrl->regs + g->io_reg); |
435 | if (value) | |
436 | val |= BIT(g->out_bit); | |
437 | else | |
438 | val &= ~BIT(g->out_bit); | |
439 | writel(val, pctrl->regs + g->io_reg); | |
f365be09 BA |
440 | |
441 | val = readl(pctrl->regs + g->ctl_reg); | |
442 | val |= BIT(g->oe_bit); | |
443 | writel(val, pctrl->regs + g->ctl_reg); | |
444 | ||
445 | spin_unlock_irqrestore(&pctrl->lock, flags); | |
446 | ||
447 | return 0; | |
448 | } | |
449 | ||
450 | static int msm_gpio_get(struct gpio_chip *chip, unsigned offset) | |
451 | { | |
452 | const struct msm_pingroup *g; | |
453 | struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip); | |
454 | u32 val; | |
455 | ||
f365be09 BA |
456 | g = &pctrl->soc->groups[offset]; |
457 | ||
458 | val = readl(pctrl->regs + g->io_reg); | |
459 | return !!(val & BIT(g->in_bit)); | |
460 | } | |
461 | ||
462 | static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int value) | |
463 | { | |
464 | const struct msm_pingroup *g; | |
465 | struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip); | |
466 | unsigned long flags; | |
467 | u32 val; | |
468 | ||
f365be09 BA |
469 | g = &pctrl->soc->groups[offset]; |
470 | ||
471 | spin_lock_irqsave(&pctrl->lock, flags); | |
472 | ||
473 | val = readl(pctrl->regs + g->io_reg); | |
e476e77f AL |
474 | if (value) |
475 | val |= BIT(g->out_bit); | |
476 | else | |
477 | val &= ~BIT(g->out_bit); | |
f365be09 BA |
478 | writel(val, pctrl->regs + g->io_reg); |
479 | ||
480 | spin_unlock_irqrestore(&pctrl->lock, flags); | |
481 | } | |
482 | ||
483 | static int msm_gpio_to_irq(struct gpio_chip *chip, unsigned offset) | |
484 | { | |
485 | struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip); | |
486 | ||
487 | return irq_find_mapping(pctrl->domain, offset); | |
488 | } | |
489 | ||
490 | static int msm_gpio_request(struct gpio_chip *chip, unsigned offset) | |
491 | { | |
492 | int gpio = chip->base + offset; | |
493 | return pinctrl_request_gpio(gpio); | |
494 | } | |
495 | ||
496 | static void msm_gpio_free(struct gpio_chip *chip, unsigned offset) | |
497 | { | |
498 | int gpio = chip->base + offset; | |
499 | return pinctrl_free_gpio(gpio); | |
500 | } | |
501 | ||
502 | #ifdef CONFIG_DEBUG_FS | |
503 | #include <linux/seq_file.h> | |
504 | ||
505 | static void msm_gpio_dbg_show_one(struct seq_file *s, | |
506 | struct pinctrl_dev *pctldev, | |
507 | struct gpio_chip *chip, | |
508 | unsigned offset, | |
509 | unsigned gpio) | |
510 | { | |
511 | const struct msm_pingroup *g; | |
512 | struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip); | |
513 | unsigned func; | |
514 | int is_out; | |
515 | int drive; | |
516 | int pull; | |
517 | u32 ctl_reg; | |
518 | ||
1f2b2398 | 519 | static const char * const pulls[] = { |
f365be09 BA |
520 | "no pull", |
521 | "pull down", | |
522 | "keeper", | |
523 | "pull up" | |
524 | }; | |
525 | ||
526 | g = &pctrl->soc->groups[offset]; | |
527 | ctl_reg = readl(pctrl->regs + g->ctl_reg); | |
528 | ||
529 | is_out = !!(ctl_reg & BIT(g->oe_bit)); | |
530 | func = (ctl_reg >> g->mux_bit) & 7; | |
531 | drive = (ctl_reg >> g->drv_bit) & 7; | |
532 | pull = (ctl_reg >> g->pull_bit) & 3; | |
533 | ||
534 | seq_printf(s, " %-8s: %-3s %d", g->name, is_out ? "out" : "in", func); | |
7cc34e2e | 535 | seq_printf(s, " %dmA", msm_regval_to_drive(drive)); |
f365be09 BA |
536 | seq_printf(s, " %s", pulls[pull]); |
537 | } | |
538 | ||
539 | static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) | |
540 | { | |
541 | unsigned gpio = chip->base; | |
542 | unsigned i; | |
543 | ||
544 | for (i = 0; i < chip->ngpio; i++, gpio++) { | |
545 | msm_gpio_dbg_show_one(s, NULL, chip, i, gpio); | |
1f2b2398 | 546 | seq_puts(s, "\n"); |
f365be09 BA |
547 | } |
548 | } | |
549 | ||
550 | #else | |
551 | #define msm_gpio_dbg_show NULL | |
552 | #endif | |
553 | ||
554 | static struct gpio_chip msm_gpio_template = { | |
555 | .direction_input = msm_gpio_direction_input, | |
556 | .direction_output = msm_gpio_direction_output, | |
557 | .get = msm_gpio_get, | |
558 | .set = msm_gpio_set, | |
559 | .to_irq = msm_gpio_to_irq, | |
560 | .request = msm_gpio_request, | |
561 | .free = msm_gpio_free, | |
562 | .dbg_show = msm_gpio_dbg_show, | |
563 | }; | |
564 | ||
565 | /* For dual-edge interrupts in software, since some hardware has no | |
566 | * such support: | |
567 | * | |
568 | * At appropriate moments, this function may be called to flip the polarity | |
569 | * settings of both-edge irq lines to try and catch the next edge. | |
570 | * | |
571 | * The attempt is considered successful if: | |
572 | * - the status bit goes high, indicating that an edge was caught, or | |
573 | * - the input value of the gpio doesn't change during the attempt. | |
574 | * If the value changes twice during the process, that would cause the first | |
575 | * test to fail but would force the second, as two opposite | |
576 | * transitions would cause a detection no matter the polarity setting. | |
577 | * | |
578 | * The do-loop tries to sledge-hammer closed the timing hole between | |
579 | * the initial value-read and the polarity-write - if the line value changes | |
580 | * during that window, an interrupt is lost, the new polarity setting is | |
581 | * incorrect, and the first success test will fail, causing a retry. | |
582 | * | |
583 | * Algorithm comes from Google's msmgpio driver. | |
584 | */ | |
585 | static void msm_gpio_update_dual_edge_pos(struct msm_pinctrl *pctrl, | |
586 | const struct msm_pingroup *g, | |
587 | struct irq_data *d) | |
588 | { | |
589 | int loop_limit = 100; | |
590 | unsigned val, val2, intstat; | |
591 | unsigned pol; | |
592 | ||
593 | do { | |
594 | val = readl(pctrl->regs + g->io_reg) & BIT(g->in_bit); | |
595 | ||
596 | pol = readl(pctrl->regs + g->intr_cfg_reg); | |
597 | pol ^= BIT(g->intr_polarity_bit); | |
598 | writel(pol, pctrl->regs + g->intr_cfg_reg); | |
599 | ||
600 | val2 = readl(pctrl->regs + g->io_reg) & BIT(g->in_bit); | |
601 | intstat = readl(pctrl->regs + g->intr_status_reg); | |
602 | if (intstat || (val == val2)) | |
603 | return; | |
604 | } while (loop_limit-- > 0); | |
605 | dev_err(pctrl->dev, "dual-edge irq failed to stabilize, %#08x != %#08x\n", | |
606 | val, val2); | |
607 | } | |
608 | ||
609 | static void msm_gpio_irq_mask(struct irq_data *d) | |
610 | { | |
611 | const struct msm_pingroup *g; | |
612 | struct msm_pinctrl *pctrl; | |
613 | unsigned long flags; | |
614 | u32 val; | |
615 | ||
616 | pctrl = irq_data_get_irq_chip_data(d); | |
f365be09 BA |
617 | g = &pctrl->soc->groups[d->hwirq]; |
618 | ||
619 | spin_lock_irqsave(&pctrl->lock, flags); | |
620 | ||
621 | val = readl(pctrl->regs + g->intr_cfg_reg); | |
622 | val &= ~BIT(g->intr_enable_bit); | |
623 | writel(val, pctrl->regs + g->intr_cfg_reg); | |
624 | ||
625 | clear_bit(d->hwirq, pctrl->enabled_irqs); | |
626 | ||
627 | spin_unlock_irqrestore(&pctrl->lock, flags); | |
628 | } | |
629 | ||
630 | static void msm_gpio_irq_unmask(struct irq_data *d) | |
631 | { | |
632 | const struct msm_pingroup *g; | |
633 | struct msm_pinctrl *pctrl; | |
634 | unsigned long flags; | |
635 | u32 val; | |
636 | ||
637 | pctrl = irq_data_get_irq_chip_data(d); | |
f365be09 BA |
638 | g = &pctrl->soc->groups[d->hwirq]; |
639 | ||
640 | spin_lock_irqsave(&pctrl->lock, flags); | |
641 | ||
642 | val = readl(pctrl->regs + g->intr_status_reg); | |
643 | val &= ~BIT(g->intr_status_bit); | |
644 | writel(val, pctrl->regs + g->intr_status_reg); | |
645 | ||
646 | val = readl(pctrl->regs + g->intr_cfg_reg); | |
647 | val |= BIT(g->intr_enable_bit); | |
648 | writel(val, pctrl->regs + g->intr_cfg_reg); | |
649 | ||
650 | set_bit(d->hwirq, pctrl->enabled_irqs); | |
651 | ||
652 | spin_unlock_irqrestore(&pctrl->lock, flags); | |
653 | } | |
654 | ||
655 | static void msm_gpio_irq_ack(struct irq_data *d) | |
656 | { | |
657 | const struct msm_pingroup *g; | |
658 | struct msm_pinctrl *pctrl; | |
659 | unsigned long flags; | |
660 | u32 val; | |
661 | ||
662 | pctrl = irq_data_get_irq_chip_data(d); | |
f365be09 BA |
663 | g = &pctrl->soc->groups[d->hwirq]; |
664 | ||
665 | spin_lock_irqsave(&pctrl->lock, flags); | |
666 | ||
667 | val = readl(pctrl->regs + g->intr_status_reg); | |
48f15e94 BA |
668 | if (g->intr_ack_high) |
669 | val |= BIT(g->intr_status_bit); | |
670 | else | |
671 | val &= ~BIT(g->intr_status_bit); | |
f365be09 BA |
672 | writel(val, pctrl->regs + g->intr_status_reg); |
673 | ||
674 | if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) | |
675 | msm_gpio_update_dual_edge_pos(pctrl, g, d); | |
676 | ||
677 | spin_unlock_irqrestore(&pctrl->lock, flags); | |
678 | } | |
679 | ||
680 | #define INTR_TARGET_PROC_APPS 4 | |
681 | ||
682 | static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type) | |
683 | { | |
684 | const struct msm_pingroup *g; | |
685 | struct msm_pinctrl *pctrl; | |
686 | unsigned long flags; | |
687 | u32 val; | |
688 | ||
689 | pctrl = irq_data_get_irq_chip_data(d); | |
f365be09 BA |
690 | g = &pctrl->soc->groups[d->hwirq]; |
691 | ||
692 | spin_lock_irqsave(&pctrl->lock, flags); | |
693 | ||
694 | /* | |
695 | * For hw without possibility of detecting both edges | |
696 | */ | |
697 | if (g->intr_detection_width == 1 && type == IRQ_TYPE_EDGE_BOTH) | |
698 | set_bit(d->hwirq, pctrl->dual_edge_irqs); | |
699 | else | |
700 | clear_bit(d->hwirq, pctrl->dual_edge_irqs); | |
701 | ||
702 | /* Route interrupts to application cpu */ | |
703 | val = readl(pctrl->regs + g->intr_target_reg); | |
704 | val &= ~(7 << g->intr_target_bit); | |
705 | val |= INTR_TARGET_PROC_APPS << g->intr_target_bit; | |
706 | writel(val, pctrl->regs + g->intr_target_reg); | |
707 | ||
708 | /* Update configuration for gpio. | |
709 | * RAW_STATUS_EN is left on for all gpio irqs. Due to the | |
710 | * internal circuitry of TLMM, toggling the RAW_STATUS | |
711 | * could cause the INTR_STATUS to be set for EDGE interrupts. | |
712 | */ | |
713 | val = readl(pctrl->regs + g->intr_cfg_reg); | |
714 | val |= BIT(g->intr_raw_status_bit); | |
715 | if (g->intr_detection_width == 2) { | |
716 | val &= ~(3 << g->intr_detection_bit); | |
717 | val &= ~(1 << g->intr_polarity_bit); | |
718 | switch (type) { | |
719 | case IRQ_TYPE_EDGE_RISING: | |
720 | val |= 1 << g->intr_detection_bit; | |
721 | val |= BIT(g->intr_polarity_bit); | |
722 | break; | |
723 | case IRQ_TYPE_EDGE_FALLING: | |
724 | val |= 2 << g->intr_detection_bit; | |
725 | val |= BIT(g->intr_polarity_bit); | |
726 | break; | |
727 | case IRQ_TYPE_EDGE_BOTH: | |
728 | val |= 3 << g->intr_detection_bit; | |
729 | val |= BIT(g->intr_polarity_bit); | |
730 | break; | |
731 | case IRQ_TYPE_LEVEL_LOW: | |
732 | break; | |
733 | case IRQ_TYPE_LEVEL_HIGH: | |
734 | val |= BIT(g->intr_polarity_bit); | |
735 | break; | |
736 | } | |
737 | } else if (g->intr_detection_width == 1) { | |
738 | val &= ~(1 << g->intr_detection_bit); | |
739 | val &= ~(1 << g->intr_polarity_bit); | |
740 | switch (type) { | |
741 | case IRQ_TYPE_EDGE_RISING: | |
742 | val |= BIT(g->intr_detection_bit); | |
743 | val |= BIT(g->intr_polarity_bit); | |
744 | break; | |
745 | case IRQ_TYPE_EDGE_FALLING: | |
746 | val |= BIT(g->intr_detection_bit); | |
747 | break; | |
748 | case IRQ_TYPE_EDGE_BOTH: | |
749 | val |= BIT(g->intr_detection_bit); | |
48f15e94 | 750 | val |= BIT(g->intr_polarity_bit); |
f365be09 BA |
751 | break; |
752 | case IRQ_TYPE_LEVEL_LOW: | |
753 | break; | |
754 | case IRQ_TYPE_LEVEL_HIGH: | |
755 | val |= BIT(g->intr_polarity_bit); | |
756 | break; | |
757 | } | |
758 | } else { | |
759 | BUG(); | |
760 | } | |
761 | writel(val, pctrl->regs + g->intr_cfg_reg); | |
762 | ||
763 | if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) | |
764 | msm_gpio_update_dual_edge_pos(pctrl, g, d); | |
765 | ||
766 | spin_unlock_irqrestore(&pctrl->lock, flags); | |
767 | ||
768 | if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) | |
769 | __irq_set_handler_locked(d->irq, handle_level_irq); | |
770 | else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) | |
771 | __irq_set_handler_locked(d->irq, handle_edge_irq); | |
772 | ||
773 | return 0; | |
774 | } | |
775 | ||
776 | static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on) | |
777 | { | |
778 | struct msm_pinctrl *pctrl; | |
779 | unsigned long flags; | |
f365be09 BA |
780 | |
781 | pctrl = irq_data_get_irq_chip_data(d); | |
f365be09 BA |
782 | |
783 | spin_lock_irqsave(&pctrl->lock, flags); | |
784 | ||
6aced33f | 785 | irq_set_irq_wake(pctrl->irq, on); |
f365be09 BA |
786 | |
787 | spin_unlock_irqrestore(&pctrl->lock, flags); | |
788 | ||
789 | return 0; | |
790 | } | |
791 | ||
57ef0428 | 792 | static int msm_gpio_irq_reqres(struct irq_data *d) |
f365be09 BA |
793 | { |
794 | struct msm_pinctrl *pctrl = irq_data_get_irq_chip_data(d); | |
795 | ||
796 | if (gpio_lock_as_irq(&pctrl->chip, d->hwirq)) { | |
797 | dev_err(pctrl->dev, "unable to lock HW IRQ %lu for IRQ\n", | |
798 | d->hwirq); | |
57ef0428 | 799 | return -EINVAL; |
f365be09 | 800 | } |
f365be09 BA |
801 | return 0; |
802 | } | |
803 | ||
57ef0428 | 804 | static void msm_gpio_irq_relres(struct irq_data *d) |
f365be09 BA |
805 | { |
806 | struct msm_pinctrl *pctrl = irq_data_get_irq_chip_data(d); | |
807 | ||
f365be09 BA |
808 | gpio_unlock_as_irq(&pctrl->chip, d->hwirq); |
809 | } | |
810 | ||
811 | static struct irq_chip msm_gpio_irq_chip = { | |
812 | .name = "msmgpio", | |
813 | .irq_mask = msm_gpio_irq_mask, | |
814 | .irq_unmask = msm_gpio_irq_unmask, | |
815 | .irq_ack = msm_gpio_irq_ack, | |
816 | .irq_set_type = msm_gpio_irq_set_type, | |
817 | .irq_set_wake = msm_gpio_irq_set_wake, | |
57ef0428 LW |
818 | .irq_request_resources = msm_gpio_irq_reqres, |
819 | .irq_release_resources = msm_gpio_irq_relres, | |
f365be09 BA |
820 | }; |
821 | ||
822 | static void msm_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) | |
823 | { | |
824 | const struct msm_pingroup *g; | |
825 | struct msm_pinctrl *pctrl = irq_desc_get_handler_data(desc); | |
826 | struct irq_chip *chip = irq_get_chip(irq); | |
827 | int irq_pin; | |
828 | int handled = 0; | |
829 | u32 val; | |
830 | int i; | |
831 | ||
832 | chained_irq_enter(chip, desc); | |
833 | ||
834 | /* | |
1f2b2398 | 835 | * Each pin has it's own IRQ status register, so use |
f365be09 BA |
836 | * enabled_irq bitmap to limit the number of reads. |
837 | */ | |
838 | for_each_set_bit(i, pctrl->enabled_irqs, pctrl->chip.ngpio) { | |
839 | g = &pctrl->soc->groups[i]; | |
840 | val = readl(pctrl->regs + g->intr_status_reg); | |
841 | if (val & BIT(g->intr_status_bit)) { | |
842 | irq_pin = irq_find_mapping(pctrl->domain, i); | |
843 | generic_handle_irq(irq_pin); | |
844 | handled++; | |
845 | } | |
846 | } | |
847 | ||
1f2b2398 | 848 | /* No interrupts were flagged */ |
f365be09 BA |
849 | if (handled == 0) |
850 | handle_bad_irq(irq, desc); | |
851 | ||
852 | chained_irq_exit(chip, desc); | |
853 | } | |
854 | ||
3525f555 SB |
855 | /* |
856 | * This lock class tells lockdep that GPIO irqs are in a different | |
857 | * category than their parents, so it won't report false recursion. | |
858 | */ | |
859 | static struct lock_class_key gpio_lock_class; | |
860 | ||
f365be09 BA |
861 | static int msm_gpio_init(struct msm_pinctrl *pctrl) |
862 | { | |
863 | struct gpio_chip *chip; | |
864 | int irq; | |
865 | int ret; | |
866 | int i; | |
867 | int r; | |
dcd278b8 SB |
868 | unsigned ngpio = pctrl->soc->ngpios; |
869 | ||
870 | if (WARN_ON(ngpio > MAX_NR_GPIO)) | |
871 | return -EINVAL; | |
f365be09 BA |
872 | |
873 | chip = &pctrl->chip; | |
874 | chip->base = 0; | |
dcd278b8 | 875 | chip->ngpio = ngpio; |
f365be09 BA |
876 | chip->label = dev_name(pctrl->dev); |
877 | chip->dev = pctrl->dev; | |
878 | chip->owner = THIS_MODULE; | |
879 | chip->of_node = pctrl->dev->of_node; | |
880 | ||
f365be09 BA |
881 | ret = gpiochip_add(&pctrl->chip); |
882 | if (ret) { | |
883 | dev_err(pctrl->dev, "Failed register gpiochip\n"); | |
884 | return ret; | |
885 | } | |
886 | ||
887 | ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), 0, 0, chip->ngpio); | |
888 | if (ret) { | |
889 | dev_err(pctrl->dev, "Failed to add pin range\n"); | |
890 | return ret; | |
891 | } | |
892 | ||
893 | pctrl->domain = irq_domain_add_linear(pctrl->dev->of_node, chip->ngpio, | |
894 | &irq_domain_simple_ops, NULL); | |
895 | if (!pctrl->domain) { | |
896 | dev_err(pctrl->dev, "Failed to register irq domain\n"); | |
897 | r = gpiochip_remove(&pctrl->chip); | |
898 | return -ENOSYS; | |
899 | } | |
900 | ||
901 | for (i = 0; i < chip->ngpio; i++) { | |
902 | irq = irq_create_mapping(pctrl->domain, i); | |
3525f555 | 903 | irq_set_lockdep_class(irq, &gpio_lock_class); |
f365be09 BA |
904 | irq_set_chip_and_handler(irq, &msm_gpio_irq_chip, handle_edge_irq); |
905 | irq_set_chip_data(irq, pctrl); | |
906 | } | |
907 | ||
908 | irq_set_handler_data(pctrl->irq, pctrl); | |
909 | irq_set_chained_handler(pctrl->irq, msm_gpio_irq_handler); | |
910 | ||
911 | return 0; | |
912 | } | |
913 | ||
914 | int msm_pinctrl_probe(struct platform_device *pdev, | |
915 | const struct msm_pinctrl_soc_data *soc_data) | |
916 | { | |
917 | struct msm_pinctrl *pctrl; | |
918 | struct resource *res; | |
919 | int ret; | |
920 | ||
921 | pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); | |
922 | if (!pctrl) { | |
923 | dev_err(&pdev->dev, "Can't allocate msm_pinctrl\n"); | |
924 | return -ENOMEM; | |
925 | } | |
926 | pctrl->dev = &pdev->dev; | |
927 | pctrl->soc = soc_data; | |
928 | pctrl->chip = msm_gpio_template; | |
929 | ||
930 | spin_lock_init(&pctrl->lock); | |
931 | ||
932 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
933 | pctrl->regs = devm_ioremap_resource(&pdev->dev, res); | |
934 | if (IS_ERR(pctrl->regs)) | |
935 | return PTR_ERR(pctrl->regs); | |
936 | ||
f393e489 | 937 | pctrl->irq = platform_get_irq(pdev, 0); |
f365be09 BA |
938 | if (pctrl->irq < 0) { |
939 | dev_err(&pdev->dev, "No interrupt defined for msmgpio\n"); | |
940 | return pctrl->irq; | |
941 | } | |
942 | ||
943 | msm_pinctrl_desc.name = dev_name(&pdev->dev); | |
944 | msm_pinctrl_desc.pins = pctrl->soc->pins; | |
945 | msm_pinctrl_desc.npins = pctrl->soc->npins; | |
946 | pctrl->pctrl = pinctrl_register(&msm_pinctrl_desc, &pdev->dev, pctrl); | |
947 | if (!pctrl->pctrl) { | |
948 | dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); | |
949 | return -ENODEV; | |
950 | } | |
951 | ||
952 | ret = msm_gpio_init(pctrl); | |
953 | if (ret) { | |
954 | pinctrl_unregister(pctrl->pctrl); | |
955 | return ret; | |
956 | } | |
957 | ||
958 | platform_set_drvdata(pdev, pctrl); | |
959 | ||
960 | dev_dbg(&pdev->dev, "Probed Qualcomm pinctrl driver\n"); | |
961 | ||
962 | return 0; | |
963 | } | |
964 | EXPORT_SYMBOL(msm_pinctrl_probe); | |
965 | ||
966 | int msm_pinctrl_remove(struct platform_device *pdev) | |
967 | { | |
968 | struct msm_pinctrl *pctrl = platform_get_drvdata(pdev); | |
969 | int ret; | |
970 | ||
f393e489 BA |
971 | ret = gpiochip_remove(&pctrl->chip); |
972 | if (ret) { | |
973 | dev_err(&pdev->dev, "Failed to remove gpiochip\n"); | |
974 | return ret; | |
975 | } | |
976 | ||
f365be09 BA |
977 | irq_set_chained_handler(pctrl->irq, NULL); |
978 | irq_domain_remove(pctrl->domain); | |
f365be09 BA |
979 | pinctrl_unregister(pctrl->pctrl); |
980 | ||
981 | return 0; | |
982 | } | |
983 | EXPORT_SYMBOL(msm_pinctrl_remove); | |
984 |