]>
Commit | Line | Data |
---|---|---|
f365be09 BA |
1 | /* |
2 | * Copyright (c) 2013, Sony Mobile Communications AB. | |
3 | * Copyright (c) 2013, The Linux Foundation. All rights reserved. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 and | |
7 | * only version 2 as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | */ | |
14 | ||
15 | #include <linux/err.h> | |
16 | #include <linux/irqdomain.h> | |
17 | #include <linux/io.h> | |
18 | #include <linux/module.h> | |
19 | #include <linux/of.h> | |
20 | #include <linux/platform_device.h> | |
21 | #include <linux/pinctrl/machine.h> | |
22 | #include <linux/pinctrl/pinctrl.h> | |
23 | #include <linux/pinctrl/pinmux.h> | |
24 | #include <linux/pinctrl/pinconf.h> | |
25 | #include <linux/pinctrl/pinconf-generic.h> | |
26 | #include <linux/slab.h> | |
27 | #include <linux/gpio.h> | |
28 | #include <linux/interrupt.h> | |
29 | #include <linux/irq.h> | |
30 | #include <linux/irqchip/chained_irq.h> | |
31 | #include <linux/of_irq.h> | |
32 | #include <linux/spinlock.h> | |
33 | ||
34 | #include "core.h" | |
35 | #include "pinconf.h" | |
36 | #include "pinctrl-msm.h" | |
37 | #include "pinctrl-utils.h" | |
38 | ||
408e3c66 BA |
39 | #define MAX_NR_GPIO 300 |
40 | ||
f365be09 BA |
41 | /** |
42 | * struct msm_pinctrl - state for a pinctrl-msm device | |
43 | * @dev: device handle. | |
44 | * @pctrl: pinctrl handle. | |
45 | * @domain: irqdomain handle. | |
46 | * @chip: gpiochip handle. | |
47 | * @irq: parent irq for the TLMM irq_chip. | |
48 | * @lock: Spinlock to protect register resources as well | |
49 | * as msm_pinctrl data structures. | |
50 | * @enabled_irqs: Bitmap of currently enabled irqs. | |
51 | * @dual_edge_irqs: Bitmap of irqs that need sw emulated dual edge | |
52 | * detection. | |
53 | * @wake_irqs: Bitmap of irqs with requested as wakeup source. | |
54 | * @soc; Reference to soc_data of platform specific data. | |
55 | * @regs: Base address for the TLMM register map. | |
56 | */ | |
57 | struct msm_pinctrl { | |
58 | struct device *dev; | |
59 | struct pinctrl_dev *pctrl; | |
60 | struct irq_domain *domain; | |
61 | struct gpio_chip chip; | |
f393e489 | 62 | int irq; |
f365be09 BA |
63 | |
64 | spinlock_t lock; | |
65 | ||
408e3c66 BA |
66 | DECLARE_BITMAP(dual_edge_irqs, MAX_NR_GPIO); |
67 | DECLARE_BITMAP(enabled_irqs, MAX_NR_GPIO); | |
68 | DECLARE_BITMAP(wake_irqs, MAX_NR_GPIO); | |
f365be09 BA |
69 | |
70 | const struct msm_pinctrl_soc_data *soc; | |
71 | void __iomem *regs; | |
72 | }; | |
73 | ||
74 | static int msm_get_groups_count(struct pinctrl_dev *pctldev) | |
75 | { | |
76 | struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
77 | ||
78 | return pctrl->soc->ngroups; | |
79 | } | |
80 | ||
81 | static const char *msm_get_group_name(struct pinctrl_dev *pctldev, | |
82 | unsigned group) | |
83 | { | |
84 | struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
85 | ||
86 | return pctrl->soc->groups[group].name; | |
87 | } | |
88 | ||
89 | static int msm_get_group_pins(struct pinctrl_dev *pctldev, | |
90 | unsigned group, | |
91 | const unsigned **pins, | |
92 | unsigned *num_pins) | |
93 | { | |
94 | struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
95 | ||
96 | *pins = pctrl->soc->groups[group].pins; | |
97 | *num_pins = pctrl->soc->groups[group].npins; | |
98 | return 0; | |
99 | } | |
100 | ||
1f2b2398 | 101 | static const struct pinctrl_ops msm_pinctrl_ops = { |
f365be09 BA |
102 | .get_groups_count = msm_get_groups_count, |
103 | .get_group_name = msm_get_group_name, | |
104 | .get_group_pins = msm_get_group_pins, | |
105 | .dt_node_to_map = pinconf_generic_dt_node_to_map_group, | |
106 | .dt_free_map = pinctrl_utils_dt_free_map, | |
107 | }; | |
108 | ||
109 | static int msm_get_functions_count(struct pinctrl_dev *pctldev) | |
110 | { | |
111 | struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
112 | ||
113 | return pctrl->soc->nfunctions; | |
114 | } | |
115 | ||
116 | static const char *msm_get_function_name(struct pinctrl_dev *pctldev, | |
117 | unsigned function) | |
118 | { | |
119 | struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
120 | ||
121 | return pctrl->soc->functions[function].name; | |
122 | } | |
123 | ||
124 | static int msm_get_function_groups(struct pinctrl_dev *pctldev, | |
125 | unsigned function, | |
126 | const char * const **groups, | |
127 | unsigned * const num_groups) | |
128 | { | |
129 | struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
130 | ||
131 | *groups = pctrl->soc->functions[function].groups; | |
132 | *num_groups = pctrl->soc->functions[function].ngroups; | |
133 | return 0; | |
134 | } | |
135 | ||
136 | static int msm_pinmux_enable(struct pinctrl_dev *pctldev, | |
137 | unsigned function, | |
138 | unsigned group) | |
139 | { | |
140 | struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
141 | const struct msm_pingroup *g; | |
142 | unsigned long flags; | |
143 | u32 val; | |
144 | int i; | |
145 | ||
146 | g = &pctrl->soc->groups[group]; | |
147 | ||
148 | if (WARN_ON(g->mux_bit < 0)) | |
149 | return -EINVAL; | |
150 | ||
151 | for (i = 0; i < ARRAY_SIZE(g->funcs); i++) { | |
152 | if (g->funcs[i] == function) | |
153 | break; | |
154 | } | |
155 | ||
156 | if (WARN_ON(i == ARRAY_SIZE(g->funcs))) | |
157 | return -EINVAL; | |
158 | ||
159 | spin_lock_irqsave(&pctrl->lock, flags); | |
160 | ||
161 | val = readl(pctrl->regs + g->ctl_reg); | |
162 | val &= ~(0x7 << g->mux_bit); | |
163 | val |= i << g->mux_bit; | |
164 | writel(val, pctrl->regs + g->ctl_reg); | |
165 | ||
166 | spin_unlock_irqrestore(&pctrl->lock, flags); | |
167 | ||
168 | return 0; | |
169 | } | |
170 | ||
171 | static void msm_pinmux_disable(struct pinctrl_dev *pctldev, | |
172 | unsigned function, | |
173 | unsigned group) | |
174 | { | |
175 | struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
176 | const struct msm_pingroup *g; | |
177 | unsigned long flags; | |
178 | u32 val; | |
179 | ||
180 | g = &pctrl->soc->groups[group]; | |
181 | ||
182 | if (WARN_ON(g->mux_bit < 0)) | |
183 | return; | |
184 | ||
185 | spin_lock_irqsave(&pctrl->lock, flags); | |
186 | ||
187 | /* Clear the mux bits to select gpio mode */ | |
188 | val = readl(pctrl->regs + g->ctl_reg); | |
189 | val &= ~(0x7 << g->mux_bit); | |
190 | writel(val, pctrl->regs + g->ctl_reg); | |
191 | ||
192 | spin_unlock_irqrestore(&pctrl->lock, flags); | |
193 | } | |
194 | ||
1f2b2398 | 195 | static const struct pinmux_ops msm_pinmux_ops = { |
f365be09 BA |
196 | .get_functions_count = msm_get_functions_count, |
197 | .get_function_name = msm_get_function_name, | |
198 | .get_function_groups = msm_get_function_groups, | |
199 | .enable = msm_pinmux_enable, | |
200 | .disable = msm_pinmux_disable, | |
201 | }; | |
202 | ||
203 | static int msm_config_reg(struct msm_pinctrl *pctrl, | |
204 | const struct msm_pingroup *g, | |
205 | unsigned param, | |
f393e489 | 206 | s16 *reg, |
f365be09 BA |
207 | unsigned *mask, |
208 | unsigned *bit) | |
209 | { | |
210 | switch (param) { | |
211 | case PIN_CONFIG_BIAS_DISABLE: | |
212 | *reg = g->ctl_reg; | |
213 | *bit = g->pull_bit; | |
214 | *mask = 3; | |
215 | break; | |
216 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
217 | *reg = g->ctl_reg; | |
218 | *bit = g->pull_bit; | |
219 | *mask = 3; | |
220 | break; | |
221 | case PIN_CONFIG_BIAS_PULL_UP: | |
222 | *reg = g->ctl_reg; | |
223 | *bit = g->pull_bit; | |
224 | *mask = 3; | |
225 | break; | |
226 | case PIN_CONFIG_DRIVE_STRENGTH: | |
227 | *reg = g->ctl_reg; | |
228 | *bit = g->drv_bit; | |
229 | *mask = 7; | |
230 | break; | |
ed118a5f BA |
231 | case PIN_CONFIG_OUTPUT: |
232 | *reg = g->ctl_reg; | |
233 | *bit = g->oe_bit; | |
234 | *mask = 1; | |
235 | break; | |
f365be09 BA |
236 | default: |
237 | dev_err(pctrl->dev, "Invalid config param %04x\n", param); | |
238 | return -ENOTSUPP; | |
239 | } | |
240 | ||
241 | if (*reg < 0) { | |
242 | dev_err(pctrl->dev, "Config param %04x not supported on group %s\n", | |
243 | param, g->name); | |
244 | return -ENOTSUPP; | |
245 | } | |
246 | ||
247 | return 0; | |
248 | } | |
249 | ||
250 | static int msm_config_get(struct pinctrl_dev *pctldev, | |
251 | unsigned int pin, | |
252 | unsigned long *config) | |
253 | { | |
254 | dev_err(pctldev->dev, "pin_config_set op not supported\n"); | |
255 | return -ENOTSUPP; | |
256 | } | |
257 | ||
258 | static int msm_config_set(struct pinctrl_dev *pctldev, unsigned int pin, | |
259 | unsigned long *configs, unsigned num_configs) | |
260 | { | |
261 | dev_err(pctldev->dev, "pin_config_set op not supported\n"); | |
262 | return -ENOTSUPP; | |
263 | } | |
264 | ||
265 | #define MSM_NO_PULL 0 | |
266 | #define MSM_PULL_DOWN 1 | |
267 | #define MSM_PULL_UP 3 | |
268 | ||
269 | static const unsigned msm_regval_to_drive[] = { 2, 4, 6, 8, 10, 12, 14, 16 }; | |
270 | static const unsigned msm_drive_to_regval[] = { -1, -1, 0, -1, 1, -1, 2, -1, 3, -1, 4, -1, 5, -1, 6, -1, 7 }; | |
271 | ||
272 | static int msm_config_group_get(struct pinctrl_dev *pctldev, | |
273 | unsigned int group, | |
274 | unsigned long *config) | |
275 | { | |
276 | const struct msm_pingroup *g; | |
277 | struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
278 | unsigned param = pinconf_to_config_param(*config); | |
279 | unsigned mask; | |
280 | unsigned arg; | |
281 | unsigned bit; | |
f393e489 | 282 | s16 reg; |
f365be09 BA |
283 | int ret; |
284 | u32 val; | |
285 | ||
286 | g = &pctrl->soc->groups[group]; | |
287 | ||
288 | ret = msm_config_reg(pctrl, g, param, ®, &mask, &bit); | |
289 | if (ret < 0) | |
290 | return ret; | |
291 | ||
292 | val = readl(pctrl->regs + reg); | |
293 | arg = (val >> bit) & mask; | |
294 | ||
295 | /* Convert register value to pinconf value */ | |
296 | switch (param) { | |
297 | case PIN_CONFIG_BIAS_DISABLE: | |
298 | arg = arg == MSM_NO_PULL; | |
299 | break; | |
300 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
301 | arg = arg == MSM_PULL_DOWN; | |
302 | break; | |
303 | case PIN_CONFIG_BIAS_PULL_UP: | |
304 | arg = arg == MSM_PULL_UP; | |
305 | break; | |
306 | case PIN_CONFIG_DRIVE_STRENGTH: | |
307 | arg = msm_regval_to_drive[arg]; | |
308 | break; | |
ed118a5f BA |
309 | case PIN_CONFIG_OUTPUT: |
310 | /* Pin is not output */ | |
311 | if (!arg) | |
312 | return -EINVAL; | |
313 | ||
314 | val = readl(pctrl->regs + g->io_reg); | |
315 | arg = !!(val & BIT(g->in_bit)); | |
316 | break; | |
f365be09 BA |
317 | default: |
318 | dev_err(pctrl->dev, "Unsupported config parameter: %x\n", | |
319 | param); | |
320 | return -EINVAL; | |
321 | } | |
322 | ||
323 | *config = pinconf_to_config_packed(param, arg); | |
324 | ||
325 | return 0; | |
326 | } | |
327 | ||
328 | static int msm_config_group_set(struct pinctrl_dev *pctldev, | |
329 | unsigned group, | |
330 | unsigned long *configs, | |
331 | unsigned num_configs) | |
332 | { | |
333 | const struct msm_pingroup *g; | |
334 | struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
335 | unsigned long flags; | |
336 | unsigned param; | |
337 | unsigned mask; | |
338 | unsigned arg; | |
339 | unsigned bit; | |
f393e489 | 340 | s16 reg; |
f365be09 BA |
341 | int ret; |
342 | u32 val; | |
343 | int i; | |
344 | ||
345 | g = &pctrl->soc->groups[group]; | |
346 | ||
347 | for (i = 0; i < num_configs; i++) { | |
348 | param = pinconf_to_config_param(configs[i]); | |
349 | arg = pinconf_to_config_argument(configs[i]); | |
350 | ||
351 | ret = msm_config_reg(pctrl, g, param, ®, &mask, &bit); | |
352 | if (ret < 0) | |
353 | return ret; | |
354 | ||
355 | /* Convert pinconf values to register values */ | |
356 | switch (param) { | |
357 | case PIN_CONFIG_BIAS_DISABLE: | |
358 | arg = MSM_NO_PULL; | |
359 | break; | |
360 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
361 | arg = MSM_PULL_DOWN; | |
362 | break; | |
363 | case PIN_CONFIG_BIAS_PULL_UP: | |
364 | arg = MSM_PULL_UP; | |
365 | break; | |
366 | case PIN_CONFIG_DRIVE_STRENGTH: | |
367 | /* Check for invalid values */ | |
f393e489 | 368 | if (arg >= ARRAY_SIZE(msm_drive_to_regval)) |
f365be09 BA |
369 | arg = -1; |
370 | else | |
371 | arg = msm_drive_to_regval[arg]; | |
372 | break; | |
ed118a5f BA |
373 | case PIN_CONFIG_OUTPUT: |
374 | /* set output value */ | |
375 | spin_lock_irqsave(&pctrl->lock, flags); | |
376 | val = readl(pctrl->regs + g->io_reg); | |
377 | if (arg) | |
378 | val |= BIT(g->out_bit); | |
379 | else | |
380 | val &= ~BIT(g->out_bit); | |
381 | writel(val, pctrl->regs + g->io_reg); | |
382 | spin_unlock_irqrestore(&pctrl->lock, flags); | |
383 | ||
384 | /* enable output */ | |
385 | arg = 1; | |
386 | break; | |
f365be09 BA |
387 | default: |
388 | dev_err(pctrl->dev, "Unsupported config parameter: %x\n", | |
389 | param); | |
390 | return -EINVAL; | |
391 | } | |
392 | ||
393 | /* Range-check user-supplied value */ | |
394 | if (arg & ~mask) { | |
395 | dev_err(pctrl->dev, "config %x: %x is invalid\n", param, arg); | |
396 | return -EINVAL; | |
397 | } | |
398 | ||
399 | spin_lock_irqsave(&pctrl->lock, flags); | |
400 | val = readl(pctrl->regs + reg); | |
401 | val &= ~(mask << bit); | |
402 | val |= arg << bit; | |
403 | writel(val, pctrl->regs + reg); | |
404 | spin_unlock_irqrestore(&pctrl->lock, flags); | |
405 | } | |
406 | ||
407 | return 0; | |
408 | } | |
409 | ||
1f2b2398 | 410 | static const struct pinconf_ops msm_pinconf_ops = { |
f365be09 BA |
411 | .pin_config_get = msm_config_get, |
412 | .pin_config_set = msm_config_set, | |
413 | .pin_config_group_get = msm_config_group_get, | |
414 | .pin_config_group_set = msm_config_group_set, | |
415 | }; | |
416 | ||
417 | static struct pinctrl_desc msm_pinctrl_desc = { | |
418 | .pctlops = &msm_pinctrl_ops, | |
419 | .pmxops = &msm_pinmux_ops, | |
420 | .confops = &msm_pinconf_ops, | |
421 | .owner = THIS_MODULE, | |
422 | }; | |
423 | ||
424 | static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset) | |
425 | { | |
426 | const struct msm_pingroup *g; | |
427 | struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip); | |
428 | unsigned long flags; | |
429 | u32 val; | |
430 | ||
f365be09 | 431 | g = &pctrl->soc->groups[offset]; |
f393e489 | 432 | if (WARN_ON(g->io_reg < 0)) |
f365be09 BA |
433 | return -EINVAL; |
434 | ||
435 | spin_lock_irqsave(&pctrl->lock, flags); | |
436 | ||
437 | val = readl(pctrl->regs + g->ctl_reg); | |
438 | val &= ~BIT(g->oe_bit); | |
439 | writel(val, pctrl->regs + g->ctl_reg); | |
440 | ||
441 | spin_unlock_irqrestore(&pctrl->lock, flags); | |
442 | ||
443 | return 0; | |
444 | } | |
445 | ||
446 | static int msm_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int value) | |
447 | { | |
448 | const struct msm_pingroup *g; | |
449 | struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip); | |
450 | unsigned long flags; | |
451 | u32 val; | |
452 | ||
f365be09 | 453 | g = &pctrl->soc->groups[offset]; |
f393e489 | 454 | if (WARN_ON(g->io_reg < 0)) |
f365be09 BA |
455 | return -EINVAL; |
456 | ||
457 | spin_lock_irqsave(&pctrl->lock, flags); | |
458 | ||
e476e77f AL |
459 | val = readl(pctrl->regs + g->io_reg); |
460 | if (value) | |
461 | val |= BIT(g->out_bit); | |
462 | else | |
463 | val &= ~BIT(g->out_bit); | |
464 | writel(val, pctrl->regs + g->io_reg); | |
f365be09 BA |
465 | |
466 | val = readl(pctrl->regs + g->ctl_reg); | |
467 | val |= BIT(g->oe_bit); | |
468 | writel(val, pctrl->regs + g->ctl_reg); | |
469 | ||
470 | spin_unlock_irqrestore(&pctrl->lock, flags); | |
471 | ||
472 | return 0; | |
473 | } | |
474 | ||
475 | static int msm_gpio_get(struct gpio_chip *chip, unsigned offset) | |
476 | { | |
477 | const struct msm_pingroup *g; | |
478 | struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip); | |
479 | u32 val; | |
480 | ||
f365be09 | 481 | g = &pctrl->soc->groups[offset]; |
f393e489 BA |
482 | if (WARN_ON(g->io_reg < 0)) |
483 | return -EINVAL; | |
f365be09 BA |
484 | |
485 | val = readl(pctrl->regs + g->io_reg); | |
486 | return !!(val & BIT(g->in_bit)); | |
487 | } | |
488 | ||
489 | static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int value) | |
490 | { | |
491 | const struct msm_pingroup *g; | |
492 | struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip); | |
493 | unsigned long flags; | |
494 | u32 val; | |
495 | ||
f365be09 | 496 | g = &pctrl->soc->groups[offset]; |
f393e489 BA |
497 | if (WARN_ON(g->io_reg < 0)) |
498 | return; | |
f365be09 BA |
499 | |
500 | spin_lock_irqsave(&pctrl->lock, flags); | |
501 | ||
502 | val = readl(pctrl->regs + g->io_reg); | |
e476e77f AL |
503 | if (value) |
504 | val |= BIT(g->out_bit); | |
505 | else | |
506 | val &= ~BIT(g->out_bit); | |
f365be09 BA |
507 | writel(val, pctrl->regs + g->io_reg); |
508 | ||
509 | spin_unlock_irqrestore(&pctrl->lock, flags); | |
510 | } | |
511 | ||
512 | static int msm_gpio_to_irq(struct gpio_chip *chip, unsigned offset) | |
513 | { | |
514 | struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip); | |
515 | ||
516 | return irq_find_mapping(pctrl->domain, offset); | |
517 | } | |
518 | ||
519 | static int msm_gpio_request(struct gpio_chip *chip, unsigned offset) | |
520 | { | |
521 | int gpio = chip->base + offset; | |
522 | return pinctrl_request_gpio(gpio); | |
523 | } | |
524 | ||
525 | static void msm_gpio_free(struct gpio_chip *chip, unsigned offset) | |
526 | { | |
527 | int gpio = chip->base + offset; | |
528 | return pinctrl_free_gpio(gpio); | |
529 | } | |
530 | ||
531 | #ifdef CONFIG_DEBUG_FS | |
532 | #include <linux/seq_file.h> | |
533 | ||
534 | static void msm_gpio_dbg_show_one(struct seq_file *s, | |
535 | struct pinctrl_dev *pctldev, | |
536 | struct gpio_chip *chip, | |
537 | unsigned offset, | |
538 | unsigned gpio) | |
539 | { | |
540 | const struct msm_pingroup *g; | |
541 | struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip); | |
542 | unsigned func; | |
543 | int is_out; | |
544 | int drive; | |
545 | int pull; | |
546 | u32 ctl_reg; | |
547 | ||
1f2b2398 | 548 | static const char * const pulls[] = { |
f365be09 BA |
549 | "no pull", |
550 | "pull down", | |
551 | "keeper", | |
552 | "pull up" | |
553 | }; | |
554 | ||
555 | g = &pctrl->soc->groups[offset]; | |
556 | ctl_reg = readl(pctrl->regs + g->ctl_reg); | |
557 | ||
558 | is_out = !!(ctl_reg & BIT(g->oe_bit)); | |
559 | func = (ctl_reg >> g->mux_bit) & 7; | |
560 | drive = (ctl_reg >> g->drv_bit) & 7; | |
561 | pull = (ctl_reg >> g->pull_bit) & 3; | |
562 | ||
563 | seq_printf(s, " %-8s: %-3s %d", g->name, is_out ? "out" : "in", func); | |
564 | seq_printf(s, " %dmA", msm_regval_to_drive[drive]); | |
565 | seq_printf(s, " %s", pulls[pull]); | |
566 | } | |
567 | ||
568 | static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) | |
569 | { | |
570 | unsigned gpio = chip->base; | |
571 | unsigned i; | |
572 | ||
573 | for (i = 0; i < chip->ngpio; i++, gpio++) { | |
574 | msm_gpio_dbg_show_one(s, NULL, chip, i, gpio); | |
1f2b2398 | 575 | seq_puts(s, "\n"); |
f365be09 BA |
576 | } |
577 | } | |
578 | ||
579 | #else | |
580 | #define msm_gpio_dbg_show NULL | |
581 | #endif | |
582 | ||
583 | static struct gpio_chip msm_gpio_template = { | |
584 | .direction_input = msm_gpio_direction_input, | |
585 | .direction_output = msm_gpio_direction_output, | |
586 | .get = msm_gpio_get, | |
587 | .set = msm_gpio_set, | |
588 | .to_irq = msm_gpio_to_irq, | |
589 | .request = msm_gpio_request, | |
590 | .free = msm_gpio_free, | |
591 | .dbg_show = msm_gpio_dbg_show, | |
592 | }; | |
593 | ||
594 | /* For dual-edge interrupts in software, since some hardware has no | |
595 | * such support: | |
596 | * | |
597 | * At appropriate moments, this function may be called to flip the polarity | |
598 | * settings of both-edge irq lines to try and catch the next edge. | |
599 | * | |
600 | * The attempt is considered successful if: | |
601 | * - the status bit goes high, indicating that an edge was caught, or | |
602 | * - the input value of the gpio doesn't change during the attempt. | |
603 | * If the value changes twice during the process, that would cause the first | |
604 | * test to fail but would force the second, as two opposite | |
605 | * transitions would cause a detection no matter the polarity setting. | |
606 | * | |
607 | * The do-loop tries to sledge-hammer closed the timing hole between | |
608 | * the initial value-read and the polarity-write - if the line value changes | |
609 | * during that window, an interrupt is lost, the new polarity setting is | |
610 | * incorrect, and the first success test will fail, causing a retry. | |
611 | * | |
612 | * Algorithm comes from Google's msmgpio driver. | |
613 | */ | |
614 | static void msm_gpio_update_dual_edge_pos(struct msm_pinctrl *pctrl, | |
615 | const struct msm_pingroup *g, | |
616 | struct irq_data *d) | |
617 | { | |
618 | int loop_limit = 100; | |
619 | unsigned val, val2, intstat; | |
620 | unsigned pol; | |
621 | ||
622 | do { | |
623 | val = readl(pctrl->regs + g->io_reg) & BIT(g->in_bit); | |
624 | ||
625 | pol = readl(pctrl->regs + g->intr_cfg_reg); | |
626 | pol ^= BIT(g->intr_polarity_bit); | |
627 | writel(pol, pctrl->regs + g->intr_cfg_reg); | |
628 | ||
629 | val2 = readl(pctrl->regs + g->io_reg) & BIT(g->in_bit); | |
630 | intstat = readl(pctrl->regs + g->intr_status_reg); | |
631 | if (intstat || (val == val2)) | |
632 | return; | |
633 | } while (loop_limit-- > 0); | |
634 | dev_err(pctrl->dev, "dual-edge irq failed to stabilize, %#08x != %#08x\n", | |
635 | val, val2); | |
636 | } | |
637 | ||
638 | static void msm_gpio_irq_mask(struct irq_data *d) | |
639 | { | |
640 | const struct msm_pingroup *g; | |
641 | struct msm_pinctrl *pctrl; | |
642 | unsigned long flags; | |
643 | u32 val; | |
644 | ||
645 | pctrl = irq_data_get_irq_chip_data(d); | |
f365be09 | 646 | g = &pctrl->soc->groups[d->hwirq]; |
f393e489 BA |
647 | if (WARN_ON(g->intr_cfg_reg < 0)) |
648 | return; | |
f365be09 BA |
649 | |
650 | spin_lock_irqsave(&pctrl->lock, flags); | |
651 | ||
652 | val = readl(pctrl->regs + g->intr_cfg_reg); | |
653 | val &= ~BIT(g->intr_enable_bit); | |
654 | writel(val, pctrl->regs + g->intr_cfg_reg); | |
655 | ||
656 | clear_bit(d->hwirq, pctrl->enabled_irqs); | |
657 | ||
658 | spin_unlock_irqrestore(&pctrl->lock, flags); | |
659 | } | |
660 | ||
661 | static void msm_gpio_irq_unmask(struct irq_data *d) | |
662 | { | |
663 | const struct msm_pingroup *g; | |
664 | struct msm_pinctrl *pctrl; | |
665 | unsigned long flags; | |
666 | u32 val; | |
667 | ||
668 | pctrl = irq_data_get_irq_chip_data(d); | |
f365be09 | 669 | g = &pctrl->soc->groups[d->hwirq]; |
f393e489 BA |
670 | if (WARN_ON(g->intr_status_reg < 0)) |
671 | return; | |
f365be09 BA |
672 | |
673 | spin_lock_irqsave(&pctrl->lock, flags); | |
674 | ||
675 | val = readl(pctrl->regs + g->intr_status_reg); | |
676 | val &= ~BIT(g->intr_status_bit); | |
677 | writel(val, pctrl->regs + g->intr_status_reg); | |
678 | ||
679 | val = readl(pctrl->regs + g->intr_cfg_reg); | |
680 | val |= BIT(g->intr_enable_bit); | |
681 | writel(val, pctrl->regs + g->intr_cfg_reg); | |
682 | ||
683 | set_bit(d->hwirq, pctrl->enabled_irqs); | |
684 | ||
685 | spin_unlock_irqrestore(&pctrl->lock, flags); | |
686 | } | |
687 | ||
688 | static void msm_gpio_irq_ack(struct irq_data *d) | |
689 | { | |
690 | const struct msm_pingroup *g; | |
691 | struct msm_pinctrl *pctrl; | |
692 | unsigned long flags; | |
693 | u32 val; | |
694 | ||
695 | pctrl = irq_data_get_irq_chip_data(d); | |
f365be09 | 696 | g = &pctrl->soc->groups[d->hwirq]; |
f393e489 BA |
697 | if (WARN_ON(g->intr_status_reg < 0)) |
698 | return; | |
f365be09 BA |
699 | |
700 | spin_lock_irqsave(&pctrl->lock, flags); | |
701 | ||
702 | val = readl(pctrl->regs + g->intr_status_reg); | |
703 | val &= ~BIT(g->intr_status_bit); | |
704 | writel(val, pctrl->regs + g->intr_status_reg); | |
705 | ||
706 | if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) | |
707 | msm_gpio_update_dual_edge_pos(pctrl, g, d); | |
708 | ||
709 | spin_unlock_irqrestore(&pctrl->lock, flags); | |
710 | } | |
711 | ||
712 | #define INTR_TARGET_PROC_APPS 4 | |
713 | ||
714 | static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type) | |
715 | { | |
716 | const struct msm_pingroup *g; | |
717 | struct msm_pinctrl *pctrl; | |
718 | unsigned long flags; | |
719 | u32 val; | |
720 | ||
721 | pctrl = irq_data_get_irq_chip_data(d); | |
f365be09 | 722 | g = &pctrl->soc->groups[d->hwirq]; |
f393e489 BA |
723 | if (WARN_ON(g->intr_cfg_reg < 0)) |
724 | return -EINVAL; | |
f365be09 BA |
725 | |
726 | spin_lock_irqsave(&pctrl->lock, flags); | |
727 | ||
728 | /* | |
729 | * For hw without possibility of detecting both edges | |
730 | */ | |
731 | if (g->intr_detection_width == 1 && type == IRQ_TYPE_EDGE_BOTH) | |
732 | set_bit(d->hwirq, pctrl->dual_edge_irqs); | |
733 | else | |
734 | clear_bit(d->hwirq, pctrl->dual_edge_irqs); | |
735 | ||
736 | /* Route interrupts to application cpu */ | |
737 | val = readl(pctrl->regs + g->intr_target_reg); | |
738 | val &= ~(7 << g->intr_target_bit); | |
739 | val |= INTR_TARGET_PROC_APPS << g->intr_target_bit; | |
740 | writel(val, pctrl->regs + g->intr_target_reg); | |
741 | ||
742 | /* Update configuration for gpio. | |
743 | * RAW_STATUS_EN is left on for all gpio irqs. Due to the | |
744 | * internal circuitry of TLMM, toggling the RAW_STATUS | |
745 | * could cause the INTR_STATUS to be set for EDGE interrupts. | |
746 | */ | |
747 | val = readl(pctrl->regs + g->intr_cfg_reg); | |
748 | val |= BIT(g->intr_raw_status_bit); | |
749 | if (g->intr_detection_width == 2) { | |
750 | val &= ~(3 << g->intr_detection_bit); | |
751 | val &= ~(1 << g->intr_polarity_bit); | |
752 | switch (type) { | |
753 | case IRQ_TYPE_EDGE_RISING: | |
754 | val |= 1 << g->intr_detection_bit; | |
755 | val |= BIT(g->intr_polarity_bit); | |
756 | break; | |
757 | case IRQ_TYPE_EDGE_FALLING: | |
758 | val |= 2 << g->intr_detection_bit; | |
759 | val |= BIT(g->intr_polarity_bit); | |
760 | break; | |
761 | case IRQ_TYPE_EDGE_BOTH: | |
762 | val |= 3 << g->intr_detection_bit; | |
763 | val |= BIT(g->intr_polarity_bit); | |
764 | break; | |
765 | case IRQ_TYPE_LEVEL_LOW: | |
766 | break; | |
767 | case IRQ_TYPE_LEVEL_HIGH: | |
768 | val |= BIT(g->intr_polarity_bit); | |
769 | break; | |
770 | } | |
771 | } else if (g->intr_detection_width == 1) { | |
772 | val &= ~(1 << g->intr_detection_bit); | |
773 | val &= ~(1 << g->intr_polarity_bit); | |
774 | switch (type) { | |
775 | case IRQ_TYPE_EDGE_RISING: | |
776 | val |= BIT(g->intr_detection_bit); | |
777 | val |= BIT(g->intr_polarity_bit); | |
778 | break; | |
779 | case IRQ_TYPE_EDGE_FALLING: | |
780 | val |= BIT(g->intr_detection_bit); | |
781 | break; | |
782 | case IRQ_TYPE_EDGE_BOTH: | |
783 | val |= BIT(g->intr_detection_bit); | |
784 | break; | |
785 | case IRQ_TYPE_LEVEL_LOW: | |
786 | break; | |
787 | case IRQ_TYPE_LEVEL_HIGH: | |
788 | val |= BIT(g->intr_polarity_bit); | |
789 | break; | |
790 | } | |
791 | } else { | |
792 | BUG(); | |
793 | } | |
794 | writel(val, pctrl->regs + g->intr_cfg_reg); | |
795 | ||
796 | if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) | |
797 | msm_gpio_update_dual_edge_pos(pctrl, g, d); | |
798 | ||
799 | spin_unlock_irqrestore(&pctrl->lock, flags); | |
800 | ||
801 | if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) | |
802 | __irq_set_handler_locked(d->irq, handle_level_irq); | |
803 | else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) | |
804 | __irq_set_handler_locked(d->irq, handle_edge_irq); | |
805 | ||
806 | return 0; | |
807 | } | |
808 | ||
809 | static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on) | |
810 | { | |
811 | struct msm_pinctrl *pctrl; | |
812 | unsigned long flags; | |
813 | unsigned ngpio; | |
814 | ||
815 | pctrl = irq_data_get_irq_chip_data(d); | |
f365be09 BA |
816 | ngpio = pctrl->chip.ngpio; |
817 | ||
818 | spin_lock_irqsave(&pctrl->lock, flags); | |
819 | ||
820 | if (on) { | |
821 | if (bitmap_empty(pctrl->wake_irqs, ngpio)) | |
822 | enable_irq_wake(pctrl->irq); | |
823 | set_bit(d->hwirq, pctrl->wake_irqs); | |
824 | } else { | |
825 | clear_bit(d->hwirq, pctrl->wake_irqs); | |
826 | if (bitmap_empty(pctrl->wake_irqs, ngpio)) | |
827 | disable_irq_wake(pctrl->irq); | |
828 | } | |
829 | ||
830 | spin_unlock_irqrestore(&pctrl->lock, flags); | |
831 | ||
832 | return 0; | |
833 | } | |
834 | ||
835 | static unsigned int msm_gpio_irq_startup(struct irq_data *d) | |
836 | { | |
837 | struct msm_pinctrl *pctrl = irq_data_get_irq_chip_data(d); | |
838 | ||
839 | if (gpio_lock_as_irq(&pctrl->chip, d->hwirq)) { | |
840 | dev_err(pctrl->dev, "unable to lock HW IRQ %lu for IRQ\n", | |
841 | d->hwirq); | |
842 | } | |
843 | msm_gpio_irq_unmask(d); | |
844 | return 0; | |
845 | } | |
846 | ||
847 | static void msm_gpio_irq_shutdown(struct irq_data *d) | |
848 | { | |
849 | struct msm_pinctrl *pctrl = irq_data_get_irq_chip_data(d); | |
850 | ||
851 | msm_gpio_irq_mask(d); | |
852 | gpio_unlock_as_irq(&pctrl->chip, d->hwirq); | |
853 | } | |
854 | ||
855 | static struct irq_chip msm_gpio_irq_chip = { | |
856 | .name = "msmgpio", | |
857 | .irq_mask = msm_gpio_irq_mask, | |
858 | .irq_unmask = msm_gpio_irq_unmask, | |
859 | .irq_ack = msm_gpio_irq_ack, | |
860 | .irq_set_type = msm_gpio_irq_set_type, | |
861 | .irq_set_wake = msm_gpio_irq_set_wake, | |
862 | .irq_startup = msm_gpio_irq_startup, | |
863 | .irq_shutdown = msm_gpio_irq_shutdown, | |
864 | }; | |
865 | ||
866 | static void msm_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) | |
867 | { | |
868 | const struct msm_pingroup *g; | |
869 | struct msm_pinctrl *pctrl = irq_desc_get_handler_data(desc); | |
870 | struct irq_chip *chip = irq_get_chip(irq); | |
871 | int irq_pin; | |
872 | int handled = 0; | |
873 | u32 val; | |
874 | int i; | |
875 | ||
876 | chained_irq_enter(chip, desc); | |
877 | ||
878 | /* | |
1f2b2398 | 879 | * Each pin has it's own IRQ status register, so use |
f365be09 BA |
880 | * enabled_irq bitmap to limit the number of reads. |
881 | */ | |
882 | for_each_set_bit(i, pctrl->enabled_irqs, pctrl->chip.ngpio) { | |
883 | g = &pctrl->soc->groups[i]; | |
884 | val = readl(pctrl->regs + g->intr_status_reg); | |
885 | if (val & BIT(g->intr_status_bit)) { | |
886 | irq_pin = irq_find_mapping(pctrl->domain, i); | |
887 | generic_handle_irq(irq_pin); | |
888 | handled++; | |
889 | } | |
890 | } | |
891 | ||
1f2b2398 | 892 | /* No interrupts were flagged */ |
f365be09 BA |
893 | if (handled == 0) |
894 | handle_bad_irq(irq, desc); | |
895 | ||
896 | chained_irq_exit(chip, desc); | |
897 | } | |
898 | ||
899 | static int msm_gpio_init(struct msm_pinctrl *pctrl) | |
900 | { | |
901 | struct gpio_chip *chip; | |
902 | int irq; | |
903 | int ret; | |
904 | int i; | |
905 | int r; | |
906 | ||
907 | chip = &pctrl->chip; | |
908 | chip->base = 0; | |
909 | chip->ngpio = pctrl->soc->ngpios; | |
910 | chip->label = dev_name(pctrl->dev); | |
911 | chip->dev = pctrl->dev; | |
912 | chip->owner = THIS_MODULE; | |
913 | chip->of_node = pctrl->dev->of_node; | |
914 | ||
f365be09 BA |
915 | ret = gpiochip_add(&pctrl->chip); |
916 | if (ret) { | |
917 | dev_err(pctrl->dev, "Failed register gpiochip\n"); | |
918 | return ret; | |
919 | } | |
920 | ||
921 | ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), 0, 0, chip->ngpio); | |
922 | if (ret) { | |
923 | dev_err(pctrl->dev, "Failed to add pin range\n"); | |
924 | return ret; | |
925 | } | |
926 | ||
927 | pctrl->domain = irq_domain_add_linear(pctrl->dev->of_node, chip->ngpio, | |
928 | &irq_domain_simple_ops, NULL); | |
929 | if (!pctrl->domain) { | |
930 | dev_err(pctrl->dev, "Failed to register irq domain\n"); | |
931 | r = gpiochip_remove(&pctrl->chip); | |
932 | return -ENOSYS; | |
933 | } | |
934 | ||
935 | for (i = 0; i < chip->ngpio; i++) { | |
936 | irq = irq_create_mapping(pctrl->domain, i); | |
937 | irq_set_chip_and_handler(irq, &msm_gpio_irq_chip, handle_edge_irq); | |
938 | irq_set_chip_data(irq, pctrl); | |
939 | } | |
940 | ||
941 | irq_set_handler_data(pctrl->irq, pctrl); | |
942 | irq_set_chained_handler(pctrl->irq, msm_gpio_irq_handler); | |
943 | ||
944 | return 0; | |
945 | } | |
946 | ||
947 | int msm_pinctrl_probe(struct platform_device *pdev, | |
948 | const struct msm_pinctrl_soc_data *soc_data) | |
949 | { | |
950 | struct msm_pinctrl *pctrl; | |
951 | struct resource *res; | |
952 | int ret; | |
953 | ||
954 | pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); | |
955 | if (!pctrl) { | |
956 | dev_err(&pdev->dev, "Can't allocate msm_pinctrl\n"); | |
957 | return -ENOMEM; | |
958 | } | |
959 | pctrl->dev = &pdev->dev; | |
960 | pctrl->soc = soc_data; | |
961 | pctrl->chip = msm_gpio_template; | |
962 | ||
963 | spin_lock_init(&pctrl->lock); | |
964 | ||
965 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
966 | pctrl->regs = devm_ioremap_resource(&pdev->dev, res); | |
967 | if (IS_ERR(pctrl->regs)) | |
968 | return PTR_ERR(pctrl->regs); | |
969 | ||
f393e489 | 970 | pctrl->irq = platform_get_irq(pdev, 0); |
f365be09 BA |
971 | if (pctrl->irq < 0) { |
972 | dev_err(&pdev->dev, "No interrupt defined for msmgpio\n"); | |
973 | return pctrl->irq; | |
974 | } | |
975 | ||
976 | msm_pinctrl_desc.name = dev_name(&pdev->dev); | |
977 | msm_pinctrl_desc.pins = pctrl->soc->pins; | |
978 | msm_pinctrl_desc.npins = pctrl->soc->npins; | |
979 | pctrl->pctrl = pinctrl_register(&msm_pinctrl_desc, &pdev->dev, pctrl); | |
980 | if (!pctrl->pctrl) { | |
981 | dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); | |
982 | return -ENODEV; | |
983 | } | |
984 | ||
985 | ret = msm_gpio_init(pctrl); | |
986 | if (ret) { | |
987 | pinctrl_unregister(pctrl->pctrl); | |
988 | return ret; | |
989 | } | |
990 | ||
991 | platform_set_drvdata(pdev, pctrl); | |
992 | ||
993 | dev_dbg(&pdev->dev, "Probed Qualcomm pinctrl driver\n"); | |
994 | ||
995 | return 0; | |
996 | } | |
997 | EXPORT_SYMBOL(msm_pinctrl_probe); | |
998 | ||
999 | int msm_pinctrl_remove(struct platform_device *pdev) | |
1000 | { | |
1001 | struct msm_pinctrl *pctrl = platform_get_drvdata(pdev); | |
1002 | int ret; | |
1003 | ||
f393e489 BA |
1004 | ret = gpiochip_remove(&pctrl->chip); |
1005 | if (ret) { | |
1006 | dev_err(&pdev->dev, "Failed to remove gpiochip\n"); | |
1007 | return ret; | |
1008 | } | |
1009 | ||
f365be09 BA |
1010 | irq_set_chained_handler(pctrl->irq, NULL); |
1011 | irq_domain_remove(pctrl->domain); | |
f365be09 BA |
1012 | pinctrl_unregister(pctrl->pctrl); |
1013 | ||
1014 | return 0; | |
1015 | } | |
1016 | EXPORT_SYMBOL(msm_pinctrl_remove); | |
1017 |