]>
Commit | Line | Data |
---|---|---|
2ec1d359 AR |
1 | /* |
2 | * Generic GPIO driver for logic cells found in the Nomadik SoC | |
3 | * | |
4 | * Copyright (C) 2008,2009 STMicroelectronics | |
5 | * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it> | |
6 | * Rewritten based on work by Prafulla WADASKAR <prafulla.wadaskar@st.com> | |
33d78647 | 7 | * Copyright (C) 2011 Linus Walleij <linus.walleij@linaro.org> |
2ec1d359 AR |
8 | * |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | #include <linux/kernel.h> | |
14 | #include <linux/module.h> | |
15 | #include <linux/init.h> | |
16 | #include <linux/device.h> | |
3e3c62ca | 17 | #include <linux/platform_device.h> |
2ec1d359 | 18 | #include <linux/io.h> |
af7dc228 RV |
19 | #include <linux/clk.h> |
20 | #include <linux/err.h> | |
2ec1d359 AR |
21 | #include <linux/gpio.h> |
22 | #include <linux/spinlock.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/irq.h> | |
a60b57ed | 25 | #include <linux/irqdomain.h> |
5a0e3ad6 | 26 | #include <linux/slab.h> |
855f80cd | 27 | #include <linux/of_device.h> |
e98ea774 | 28 | #include <linux/pinctrl/pinctrl.h> |
dbfe8ca2 | 29 | #include <linux/pinctrl/pinmux.h> |
d41af627 | 30 | #include <linux/pinctrl/pinconf.h> |
dbfe8ca2 LW |
31 | /* Since we request GPIOs from ourself */ |
32 | #include <linux/pinctrl/consumer.h> | |
bb16bd9b | 33 | #include <linux/platform_data/pinctrl-nomadik.h> |
adfed159 | 34 | #include <asm/mach/irq.h> |
c3b9d1db | 35 | #include <mach/irqs.h> |
e98ea774 LW |
36 | #include "pinctrl-nomadik.h" |
37 | ||
2ec1d359 AR |
38 | /* |
39 | * The GPIO module in the Nomadik family of Systems-on-Chip is an | |
40 | * AMBA device, managing 32 pins and alternate functions. The logic block | |
9c66ee6f | 41 | * is currently used in the Nomadik and ux500. |
2ec1d359 AR |
42 | * |
43 | * Symbols in this file are called "nmk_gpio" for "nomadik gpio" | |
44 | */ | |
45 | ||
2ec1d359 AR |
46 | struct nmk_gpio_chip { |
47 | struct gpio_chip chip; | |
a60b57ed | 48 | struct irq_domain *domain; |
2ec1d359 | 49 | void __iomem *addr; |
af7dc228 | 50 | struct clk *clk; |
33b744b3 | 51 | unsigned int bank; |
2ec1d359 | 52 | unsigned int parent_irq; |
2c8bb0eb | 53 | int secondary_parent_irq; |
33b744b3 | 54 | u32 (*get_secondary_status)(unsigned int bank); |
01727e61 | 55 | void (*set_ioforce)(bool enable); |
c0fcb8db | 56 | spinlock_t lock; |
33d78647 | 57 | bool sleepmode; |
2ec1d359 AR |
58 | /* Keep track of configured edges */ |
59 | u32 edge_rising; | |
60 | u32 edge_falling; | |
b9df468d RV |
61 | u32 real_wake; |
62 | u32 rwimsc; | |
63 | u32 fwimsc; | |
6c12fe88 RV |
64 | u32 rimsc; |
65 | u32 fimsc; | |
bc6f5cf6 | 66 | u32 pull_up; |
ebc6178d | 67 | u32 lowemi; |
2ec1d359 AR |
68 | }; |
69 | ||
f1671bf5 JA |
70 | /** |
71 | * struct nmk_pinctrl - state container for the Nomadik pin controller | |
72 | * @dev: containing device pointer | |
73 | * @pctl: corresponding pin controller device | |
74 | * @soc: SoC data for this specific chip | |
75 | * @prcm_base: PRCM register range virtual base | |
76 | */ | |
e98ea774 LW |
77 | struct nmk_pinctrl { |
78 | struct device *dev; | |
79 | struct pinctrl_dev *pctl; | |
80 | const struct nmk_pinctrl_soc_data *soc; | |
f1671bf5 | 81 | void __iomem *prcm_base; |
e98ea774 LW |
82 | }; |
83 | ||
01727e61 RV |
84 | static struct nmk_gpio_chip * |
85 | nmk_gpio_chips[DIV_ROUND_UP(ARCH_NR_GPIOS, NMK_GPIO_PER_CHIP)]; | |
86 | ||
87 | static DEFINE_SPINLOCK(nmk_gpio_slpm_lock); | |
88 | ||
89 | #define NUM_BANKS ARRAY_SIZE(nmk_gpio_chips) | |
90 | ||
6f9a974c RV |
91 | static void __nmk_gpio_set_mode(struct nmk_gpio_chip *nmk_chip, |
92 | unsigned offset, int gpio_mode) | |
93 | { | |
94 | u32 bit = 1 << offset; | |
95 | u32 afunc, bfunc; | |
96 | ||
97 | afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & ~bit; | |
98 | bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & ~bit; | |
99 | if (gpio_mode & NMK_GPIO_ALT_A) | |
100 | afunc |= bit; | |
101 | if (gpio_mode & NMK_GPIO_ALT_B) | |
102 | bfunc |= bit; | |
103 | writel(afunc, nmk_chip->addr + NMK_GPIO_AFSLA); | |
104 | writel(bfunc, nmk_chip->addr + NMK_GPIO_AFSLB); | |
105 | } | |
106 | ||
81a3c298 RV |
107 | static void __nmk_gpio_set_slpm(struct nmk_gpio_chip *nmk_chip, |
108 | unsigned offset, enum nmk_gpio_slpm mode) | |
109 | { | |
110 | u32 bit = 1 << offset; | |
111 | u32 slpm; | |
112 | ||
113 | slpm = readl(nmk_chip->addr + NMK_GPIO_SLPC); | |
114 | if (mode == NMK_GPIO_SLPM_NOCHANGE) | |
115 | slpm |= bit; | |
116 | else | |
117 | slpm &= ~bit; | |
118 | writel(slpm, nmk_chip->addr + NMK_GPIO_SLPC); | |
119 | } | |
120 | ||
5b327edf RV |
121 | static void __nmk_gpio_set_pull(struct nmk_gpio_chip *nmk_chip, |
122 | unsigned offset, enum nmk_gpio_pull pull) | |
123 | { | |
124 | u32 bit = 1 << offset; | |
125 | u32 pdis; | |
126 | ||
127 | pdis = readl(nmk_chip->addr + NMK_GPIO_PDIS); | |
bc6f5cf6 | 128 | if (pull == NMK_GPIO_PULL_NONE) { |
5b327edf | 129 | pdis |= bit; |
bc6f5cf6 RA |
130 | nmk_chip->pull_up &= ~bit; |
131 | } else { | |
5b327edf | 132 | pdis &= ~bit; |
bc6f5cf6 RA |
133 | } |
134 | ||
5b327edf RV |
135 | writel(pdis, nmk_chip->addr + NMK_GPIO_PDIS); |
136 | ||
bc6f5cf6 RA |
137 | if (pull == NMK_GPIO_PULL_UP) { |
138 | nmk_chip->pull_up |= bit; | |
5b327edf | 139 | writel(bit, nmk_chip->addr + NMK_GPIO_DATS); |
bc6f5cf6 RA |
140 | } else if (pull == NMK_GPIO_PULL_DOWN) { |
141 | nmk_chip->pull_up &= ~bit; | |
5b327edf | 142 | writel(bit, nmk_chip->addr + NMK_GPIO_DATC); |
bc6f5cf6 | 143 | } |
5b327edf RV |
144 | } |
145 | ||
ebc6178d RV |
146 | static void __nmk_gpio_set_lowemi(struct nmk_gpio_chip *nmk_chip, |
147 | unsigned offset, bool lowemi) | |
148 | { | |
149 | u32 bit = BIT(offset); | |
150 | bool enabled = nmk_chip->lowemi & bit; | |
151 | ||
152 | if (lowemi == enabled) | |
153 | return; | |
154 | ||
155 | if (lowemi) | |
156 | nmk_chip->lowemi |= bit; | |
157 | else | |
158 | nmk_chip->lowemi &= ~bit; | |
159 | ||
160 | writel_relaxed(nmk_chip->lowemi, | |
161 | nmk_chip->addr + NMK_GPIO_LOWEMI); | |
162 | } | |
163 | ||
378be066 RV |
164 | static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip, |
165 | unsigned offset) | |
166 | { | |
167 | writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC); | |
168 | } | |
169 | ||
6720db7c RV |
170 | static void __nmk_gpio_set_output(struct nmk_gpio_chip *nmk_chip, |
171 | unsigned offset, int val) | |
172 | { | |
173 | if (val) | |
174 | writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATS); | |
175 | else | |
176 | writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATC); | |
177 | } | |
178 | ||
179 | static void __nmk_gpio_make_output(struct nmk_gpio_chip *nmk_chip, | |
180 | unsigned offset, int val) | |
181 | { | |
182 | writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRS); | |
183 | __nmk_gpio_set_output(nmk_chip, offset, val); | |
184 | } | |
185 | ||
01727e61 RV |
186 | static void __nmk_gpio_set_mode_safe(struct nmk_gpio_chip *nmk_chip, |
187 | unsigned offset, int gpio_mode, | |
188 | bool glitch) | |
189 | { | |
6c12fe88 RV |
190 | u32 rwimsc = nmk_chip->rwimsc; |
191 | u32 fwimsc = nmk_chip->fwimsc; | |
01727e61 RV |
192 | |
193 | if (glitch && nmk_chip->set_ioforce) { | |
194 | u32 bit = BIT(offset); | |
195 | ||
01727e61 RV |
196 | /* Prevent spurious wakeups */ |
197 | writel(rwimsc & ~bit, nmk_chip->addr + NMK_GPIO_RWIMSC); | |
198 | writel(fwimsc & ~bit, nmk_chip->addr + NMK_GPIO_FWIMSC); | |
199 | ||
200 | nmk_chip->set_ioforce(true); | |
201 | } | |
202 | ||
203 | __nmk_gpio_set_mode(nmk_chip, offset, gpio_mode); | |
204 | ||
205 | if (glitch && nmk_chip->set_ioforce) { | |
206 | nmk_chip->set_ioforce(false); | |
207 | ||
208 | writel(rwimsc, nmk_chip->addr + NMK_GPIO_RWIMSC); | |
209 | writel(fwimsc, nmk_chip->addr + NMK_GPIO_FWIMSC); | |
210 | } | |
211 | } | |
212 | ||
6c42ad1c RV |
213 | static void |
214 | nmk_gpio_disable_lazy_irq(struct nmk_gpio_chip *nmk_chip, unsigned offset) | |
215 | { | |
216 | u32 falling = nmk_chip->fimsc & BIT(offset); | |
217 | u32 rising = nmk_chip->rimsc & BIT(offset); | |
218 | int gpio = nmk_chip->chip.base + offset; | |
219 | int irq = NOMADIK_GPIO_TO_IRQ(gpio); | |
220 | struct irq_data *d = irq_get_irq_data(irq); | |
221 | ||
222 | if (!rising && !falling) | |
223 | return; | |
224 | ||
225 | if (!d || !irqd_irq_disabled(d)) | |
226 | return; | |
227 | ||
228 | if (rising) { | |
229 | nmk_chip->rimsc &= ~BIT(offset); | |
230 | writel_relaxed(nmk_chip->rimsc, | |
231 | nmk_chip->addr + NMK_GPIO_RIMSC); | |
232 | } | |
233 | ||
234 | if (falling) { | |
235 | nmk_chip->fimsc &= ~BIT(offset); | |
236 | writel_relaxed(nmk_chip->fimsc, | |
237 | nmk_chip->addr + NMK_GPIO_FIMSC); | |
238 | } | |
239 | ||
240 | dev_dbg(nmk_chip->chip.dev, "%d: clearing interrupt mask\n", gpio); | |
241 | } | |
242 | ||
f1671bf5 JA |
243 | static void nmk_write_masked(void __iomem *reg, u32 mask, u32 value) |
244 | { | |
245 | u32 val; | |
246 | ||
247 | val = readl(reg); | |
248 | val = ((val & ~mask) | (value & mask)); | |
249 | writel(val, reg); | |
250 | } | |
251 | ||
c22df08c JNG |
252 | static void nmk_prcm_altcx_set_mode(struct nmk_pinctrl *npct, |
253 | unsigned offset, unsigned alt_num) | |
254 | { | |
255 | int i; | |
256 | u16 reg; | |
257 | u8 bit; | |
258 | u8 alt_index; | |
259 | const struct prcm_gpiocr_altcx_pin_desc *pin_desc; | |
260 | const u16 *gpiocr_regs; | |
261 | ||
4ca075de FB |
262 | if (!npct->prcm_base) |
263 | return; | |
264 | ||
c22df08c JNG |
265 | if (alt_num > PRCM_IDX_GPIOCR_ALTC_MAX) { |
266 | dev_err(npct->dev, "PRCM GPIOCR: alternate-C%i is invalid\n", | |
267 | alt_num); | |
268 | return; | |
269 | } | |
270 | ||
271 | for (i = 0 ; i < npct->soc->npins_altcx ; i++) { | |
272 | if (npct->soc->altcx_pins[i].pin == offset) | |
273 | break; | |
274 | } | |
275 | if (i == npct->soc->npins_altcx) { | |
276 | dev_dbg(npct->dev, "PRCM GPIOCR: pin %i is not found\n", | |
277 | offset); | |
278 | return; | |
279 | } | |
280 | ||
281 | pin_desc = npct->soc->altcx_pins + i; | |
282 | gpiocr_regs = npct->soc->prcm_gpiocr_registers; | |
283 | ||
284 | /* | |
285 | * If alt_num is NULL, just clear current ALTCx selection | |
286 | * to make sure we come back to a pure ALTC selection | |
287 | */ | |
288 | if (!alt_num) { | |
289 | for (i = 0 ; i < PRCM_IDX_GPIOCR_ALTC_MAX ; i++) { | |
290 | if (pin_desc->altcx[i].used == true) { | |
291 | reg = gpiocr_regs[pin_desc->altcx[i].reg_index]; | |
292 | bit = pin_desc->altcx[i].control_bit; | |
f1671bf5 JA |
293 | if (readl(npct->prcm_base + reg) & BIT(bit)) { |
294 | nmk_write_masked(npct->prcm_base + reg, BIT(bit), 0); | |
c22df08c JNG |
295 | dev_dbg(npct->dev, |
296 | "PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n", | |
297 | offset, i+1); | |
298 | } | |
299 | } | |
300 | } | |
301 | return; | |
302 | } | |
303 | ||
304 | alt_index = alt_num - 1; | |
305 | if (pin_desc->altcx[alt_index].used == false) { | |
306 | dev_warn(npct->dev, | |
307 | "PRCM GPIOCR: pin %i: alternate-C%i does not exist\n", | |
308 | offset, alt_num); | |
309 | return; | |
310 | } | |
311 | ||
312 | /* | |
313 | * Check if any other ALTCx functions are activated on this pin | |
314 | * and disable it first. | |
315 | */ | |
316 | for (i = 0 ; i < PRCM_IDX_GPIOCR_ALTC_MAX ; i++) { | |
317 | if (i == alt_index) | |
318 | continue; | |
319 | if (pin_desc->altcx[i].used == true) { | |
320 | reg = gpiocr_regs[pin_desc->altcx[i].reg_index]; | |
321 | bit = pin_desc->altcx[i].control_bit; | |
f1671bf5 JA |
322 | if (readl(npct->prcm_base + reg) & BIT(bit)) { |
323 | nmk_write_masked(npct->prcm_base + reg, BIT(bit), 0); | |
c22df08c JNG |
324 | dev_dbg(npct->dev, |
325 | "PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n", | |
326 | offset, i+1); | |
327 | } | |
328 | } | |
329 | } | |
330 | ||
331 | reg = gpiocr_regs[pin_desc->altcx[alt_index].reg_index]; | |
332 | bit = pin_desc->altcx[alt_index].control_bit; | |
333 | dev_dbg(npct->dev, "PRCM GPIOCR: pin %i: alternate-C%i has been selected\n", | |
334 | offset, alt_index+1); | |
f1671bf5 | 335 | nmk_write_masked(npct->prcm_base + reg, BIT(bit), BIT(bit)); |
c22df08c JNG |
336 | } |
337 | ||
378be066 | 338 | static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset, |
01727e61 | 339 | pin_cfg_t cfg, bool sleep, unsigned int *slpmregs) |
378be066 RV |
340 | { |
341 | static const char *afnames[] = { | |
342 | [NMK_GPIO_ALT_GPIO] = "GPIO", | |
343 | [NMK_GPIO_ALT_A] = "A", | |
344 | [NMK_GPIO_ALT_B] = "B", | |
345 | [NMK_GPIO_ALT_C] = "C" | |
346 | }; | |
347 | static const char *pullnames[] = { | |
348 | [NMK_GPIO_PULL_NONE] = "none", | |
349 | [NMK_GPIO_PULL_UP] = "up", | |
350 | [NMK_GPIO_PULL_DOWN] = "down", | |
351 | [3] /* illegal */ = "??" | |
352 | }; | |
353 | static const char *slpmnames[] = { | |
7e3f7e59 RV |
354 | [NMK_GPIO_SLPM_INPUT] = "input/wakeup", |
355 | [NMK_GPIO_SLPM_NOCHANGE] = "no-change/no-wakeup", | |
378be066 RV |
356 | }; |
357 | ||
358 | int pin = PIN_NUM(cfg); | |
359 | int pull = PIN_PULL(cfg); | |
360 | int af = PIN_ALT(cfg); | |
361 | int slpm = PIN_SLPM(cfg); | |
6720db7c RV |
362 | int output = PIN_DIR(cfg); |
363 | int val = PIN_VAL(cfg); | |
01727e61 | 364 | bool glitch = af == NMK_GPIO_ALT_C; |
378be066 | 365 | |
dacdc96c RV |
366 | dev_dbg(nmk_chip->chip.dev, "pin %d [%#lx]: af %s, pull %s, slpm %s (%s%s)\n", |
367 | pin, cfg, afnames[af], pullnames[pull], slpmnames[slpm], | |
6720db7c RV |
368 | output ? "output " : "input", |
369 | output ? (val ? "high" : "low") : ""); | |
370 | ||
dacdc96c RV |
371 | if (sleep) { |
372 | int slpm_pull = PIN_SLPM_PULL(cfg); | |
373 | int slpm_output = PIN_SLPM_DIR(cfg); | |
374 | int slpm_val = PIN_SLPM_VAL(cfg); | |
375 | ||
3546d15c RV |
376 | af = NMK_GPIO_ALT_GPIO; |
377 | ||
dacdc96c RV |
378 | /* |
379 | * The SLPM_* values are normal values + 1 to allow zero to | |
380 | * mean "same as normal". | |
381 | */ | |
382 | if (slpm_pull) | |
383 | pull = slpm_pull - 1; | |
384 | if (slpm_output) | |
385 | output = slpm_output - 1; | |
386 | if (slpm_val) | |
387 | val = slpm_val - 1; | |
388 | ||
389 | dev_dbg(nmk_chip->chip.dev, "pin %d: sleep pull %s, dir %s, val %s\n", | |
390 | pin, | |
391 | slpm_pull ? pullnames[pull] : "same", | |
392 | slpm_output ? (output ? "output" : "input") : "same", | |
393 | slpm_val ? (val ? "high" : "low") : "same"); | |
394 | } | |
395 | ||
6720db7c RV |
396 | if (output) |
397 | __nmk_gpio_make_output(nmk_chip, offset, val); | |
398 | else { | |
399 | __nmk_gpio_make_input(nmk_chip, offset); | |
400 | __nmk_gpio_set_pull(nmk_chip, offset, pull); | |
401 | } | |
378be066 | 402 | |
ebc6178d RV |
403 | __nmk_gpio_set_lowemi(nmk_chip, offset, PIN_LOWEMI(cfg)); |
404 | ||
6c42ad1c RV |
405 | /* |
406 | * If the pin is switching to altfunc, and there was an interrupt | |
407 | * installed on it which has been lazy disabled, actually mask the | |
408 | * interrupt to prevent spurious interrupts that would occur while the | |
409 | * pin is under control of the peripheral. Only SKE does this. | |
410 | */ | |
411 | if (af != NMK_GPIO_ALT_GPIO) | |
412 | nmk_gpio_disable_lazy_irq(nmk_chip, offset); | |
413 | ||
01727e61 RV |
414 | /* |
415 | * If we've backed up the SLPM registers (glitch workaround), modify | |
416 | * the backups since they will be restored. | |
417 | */ | |
418 | if (slpmregs) { | |
419 | if (slpm == NMK_GPIO_SLPM_NOCHANGE) | |
420 | slpmregs[nmk_chip->bank] |= BIT(offset); | |
421 | else | |
422 | slpmregs[nmk_chip->bank] &= ~BIT(offset); | |
423 | } else | |
424 | __nmk_gpio_set_slpm(nmk_chip, offset, slpm); | |
425 | ||
426 | __nmk_gpio_set_mode_safe(nmk_chip, offset, af, glitch); | |
427 | } | |
428 | ||
429 | /* | |
430 | * Safe sequence used to switch IOs between GPIO and Alternate-C mode: | |
431 | * - Save SLPM registers | |
432 | * - Set SLPM=0 for the IOs you want to switch and others to 1 | |
433 | * - Configure the GPIO registers for the IOs that are being switched | |
434 | * - Set IOFORCE=1 | |
435 | * - Modify the AFLSA/B registers for the IOs that are being switched | |
436 | * - Set IOFORCE=0 | |
437 | * - Restore SLPM registers | |
438 | * - Any spurious wake up event during switch sequence to be ignored and | |
439 | * cleared | |
440 | */ | |
441 | static void nmk_gpio_glitch_slpm_init(unsigned int *slpm) | |
442 | { | |
443 | int i; | |
444 | ||
445 | for (i = 0; i < NUM_BANKS; i++) { | |
446 | struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; | |
447 | unsigned int temp = slpm[i]; | |
448 | ||
449 | if (!chip) | |
450 | break; | |
451 | ||
3c0227d2 RV |
452 | clk_enable(chip->clk); |
453 | ||
01727e61 RV |
454 | slpm[i] = readl(chip->addr + NMK_GPIO_SLPC); |
455 | writel(temp, chip->addr + NMK_GPIO_SLPC); | |
456 | } | |
457 | } | |
458 | ||
459 | static void nmk_gpio_glitch_slpm_restore(unsigned int *slpm) | |
460 | { | |
461 | int i; | |
462 | ||
463 | for (i = 0; i < NUM_BANKS; i++) { | |
464 | struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; | |
465 | ||
466 | if (!chip) | |
467 | break; | |
468 | ||
469 | writel(slpm[i], chip->addr + NMK_GPIO_SLPC); | |
3c0227d2 RV |
470 | |
471 | clk_disable(chip->clk); | |
01727e61 RV |
472 | } |
473 | } | |
474 | ||
475 | static int __nmk_config_pins(pin_cfg_t *cfgs, int num, bool sleep) | |
476 | { | |
477 | static unsigned int slpm[NUM_BANKS]; | |
478 | unsigned long flags; | |
479 | bool glitch = false; | |
480 | int ret = 0; | |
481 | int i; | |
482 | ||
483 | for (i = 0; i < num; i++) { | |
484 | if (PIN_ALT(cfgs[i]) == NMK_GPIO_ALT_C) { | |
485 | glitch = true; | |
486 | break; | |
487 | } | |
488 | } | |
489 | ||
490 | spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); | |
491 | ||
492 | if (glitch) { | |
493 | memset(slpm, 0xff, sizeof(slpm)); | |
494 | ||
495 | for (i = 0; i < num; i++) { | |
496 | int pin = PIN_NUM(cfgs[i]); | |
497 | int offset = pin % NMK_GPIO_PER_CHIP; | |
498 | ||
499 | if (PIN_ALT(cfgs[i]) == NMK_GPIO_ALT_C) | |
500 | slpm[pin / NMK_GPIO_PER_CHIP] &= ~BIT(offset); | |
501 | } | |
502 | ||
503 | nmk_gpio_glitch_slpm_init(slpm); | |
504 | } | |
505 | ||
506 | for (i = 0; i < num; i++) { | |
507 | struct nmk_gpio_chip *nmk_chip; | |
508 | int pin = PIN_NUM(cfgs[i]); | |
509 | ||
a60b57ed | 510 | nmk_chip = nmk_gpio_chips[pin / NMK_GPIO_PER_CHIP]; |
01727e61 RV |
511 | if (!nmk_chip) { |
512 | ret = -EINVAL; | |
513 | break; | |
514 | } | |
515 | ||
3c0227d2 | 516 | clk_enable(nmk_chip->clk); |
01727e61 | 517 | spin_lock(&nmk_chip->lock); |
a60b57ed | 518 | __nmk_config_pin(nmk_chip, pin % NMK_GPIO_PER_CHIP, |
01727e61 RV |
519 | cfgs[i], sleep, glitch ? slpm : NULL); |
520 | spin_unlock(&nmk_chip->lock); | |
3c0227d2 | 521 | clk_disable(nmk_chip->clk); |
01727e61 RV |
522 | } |
523 | ||
524 | if (glitch) | |
525 | nmk_gpio_glitch_slpm_restore(slpm); | |
526 | ||
527 | spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); | |
528 | ||
529 | return ret; | |
378be066 RV |
530 | } |
531 | ||
532 | /** | |
533 | * nmk_config_pin - configure a pin's mux attributes | |
534 | * @cfg: pin confguration | |
50bcd47c | 535 | * @sleep: Non-zero to apply the sleep mode configuration |
378be066 RV |
536 | * Configures a pin's mode (alternate function or GPIO), its pull up status, |
537 | * and its sleep mode based on the specified configuration. The @cfg is | |
538 | * usually one of the SoC specific macros defined in mach/<soc>-pins.h. These | |
539 | * are constructed using, and can be further enhanced with, the macros in | |
287f121c | 540 | * <linux/platform_data/pinctrl-nomadik.h> |
378be066 RV |
541 | * |
542 | * If a pin's mode is set to GPIO, it is configured as an input to avoid | |
543 | * side-effects. The gpio can be manipulated later using standard GPIO API | |
544 | * calls. | |
545 | */ | |
dacdc96c | 546 | int nmk_config_pin(pin_cfg_t cfg, bool sleep) |
378be066 | 547 | { |
01727e61 | 548 | return __nmk_config_pins(&cfg, 1, sleep); |
378be066 RV |
549 | } |
550 | EXPORT_SYMBOL(nmk_config_pin); | |
551 | ||
552 | /** | |
553 | * nmk_config_pins - configure several pins at once | |
554 | * @cfgs: array of pin configurations | |
555 | * @num: number of elments in the array | |
556 | * | |
557 | * Configures several pins using nmk_config_pin(). Refer to that function for | |
558 | * further information. | |
559 | */ | |
560 | int nmk_config_pins(pin_cfg_t *cfgs, int num) | |
561 | { | |
01727e61 | 562 | return __nmk_config_pins(cfgs, num, false); |
378be066 RV |
563 | } |
564 | EXPORT_SYMBOL(nmk_config_pins); | |
565 | ||
dacdc96c RV |
566 | int nmk_config_pins_sleep(pin_cfg_t *cfgs, int num) |
567 | { | |
01727e61 | 568 | return __nmk_config_pins(cfgs, num, true); |
dacdc96c RV |
569 | } |
570 | EXPORT_SYMBOL(nmk_config_pins_sleep); | |
571 | ||
81a3c298 RV |
572 | /** |
573 | * nmk_gpio_set_slpm() - configure the sleep mode of a pin | |
574 | * @gpio: pin number | |
575 | * @mode: NMK_GPIO_SLPM_INPUT or NMK_GPIO_SLPM_NOCHANGE, | |
576 | * | |
33d78647 LW |
577 | * This register is actually in the pinmux layer, not the GPIO block itself. |
578 | * The GPIO1B_SLPM register defines the GPIO mode when SLEEP/DEEP-SLEEP | |
579 | * mode is entered (i.e. when signal IOFORCE is HIGH by the platform code). | |
580 | * Each GPIO can be configured to be forced into GPIO mode when IOFORCE is | |
581 | * HIGH, overriding the normal setting defined by GPIO_AFSELx registers. | |
582 | * When IOFORCE returns LOW (by software, after SLEEP/DEEP-SLEEP exit), | |
583 | * the GPIOs return to the normal setting defined by GPIO_AFSELx registers. | |
7e3f7e59 | 584 | * |
33d78647 LW |
585 | * If @mode is NMK_GPIO_SLPM_INPUT, the corresponding GPIO is switched to GPIO |
586 | * mode when signal IOFORCE is HIGH (i.e. when SLEEP/DEEP-SLEEP mode is | |
587 | * entered) regardless of the altfunction selected. Also wake-up detection is | |
588 | * ENABLED. | |
589 | * | |
590 | * If @mode is NMK_GPIO_SLPM_NOCHANGE, the corresponding GPIO remains | |
591 | * controlled by NMK_GPIO_DATC, NMK_GPIO_DATS, NMK_GPIO_DIR, NMK_GPIO_PDIS | |
592 | * (for altfunction GPIO) or respective on-chip peripherals (for other | |
593 | * altfuncs) when IOFORCE is HIGH. Also wake-up detection DISABLED. | |
594 | * | |
595 | * Note that enable_irq_wake() will automatically enable wakeup detection. | |
81a3c298 RV |
596 | */ |
597 | int nmk_gpio_set_slpm(int gpio, enum nmk_gpio_slpm mode) | |
598 | { | |
599 | struct nmk_gpio_chip *nmk_chip; | |
600 | unsigned long flags; | |
601 | ||
a60b57ed | 602 | nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP]; |
81a3c298 RV |
603 | if (!nmk_chip) |
604 | return -EINVAL; | |
605 | ||
3c0227d2 | 606 | clk_enable(nmk_chip->clk); |
01727e61 RV |
607 | spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); |
608 | spin_lock(&nmk_chip->lock); | |
609 | ||
a60b57ed | 610 | __nmk_gpio_set_slpm(nmk_chip, gpio % NMK_GPIO_PER_CHIP, mode); |
01727e61 RV |
611 | |
612 | spin_unlock(&nmk_chip->lock); | |
613 | spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); | |
3c0227d2 | 614 | clk_disable(nmk_chip->clk); |
81a3c298 RV |
615 | |
616 | return 0; | |
617 | } | |
618 | ||
5b327edf RV |
619 | /** |
620 | * nmk_gpio_set_pull() - enable/disable pull up/down on a gpio | |
621 | * @gpio: pin number | |
622 | * @pull: one of NMK_GPIO_PULL_DOWN, NMK_GPIO_PULL_UP, and NMK_GPIO_PULL_NONE | |
623 | * | |
624 | * Enables/disables pull up/down on a specified pin. This only takes effect if | |
625 | * the pin is configured as an input (either explicitly or by the alternate | |
626 | * function). | |
627 | * | |
628 | * NOTE: If enabling the pull up/down, the caller must ensure that the GPIO is | |
629 | * configured as an input. Otherwise, due to the way the controller registers | |
630 | * work, this function will change the value output on the pin. | |
631 | */ | |
632 | int nmk_gpio_set_pull(int gpio, enum nmk_gpio_pull pull) | |
633 | { | |
634 | struct nmk_gpio_chip *nmk_chip; | |
635 | unsigned long flags; | |
636 | ||
a60b57ed | 637 | nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP]; |
5b327edf RV |
638 | if (!nmk_chip) |
639 | return -EINVAL; | |
640 | ||
3c0227d2 | 641 | clk_enable(nmk_chip->clk); |
5b327edf | 642 | spin_lock_irqsave(&nmk_chip->lock, flags); |
a60b57ed | 643 | __nmk_gpio_set_pull(nmk_chip, gpio % NMK_GPIO_PER_CHIP, pull); |
5b327edf | 644 | spin_unlock_irqrestore(&nmk_chip->lock, flags); |
3c0227d2 | 645 | clk_disable(nmk_chip->clk); |
5b327edf RV |
646 | |
647 | return 0; | |
648 | } | |
649 | ||
2ec1d359 | 650 | /* Mode functions */ |
9c66ee6f JA |
651 | /** |
652 | * nmk_gpio_set_mode() - set the mux mode of a gpio pin | |
653 | * @gpio: pin number | |
654 | * @gpio_mode: one of NMK_GPIO_ALT_GPIO, NMK_GPIO_ALT_A, | |
655 | * NMK_GPIO_ALT_B, and NMK_GPIO_ALT_C | |
656 | * | |
657 | * Sets the mode of the specified pin to one of the alternate functions or | |
658 | * plain GPIO. | |
659 | */ | |
2ec1d359 AR |
660 | int nmk_gpio_set_mode(int gpio, int gpio_mode) |
661 | { | |
662 | struct nmk_gpio_chip *nmk_chip; | |
663 | unsigned long flags; | |
2ec1d359 | 664 | |
a60b57ed | 665 | nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP]; |
2ec1d359 AR |
666 | if (!nmk_chip) |
667 | return -EINVAL; | |
668 | ||
3c0227d2 | 669 | clk_enable(nmk_chip->clk); |
2ec1d359 | 670 | spin_lock_irqsave(&nmk_chip->lock, flags); |
a60b57ed | 671 | __nmk_gpio_set_mode(nmk_chip, gpio % NMK_GPIO_PER_CHIP, gpio_mode); |
2ec1d359 | 672 | spin_unlock_irqrestore(&nmk_chip->lock, flags); |
3c0227d2 | 673 | clk_disable(nmk_chip->clk); |
2ec1d359 AR |
674 | |
675 | return 0; | |
676 | } | |
677 | EXPORT_SYMBOL(nmk_gpio_set_mode); | |
678 | ||
2249b19f JNG |
679 | static int nmk_prcm_gpiocr_get_mode(struct pinctrl_dev *pctldev, int gpio) |
680 | { | |
681 | int i; | |
682 | u16 reg; | |
683 | u8 bit; | |
684 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
685 | const struct prcm_gpiocr_altcx_pin_desc *pin_desc; | |
686 | const u16 *gpiocr_regs; | |
687 | ||
4ca075de FB |
688 | if (!npct->prcm_base) |
689 | return NMK_GPIO_ALT_C; | |
690 | ||
2249b19f JNG |
691 | for (i = 0; i < npct->soc->npins_altcx; i++) { |
692 | if (npct->soc->altcx_pins[i].pin == gpio) | |
693 | break; | |
694 | } | |
695 | if (i == npct->soc->npins_altcx) | |
696 | return NMK_GPIO_ALT_C; | |
697 | ||
698 | pin_desc = npct->soc->altcx_pins + i; | |
699 | gpiocr_regs = npct->soc->prcm_gpiocr_registers; | |
700 | for (i = 0; i < PRCM_IDX_GPIOCR_ALTC_MAX; i++) { | |
701 | if (pin_desc->altcx[i].used == true) { | |
702 | reg = gpiocr_regs[pin_desc->altcx[i].reg_index]; | |
703 | bit = pin_desc->altcx[i].control_bit; | |
f1671bf5 | 704 | if (readl(npct->prcm_base + reg) & BIT(bit)) |
2249b19f JNG |
705 | return NMK_GPIO_ALT_C+i+1; |
706 | } | |
707 | } | |
708 | return NMK_GPIO_ALT_C; | |
709 | } | |
710 | ||
2ec1d359 AR |
711 | int nmk_gpio_get_mode(int gpio) |
712 | { | |
713 | struct nmk_gpio_chip *nmk_chip; | |
714 | u32 afunc, bfunc, bit; | |
715 | ||
a60b57ed | 716 | nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP]; |
2ec1d359 AR |
717 | if (!nmk_chip) |
718 | return -EINVAL; | |
719 | ||
a60b57ed | 720 | bit = 1 << (gpio % NMK_GPIO_PER_CHIP); |
2ec1d359 | 721 | |
3c0227d2 RV |
722 | clk_enable(nmk_chip->clk); |
723 | ||
2ec1d359 AR |
724 | afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & bit; |
725 | bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & bit; | |
726 | ||
3c0227d2 RV |
727 | clk_disable(nmk_chip->clk); |
728 | ||
2ec1d359 AR |
729 | return (afunc ? NMK_GPIO_ALT_A : 0) | (bfunc ? NMK_GPIO_ALT_B : 0); |
730 | } | |
731 | EXPORT_SYMBOL(nmk_gpio_get_mode); | |
732 | ||
733 | ||
734 | /* IRQ functions */ | |
735 | static inline int nmk_gpio_get_bitmask(int gpio) | |
736 | { | |
a60b57ed | 737 | return 1 << (gpio % NMK_GPIO_PER_CHIP); |
2ec1d359 AR |
738 | } |
739 | ||
f272c00e | 740 | static void nmk_gpio_irq_ack(struct irq_data *d) |
2ec1d359 | 741 | { |
2ec1d359 AR |
742 | struct nmk_gpio_chip *nmk_chip; |
743 | ||
f272c00e | 744 | nmk_chip = irq_data_get_irq_chip_data(d); |
2ec1d359 AR |
745 | if (!nmk_chip) |
746 | return; | |
3c0227d2 RV |
747 | |
748 | clk_enable(nmk_chip->clk); | |
a60b57ed | 749 | writel(nmk_gpio_get_bitmask(d->hwirq), nmk_chip->addr + NMK_GPIO_IC); |
3c0227d2 | 750 | clk_disable(nmk_chip->clk); |
2ec1d359 AR |
751 | } |
752 | ||
4d4e20f7 RV |
753 | enum nmk_gpio_irq_type { |
754 | NORMAL, | |
755 | WAKE, | |
756 | }; | |
757 | ||
040e5ecd | 758 | static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip, |
4d4e20f7 RV |
759 | int gpio, enum nmk_gpio_irq_type which, |
760 | bool enable) | |
2ec1d359 | 761 | { |
040e5ecd | 762 | u32 bitmask = nmk_gpio_get_bitmask(gpio); |
6c12fe88 RV |
763 | u32 *rimscval; |
764 | u32 *fimscval; | |
765 | u32 rimscreg; | |
766 | u32 fimscreg; | |
767 | ||
768 | if (which == NORMAL) { | |
769 | rimscreg = NMK_GPIO_RIMSC; | |
770 | fimscreg = NMK_GPIO_FIMSC; | |
771 | rimscval = &nmk_chip->rimsc; | |
772 | fimscval = &nmk_chip->fimsc; | |
773 | } else { | |
774 | rimscreg = NMK_GPIO_RWIMSC; | |
775 | fimscreg = NMK_GPIO_FWIMSC; | |
776 | rimscval = &nmk_chip->rwimsc; | |
777 | fimscval = &nmk_chip->fwimsc; | |
778 | } | |
2ec1d359 | 779 | |
040e5ecd | 780 | /* we must individually set/clear the two edges */ |
2ec1d359 | 781 | if (nmk_chip->edge_rising & bitmask) { |
040e5ecd | 782 | if (enable) |
6c12fe88 | 783 | *rimscval |= bitmask; |
040e5ecd | 784 | else |
6c12fe88 RV |
785 | *rimscval &= ~bitmask; |
786 | writel(*rimscval, nmk_chip->addr + rimscreg); | |
2ec1d359 AR |
787 | } |
788 | if (nmk_chip->edge_falling & bitmask) { | |
040e5ecd | 789 | if (enable) |
6c12fe88 | 790 | *fimscval |= bitmask; |
040e5ecd | 791 | else |
6c12fe88 RV |
792 | *fimscval &= ~bitmask; |
793 | writel(*fimscval, nmk_chip->addr + fimscreg); | |
2ec1d359 | 794 | } |
040e5ecd | 795 | } |
2ec1d359 | 796 | |
b9df468d RV |
797 | static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip, |
798 | int gpio, bool on) | |
799 | { | |
b982ff0e RV |
800 | /* |
801 | * Ensure WAKEUP_ENABLE is on. No need to disable it if wakeup is | |
802 | * disabled, since setting SLPM to 1 increases power consumption, and | |
803 | * wakeup is anyhow controlled by the RIMSC and FIMSC registers. | |
804 | */ | |
805 | if (nmk_chip->sleepmode && on) { | |
e85bbc19 | 806 | __nmk_gpio_set_slpm(nmk_chip, gpio % NMK_GPIO_PER_CHIP, |
b982ff0e | 807 | NMK_GPIO_SLPM_WAKEUP_ENABLE); |
33d78647 LW |
808 | } |
809 | ||
b9df468d RV |
810 | __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, on); |
811 | } | |
812 | ||
813 | static int nmk_gpio_irq_maskunmask(struct irq_data *d, bool enable) | |
2ec1d359 | 814 | { |
2ec1d359 AR |
815 | struct nmk_gpio_chip *nmk_chip; |
816 | unsigned long flags; | |
040e5ecd | 817 | u32 bitmask; |
2ec1d359 | 818 | |
f272c00e | 819 | nmk_chip = irq_data_get_irq_chip_data(d); |
a60b57ed | 820 | bitmask = nmk_gpio_get_bitmask(d->hwirq); |
2ec1d359 | 821 | if (!nmk_chip) |
4d4e20f7 | 822 | return -EINVAL; |
2ec1d359 | 823 | |
3c0227d2 | 824 | clk_enable(nmk_chip->clk); |
b9df468d RV |
825 | spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); |
826 | spin_lock(&nmk_chip->lock); | |
827 | ||
a60b57ed | 828 | __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, enable); |
b9df468d RV |
829 | |
830 | if (!(nmk_chip->real_wake & bitmask)) | |
a60b57ed | 831 | __nmk_gpio_set_wake(nmk_chip, d->hwirq, enable); |
b9df468d RV |
832 | |
833 | spin_unlock(&nmk_chip->lock); | |
834 | spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); | |
3c0227d2 | 835 | clk_disable(nmk_chip->clk); |
4d4e20f7 RV |
836 | |
837 | return 0; | |
2ec1d359 AR |
838 | } |
839 | ||
f272c00e | 840 | static void nmk_gpio_irq_mask(struct irq_data *d) |
040e5ecd | 841 | { |
b9df468d | 842 | nmk_gpio_irq_maskunmask(d, false); |
4d4e20f7 | 843 | } |
040e5ecd | 844 | |
f272c00e | 845 | static void nmk_gpio_irq_unmask(struct irq_data *d) |
040e5ecd | 846 | { |
b9df468d | 847 | nmk_gpio_irq_maskunmask(d, true); |
4d4e20f7 RV |
848 | } |
849 | ||
f272c00e | 850 | static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on) |
4d4e20f7 | 851 | { |
7e3f7e59 RV |
852 | struct nmk_gpio_chip *nmk_chip; |
853 | unsigned long flags; | |
b9df468d | 854 | u32 bitmask; |
7e3f7e59 | 855 | |
f272c00e | 856 | nmk_chip = irq_data_get_irq_chip_data(d); |
7e3f7e59 RV |
857 | if (!nmk_chip) |
858 | return -EINVAL; | |
a60b57ed | 859 | bitmask = nmk_gpio_get_bitmask(d->hwirq); |
7e3f7e59 | 860 | |
3c0227d2 | 861 | clk_enable(nmk_chip->clk); |
01727e61 RV |
862 | spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); |
863 | spin_lock(&nmk_chip->lock); | |
864 | ||
479a0c7e | 865 | if (irqd_irq_disabled(d)) |
a60b57ed | 866 | __nmk_gpio_set_wake(nmk_chip, d->hwirq, on); |
b9df468d RV |
867 | |
868 | if (on) | |
869 | nmk_chip->real_wake |= bitmask; | |
870 | else | |
871 | nmk_chip->real_wake &= ~bitmask; | |
01727e61 RV |
872 | |
873 | spin_unlock(&nmk_chip->lock); | |
874 | spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); | |
3c0227d2 | 875 | clk_disable(nmk_chip->clk); |
7e3f7e59 RV |
876 | |
877 | return 0; | |
040e5ecd RV |
878 | } |
879 | ||
f272c00e | 880 | static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type) |
2ec1d359 | 881 | { |
479a0c7e | 882 | bool enabled = !irqd_irq_disabled(d); |
3c0227d2 | 883 | bool wake = irqd_is_wakeup_set(d); |
2ec1d359 AR |
884 | struct nmk_gpio_chip *nmk_chip; |
885 | unsigned long flags; | |
886 | u32 bitmask; | |
887 | ||
f272c00e | 888 | nmk_chip = irq_data_get_irq_chip_data(d); |
a60b57ed | 889 | bitmask = nmk_gpio_get_bitmask(d->hwirq); |
2ec1d359 AR |
890 | if (!nmk_chip) |
891 | return -EINVAL; | |
2ec1d359 AR |
892 | if (type & IRQ_TYPE_LEVEL_HIGH) |
893 | return -EINVAL; | |
894 | if (type & IRQ_TYPE_LEVEL_LOW) | |
895 | return -EINVAL; | |
896 | ||
3c0227d2 | 897 | clk_enable(nmk_chip->clk); |
2ec1d359 AR |
898 | spin_lock_irqsave(&nmk_chip->lock, flags); |
899 | ||
7a852d80 | 900 | if (enabled) |
a60b57ed | 901 | __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, false); |
4d4e20f7 | 902 | |
b9df468d | 903 | if (enabled || wake) |
a60b57ed | 904 | __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, false); |
7a852d80 | 905 | |
2ec1d359 AR |
906 | nmk_chip->edge_rising &= ~bitmask; |
907 | if (type & IRQ_TYPE_EDGE_RISING) | |
908 | nmk_chip->edge_rising |= bitmask; | |
2ec1d359 AR |
909 | |
910 | nmk_chip->edge_falling &= ~bitmask; | |
911 | if (type & IRQ_TYPE_EDGE_FALLING) | |
912 | nmk_chip->edge_falling |= bitmask; | |
2ec1d359 | 913 | |
7a852d80 | 914 | if (enabled) |
a60b57ed | 915 | __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, true); |
4d4e20f7 | 916 | |
b9df468d | 917 | if (enabled || wake) |
a60b57ed | 918 | __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, true); |
2ec1d359 | 919 | |
7a852d80 | 920 | spin_unlock_irqrestore(&nmk_chip->lock, flags); |
3c0227d2 | 921 | clk_disable(nmk_chip->clk); |
2ec1d359 AR |
922 | |
923 | return 0; | |
924 | } | |
925 | ||
3c0227d2 RV |
926 | static unsigned int nmk_gpio_irq_startup(struct irq_data *d) |
927 | { | |
928 | struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d); | |
2ec1d359 | 929 | |
3c0227d2 RV |
930 | clk_enable(nmk_chip->clk); |
931 | nmk_gpio_irq_unmask(d); | |
2ec1d359 AR |
932 | return 0; |
933 | } | |
934 | ||
3c0227d2 RV |
935 | static void nmk_gpio_irq_shutdown(struct irq_data *d) |
936 | { | |
937 | struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d); | |
938 | ||
939 | nmk_gpio_irq_mask(d); | |
940 | clk_disable(nmk_chip->clk); | |
941 | } | |
942 | ||
2ec1d359 AR |
943 | static struct irq_chip nmk_gpio_irq_chip = { |
944 | .name = "Nomadik-GPIO", | |
f272c00e LB |
945 | .irq_ack = nmk_gpio_irq_ack, |
946 | .irq_mask = nmk_gpio_irq_mask, | |
947 | .irq_unmask = nmk_gpio_irq_unmask, | |
948 | .irq_set_type = nmk_gpio_irq_set_type, | |
949 | .irq_set_wake = nmk_gpio_irq_set_wake, | |
3c0227d2 RV |
950 | .irq_startup = nmk_gpio_irq_startup, |
951 | .irq_shutdown = nmk_gpio_irq_shutdown, | |
4921e745 | 952 | .flags = IRQCHIP_MASK_ON_SUSPEND, |
2ec1d359 AR |
953 | }; |
954 | ||
33b744b3 RV |
955 | static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc, |
956 | u32 status) | |
2ec1d359 AR |
957 | { |
958 | struct nmk_gpio_chip *nmk_chip; | |
6845664a | 959 | struct irq_chip *host_chip = irq_get_chip(irq); |
2ec1d359 | 960 | |
adfed159 | 961 | chained_irq_enter(host_chip, desc); |
aaedaa2b | 962 | |
6845664a | 963 | nmk_chip = irq_get_handler_data(irq); |
33b744b3 RV |
964 | while (status) { |
965 | int bit = __ffs(status); | |
966 | ||
95f0bc9b | 967 | generic_handle_irq(irq_find_mapping(nmk_chip->domain, bit)); |
33b744b3 | 968 | status &= ~BIT(bit); |
2ec1d359 | 969 | } |
aaedaa2b | 970 | |
adfed159 | 971 | chained_irq_exit(host_chip, desc); |
2ec1d359 AR |
972 | } |
973 | ||
33b744b3 RV |
974 | static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) |
975 | { | |
6845664a | 976 | struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq); |
3c0227d2 RV |
977 | u32 status; |
978 | ||
979 | clk_enable(nmk_chip->clk); | |
980 | status = readl(nmk_chip->addr + NMK_GPIO_IS); | |
981 | clk_disable(nmk_chip->clk); | |
33b744b3 RV |
982 | |
983 | __nmk_gpio_irq_handler(irq, desc, status); | |
984 | } | |
985 | ||
986 | static void nmk_gpio_secondary_irq_handler(unsigned int irq, | |
987 | struct irq_desc *desc) | |
988 | { | |
6845664a | 989 | struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq); |
33b744b3 RV |
990 | u32 status = nmk_chip->get_secondary_status(nmk_chip->bank); |
991 | ||
992 | __nmk_gpio_irq_handler(irq, desc, status); | |
993 | } | |
994 | ||
2ec1d359 AR |
995 | static int nmk_gpio_init_irq(struct nmk_gpio_chip *nmk_chip) |
996 | { | |
6845664a TG |
997 | irq_set_chained_handler(nmk_chip->parent_irq, nmk_gpio_irq_handler); |
998 | irq_set_handler_data(nmk_chip->parent_irq, nmk_chip); | |
33b744b3 RV |
999 | |
1000 | if (nmk_chip->secondary_parent_irq >= 0) { | |
6845664a | 1001 | irq_set_chained_handler(nmk_chip->secondary_parent_irq, |
33b744b3 | 1002 | nmk_gpio_secondary_irq_handler); |
6845664a | 1003 | irq_set_handler_data(nmk_chip->secondary_parent_irq, nmk_chip); |
33b744b3 RV |
1004 | } |
1005 | ||
2ec1d359 AR |
1006 | return 0; |
1007 | } | |
1008 | ||
1009 | /* I/O Functions */ | |
dbfe8ca2 LW |
1010 | |
1011 | static int nmk_gpio_request(struct gpio_chip *chip, unsigned offset) | |
1012 | { | |
1013 | /* | |
1014 | * Map back to global GPIO space and request muxing, the direction | |
1015 | * parameter does not matter for this controller. | |
1016 | */ | |
1017 | int gpio = chip->base + offset; | |
1018 | ||
1019 | return pinctrl_request_gpio(gpio); | |
1020 | } | |
1021 | ||
1022 | static void nmk_gpio_free(struct gpio_chip *chip, unsigned offset) | |
1023 | { | |
1024 | int gpio = chip->base + offset; | |
1025 | ||
1026 | pinctrl_free_gpio(gpio); | |
1027 | } | |
1028 | ||
2ec1d359 AR |
1029 | static int nmk_gpio_make_input(struct gpio_chip *chip, unsigned offset) |
1030 | { | |
1031 | struct nmk_gpio_chip *nmk_chip = | |
1032 | container_of(chip, struct nmk_gpio_chip, chip); | |
1033 | ||
3c0227d2 RV |
1034 | clk_enable(nmk_chip->clk); |
1035 | ||
2ec1d359 | 1036 | writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC); |
3c0227d2 RV |
1037 | |
1038 | clk_disable(nmk_chip->clk); | |
1039 | ||
2ec1d359 AR |
1040 | return 0; |
1041 | } | |
1042 | ||
2ec1d359 AR |
1043 | static int nmk_gpio_get_input(struct gpio_chip *chip, unsigned offset) |
1044 | { | |
1045 | struct nmk_gpio_chip *nmk_chip = | |
1046 | container_of(chip, struct nmk_gpio_chip, chip); | |
1047 | u32 bit = 1 << offset; | |
3c0227d2 RV |
1048 | int value; |
1049 | ||
1050 | clk_enable(nmk_chip->clk); | |
2ec1d359 | 1051 | |
3c0227d2 | 1052 | value = (readl(nmk_chip->addr + NMK_GPIO_DAT) & bit) != 0; |
2ec1d359 | 1053 | |
3c0227d2 RV |
1054 | clk_disable(nmk_chip->clk); |
1055 | ||
1056 | return value; | |
2ec1d359 AR |
1057 | } |
1058 | ||
1059 | static void nmk_gpio_set_output(struct gpio_chip *chip, unsigned offset, | |
1060 | int val) | |
1061 | { | |
1062 | struct nmk_gpio_chip *nmk_chip = | |
1063 | container_of(chip, struct nmk_gpio_chip, chip); | |
2ec1d359 | 1064 | |
3c0227d2 RV |
1065 | clk_enable(nmk_chip->clk); |
1066 | ||
6720db7c | 1067 | __nmk_gpio_set_output(nmk_chip, offset, val); |
3c0227d2 RV |
1068 | |
1069 | clk_disable(nmk_chip->clk); | |
2ec1d359 AR |
1070 | } |
1071 | ||
6647c6c0 RV |
1072 | static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned offset, |
1073 | int val) | |
1074 | { | |
1075 | struct nmk_gpio_chip *nmk_chip = | |
1076 | container_of(chip, struct nmk_gpio_chip, chip); | |
1077 | ||
3c0227d2 RV |
1078 | clk_enable(nmk_chip->clk); |
1079 | ||
6720db7c | 1080 | __nmk_gpio_make_output(nmk_chip, offset, val); |
6647c6c0 | 1081 | |
3c0227d2 RV |
1082 | clk_disable(nmk_chip->clk); |
1083 | ||
6647c6c0 RV |
1084 | return 0; |
1085 | } | |
1086 | ||
0d2aec9c RV |
1087 | static int nmk_gpio_to_irq(struct gpio_chip *chip, unsigned offset) |
1088 | { | |
1089 | struct nmk_gpio_chip *nmk_chip = | |
1090 | container_of(chip, struct nmk_gpio_chip, chip); | |
1091 | ||
268300be | 1092 | return irq_create_mapping(nmk_chip->domain, offset); |
0d2aec9c RV |
1093 | } |
1094 | ||
d0b543c7 RV |
1095 | #ifdef CONFIG_DEBUG_FS |
1096 | ||
1097 | #include <linux/seq_file.h> | |
1098 | ||
2249b19f JNG |
1099 | static void nmk_gpio_dbg_show_one(struct seq_file *s, |
1100 | struct pinctrl_dev *pctldev, struct gpio_chip *chip, | |
1101 | unsigned offset, unsigned gpio) | |
d0b543c7 | 1102 | { |
6f4350a6 | 1103 | const char *label = gpiochip_is_requested(chip, offset); |
d0b543c7 RV |
1104 | struct nmk_gpio_chip *nmk_chip = |
1105 | container_of(chip, struct nmk_gpio_chip, chip); | |
6f4350a6 LW |
1106 | int mode; |
1107 | bool is_out; | |
1108 | bool pull; | |
1109 | u32 bit = 1 << offset; | |
d0b543c7 RV |
1110 | const char *modes[] = { |
1111 | [NMK_GPIO_ALT_GPIO] = "gpio", | |
1112 | [NMK_GPIO_ALT_A] = "altA", | |
1113 | [NMK_GPIO_ALT_B] = "altB", | |
1114 | [NMK_GPIO_ALT_C] = "altC", | |
2249b19f JNG |
1115 | [NMK_GPIO_ALT_C+1] = "altC1", |
1116 | [NMK_GPIO_ALT_C+2] = "altC2", | |
1117 | [NMK_GPIO_ALT_C+3] = "altC3", | |
1118 | [NMK_GPIO_ALT_C+4] = "altC4", | |
d0b543c7 RV |
1119 | }; |
1120 | ||
3c0227d2 | 1121 | clk_enable(nmk_chip->clk); |
6f4350a6 LW |
1122 | is_out = !!(readl(nmk_chip->addr + NMK_GPIO_DIR) & bit); |
1123 | pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & bit); | |
1124 | mode = nmk_gpio_get_mode(gpio); | |
2249b19f JNG |
1125 | if ((mode == NMK_GPIO_ALT_C) && pctldev) |
1126 | mode = nmk_prcm_gpiocr_get_mode(pctldev, gpio); | |
6f4350a6 LW |
1127 | |
1128 | seq_printf(s, " gpio-%-3d (%-20.20s) %s %s %s %s", | |
1129 | gpio, label ?: "(none)", | |
1130 | is_out ? "out" : "in ", | |
1131 | chip->get | |
1132 | ? (chip->get(chip, offset) ? "hi" : "lo") | |
1133 | : "? ", | |
1134 | (mode < 0) ? "unknown" : modes[mode], | |
1135 | pull ? "pull" : "none"); | |
1136 | ||
1137 | if (label && !is_out) { | |
1138 | int irq = gpio_to_irq(gpio); | |
1139 | struct irq_desc *desc = irq_to_desc(irq); | |
1140 | ||
1141 | /* This races with request_irq(), set_irq_type(), | |
1142 | * and set_irq_wake() ... but those are "rare". | |
1143 | */ | |
1144 | if (irq >= 0 && desc->action) { | |
1145 | char *trigger; | |
1146 | u32 bitmask = nmk_gpio_get_bitmask(gpio); | |
1147 | ||
1148 | if (nmk_chip->edge_rising & bitmask) | |
1149 | trigger = "edge-rising"; | |
1150 | else if (nmk_chip->edge_falling & bitmask) | |
1151 | trigger = "edge-falling"; | |
1152 | else | |
1153 | trigger = "edge-undefined"; | |
1154 | ||
1155 | seq_printf(s, " irq-%d %s%s", | |
1156 | irq, trigger, | |
1157 | irqd_is_wakeup_set(&desc->irq_data) | |
1158 | ? " wakeup" : ""); | |
8ea72a30 | 1159 | } |
6f4350a6 LW |
1160 | } |
1161 | clk_disable(nmk_chip->clk); | |
1162 | } | |
1163 | ||
1164 | static void nmk_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) | |
1165 | { | |
1166 | unsigned i; | |
1167 | unsigned gpio = chip->base; | |
8ea72a30 | 1168 | |
6f4350a6 | 1169 | for (i = 0; i < chip->ngpio; i++, gpio++) { |
2249b19f | 1170 | nmk_gpio_dbg_show_one(s, NULL, chip, i, gpio); |
d0b543c7 RV |
1171 | seq_printf(s, "\n"); |
1172 | } | |
1173 | } | |
1174 | ||
1175 | #else | |
6f4350a6 | 1176 | static inline void nmk_gpio_dbg_show_one(struct seq_file *s, |
2249b19f | 1177 | struct pinctrl_dev *pctldev, |
6f4350a6 LW |
1178 | struct gpio_chip *chip, |
1179 | unsigned offset, unsigned gpio) | |
1180 | { | |
1181 | } | |
d0b543c7 RV |
1182 | #define nmk_gpio_dbg_show NULL |
1183 | #endif | |
1184 | ||
2ec1d359 AR |
1185 | /* This structure is replicated for each GPIO block allocated at probe time */ |
1186 | static struct gpio_chip nmk_gpio_template = { | |
dbfe8ca2 LW |
1187 | .request = nmk_gpio_request, |
1188 | .free = nmk_gpio_free, | |
2ec1d359 AR |
1189 | .direction_input = nmk_gpio_make_input, |
1190 | .get = nmk_gpio_get_input, | |
1191 | .direction_output = nmk_gpio_make_output, | |
1192 | .set = nmk_gpio_set_output, | |
0d2aec9c | 1193 | .to_irq = nmk_gpio_to_irq, |
d0b543c7 | 1194 | .dbg_show = nmk_gpio_dbg_show, |
2ec1d359 AR |
1195 | .can_sleep = 0, |
1196 | }; | |
1197 | ||
3c0227d2 RV |
1198 | void nmk_gpio_clocks_enable(void) |
1199 | { | |
1200 | int i; | |
1201 | ||
1202 | for (i = 0; i < NUM_BANKS; i++) { | |
1203 | struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; | |
1204 | ||
1205 | if (!chip) | |
1206 | continue; | |
1207 | ||
1208 | clk_enable(chip->clk); | |
1209 | } | |
1210 | } | |
1211 | ||
1212 | void nmk_gpio_clocks_disable(void) | |
1213 | { | |
1214 | int i; | |
1215 | ||
1216 | for (i = 0; i < NUM_BANKS; i++) { | |
1217 | struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; | |
1218 | ||
1219 | if (!chip) | |
1220 | continue; | |
1221 | ||
1222 | clk_disable(chip->clk); | |
1223 | } | |
1224 | } | |
1225 | ||
b9df468d RV |
1226 | /* |
1227 | * Called from the suspend/resume path to only keep the real wakeup interrupts | |
1228 | * (those that have had set_irq_wake() called on them) as wakeup interrupts, | |
1229 | * and not the rest of the interrupts which we needed to have as wakeups for | |
1230 | * cpuidle. | |
1231 | * | |
1232 | * PM ops are not used since this needs to be done at the end, after all the | |
1233 | * other drivers are done with their suspend callbacks. | |
1234 | */ | |
1235 | void nmk_gpio_wakeups_suspend(void) | |
1236 | { | |
1237 | int i; | |
1238 | ||
1239 | for (i = 0; i < NUM_BANKS; i++) { | |
1240 | struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; | |
1241 | ||
1242 | if (!chip) | |
1243 | break; | |
1244 | ||
3c0227d2 RV |
1245 | clk_enable(chip->clk); |
1246 | ||
b9df468d RV |
1247 | writel(chip->rwimsc & chip->real_wake, |
1248 | chip->addr + NMK_GPIO_RWIMSC); | |
1249 | writel(chip->fwimsc & chip->real_wake, | |
1250 | chip->addr + NMK_GPIO_FWIMSC); | |
1251 | ||
3c0227d2 | 1252 | clk_disable(chip->clk); |
b9df468d RV |
1253 | } |
1254 | } | |
1255 | ||
1256 | void nmk_gpio_wakeups_resume(void) | |
1257 | { | |
1258 | int i; | |
1259 | ||
1260 | for (i = 0; i < NUM_BANKS; i++) { | |
1261 | struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; | |
1262 | ||
1263 | if (!chip) | |
1264 | break; | |
1265 | ||
3c0227d2 RV |
1266 | clk_enable(chip->clk); |
1267 | ||
b9df468d RV |
1268 | writel(chip->rwimsc, chip->addr + NMK_GPIO_RWIMSC); |
1269 | writel(chip->fwimsc, chip->addr + NMK_GPIO_FWIMSC); | |
1270 | ||
3c0227d2 | 1271 | clk_disable(chip->clk); |
b9df468d RV |
1272 | } |
1273 | } | |
1274 | ||
bc6f5cf6 RA |
1275 | /* |
1276 | * Read the pull up/pull down status. | |
1277 | * A bit set in 'pull_up' means that pull up | |
1278 | * is selected if pull is enabled in PDIS register. | |
1279 | * Note: only pull up/down set via this driver can | |
1280 | * be detected due to HW limitations. | |
1281 | */ | |
1282 | void nmk_gpio_read_pull(int gpio_bank, u32 *pull_up) | |
1283 | { | |
1284 | if (gpio_bank < NUM_BANKS) { | |
1285 | struct nmk_gpio_chip *chip = nmk_gpio_chips[gpio_bank]; | |
1286 | ||
1287 | if (!chip) | |
1288 | return; | |
1289 | ||
1290 | *pull_up = chip->pull_up; | |
1291 | } | |
1292 | } | |
1293 | ||
5212d096 AL |
1294 | static int nmk_gpio_irq_map(struct irq_domain *d, unsigned int irq, |
1295 | irq_hw_number_t hwirq) | |
a60b57ed LJ |
1296 | { |
1297 | struct nmk_gpio_chip *nmk_chip = d->host_data; | |
1298 | ||
1299 | if (!nmk_chip) | |
1300 | return -EINVAL; | |
1301 | ||
1302 | irq_set_chip_and_handler(irq, &nmk_gpio_irq_chip, handle_edge_irq); | |
1303 | set_irq_flags(irq, IRQF_VALID); | |
1304 | irq_set_chip_data(irq, nmk_chip); | |
1305 | irq_set_irq_type(irq, IRQ_TYPE_EDGE_FALLING); | |
1306 | ||
1307 | return 0; | |
1308 | } | |
1309 | ||
1310 | const struct irq_domain_ops nmk_gpio_irq_simple_ops = { | |
1311 | .map = nmk_gpio_irq_map, | |
1312 | .xlate = irq_domain_xlate_twocell, | |
1313 | }; | |
1314 | ||
150632b0 | 1315 | static int nmk_gpio_probe(struct platform_device *dev) |
2ec1d359 | 1316 | { |
3e3c62ca | 1317 | struct nmk_gpio_platform_data *pdata = dev->dev.platform_data; |
513c27f8 | 1318 | struct device_node *np = dev->dev.of_node; |
2ec1d359 AR |
1319 | struct nmk_gpio_chip *nmk_chip; |
1320 | struct gpio_chip *chip; | |
3e3c62ca | 1321 | struct resource *res; |
af7dc228 | 1322 | struct clk *clk; |
33b744b3 | 1323 | int secondary_irq; |
8d91771c | 1324 | void __iomem *base; |
832b6cdf | 1325 | int irq_start = 0; |
3e3c62ca | 1326 | int irq; |
2ec1d359 AR |
1327 | int ret; |
1328 | ||
513c27f8 LJ |
1329 | if (!pdata && !np) { |
1330 | dev_err(&dev->dev, "No platform data or device tree found\n"); | |
3e3c62ca | 1331 | return -ENODEV; |
513c27f8 LJ |
1332 | } |
1333 | ||
1334 | if (np) { | |
5e754f33 | 1335 | pdata = devm_kzalloc(&dev->dev, sizeof(*pdata), GFP_KERNEL); |
513c27f8 LJ |
1336 | if (!pdata) |
1337 | return -ENOMEM; | |
1338 | ||
612e1d5f | 1339 | if (of_get_property(np, "st,supports-sleepmode", NULL)) |
513c27f8 LJ |
1340 | pdata->supports_sleepmode = true; |
1341 | ||
1342 | if (of_property_read_u32(np, "gpio-bank", &dev->id)) { | |
1343 | dev_err(&dev->dev, "gpio-bank property not found\n"); | |
1344 | ret = -EINVAL; | |
a60b57ed | 1345 | goto out; |
513c27f8 LJ |
1346 | } |
1347 | ||
1348 | pdata->first_gpio = dev->id * NMK_GPIO_PER_CHIP; | |
1349 | pdata->num_gpio = NMK_GPIO_PER_CHIP; | |
1350 | } | |
3e3c62ca RV |
1351 | |
1352 | res = platform_get_resource(dev, IORESOURCE_MEM, 0); | |
1353 | if (!res) { | |
1354 | ret = -ENOENT; | |
1355 | goto out; | |
1356 | } | |
1357 | ||
1358 | irq = platform_get_irq(dev, 0); | |
1359 | if (irq < 0) { | |
1360 | ret = irq; | |
1361 | goto out; | |
1362 | } | |
1363 | ||
33b744b3 RV |
1364 | secondary_irq = platform_get_irq(dev, 1); |
1365 | if (secondary_irq >= 0 && !pdata->get_secondary_status) { | |
1366 | ret = -EINVAL; | |
1367 | goto out; | |
1368 | } | |
1369 | ||
5e754f33 | 1370 | base = devm_request_and_ioremap(&dev->dev, res); |
8d91771c LW |
1371 | if (!base) { |
1372 | ret = -ENOMEM; | |
5e754f33 | 1373 | goto out; |
8d91771c LW |
1374 | } |
1375 | ||
5e754f33 | 1376 | clk = devm_clk_get(&dev->dev, NULL); |
af7dc228 RV |
1377 | if (IS_ERR(clk)) { |
1378 | ret = PTR_ERR(clk); | |
5e754f33 | 1379 | goto out; |
af7dc228 | 1380 | } |
efec381c | 1381 | clk_prepare(clk); |
af7dc228 | 1382 | |
5e754f33 | 1383 | nmk_chip = devm_kzalloc(&dev->dev, sizeof(*nmk_chip), GFP_KERNEL); |
2ec1d359 AR |
1384 | if (!nmk_chip) { |
1385 | ret = -ENOMEM; | |
5e754f33 | 1386 | goto out; |
2ec1d359 | 1387 | } |
513c27f8 | 1388 | |
2ec1d359 AR |
1389 | /* |
1390 | * The virt address in nmk_chip->addr is in the nomadik register space, | |
1391 | * so we can simply convert the resource address, without remapping | |
1392 | */ | |
33b744b3 | 1393 | nmk_chip->bank = dev->id; |
af7dc228 | 1394 | nmk_chip->clk = clk; |
8d91771c | 1395 | nmk_chip->addr = base; |
2ec1d359 | 1396 | nmk_chip->chip = nmk_gpio_template; |
3e3c62ca | 1397 | nmk_chip->parent_irq = irq; |
33b744b3 RV |
1398 | nmk_chip->secondary_parent_irq = secondary_irq; |
1399 | nmk_chip->get_secondary_status = pdata->get_secondary_status; | |
01727e61 | 1400 | nmk_chip->set_ioforce = pdata->set_ioforce; |
33d78647 | 1401 | nmk_chip->sleepmode = pdata->supports_sleepmode; |
c0fcb8db | 1402 | spin_lock_init(&nmk_chip->lock); |
2ec1d359 AR |
1403 | |
1404 | chip = &nmk_chip->chip; | |
1405 | chip->base = pdata->first_gpio; | |
e493e06f | 1406 | chip->ngpio = pdata->num_gpio; |
8d568ae5 | 1407 | chip->label = pdata->name ?: dev_name(&dev->dev); |
2ec1d359 AR |
1408 | chip->dev = &dev->dev; |
1409 | chip->owner = THIS_MODULE; | |
1410 | ||
ebc6178d RV |
1411 | clk_enable(nmk_chip->clk); |
1412 | nmk_chip->lowemi = readl_relaxed(nmk_chip->addr + NMK_GPIO_LOWEMI); | |
1413 | clk_disable(nmk_chip->clk); | |
1414 | ||
072e82a1 | 1415 | #ifdef CONFIG_OF_GPIO |
513c27f8 | 1416 | chip->of_node = np; |
072e82a1 | 1417 | #endif |
513c27f8 | 1418 | |
2ec1d359 AR |
1419 | ret = gpiochip_add(&nmk_chip->chip); |
1420 | if (ret) | |
5e754f33 | 1421 | goto out; |
2ec1d359 | 1422 | |
01727e61 RV |
1423 | BUG_ON(nmk_chip->bank >= ARRAY_SIZE(nmk_gpio_chips)); |
1424 | ||
1425 | nmk_gpio_chips[nmk_chip->bank] = nmk_chip; | |
513c27f8 | 1426 | |
3e3c62ca | 1427 | platform_set_drvdata(dev, nmk_chip); |
2ec1d359 | 1428 | |
51f58c68 | 1429 | if (!np) |
6054b9ca | 1430 | irq_start = NOMADIK_GPIO_TO_IRQ(pdata->first_gpio); |
38843e29 | 1431 | nmk_chip->domain = irq_domain_add_simple(np, |
6054b9ca LW |
1432 | NMK_GPIO_PER_CHIP, irq_start, |
1433 | &nmk_gpio_irq_simple_ops, nmk_chip); | |
a60b57ed | 1434 | if (!nmk_chip->domain) { |
2ee38d4d | 1435 | dev_err(&dev->dev, "failed to create irqdomain\n"); |
a60b57ed | 1436 | ret = -ENOSYS; |
5e754f33 | 1437 | goto out; |
a60b57ed LJ |
1438 | } |
1439 | ||
2ec1d359 AR |
1440 | nmk_gpio_init_irq(nmk_chip); |
1441 | ||
513c27f8 LJ |
1442 | dev_info(&dev->dev, "at address %p\n", nmk_chip->addr); |
1443 | ||
2ec1d359 AR |
1444 | return 0; |
1445 | ||
3e3c62ca | 1446 | out: |
2ec1d359 AR |
1447 | dev_err(&dev->dev, "Failure %i for GPIO %i-%i\n", ret, |
1448 | pdata->first_gpio, pdata->first_gpio+31); | |
513c27f8 | 1449 | |
2ec1d359 AR |
1450 | return ret; |
1451 | } | |
1452 | ||
e98ea774 LW |
1453 | static int nmk_get_groups_cnt(struct pinctrl_dev *pctldev) |
1454 | { | |
1455 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1456 | ||
1457 | return npct->soc->ngroups; | |
1458 | } | |
1459 | ||
1460 | static const char *nmk_get_group_name(struct pinctrl_dev *pctldev, | |
1461 | unsigned selector) | |
1462 | { | |
1463 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1464 | ||
1465 | return npct->soc->groups[selector].name; | |
1466 | } | |
1467 | ||
1468 | static int nmk_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, | |
1469 | const unsigned **pins, | |
1470 | unsigned *num_pins) | |
1471 | { | |
1472 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1473 | ||
1474 | *pins = npct->soc->groups[selector].pins; | |
1475 | *num_pins = npct->soc->groups[selector].npins; | |
1476 | return 0; | |
1477 | } | |
1478 | ||
24cbdd75 LW |
1479 | static struct pinctrl_gpio_range * |
1480 | nmk_match_gpio_range(struct pinctrl_dev *pctldev, unsigned offset) | |
1481 | { | |
1482 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1483 | int i; | |
1484 | ||
1485 | for (i = 0; i < npct->soc->gpio_num_ranges; i++) { | |
1486 | struct pinctrl_gpio_range *range; | |
1487 | ||
1488 | range = &npct->soc->gpio_ranges[i]; | |
1489 | if (offset >= range->pin_base && | |
1490 | offset <= (range->pin_base + range->npins - 1)) | |
1491 | return range; | |
1492 | } | |
1493 | return NULL; | |
1494 | } | |
1495 | ||
e98ea774 LW |
1496 | static void nmk_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, |
1497 | unsigned offset) | |
1498 | { | |
24cbdd75 LW |
1499 | struct pinctrl_gpio_range *range; |
1500 | struct gpio_chip *chip; | |
1501 | ||
1502 | range = nmk_match_gpio_range(pctldev, offset); | |
1503 | if (!range || !range->gc) { | |
1504 | seq_printf(s, "invalid pin offset"); | |
1505 | return; | |
1506 | } | |
1507 | chip = range->gc; | |
2249b19f | 1508 | nmk_gpio_dbg_show_one(s, pctldev, chip, offset - chip->base, offset); |
e98ea774 LW |
1509 | } |
1510 | ||
1511 | static struct pinctrl_ops nmk_pinctrl_ops = { | |
1512 | .get_groups_count = nmk_get_groups_cnt, | |
1513 | .get_group_name = nmk_get_group_name, | |
1514 | .get_group_pins = nmk_get_group_pins, | |
1515 | .pin_dbg_show = nmk_pin_dbg_show, | |
1516 | }; | |
1517 | ||
dbfe8ca2 LW |
1518 | static int nmk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) |
1519 | { | |
1520 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1521 | ||
1522 | return npct->soc->nfunctions; | |
1523 | } | |
1524 | ||
1525 | static const char *nmk_pmx_get_func_name(struct pinctrl_dev *pctldev, | |
1526 | unsigned function) | |
1527 | { | |
1528 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1529 | ||
1530 | return npct->soc->functions[function].name; | |
1531 | } | |
1532 | ||
1533 | static int nmk_pmx_get_func_groups(struct pinctrl_dev *pctldev, | |
1534 | unsigned function, | |
1535 | const char * const **groups, | |
1536 | unsigned * const num_groups) | |
1537 | { | |
1538 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1539 | ||
1540 | *groups = npct->soc->functions[function].groups; | |
1541 | *num_groups = npct->soc->functions[function].ngroups; | |
1542 | ||
1543 | return 0; | |
1544 | } | |
1545 | ||
1546 | static int nmk_pmx_enable(struct pinctrl_dev *pctldev, unsigned function, | |
1547 | unsigned group) | |
1548 | { | |
1549 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1550 | const struct nmk_pingroup *g; | |
1551 | static unsigned int slpm[NUM_BANKS]; | |
1552 | unsigned long flags; | |
1553 | bool glitch; | |
1554 | int ret = -EINVAL; | |
1555 | int i; | |
1556 | ||
1557 | g = &npct->soc->groups[group]; | |
1558 | ||
1559 | if (g->altsetting < 0) | |
1560 | return -EINVAL; | |
1561 | ||
1562 | dev_dbg(npct->dev, "enable group %s, %u pins\n", g->name, g->npins); | |
1563 | ||
daf73174 LW |
1564 | /* |
1565 | * If we're setting altfunc C by setting both AFSLA and AFSLB to 1, | |
1566 | * we may pass through an undesired state. In this case we take | |
1567 | * some extra care. | |
1568 | * | |
1569 | * Safe sequence used to switch IOs between GPIO and Alternate-C mode: | |
1570 | * - Save SLPM registers (since we have a shadow register in the | |
1571 | * nmk_chip we're using that as backup) | |
1572 | * - Set SLPM=0 for the IOs you want to switch and others to 1 | |
1573 | * - Configure the GPIO registers for the IOs that are being switched | |
1574 | * - Set IOFORCE=1 | |
1575 | * - Modify the AFLSA/B registers for the IOs that are being switched | |
1576 | * - Set IOFORCE=0 | |
1577 | * - Restore SLPM registers | |
1578 | * - Any spurious wake up event during switch sequence to be ignored | |
1579 | * and cleared | |
1580 | * | |
1581 | * We REALLY need to save ALL slpm registers, because the external | |
1582 | * IOFORCE will switch *all* ports to their sleepmode setting to as | |
1583 | * to avoid glitches. (Not just one port!) | |
1584 | */ | |
c22df08c | 1585 | glitch = ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C); |
dbfe8ca2 LW |
1586 | |
1587 | if (glitch) { | |
1588 | spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); | |
1589 | ||
1590 | /* Initially don't put any pins to sleep when switching */ | |
1591 | memset(slpm, 0xff, sizeof(slpm)); | |
1592 | ||
1593 | /* | |
1594 | * Then mask the pins that need to be sleeping now when we're | |
1595 | * switching to the ALT C function. | |
1596 | */ | |
1597 | for (i = 0; i < g->npins; i++) | |
1598 | slpm[g->pins[i] / NMK_GPIO_PER_CHIP] &= ~BIT(g->pins[i]); | |
1599 | nmk_gpio_glitch_slpm_init(slpm); | |
1600 | } | |
1601 | ||
1602 | for (i = 0; i < g->npins; i++) { | |
1603 | struct pinctrl_gpio_range *range; | |
1604 | struct nmk_gpio_chip *nmk_chip; | |
1605 | struct gpio_chip *chip; | |
1606 | unsigned bit; | |
1607 | ||
1608 | range = nmk_match_gpio_range(pctldev, g->pins[i]); | |
1609 | if (!range) { | |
1610 | dev_err(npct->dev, | |
1611 | "invalid pin offset %d in group %s at index %d\n", | |
1612 | g->pins[i], g->name, i); | |
1613 | goto out_glitch; | |
1614 | } | |
1615 | if (!range->gc) { | |
1616 | dev_err(npct->dev, "GPIO chip missing in range for pin offset %d in group %s at index %d\n", | |
1617 | g->pins[i], g->name, i); | |
1618 | goto out_glitch; | |
1619 | } | |
1620 | chip = range->gc; | |
1621 | nmk_chip = container_of(chip, struct nmk_gpio_chip, chip); | |
1622 | dev_dbg(npct->dev, "setting pin %d to altsetting %d\n", g->pins[i], g->altsetting); | |
1623 | ||
1624 | clk_enable(nmk_chip->clk); | |
1625 | bit = g->pins[i] % NMK_GPIO_PER_CHIP; | |
1626 | /* | |
1627 | * If the pin is switching to altfunc, and there was an | |
1628 | * interrupt installed on it which has been lazy disabled, | |
1629 | * actually mask the interrupt to prevent spurious interrupts | |
1630 | * that would occur while the pin is under control of the | |
1631 | * peripheral. Only SKE does this. | |
1632 | */ | |
1633 | nmk_gpio_disable_lazy_irq(nmk_chip, bit); | |
1634 | ||
c22df08c JNG |
1635 | __nmk_gpio_set_mode_safe(nmk_chip, bit, |
1636 | (g->altsetting & NMK_GPIO_ALT_C), glitch); | |
dbfe8ca2 | 1637 | clk_disable(nmk_chip->clk); |
c22df08c JNG |
1638 | |
1639 | /* | |
1640 | * Call PRCM GPIOCR config function in case ALTC | |
1641 | * has been selected: | |
1642 | * - If selection is a ALTCx, some bits in PRCM GPIOCR registers | |
1643 | * must be set. | |
1644 | * - If selection is pure ALTC and previous selection was ALTCx, | |
1645 | * then some bits in PRCM GPIOCR registers must be cleared. | |
1646 | */ | |
1647 | if ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C) | |
1648 | nmk_prcm_altcx_set_mode(npct, g->pins[i], | |
1649 | g->altsetting >> NMK_GPIO_ALT_CX_SHIFT); | |
dbfe8ca2 LW |
1650 | } |
1651 | ||
1652 | /* When all pins are successfully reconfigured we get here */ | |
1653 | ret = 0; | |
1654 | ||
1655 | out_glitch: | |
1656 | if (glitch) { | |
1657 | nmk_gpio_glitch_slpm_restore(slpm); | |
1658 | spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); | |
1659 | } | |
1660 | ||
1661 | return ret; | |
1662 | } | |
1663 | ||
1664 | static void nmk_pmx_disable(struct pinctrl_dev *pctldev, | |
1665 | unsigned function, unsigned group) | |
1666 | { | |
1667 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1668 | const struct nmk_pingroup *g; | |
1669 | ||
1670 | g = &npct->soc->groups[group]; | |
1671 | ||
1672 | if (g->altsetting < 0) | |
1673 | return; | |
1674 | ||
1675 | /* Poke out the mux, set the pin to some default state? */ | |
1676 | dev_dbg(npct->dev, "disable group %s, %u pins\n", g->name, g->npins); | |
1677 | } | |
1678 | ||
5212d096 AL |
1679 | static int nmk_gpio_request_enable(struct pinctrl_dev *pctldev, |
1680 | struct pinctrl_gpio_range *range, | |
1681 | unsigned offset) | |
dbfe8ca2 LW |
1682 | { |
1683 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1684 | struct nmk_gpio_chip *nmk_chip; | |
1685 | struct gpio_chip *chip; | |
1686 | unsigned bit; | |
1687 | ||
1688 | if (!range) { | |
1689 | dev_err(npct->dev, "invalid range\n"); | |
1690 | return -EINVAL; | |
1691 | } | |
1692 | if (!range->gc) { | |
1693 | dev_err(npct->dev, "missing GPIO chip in range\n"); | |
1694 | return -EINVAL; | |
1695 | } | |
1696 | chip = range->gc; | |
1697 | nmk_chip = container_of(chip, struct nmk_gpio_chip, chip); | |
1698 | ||
1699 | dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset); | |
1700 | ||
1701 | clk_enable(nmk_chip->clk); | |
1702 | bit = offset % NMK_GPIO_PER_CHIP; | |
1703 | /* There is no glitch when converting any pin to GPIO */ | |
1704 | __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO); | |
1705 | clk_disable(nmk_chip->clk); | |
1706 | ||
1707 | return 0; | |
1708 | } | |
1709 | ||
5212d096 AL |
1710 | static void nmk_gpio_disable_free(struct pinctrl_dev *pctldev, |
1711 | struct pinctrl_gpio_range *range, | |
1712 | unsigned offset) | |
dbfe8ca2 LW |
1713 | { |
1714 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1715 | ||
1716 | dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset); | |
1717 | /* Set the pin to some default state, GPIO is usually default */ | |
1718 | } | |
1719 | ||
1720 | static struct pinmux_ops nmk_pinmux_ops = { | |
1721 | .get_functions_count = nmk_pmx_get_funcs_cnt, | |
1722 | .get_function_name = nmk_pmx_get_func_name, | |
1723 | .get_function_groups = nmk_pmx_get_func_groups, | |
1724 | .enable = nmk_pmx_enable, | |
1725 | .disable = nmk_pmx_disable, | |
1726 | .gpio_request_enable = nmk_gpio_request_enable, | |
1727 | .gpio_disable_free = nmk_gpio_disable_free, | |
1728 | }; | |
1729 | ||
5212d096 AL |
1730 | static int nmk_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin, |
1731 | unsigned long *config) | |
d41af627 LW |
1732 | { |
1733 | /* Not implemented */ | |
1734 | return -EINVAL; | |
1735 | } | |
1736 | ||
5212d096 AL |
1737 | static int nmk_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin, |
1738 | unsigned long config) | |
d41af627 LW |
1739 | { |
1740 | static const char *pullnames[] = { | |
1741 | [NMK_GPIO_PULL_NONE] = "none", | |
1742 | [NMK_GPIO_PULL_UP] = "up", | |
1743 | [NMK_GPIO_PULL_DOWN] = "down", | |
1744 | [3] /* illegal */ = "??" | |
1745 | }; | |
1746 | static const char *slpmnames[] = { | |
1747 | [NMK_GPIO_SLPM_INPUT] = "input/wakeup", | |
1748 | [NMK_GPIO_SLPM_NOCHANGE] = "no-change/no-wakeup", | |
1749 | }; | |
1750 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1751 | struct nmk_gpio_chip *nmk_chip; | |
1752 | struct pinctrl_gpio_range *range; | |
1753 | struct gpio_chip *chip; | |
1754 | unsigned bit; | |
1755 | ||
1756 | /* | |
1757 | * The pin config contains pin number and altfunction fields, here | |
1758 | * we just ignore that part. It's being handled by the framework and | |
1759 | * pinmux callback respectively. | |
1760 | */ | |
1761 | pin_cfg_t cfg = (pin_cfg_t) config; | |
1762 | int pull = PIN_PULL(cfg); | |
1763 | int slpm = PIN_SLPM(cfg); | |
1764 | int output = PIN_DIR(cfg); | |
1765 | int val = PIN_VAL(cfg); | |
1766 | bool lowemi = PIN_LOWEMI(cfg); | |
1767 | bool gpiomode = PIN_GPIOMODE(cfg); | |
1768 | bool sleep = PIN_SLEEPMODE(cfg); | |
1769 | ||
1770 | range = nmk_match_gpio_range(pctldev, pin); | |
1771 | if (!range) { | |
1772 | dev_err(npct->dev, "invalid pin offset %d\n", pin); | |
1773 | return -EINVAL; | |
1774 | } | |
1775 | if (!range->gc) { | |
1776 | dev_err(npct->dev, "GPIO chip missing in range for pin %d\n", | |
1777 | pin); | |
1778 | return -EINVAL; | |
1779 | } | |
1780 | chip = range->gc; | |
1781 | nmk_chip = container_of(chip, struct nmk_gpio_chip, chip); | |
1782 | ||
1783 | if (sleep) { | |
1784 | int slpm_pull = PIN_SLPM_PULL(cfg); | |
1785 | int slpm_output = PIN_SLPM_DIR(cfg); | |
1786 | int slpm_val = PIN_SLPM_VAL(cfg); | |
1787 | ||
1788 | /* All pins go into GPIO mode at sleep */ | |
1789 | gpiomode = true; | |
1790 | ||
1791 | /* | |
1792 | * The SLPM_* values are normal values + 1 to allow zero to | |
1793 | * mean "same as normal". | |
1794 | */ | |
1795 | if (slpm_pull) | |
1796 | pull = slpm_pull - 1; | |
1797 | if (slpm_output) | |
1798 | output = slpm_output - 1; | |
1799 | if (slpm_val) | |
1800 | val = slpm_val - 1; | |
1801 | ||
1802 | dev_dbg(nmk_chip->chip.dev, "pin %d: sleep pull %s, dir %s, val %s\n", | |
1803 | pin, | |
1804 | slpm_pull ? pullnames[pull] : "same", | |
1805 | slpm_output ? (output ? "output" : "input") : "same", | |
1806 | slpm_val ? (val ? "high" : "low") : "same"); | |
1807 | } | |
1808 | ||
1809 | dev_dbg(nmk_chip->chip.dev, "pin %d [%#lx]: pull %s, slpm %s (%s%s), lowemi %s\n", | |
1810 | pin, cfg, pullnames[pull], slpmnames[slpm], | |
1811 | output ? "output " : "input", | |
1812 | output ? (val ? "high" : "low") : "", | |
1813 | lowemi ? "on" : "off" ); | |
1814 | ||
1815 | clk_enable(nmk_chip->clk); | |
1816 | bit = pin % NMK_GPIO_PER_CHIP; | |
1817 | if (gpiomode) | |
1818 | /* No glitch when going to GPIO mode */ | |
1819 | __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO); | |
1820 | if (output) | |
1821 | __nmk_gpio_make_output(nmk_chip, bit, val); | |
1822 | else { | |
1823 | __nmk_gpio_make_input(nmk_chip, bit); | |
1824 | __nmk_gpio_set_pull(nmk_chip, bit, pull); | |
1825 | } | |
1826 | /* TODO: isn't this only applicable on output pins? */ | |
1827 | __nmk_gpio_set_lowemi(nmk_chip, bit, lowemi); | |
1828 | ||
1829 | __nmk_gpio_set_slpm(nmk_chip, bit, slpm); | |
1830 | clk_disable(nmk_chip->clk); | |
1831 | return 0; | |
1832 | } | |
1833 | ||
1834 | static struct pinconf_ops nmk_pinconf_ops = { | |
1835 | .pin_config_get = nmk_pin_config_get, | |
1836 | .pin_config_set = nmk_pin_config_set, | |
1837 | }; | |
1838 | ||
e98ea774 LW |
1839 | static struct pinctrl_desc nmk_pinctrl_desc = { |
1840 | .name = "pinctrl-nomadik", | |
1841 | .pctlops = &nmk_pinctrl_ops, | |
dbfe8ca2 | 1842 | .pmxops = &nmk_pinmux_ops, |
d41af627 | 1843 | .confops = &nmk_pinconf_ops, |
e98ea774 LW |
1844 | .owner = THIS_MODULE, |
1845 | }; | |
1846 | ||
855f80cd | 1847 | static const struct of_device_id nmk_pinctrl_match[] = { |
6010d403 LW |
1848 | { |
1849 | .compatible = "stericsson,nmk-pinctrl-stn8815", | |
1850 | .data = (void *)PINCTRL_NMK_STN8815, | |
1851 | }, | |
855f80cd LJ |
1852 | { |
1853 | .compatible = "stericsson,nmk_pinctrl", | |
1854 | .data = (void *)PINCTRL_NMK_DB8500, | |
1855 | }, | |
1856 | {}, | |
1857 | }; | |
1858 | ||
150632b0 | 1859 | static int nmk_pinctrl_probe(struct platform_device *pdev) |
e98ea774 LW |
1860 | { |
1861 | const struct platform_device_id *platid = platform_get_device_id(pdev); | |
855f80cd | 1862 | struct device_node *np = pdev->dev.of_node; |
e98ea774 | 1863 | struct nmk_pinctrl *npct; |
f1671bf5 | 1864 | struct resource *res; |
855f80cd | 1865 | unsigned int version = 0; |
e98ea774 LW |
1866 | int i; |
1867 | ||
1868 | npct = devm_kzalloc(&pdev->dev, sizeof(*npct), GFP_KERNEL); | |
1869 | if (!npct) | |
1870 | return -ENOMEM; | |
1871 | ||
855f80cd LJ |
1872 | if (platid) |
1873 | version = platid->driver_data; | |
953e9e93 AL |
1874 | else if (np) { |
1875 | const struct of_device_id *match; | |
1876 | ||
1877 | match = of_match_device(nmk_pinctrl_match, &pdev->dev); | |
1878 | if (!match) | |
1879 | return -ENODEV; | |
1880 | version = (unsigned int) match->data; | |
1881 | } | |
855f80cd | 1882 | |
e98ea774 | 1883 | /* Poke in other ASIC variants here */ |
f79c5ed9 LW |
1884 | if (version == PINCTRL_NMK_STN8815) |
1885 | nmk_pinctrl_stn8815_init(&npct->soc); | |
855f80cd | 1886 | if (version == PINCTRL_NMK_DB8500) |
e98ea774 | 1887 | nmk_pinctrl_db8500_init(&npct->soc); |
45a1b531 PC |
1888 | if (version == PINCTRL_NMK_DB8540) |
1889 | nmk_pinctrl_db8540_init(&npct->soc); | |
e98ea774 | 1890 | |
f1671bf5 JA |
1891 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1892 | if (res) { | |
1893 | npct->prcm_base = devm_ioremap(&pdev->dev, res->start, | |
1894 | resource_size(res)); | |
1895 | if (!npct->prcm_base) { | |
1896 | dev_err(&pdev->dev, | |
1897 | "failed to ioremap PRCM registers\n"); | |
1898 | return -ENOMEM; | |
1899 | } | |
4ca075de | 1900 | } else if (version == PINCTRL_NMK_STN8815) { |
f1671bf5 JA |
1901 | dev_info(&pdev->dev, |
1902 | "No PRCM base, assume no ALT-Cx control is available\n"); | |
4ca075de FB |
1903 | } else { |
1904 | dev_err(&pdev->dev, "missing PRCM base address\n"); | |
1905 | return -EINVAL; | |
f1671bf5 JA |
1906 | } |
1907 | ||
e98ea774 LW |
1908 | /* |
1909 | * We need all the GPIO drivers to probe FIRST, or we will not be able | |
1910 | * to obtain references to the struct gpio_chip * for them, and we | |
1911 | * need this to proceed. | |
1912 | */ | |
1913 | for (i = 0; i < npct->soc->gpio_num_ranges; i++) { | |
1d853ca5 | 1914 | if (!nmk_gpio_chips[npct->soc->gpio_ranges[i].id]) { |
e98ea774 | 1915 | dev_warn(&pdev->dev, "GPIO chip %d not registered yet\n", i); |
e98ea774 LW |
1916 | return -EPROBE_DEFER; |
1917 | } | |
1d853ca5 | 1918 | npct->soc->gpio_ranges[i].gc = &nmk_gpio_chips[npct->soc->gpio_ranges[i].id]->chip; |
e98ea774 LW |
1919 | } |
1920 | ||
1921 | nmk_pinctrl_desc.pins = npct->soc->pins; | |
1922 | nmk_pinctrl_desc.npins = npct->soc->npins; | |
1923 | npct->dev = &pdev->dev; | |
f1671bf5 | 1924 | |
e98ea774 LW |
1925 | npct->pctl = pinctrl_register(&nmk_pinctrl_desc, &pdev->dev, npct); |
1926 | if (!npct->pctl) { | |
1927 | dev_err(&pdev->dev, "could not register Nomadik pinctrl driver\n"); | |
1928 | return -EINVAL; | |
1929 | } | |
1930 | ||
1931 | /* We will handle a range of GPIO pins */ | |
1932 | for (i = 0; i < npct->soc->gpio_num_ranges; i++) | |
1933 | pinctrl_add_gpio_range(npct->pctl, &npct->soc->gpio_ranges[i]); | |
1934 | ||
1935 | platform_set_drvdata(pdev, npct); | |
1936 | dev_info(&pdev->dev, "initialized Nomadik pin control driver\n"); | |
1937 | ||
1938 | return 0; | |
1939 | } | |
1940 | ||
513c27f8 LJ |
1941 | static const struct of_device_id nmk_gpio_match[] = { |
1942 | { .compatible = "st,nomadik-gpio", }, | |
1943 | {} | |
1944 | }; | |
1945 | ||
3e3c62ca RV |
1946 | static struct platform_driver nmk_gpio_driver = { |
1947 | .driver = { | |
2ec1d359 AR |
1948 | .owner = THIS_MODULE, |
1949 | .name = "gpio", | |
513c27f8 | 1950 | .of_match_table = nmk_gpio_match, |
5317e4d1 | 1951 | }, |
2ec1d359 | 1952 | .probe = nmk_gpio_probe, |
2ec1d359 AR |
1953 | }; |
1954 | ||
e98ea774 LW |
1955 | static const struct platform_device_id nmk_pinctrl_id[] = { |
1956 | { "pinctrl-stn8815", PINCTRL_NMK_STN8815 }, | |
1957 | { "pinctrl-db8500", PINCTRL_NMK_DB8500 }, | |
45a1b531 | 1958 | { "pinctrl-db8540", PINCTRL_NMK_DB8540 }, |
8c995d6d | 1959 | { } |
e98ea774 LW |
1960 | }; |
1961 | ||
1962 | static struct platform_driver nmk_pinctrl_driver = { | |
1963 | .driver = { | |
1964 | .owner = THIS_MODULE, | |
1965 | .name = "pinctrl-nomadik", | |
855f80cd | 1966 | .of_match_table = nmk_pinctrl_match, |
e98ea774 LW |
1967 | }, |
1968 | .probe = nmk_pinctrl_probe, | |
1969 | .id_table = nmk_pinctrl_id, | |
1970 | }; | |
1971 | ||
2ec1d359 AR |
1972 | static int __init nmk_gpio_init(void) |
1973 | { | |
e98ea774 LW |
1974 | int ret; |
1975 | ||
1976 | ret = platform_driver_register(&nmk_gpio_driver); | |
1977 | if (ret) | |
1978 | return ret; | |
1979 | return platform_driver_register(&nmk_pinctrl_driver); | |
2ec1d359 AR |
1980 | } |
1981 | ||
33f45ea9 | 1982 | core_initcall(nmk_gpio_init); |
2ec1d359 AR |
1983 | |
1984 | MODULE_AUTHOR("Prafulla WADASKAR and Alessandro Rubini"); | |
1985 | MODULE_DESCRIPTION("Nomadik GPIO Driver"); | |
1986 | MODULE_LICENSE("GPL"); |