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Merge branch 'i2c/for-current' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa...
[mirror_ubuntu-zesty-kernel.git] / drivers / pinctrl / pinctrl-oxnas.c
CommitLineData
611dac1e
NA		 1/*
2 * Oxford Semiconductor OXNAS SoC Family pinctrl driver
3 *
4 * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
5 *
6 * Based on pinctrl-pic32.c
7 * Joshua Henderson, <joshua.henderson@microchip.com>
8 * Copyright (C) 2015 Microchip Technology Inc. All rights reserved.
9 *
10 * This program is free software; you can distribute it and/or modify it
11 * under the terms of the GNU General Public License (Version 2) as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 * for more details.
18 */
19#include <linux/gpio/driver.h>
20#include <linux/interrupt.h>
21#include <linux/io.h>
22#include <linux/irq.h>
23#include <linux/of.h>
24#include <linux/of_device.h>
25#include <linux/pinctrl/pinconf.h>
26#include <linux/pinctrl/pinconf-generic.h>
27#include <linux/pinctrl/pinctrl.h>
28#include <linux/pinctrl/pinmux.h>
29#include <linux/platform_device.h>
30#include <linux/slab.h>
31#include <linux/regmap.h>
32#include <linux/mfd/syscon.h>
33
34#include "pinctrl-utils.h"
35
36#define PINS_PER_BANK 32
37
38#define GPIO_BANK_START(bank) ((bank) * PINS_PER_BANK)
39
93f889b9
NA		 40/* OX810 Regmap Offsets */
41#define PINMUX_810_PRIMARY_SEL0 0x0c
42#define PINMUX_810_SECONDARY_SEL0 0x14
43#define PINMUX_810_TERTIARY_SEL0 0x8c
44#define PINMUX_810_PRIMARY_SEL1 0x10
45#define PINMUX_810_SECONDARY_SEL1 0x18
46#define PINMUX_810_TERTIARY_SEL1 0x90
47#define PINMUX_810_PULLUP_CTRL0 0xac
48#define PINMUX_810_PULLUP_CTRL1 0xb0
611dac1e 49
4b0c0c25
NA		 50/* OX820 Regmap Offsets */
51#define PINMUX_820_BANK_OFFSET 0x100000
52#define PINMUX_820_SECONDARY_SEL 0x14
53#define PINMUX_820_TERTIARY_SEL 0x8c
54#define PINMUX_820_QUATERNARY_SEL 0x94
55#define PINMUX_820_DEBUG_SEL 0x9c
56#define PINMUX_820_ALTERNATIVE_SEL 0xa4
57#define PINMUX_820_PULLUP_CTRL 0xac
58
611dac1e
NA		 59/* GPIO Registers */
60#define INPUT_VALUE 0x00
2f94ced7 61#define OUTPUT_EN 0x04
611dac1e
NA		 62#define IRQ_PENDING 0x0c
63#define OUTPUT_SET 0x14
64#define OUTPUT_CLEAR 0x18
65#define OUTPUT_EN_SET 0x1c
66#define OUTPUT_EN_CLEAR 0x20
67#define RE_IRQ_ENABLE 0x28
68#define FE_IRQ_ENABLE 0x2c
69
70struct oxnas_function {
71 const char *name;
72 const char * const *groups;
73 unsigned int ngroups;
74};
75
76struct oxnas_pin_group {
77 const char *name;
78 unsigned int pin;
79 unsigned int bank;
80 struct oxnas_desc_function *functions;
81};
82
83struct oxnas_desc_function {
84 const char *name;
85 unsigned int fct;
86};
87
88struct oxnas_gpio_bank {
89 void __iomem *reg_base;
90 struct gpio_chip gpio_chip;
91 struct irq_chip irq_chip;
92 unsigned int id;
93};
94
95struct oxnas_pinctrl {
96 struct regmap *regmap;
97 struct device *dev;
98 struct pinctrl_dev *pctldev;
611dac1e
NA		 99 const struct oxnas_function *functions;
100 unsigned int nfunctions;
101 const struct oxnas_pin_group *groups;
102 unsigned int ngroups;
103 struct oxnas_gpio_bank *gpio_banks;
104 unsigned int nbanks;
105};
106
93f889b9
NA		 107struct oxnas_pinctrl_data {
108 struct pinctrl_desc *desc;
109 struct oxnas_pinctrl *pctl;
110};
111
112static const struct pinctrl_pin_desc oxnas_ox810se_pins[] = {
611dac1e
NA		 113 PINCTRL_PIN(0, "gpio0"),
114 PINCTRL_PIN(1, "gpio1"),
115 PINCTRL_PIN(2, "gpio2"),
116 PINCTRL_PIN(3, "gpio3"),
117 PINCTRL_PIN(4, "gpio4"),
118 PINCTRL_PIN(5, "gpio5"),
119 PINCTRL_PIN(6, "gpio6"),
120 PINCTRL_PIN(7, "gpio7"),
121 PINCTRL_PIN(8, "gpio8"),
122 PINCTRL_PIN(9, "gpio9"),
123 PINCTRL_PIN(10, "gpio10"),
124 PINCTRL_PIN(11, "gpio11"),
125 PINCTRL_PIN(12, "gpio12"),
126 PINCTRL_PIN(13, "gpio13"),
127 PINCTRL_PIN(14, "gpio14"),
128 PINCTRL_PIN(15, "gpio15"),
129 PINCTRL_PIN(16, "gpio16"),
130 PINCTRL_PIN(17, "gpio17"),
131 PINCTRL_PIN(18, "gpio18"),
132 PINCTRL_PIN(19, "gpio19"),
133 PINCTRL_PIN(20, "gpio20"),
134 PINCTRL_PIN(21, "gpio21"),
135 PINCTRL_PIN(22, "gpio22"),
136 PINCTRL_PIN(23, "gpio23"),
137 PINCTRL_PIN(24, "gpio24"),
138 PINCTRL_PIN(25, "gpio25"),
139 PINCTRL_PIN(26, "gpio26"),
140 PINCTRL_PIN(27, "gpio27"),
141 PINCTRL_PIN(28, "gpio28"),
142 PINCTRL_PIN(29, "gpio29"),
143 PINCTRL_PIN(30, "gpio30"),
144 PINCTRL_PIN(31, "gpio31"),
145 PINCTRL_PIN(32, "gpio32"),
146 PINCTRL_PIN(33, "gpio33"),
147 PINCTRL_PIN(34, "gpio34"),
148};
149
4b0c0c25
NA		 150static const struct pinctrl_pin_desc oxnas_ox820_pins[] = {
151 PINCTRL_PIN(0, "gpio0"),
152 PINCTRL_PIN(1, "gpio1"),
153 PINCTRL_PIN(2, "gpio2"),
154 PINCTRL_PIN(3, "gpio3"),
155 PINCTRL_PIN(4, "gpio4"),
156 PINCTRL_PIN(5, "gpio5"),
157 PINCTRL_PIN(6, "gpio6"),
158 PINCTRL_PIN(7, "gpio7"),
159 PINCTRL_PIN(8, "gpio8"),
160 PINCTRL_PIN(9, "gpio9"),
161 PINCTRL_PIN(10, "gpio10"),
162 PINCTRL_PIN(11, "gpio11"),
163 PINCTRL_PIN(12, "gpio12"),
164 PINCTRL_PIN(13, "gpio13"),
165 PINCTRL_PIN(14, "gpio14"),
166 PINCTRL_PIN(15, "gpio15"),
167 PINCTRL_PIN(16, "gpio16"),
168 PINCTRL_PIN(17, "gpio17"),
169 PINCTRL_PIN(18, "gpio18"),
170 PINCTRL_PIN(19, "gpio19"),
171 PINCTRL_PIN(20, "gpio20"),
172 PINCTRL_PIN(21, "gpio21"),
173 PINCTRL_PIN(22, "gpio22"),
174 PINCTRL_PIN(23, "gpio23"),
175 PINCTRL_PIN(24, "gpio24"),
176 PINCTRL_PIN(25, "gpio25"),
177 PINCTRL_PIN(26, "gpio26"),
178 PINCTRL_PIN(27, "gpio27"),
179 PINCTRL_PIN(28, "gpio28"),
180 PINCTRL_PIN(29, "gpio29"),
181 PINCTRL_PIN(30, "gpio30"),
182 PINCTRL_PIN(31, "gpio31"),
183 PINCTRL_PIN(32, "gpio32"),
184 PINCTRL_PIN(33, "gpio33"),
185 PINCTRL_PIN(34, "gpio34"),
186 PINCTRL_PIN(35, "gpio35"),
187 PINCTRL_PIN(36, "gpio36"),
188 PINCTRL_PIN(37, "gpio37"),
189 PINCTRL_PIN(38, "gpio38"),
190 PINCTRL_PIN(39, "gpio39"),
191 PINCTRL_PIN(40, "gpio40"),
192 PINCTRL_PIN(41, "gpio41"),
193 PINCTRL_PIN(42, "gpio42"),
194 PINCTRL_PIN(43, "gpio43"),
195 PINCTRL_PIN(44, "gpio44"),
196 PINCTRL_PIN(45, "gpio45"),
197 PINCTRL_PIN(46, "gpio46"),
198 PINCTRL_PIN(47, "gpio47"),
199 PINCTRL_PIN(48, "gpio48"),
200 PINCTRL_PIN(49, "gpio49"),
201};
202
93f889b9 203static const char * const oxnas_ox810se_fct0_group[] = {
611dac1e
NA		 204 "gpio0", "gpio1", "gpio2", "gpio3",
205 "gpio4", "gpio5", "gpio6", "gpio7",
206 "gpio8", "gpio9", "gpio10", "gpio11",
207 "gpio12", "gpio13", "gpio14", "gpio15",
208 "gpio16", "gpio17", "gpio18", "gpio19",
209 "gpio20", "gpio21", "gpio22", "gpio23",
210 "gpio24", "gpio25", "gpio26", "gpio27",
211 "gpio28", "gpio29", "gpio30", "gpio31",
212 "gpio32", "gpio33", "gpio34"
213};
214
93f889b9 215static const char * const oxnas_ox810se_fct3_group[] = {
611dac1e
NA		 216 "gpio0", "gpio1", "gpio2", "gpio3",
217 "gpio4", "gpio5", "gpio6", "gpio7",
218 "gpio8", "gpio9",
219 "gpio20",
220 "gpio22", "gpio23", "gpio24", "gpio25",
221 "gpio26", "gpio27", "gpio28", "gpio29",
222 "gpio30", "gpio31", "gpio32", "gpio33",
223 "gpio34"
224};
225
4b0c0c25
NA		 226static const char * const oxnas_ox820_fct0_group[] = {
227 "gpio0", "gpio1", "gpio2", "gpio3",
228 "gpio4", "gpio5", "gpio6", "gpio7",
229 "gpio8", "gpio9", "gpio10", "gpio11",
230 "gpio12", "gpio13", "gpio14", "gpio15",
231 "gpio16", "gpio17", "gpio18", "gpio19",
232 "gpio20", "gpio21", "gpio22", "gpio23",
233 "gpio24", "gpio25", "gpio26", "gpio27",
234 "gpio28", "gpio29", "gpio30", "gpio31",
235 "gpio32", "gpio33", "gpio34", "gpio35",
236 "gpio36", "gpio37", "gpio38", "gpio39",
237 "gpio40", "gpio41", "gpio42", "gpio43",
238 "gpio44", "gpio45", "gpio46", "gpio47",
239 "gpio48", "gpio49"
240};
241
242static const char * const oxnas_ox820_fct1_group[] = {
243 "gpio3", "gpio4",
244 "gpio12", "gpio13", "gpio14", "gpio15",
245 "gpio16", "gpio17", "gpio18", "gpio19",
246 "gpio20", "gpio21", "gpio22", "gpio23",
247 "gpio24"
248};
249
250static const char * const oxnas_ox820_fct4_group[] = {
251 "gpio5", "gpio6", "gpio7", "gpio8",
252 "gpio24", "gpio25", "gpio26", "gpio27",
253 "gpio40", "gpio41", "gpio42", "gpio43"
254};
255
256static const char * const oxnas_ox820_fct5_group[] = {
257 "gpio28", "gpio29", "gpio30", "gpio31"
258};
259
611dac1e
NA		 260#define FUNCTION(_name, _gr) \
261 { \
262 .name = #_name, \
263 .groups = oxnas_##_gr##_group, \
264 .ngroups = ARRAY_SIZE(oxnas_##_gr##_group), \
265 }
266
93f889b9
NA		 267static const struct oxnas_function oxnas_ox810se_functions[] = {
268 FUNCTION(gpio, ox810se_fct0),
269 FUNCTION(fct3, ox810se_fct3),
611dac1e
NA		 270};
271
4b0c0c25
NA		 272static const struct oxnas_function oxnas_ox820_functions[] = {
273 FUNCTION(gpio, ox820_fct0),
274 FUNCTION(fct1, ox820_fct1),
275 FUNCTION(fct4, ox820_fct4),
276 FUNCTION(fct5, ox820_fct5),
277};
278
611dac1e
NA		 279#define OXNAS_PINCTRL_GROUP(_pin, _name, ...) \
280 { \
281 .name = #_name, \
282 .pin = _pin, \
283 .bank = _pin / PINS_PER_BANK, \
284 .functions = (struct oxnas_desc_function[]){ \
285 __VA_ARGS__, { } }, \
286 }
287
288#define OXNAS_PINCTRL_FUNCTION(_name, _fct) \
289 { \
290 .name = #_name, \
291 .fct = _fct, \
292 }
293
93f889b9 294static const struct oxnas_pin_group oxnas_ox810se_groups[] = {
611dac1e
NA		 295 OXNAS_PINCTRL_GROUP(0, gpio0,
296 OXNAS_PINCTRL_FUNCTION(gpio, 0),
297 OXNAS_PINCTRL_FUNCTION(fct3, 3)),
298 OXNAS_PINCTRL_GROUP(1, gpio1,
299 OXNAS_PINCTRL_FUNCTION(gpio, 0),
300 OXNAS_PINCTRL_FUNCTION(fct3, 3)),
301 OXNAS_PINCTRL_GROUP(2, gpio2,
302 OXNAS_PINCTRL_FUNCTION(gpio, 0),
303 OXNAS_PINCTRL_FUNCTION(fct3, 3)),
304 OXNAS_PINCTRL_GROUP(3, gpio3,
305 OXNAS_PINCTRL_FUNCTION(gpio, 0),
306 OXNAS_PINCTRL_FUNCTION(fct3, 3)),
307 OXNAS_PINCTRL_GROUP(4, gpio4,
308 OXNAS_PINCTRL_FUNCTION(gpio, 0),
309 OXNAS_PINCTRL_FUNCTION(fct3, 3)),
310 OXNAS_PINCTRL_GROUP(5, gpio5,
311 OXNAS_PINCTRL_FUNCTION(gpio, 0),
312 OXNAS_PINCTRL_FUNCTION(fct3, 3)),
313 OXNAS_PINCTRL_GROUP(6, gpio6,
314 OXNAS_PINCTRL_FUNCTION(gpio, 0),
315 OXNAS_PINCTRL_FUNCTION(fct3, 3)),
316 OXNAS_PINCTRL_GROUP(7, gpio7,
317 OXNAS_PINCTRL_FUNCTION(gpio, 0),
318 OXNAS_PINCTRL_FUNCTION(fct3, 3)),
319 OXNAS_PINCTRL_GROUP(8, gpio8,
320 OXNAS_PINCTRL_FUNCTION(gpio, 0),
321 OXNAS_PINCTRL_FUNCTION(fct3, 3)),
322 OXNAS_PINCTRL_GROUP(9, gpio9,
323 OXNAS_PINCTRL_FUNCTION(gpio, 0),
324 OXNAS_PINCTRL_FUNCTION(fct3, 3)),
325 OXNAS_PINCTRL_GROUP(10, gpio10,
326 OXNAS_PINCTRL_FUNCTION(gpio, 0)),
327 OXNAS_PINCTRL_GROUP(11, gpio11,
328 OXNAS_PINCTRL_FUNCTION(gpio, 0)),
329 OXNAS_PINCTRL_GROUP(12, gpio12,
330 OXNAS_PINCTRL_FUNCTION(gpio, 0)),
331 OXNAS_PINCTRL_GROUP(13, gpio13,
332 OXNAS_PINCTRL_FUNCTION(gpio, 0)),
333 OXNAS_PINCTRL_GROUP(14, gpio14,
334 OXNAS_PINCTRL_FUNCTION(gpio, 0)),
335 OXNAS_PINCTRL_GROUP(15, gpio15,
336 OXNAS_PINCTRL_FUNCTION(gpio, 0)),
337 OXNAS_PINCTRL_GROUP(16, gpio16,
338 OXNAS_PINCTRL_FUNCTION(gpio, 0)),
339 OXNAS_PINCTRL_GROUP(17, gpio17,
340 OXNAS_PINCTRL_FUNCTION(gpio, 0)),
341 OXNAS_PINCTRL_GROUP(18, gpio18,
342 OXNAS_PINCTRL_FUNCTION(gpio, 0)),
343 OXNAS_PINCTRL_GROUP(19, gpio19,
344 OXNAS_PINCTRL_FUNCTION(gpio, 0)),
345 OXNAS_PINCTRL_GROUP(20, gpio20,
346 OXNAS_PINCTRL_FUNCTION(gpio, 0),
347 OXNAS_PINCTRL_FUNCTION(fct3, 3)),
348 OXNAS_PINCTRL_GROUP(21, gpio21,
349 OXNAS_PINCTRL_FUNCTION(gpio, 0)),
350 OXNAS_PINCTRL_GROUP(22, gpio22,
351 OXNAS_PINCTRL_FUNCTION(gpio, 0),
352 OXNAS_PINCTRL_FUNCTION(fct3, 3)),
353 OXNAS_PINCTRL_GROUP(23, gpio23,
354 OXNAS_PINCTRL_FUNCTION(gpio, 0),
355 OXNAS_PINCTRL_FUNCTION(fct3, 3)),
356 OXNAS_PINCTRL_GROUP(24, gpio24,
357 OXNAS_PINCTRL_FUNCTION(gpio, 0),
358 OXNAS_PINCTRL_FUNCTION(fct3, 3)),
359 OXNAS_PINCTRL_GROUP(25, gpio25,
360 OXNAS_PINCTRL_FUNCTION(gpio, 0),
361 OXNAS_PINCTRL_FUNCTION(fct3, 3)),
362 OXNAS_PINCTRL_GROUP(26, gpio26,
363 OXNAS_PINCTRL_FUNCTION(gpio, 0),
364 OXNAS_PINCTRL_FUNCTION(fct3, 3)),
365 OXNAS_PINCTRL_GROUP(27, gpio27,
366 OXNAS_PINCTRL_FUNCTION(gpio, 0),
367 OXNAS_PINCTRL_FUNCTION(fct3, 3)),
368 OXNAS_PINCTRL_GROUP(28, gpio28,
369 OXNAS_PINCTRL_FUNCTION(gpio, 0),
370 OXNAS_PINCTRL_FUNCTION(fct3, 3)),
371 OXNAS_PINCTRL_GROUP(29, gpio29,
372 OXNAS_PINCTRL_FUNCTION(gpio, 0),
373 OXNAS_PINCTRL_FUNCTION(fct3, 3)),
374 OXNAS_PINCTRL_GROUP(30, gpio30,
375 OXNAS_PINCTRL_FUNCTION(gpio, 0),
376 OXNAS_PINCTRL_FUNCTION(fct3, 3)),
377 OXNAS_PINCTRL_GROUP(31, gpio31,
378 OXNAS_PINCTRL_FUNCTION(gpio, 0),
379 OXNAS_PINCTRL_FUNCTION(fct3, 3)),
380 OXNAS_PINCTRL_GROUP(32, gpio32,
381 OXNAS_PINCTRL_FUNCTION(gpio, 0),
382 OXNAS_PINCTRL_FUNCTION(fct3, 3)),
383 OXNAS_PINCTRL_GROUP(33, gpio33,
384 OXNAS_PINCTRL_FUNCTION(gpio, 0),
385 OXNAS_PINCTRL_FUNCTION(fct3, 3)),
386 OXNAS_PINCTRL_GROUP(34, gpio34,
387 OXNAS_PINCTRL_FUNCTION(gpio, 0),
388 OXNAS_PINCTRL_FUNCTION(fct3, 3)),
389};
390
4b0c0c25
NA		 391static const struct oxnas_pin_group oxnas_ox820_groups[] = {
392 OXNAS_PINCTRL_GROUP(0, gpio0,
393 OXNAS_PINCTRL_FUNCTION(gpio, 0)),
394 OXNAS_PINCTRL_GROUP(1, gpio1,
395 OXNAS_PINCTRL_FUNCTION(gpio, 0)),
396 OXNAS_PINCTRL_GROUP(2, gpio2,
397 OXNAS_PINCTRL_FUNCTION(gpio, 0)),
398 OXNAS_PINCTRL_GROUP(3, gpio3,
399 OXNAS_PINCTRL_FUNCTION(gpio, 0),
400 OXNAS_PINCTRL_FUNCTION(fct1, 1)),
401 OXNAS_PINCTRL_GROUP(4, gpio4,
402 OXNAS_PINCTRL_FUNCTION(gpio, 0),
403 OXNAS_PINCTRL_FUNCTION(fct1, 1)),
404 OXNAS_PINCTRL_GROUP(5, gpio5,
405 OXNAS_PINCTRL_FUNCTION(gpio, 0),
406 OXNAS_PINCTRL_FUNCTION(fct4, 4)),
407 OXNAS_PINCTRL_GROUP(6, gpio6,
408 OXNAS_PINCTRL_FUNCTION(gpio, 0),
409 OXNAS_PINCTRL_FUNCTION(fct4, 4)),
410 OXNAS_PINCTRL_GROUP(7, gpio7,
411 OXNAS_PINCTRL_FUNCTION(gpio, 0),
412 OXNAS_PINCTRL_FUNCTION(fct4, 4)),
413 OXNAS_PINCTRL_GROUP(8, gpio8,
414 OXNAS_PINCTRL_FUNCTION(gpio, 0),
415 OXNAS_PINCTRL_FUNCTION(fct4, 4)),
416 OXNAS_PINCTRL_GROUP(9, gpio9,
417 OXNAS_PINCTRL_FUNCTION(gpio, 0)),
418 OXNAS_PINCTRL_GROUP(10, gpio10,
419 OXNAS_PINCTRL_FUNCTION(gpio, 0)),
420 OXNAS_PINCTRL_GROUP(11, gpio11,
421 OXNAS_PINCTRL_FUNCTION(gpio, 0)),
422 OXNAS_PINCTRL_GROUP(12, gpio12,
423 OXNAS_PINCTRL_FUNCTION(gpio, 0),
424 OXNAS_PINCTRL_FUNCTION(fct1, 1)),
425 OXNAS_PINCTRL_GROUP(13, gpio13,
426 OXNAS_PINCTRL_FUNCTION(gpio, 0),
427 OXNAS_PINCTRL_FUNCTION(fct1, 1)),
428 OXNAS_PINCTRL_GROUP(14, gpio14,
429 OXNAS_PINCTRL_FUNCTION(gpio, 0),
430 OXNAS_PINCTRL_FUNCTION(fct1, 1)),
431 OXNAS_PINCTRL_GROUP(15, gpio15,
432 OXNAS_PINCTRL_FUNCTION(gpio, 0),
433 OXNAS_PINCTRL_FUNCTION(fct1, 1)),
434 OXNAS_PINCTRL_GROUP(16, gpio16,
435 OXNAS_PINCTRL_FUNCTION(gpio, 0),
436 OXNAS_PINCTRL_FUNCTION(fct1, 1)),
437 OXNAS_PINCTRL_GROUP(17, gpio17,
438 OXNAS_PINCTRL_FUNCTION(gpio, 0),
439 OXNAS_PINCTRL_FUNCTION(fct1, 1)),
440 OXNAS_PINCTRL_GROUP(18, gpio18,
441 OXNAS_PINCTRL_FUNCTION(gpio, 0),
442 OXNAS_PINCTRL_FUNCTION(fct1, 1)),
443 OXNAS_PINCTRL_GROUP(19, gpio19,
444 OXNAS_PINCTRL_FUNCTION(gpio, 0),
445 OXNAS_PINCTRL_FUNCTION(fct1, 1)),
446 OXNAS_PINCTRL_GROUP(20, gpio20,
447 OXNAS_PINCTRL_FUNCTION(gpio, 0),
448 OXNAS_PINCTRL_FUNCTION(fct1, 1)),
449 OXNAS_PINCTRL_GROUP(21, gpio21,
450 OXNAS_PINCTRL_FUNCTION(gpio, 0),
451 OXNAS_PINCTRL_FUNCTION(fct1, 1)),
452 OXNAS_PINCTRL_GROUP(22, gpio22,
453 OXNAS_PINCTRL_FUNCTION(gpio, 0),
454 OXNAS_PINCTRL_FUNCTION(fct1, 1)),
455 OXNAS_PINCTRL_GROUP(23, gpio23,
456 OXNAS_PINCTRL_FUNCTION(gpio, 0),
457 OXNAS_PINCTRL_FUNCTION(fct1, 1)),
458 OXNAS_PINCTRL_GROUP(24, gpio24,
459 OXNAS_PINCTRL_FUNCTION(gpio, 0),
460 OXNAS_PINCTRL_FUNCTION(fct1, 1),
461 OXNAS_PINCTRL_FUNCTION(fct4, 5)),
462 OXNAS_PINCTRL_GROUP(25, gpio25,
463 OXNAS_PINCTRL_FUNCTION(gpio, 0),
464 OXNAS_PINCTRL_FUNCTION(fct4, 4)),
465 OXNAS_PINCTRL_GROUP(26, gpio26,
466 OXNAS_PINCTRL_FUNCTION(gpio, 0),
467 OXNAS_PINCTRL_FUNCTION(fct4, 4)),
468 OXNAS_PINCTRL_GROUP(27, gpio27,
469 OXNAS_PINCTRL_FUNCTION(gpio, 0),
470 OXNAS_PINCTRL_FUNCTION(fct4, 4)),
471 OXNAS_PINCTRL_GROUP(28, gpio28,
472 OXNAS_PINCTRL_FUNCTION(gpio, 0),
473 OXNAS_PINCTRL_FUNCTION(fct5, 5)),
474 OXNAS_PINCTRL_GROUP(29, gpio29,
475 OXNAS_PINCTRL_FUNCTION(gpio, 0),
476 OXNAS_PINCTRL_FUNCTION(fct5, 5)),
477 OXNAS_PINCTRL_GROUP(30, gpio30,
478 OXNAS_PINCTRL_FUNCTION(gpio, 0),
479 OXNAS_PINCTRL_FUNCTION(fct5, 5)),
480 OXNAS_PINCTRL_GROUP(31, gpio31,
481 OXNAS_PINCTRL_FUNCTION(gpio, 0),
482 OXNAS_PINCTRL_FUNCTION(fct5, 5)),
483 OXNAS_PINCTRL_GROUP(32, gpio32,
484 OXNAS_PINCTRL_FUNCTION(gpio, 0)),
485 OXNAS_PINCTRL_GROUP(33, gpio33,
486 OXNAS_PINCTRL_FUNCTION(gpio, 0)),
487 OXNAS_PINCTRL_GROUP(34, gpio34,
488 OXNAS_PINCTRL_FUNCTION(gpio, 0)),
489 OXNAS_PINCTRL_GROUP(35, gpio35,
490 OXNAS_PINCTRL_FUNCTION(gpio, 0)),
491 OXNAS_PINCTRL_GROUP(36, gpio36,
492 OXNAS_PINCTRL_FUNCTION(gpio, 0)),
493 OXNAS_PINCTRL_GROUP(37, gpio37,
494 OXNAS_PINCTRL_FUNCTION(gpio, 0)),
495 OXNAS_PINCTRL_GROUP(38, gpio38,
496 OXNAS_PINCTRL_FUNCTION(gpio, 0)),
497 OXNAS_PINCTRL_GROUP(39, gpio39,
498 OXNAS_PINCTRL_FUNCTION(gpio, 0)),
499 OXNAS_PINCTRL_GROUP(40, gpio40,
500 OXNAS_PINCTRL_FUNCTION(gpio, 0),
501 OXNAS_PINCTRL_FUNCTION(fct4, 4)),
502 OXNAS_PINCTRL_GROUP(41, gpio41,
503 OXNAS_PINCTRL_FUNCTION(gpio, 0),
504 OXNAS_PINCTRL_FUNCTION(fct4, 4)),
505 OXNAS_PINCTRL_GROUP(42, gpio42,
506 OXNAS_PINCTRL_FUNCTION(gpio, 0),
507 OXNAS_PINCTRL_FUNCTION(fct4, 4)),
508 OXNAS_PINCTRL_GROUP(43, gpio43,
509 OXNAS_PINCTRL_FUNCTION(gpio, 0),
510 OXNAS_PINCTRL_FUNCTION(fct4, 4)),
511 OXNAS_PINCTRL_GROUP(44, gpio44,
512 OXNAS_PINCTRL_FUNCTION(gpio, 0)),
513 OXNAS_PINCTRL_GROUP(45, gpio45,
514 OXNAS_PINCTRL_FUNCTION(gpio, 0)),
515 OXNAS_PINCTRL_GROUP(46, gpio46,
516 OXNAS_PINCTRL_FUNCTION(gpio, 0)),
517 OXNAS_PINCTRL_GROUP(47, gpio47,
518 OXNAS_PINCTRL_FUNCTION(gpio, 0)),
519 OXNAS_PINCTRL_GROUP(48, gpio48,
520 OXNAS_PINCTRL_FUNCTION(gpio, 0)),
521 OXNAS_PINCTRL_GROUP(49, gpio49,
522 OXNAS_PINCTRL_FUNCTION(gpio, 0)),
523};
524
611dac1e
NA		 525static inline struct oxnas_gpio_bank *pctl_to_bank(struct oxnas_pinctrl *pctl,
526 unsigned int pin)
527{
528 return &pctl->gpio_banks[pin / PINS_PER_BANK];
529}
530
531static int oxnas_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
532{
533 struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
534
535 return pctl->ngroups;
536}
537
538static const char *oxnas_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
539 unsigned int group)
540{
541 struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
542
543 return pctl->groups[group].name;
544}
545
546static int oxnas_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
547 unsigned int group,
548 const unsigned int **pins,
549 unsigned int *num_pins)
550{
551 struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
552
553 *pins = &pctl->groups[group].pin;
554 *num_pins = 1;
555
556 return 0;
557}
558
559static const struct pinctrl_ops oxnas_pinctrl_ops = {
560 .get_groups_count = oxnas_pinctrl_get_groups_count,
561 .get_group_name = oxnas_pinctrl_get_group_name,
562 .get_group_pins = oxnas_pinctrl_get_group_pins,
563 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
4d6ddd3b 564 .dt_free_map = pinctrl_utils_free_map,
611dac1e
NA		 565};
566
567static int oxnas_pinmux_get_functions_count(struct pinctrl_dev *pctldev)
568{
569 struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
570
571 return pctl->nfunctions;
572}
573
574static const char *
575oxnas_pinmux_get_function_name(struct pinctrl_dev *pctldev, unsigned int func)
576{
577 struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
578
579 return pctl->functions[func].name;
580}
581
582static int oxnas_pinmux_get_function_groups(struct pinctrl_dev *pctldev,
583 unsigned int func,
584 const char * const **groups,
585 unsigned int * const num_groups)
586{
587 struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
588
589 *groups = pctl->functions[func].groups;
590 *num_groups = pctl->functions[func].ngroups;
591
592 return 0;
593}
594
93f889b9
NA		 595static int oxnas_ox810se_pinmux_enable(struct pinctrl_dev *pctldev,
596 unsigned int func, unsigned int group)
611dac1e
NA		 597{
598 struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
599 const struct oxnas_pin_group *pg = &pctl->groups[group];
600 const struct oxnas_function *pf = &pctl->functions[func];
601 const char *fname = pf->name;
602 struct oxnas_desc_function *functions = pg->functions;
603 u32 mask = BIT(pg->pin);
604
605 while (functions->name) {
606 if (!strcmp(functions->name, fname)) {
607 dev_dbg(pctl->dev,
608 "setting function %s bank %d pin %d fct %d mask %x\n",
609 fname, pg->bank, pg->pin,
610 functions->fct, mask);
611
612 regmap_write_bits(pctl->regmap,
613 (pg->bank ?
93f889b9
NA		 614 PINMUX_810_PRIMARY_SEL1 :
615 PINMUX_810_PRIMARY_SEL0),
611dac1e
NA		 616 mask,
617 (functions->fct == 1 ?
618 mask : 0));
619 regmap_write_bits(pctl->regmap,
620 (pg->bank ?
93f889b9
NA		 621 PINMUX_810_SECONDARY_SEL1 :
622 PINMUX_810_SECONDARY_SEL0),
611dac1e
NA		 623 mask,
624 (functions->fct == 2 ?
625 mask : 0));
626 regmap_write_bits(pctl->regmap,
627 (pg->bank ?
93f889b9
NA		 628 PINMUX_810_TERTIARY_SEL1 :
629 PINMUX_810_TERTIARY_SEL0),
611dac1e
NA		 630 mask,
631 (functions->fct == 3 ?
632 mask : 0));
633
634 return 0;
635 }
636
637 functions++;
638 }
639
640 dev_err(pctl->dev, "cannot mux pin %u to function %u\n", group, func);
641
642 return -EINVAL;
643}
644
4b0c0c25
NA		 645static int oxnas_ox820_pinmux_enable(struct pinctrl_dev *pctldev,
646 unsigned int func, unsigned int group)
647{
648 struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
649 const struct oxnas_pin_group *pg = &pctl->groups[group];
650 const struct oxnas_function *pf = &pctl->functions[func];
651 const char *fname = pf->name;
652 struct oxnas_desc_function *functions = pg->functions;
653 unsigned int offset = (pg->bank ? PINMUX_820_BANK_OFFSET : 0);
654 u32 mask = BIT(pg->pin);
655
656 while (functions->name) {
657 if (!strcmp(functions->name, fname)) {
658 dev_dbg(pctl->dev,
659 "setting function %s bank %d pin %d fct %d mask %x\n",
660 fname, pg->bank, pg->pin,
661 functions->fct, mask);
662
663 regmap_write_bits(pctl->regmap,
664 offset + PINMUX_820_SECONDARY_SEL,
665 mask,
666 (functions->fct == 1 ?
667 mask : 0));
668 regmap_write_bits(pctl->regmap,
669 offset + PINMUX_820_TERTIARY_SEL,
670 mask,
671 (functions->fct == 2 ?
672 mask : 0));
673 regmap_write_bits(pctl->regmap,
674 offset + PINMUX_820_QUATERNARY_SEL,
675 mask,
676 (functions->fct == 3 ?
677 mask : 0));
678 regmap_write_bits(pctl->regmap,
679 offset + PINMUX_820_DEBUG_SEL,
680 mask,
681 (functions->fct == 4 ?
682 mask : 0));
683 regmap_write_bits(pctl->regmap,
684 offset + PINMUX_820_ALTERNATIVE_SEL,
685 mask,
686 (functions->fct == 5 ?
687 mask : 0));
688
689 return 0;
690 }
691
692 functions++;
693 }
694
695 dev_err(pctl->dev, "cannot mux pin %u to function %u\n", group, func);
696
697 return -EINVAL;
698}
699
93f889b9
NA		 700static int oxnas_ox810se_gpio_request_enable(struct pinctrl_dev *pctldev,
701 struct pinctrl_gpio_range *range,
702 unsigned int offset)
611dac1e
NA		 703{
704 struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
705 struct oxnas_gpio_bank *bank = gpiochip_get_data(range->gc);
706 u32 mask = BIT(offset - bank->gpio_chip.base);
707
708 dev_dbg(pctl->dev, "requesting gpio %d in bank %d (id %d) with mask 0x%x\n",
709 offset, bank->gpio_chip.base, bank->id, mask);
710
711 regmap_write_bits(pctl->regmap,
712 (bank->id ?
93f889b9
NA		 713 PINMUX_810_PRIMARY_SEL1 :
714 PINMUX_810_PRIMARY_SEL0),
611dac1e
NA		 715 mask, 0);
716 regmap_write_bits(pctl->regmap,
717 (bank->id ?
93f889b9
NA		 718 PINMUX_810_SECONDARY_SEL1 :
719 PINMUX_810_SECONDARY_SEL0),
611dac1e
NA		 720 mask, 0);
721 regmap_write_bits(pctl->regmap,
722 (bank->id ?
93f889b9
NA		 723 PINMUX_810_TERTIARY_SEL1 :
724 PINMUX_810_TERTIARY_SEL0),
611dac1e
NA		 725 mask, 0);
726
727 return 0;
728}
729
4b0c0c25
NA		 730static int oxnas_ox820_gpio_request_enable(struct pinctrl_dev *pctldev,
731 struct pinctrl_gpio_range *range,
732 unsigned int offset)
733{
734 struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
735 struct oxnas_gpio_bank *bank = gpiochip_get_data(range->gc);
736 unsigned int bank_offset = (bank->id ? PINMUX_820_BANK_OFFSET : 0);
737 u32 mask = BIT(offset - bank->gpio_chip.base);
738
739 dev_dbg(pctl->dev, "requesting gpio %d in bank %d (id %d) with mask 0x%x\n",
740 offset, bank->gpio_chip.base, bank->id, mask);
741
742 regmap_write_bits(pctl->regmap,
743 bank_offset + PINMUX_820_SECONDARY_SEL,
744 mask, 0);
745 regmap_write_bits(pctl->regmap,
746 bank_offset + PINMUX_820_TERTIARY_SEL,
747 mask, 0);
748 regmap_write_bits(pctl->regmap,
749 bank_offset + PINMUX_820_QUATERNARY_SEL,
750 mask, 0);
751 regmap_write_bits(pctl->regmap,
752 bank_offset + PINMUX_820_DEBUG_SEL,
753 mask, 0);
754 regmap_write_bits(pctl->regmap,
755 bank_offset + PINMUX_820_ALTERNATIVE_SEL,
756 mask, 0);
757
758 return 0;
759}
760
2f94ced7
NA		 761static int oxnas_gpio_get_direction(struct gpio_chip *chip,
762 unsigned int offset)
763{
764 struct oxnas_gpio_bank *bank = gpiochip_get_data(chip);
765 u32 mask = BIT(offset);
766
767 return !(readl_relaxed(bank->reg_base + OUTPUT_EN) & mask);
768}
769
611dac1e
NA		 770static int oxnas_gpio_direction_input(struct gpio_chip *chip,
771 unsigned int offset)
772{
773 struct oxnas_gpio_bank *bank = gpiochip_get_data(chip);
774 u32 mask = BIT(offset);
775
776 writel_relaxed(mask, bank->reg_base + OUTPUT_EN_CLEAR);
777
778 return 0;
779}
780
781static int oxnas_gpio_get(struct gpio_chip *chip, unsigned int offset)
782{
783 struct oxnas_gpio_bank *bank = gpiochip_get_data(chip);
784 u32 mask = BIT(offset);
785
786 return (readl_relaxed(bank->reg_base + INPUT_VALUE) & mask) != 0;
787}
788
789static void oxnas_gpio_set(struct gpio_chip *chip, unsigned int offset,
790 int value)
791{
792 struct oxnas_gpio_bank *bank = gpiochip_get_data(chip);
793 u32 mask = BIT(offset);
794
795 if (value)
796 writel_relaxed(mask, bank->reg_base + OUTPUT_SET);
797 else
798 writel_relaxed(mask, bank->reg_base + OUTPUT_CLEAR);
799}
800
801static int oxnas_gpio_direction_output(struct gpio_chip *chip,
802 unsigned int offset, int value)
803{
804 struct oxnas_gpio_bank *bank = gpiochip_get_data(chip);
805 u32 mask = BIT(offset);
806
807 oxnas_gpio_set(chip, offset, value);
808 writel_relaxed(mask, bank->reg_base + OUTPUT_EN_SET);
809
810 return 0;
811}
812
813static int oxnas_gpio_set_direction(struct pinctrl_dev *pctldev,
814 struct pinctrl_gpio_range *range,
815 unsigned int offset, bool input)
816{
817 struct gpio_chip *chip = range->gc;
818
819 if (input)
820 oxnas_gpio_direction_input(chip, offset);
821 else
822 oxnas_gpio_direction_output(chip, offset, 0);
823
824 return 0;
825}
826
93f889b9 827static const struct pinmux_ops oxnas_ox810se_pinmux_ops = {
611dac1e
NA		 828 .get_functions_count = oxnas_pinmux_get_functions_count,
829 .get_function_name = oxnas_pinmux_get_function_name,
830 .get_function_groups = oxnas_pinmux_get_function_groups,
93f889b9
NA		 831 .set_mux = oxnas_ox810se_pinmux_enable,
832 .gpio_request_enable = oxnas_ox810se_gpio_request_enable,
611dac1e
NA		 833 .gpio_set_direction = oxnas_gpio_set_direction,
834};
835
4b0c0c25
NA		 836static const struct pinmux_ops oxnas_ox820_pinmux_ops = {
837 .get_functions_count = oxnas_pinmux_get_functions_count,
838 .get_function_name = oxnas_pinmux_get_function_name,
839 .get_function_groups = oxnas_pinmux_get_function_groups,
840 .set_mux = oxnas_ox820_pinmux_enable,
841 .gpio_request_enable = oxnas_ox820_gpio_request_enable,
842 .gpio_set_direction = oxnas_gpio_set_direction,
843};
844
93f889b9
NA		 845static int oxnas_ox810se_pinconf_get(struct pinctrl_dev *pctldev,
846 unsigned int pin, unsigned long *config)
611dac1e
NA		 847{
848 struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
849 struct oxnas_gpio_bank *bank = pctl_to_bank(pctl, pin);
850 unsigned int param = pinconf_to_config_param(*config);
851 u32 mask = BIT(pin - bank->gpio_chip.base);
852 int ret;
853 u32 arg;
854
855 switch (param) {
856 case PIN_CONFIG_BIAS_PULL_UP:
857 ret = regmap_read(pctl->regmap,
858 (bank->id ?
93f889b9
NA		 859 PINMUX_810_PULLUP_CTRL1 :
860 PINMUX_810_PULLUP_CTRL0),
611dac1e
NA		 861 &arg);
862 if (ret)
863 return ret;
864
865 arg = !!(arg & mask);
866 break;
867 default:
868 return -ENOTSUPP;
869 }
870
871 *config = pinconf_to_config_packed(param, arg);
872
873 return 0;
874}
875
4b0c0c25
NA		 876static int oxnas_ox820_pinconf_get(struct pinctrl_dev *pctldev,
877 unsigned int pin, unsigned long *config)
878{
879 struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
880 struct oxnas_gpio_bank *bank = pctl_to_bank(pctl, pin);
881 unsigned int param = pinconf_to_config_param(*config);
882 unsigned int bank_offset = (bank->id ? PINMUX_820_BANK_OFFSET : 0);
883 u32 mask = BIT(pin - bank->gpio_chip.base);
884 int ret;
885 u32 arg;
886
887 switch (param) {
888 case PIN_CONFIG_BIAS_PULL_UP:
889 ret = regmap_read(pctl->regmap,
890 bank_offset + PINMUX_820_PULLUP_CTRL,
891 &arg);
892 if (ret)
893 return ret;
894
895 arg = !!(arg & mask);
896 break;
897 default:
898 return -ENOTSUPP;
899 }
900
901 *config = pinconf_to_config_packed(param, arg);
902
903 return 0;
904}
905
93f889b9
NA		 906static int oxnas_ox810se_pinconf_set(struct pinctrl_dev *pctldev,
907 unsigned int pin, unsigned long *configs,
908 unsigned int num_configs)
611dac1e
NA		 909{
910 struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
911 struct oxnas_gpio_bank *bank = pctl_to_bank(pctl, pin);
912 unsigned int param;
913 u32 arg;
914 unsigned int i;
915 u32 offset = pin - bank->gpio_chip.base;
916 u32 mask = BIT(offset);
917
918 dev_dbg(pctl->dev, "setting pin %d bank %d mask 0x%x\n",
919 pin, bank->gpio_chip.base, mask);
920
921 for (i = 0; i < num_configs; i++) {
922 param = pinconf_to_config_param(configs[i]);
923 arg = pinconf_to_config_argument(configs[i]);
924
925 switch (param) {
926 case PIN_CONFIG_BIAS_PULL_UP:
927 dev_dbg(pctl->dev, " pullup\n");
928 regmap_write_bits(pctl->regmap,
929 (bank->id ?
93f889b9
NA		 930 PINMUX_810_PULLUP_CTRL1 :
931 PINMUX_810_PULLUP_CTRL0),
611dac1e
NA		 932 mask, mask);
933 break;
934 default:
935 dev_err(pctl->dev, "Property %u not supported\n",
936 param);
937 return -ENOTSUPP;
938 }
939 }
940
941 return 0;
942}
943
4b0c0c25
NA		 944static int oxnas_ox820_pinconf_set(struct pinctrl_dev *pctldev,
945 unsigned int pin, unsigned long *configs,
946 unsigned int num_configs)
947{
948 struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
949 struct oxnas_gpio_bank *bank = pctl_to_bank(pctl, pin);
950 unsigned int bank_offset = (bank->id ? PINMUX_820_BANK_OFFSET : 0);
951 unsigned int param;
952 u32 arg;
953 unsigned int i;
954 u32 offset = pin - bank->gpio_chip.base;
955 u32 mask = BIT(offset);
956
957 dev_dbg(pctl->dev, "setting pin %d bank %d mask 0x%x\n",
958 pin, bank->gpio_chip.base, mask);
959
960 for (i = 0; i < num_configs; i++) {
961 param = pinconf_to_config_param(configs[i]);
962 arg = pinconf_to_config_argument(configs[i]);
963
964 switch (param) {
965 case PIN_CONFIG_BIAS_PULL_UP:
966 dev_dbg(pctl->dev, " pullup\n");
967 regmap_write_bits(pctl->regmap,
968 bank_offset + PINMUX_820_PULLUP_CTRL,
969 mask, mask);
970 break;
971 default:
972 dev_err(pctl->dev, "Property %u not supported\n",
973 param);
974 return -ENOTSUPP;
975 }
976 }
977
978 return 0;
979}
980
93f889b9
NA		 981static const struct pinconf_ops oxnas_ox810se_pinconf_ops = {
982 .pin_config_get = oxnas_ox810se_pinconf_get,
983 .pin_config_set = oxnas_ox810se_pinconf_set,
611dac1e
NA		 984 .is_generic = true,
985};
986
4b0c0c25
NA		 987static const struct pinconf_ops oxnas_ox820_pinconf_ops = {
988 .pin_config_get = oxnas_ox820_pinconf_get,
989 .pin_config_set = oxnas_ox820_pinconf_set,
990 .is_generic = true,
991};
992
611dac1e
NA		 993static void oxnas_gpio_irq_ack(struct irq_data *data)
994{
995 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
996 struct oxnas_gpio_bank *bank = gpiochip_get_data(chip);
997 u32 mask = BIT(data->hwirq);
998
999 writel(mask, bank->reg_base + IRQ_PENDING);
1000}
1001
1002static void oxnas_gpio_irq_mask(struct irq_data *data)
1003{
1004 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
1005 struct oxnas_gpio_bank *bank = gpiochip_get_data(chip);
1006 unsigned int type = irqd_get_trigger_type(data);
1007 u32 mask = BIT(data->hwirq);
1008
1009 if (type & IRQ_TYPE_EDGE_RISING)
1010 writel(readl(bank->reg_base + RE_IRQ_ENABLE) & ~mask,
1011 bank->reg_base + RE_IRQ_ENABLE);
1012
1013 if (type & IRQ_TYPE_EDGE_FALLING)
1014 writel(readl(bank->reg_base + FE_IRQ_ENABLE) & ~mask,
1015 bank->reg_base + FE_IRQ_ENABLE);
1016}
1017
1018static void oxnas_gpio_irq_unmask(struct irq_data *data)
1019{
1020 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
1021 struct oxnas_gpio_bank *bank = gpiochip_get_data(chip);
1022 unsigned int type = irqd_get_trigger_type(data);
1023 u32 mask = BIT(data->hwirq);
1024
1025 if (type & IRQ_TYPE_EDGE_RISING)
1026 writel(readl(bank->reg_base + RE_IRQ_ENABLE) | mask,
1027 bank->reg_base + RE_IRQ_ENABLE);
1028
1029 if (type & IRQ_TYPE_EDGE_FALLING)
1030 writel(readl(bank->reg_base + FE_IRQ_ENABLE) | mask,
1031 bank->reg_base + FE_IRQ_ENABLE);
1032}
1033
1034static unsigned int oxnas_gpio_irq_startup(struct irq_data *data)
1035{
1036 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
1037
1038 oxnas_gpio_direction_input(chip, data->hwirq);
1039 oxnas_gpio_irq_unmask(data);
1040
1041 return 0;
1042}
1043
1044static int oxnas_gpio_irq_set_type(struct irq_data *data, unsigned int type)
1045{
1046 if ((type & (IRQ_TYPE_EDGE_RISING|IRQ_TYPE_EDGE_FALLING)) == 0)
1047 return -EINVAL;
1048
1049 irq_set_handler_locked(data, handle_edge_irq);
1050
1051 return 0;
1052}
1053
1054static void oxnas_gpio_irq_handler(struct irq_desc *desc)
1055{
1056 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
1057 struct oxnas_gpio_bank *bank = gpiochip_get_data(gc);
1058 struct irq_chip *chip = irq_desc_get_chip(desc);
1059 unsigned long stat;
1060 unsigned int pin;
1061
1062 chained_irq_enter(chip, desc);
1063
1064 stat = readl(bank->reg_base + IRQ_PENDING);
1065
1066 for_each_set_bit(pin, &stat, BITS_PER_LONG)
1067 generic_handle_irq(irq_linear_revmap(gc->irqdomain, pin));
1068
1069 chained_irq_exit(chip, desc);
1070}
1071
1072#define GPIO_BANK(_bank) \
1073 { \
1074 .gpio_chip = { \
1075 .label = "GPIO" #_bank, \
1076 .request = gpiochip_generic_request, \
1077 .free = gpiochip_generic_free, \
2f94ced7 1078 .get_direction = oxnas_gpio_get_direction, \
611dac1e
NA		 1079 .direction_input = oxnas_gpio_direction_input, \
1080 .direction_output = oxnas_gpio_direction_output, \
1081 .get = oxnas_gpio_get, \
1082 .set = oxnas_gpio_set, \
1083 .ngpio = PINS_PER_BANK, \
1084 .base = GPIO_BANK_START(_bank), \
1085 .owner = THIS_MODULE, \
1086 .can_sleep = 0, \
1087 }, \
1088 .irq_chip = { \
1089 .name = "GPIO" #_bank, \
1090 .irq_startup = oxnas_gpio_irq_startup, \
1091 .irq_ack = oxnas_gpio_irq_ack, \
1092 .irq_mask = oxnas_gpio_irq_mask, \
1093 .irq_unmask = oxnas_gpio_irq_unmask, \
1094 .irq_set_type = oxnas_gpio_irq_set_type, \
1095 }, \
1096 }
1097
1098static struct oxnas_gpio_bank oxnas_gpio_banks[] = {
1099 GPIO_BANK(0),
1100 GPIO_BANK(1),
1101};
1102
93f889b9
NA		 1103static struct oxnas_pinctrl ox810se_pinctrl = {
1104 .functions = oxnas_ox810se_functions,
1105 .nfunctions = ARRAY_SIZE(oxnas_ox810se_functions),
1106 .groups = oxnas_ox810se_groups,
1107 .ngroups = ARRAY_SIZE(oxnas_ox810se_groups),
1108 .gpio_banks = oxnas_gpio_banks,
1109 .nbanks = ARRAY_SIZE(oxnas_gpio_banks),
1110};
1111
1112static struct pinctrl_desc oxnas_ox810se_pinctrl_desc = {
1113 .name = "oxnas-pinctrl",
1114 .pins = oxnas_ox810se_pins,
1115 .npins = ARRAY_SIZE(oxnas_ox810se_pins),
1116 .pctlops = &oxnas_pinctrl_ops,
1117 .pmxops = &oxnas_ox810se_pinmux_ops,
1118 .confops = &oxnas_ox810se_pinconf_ops,
1119 .owner = THIS_MODULE,
1120};
1121
4b0c0c25
NA		 1122static struct oxnas_pinctrl ox820_pinctrl = {
1123 .functions = oxnas_ox820_functions,
1124 .nfunctions = ARRAY_SIZE(oxnas_ox820_functions),
1125 .groups = oxnas_ox820_groups,
1126 .ngroups = ARRAY_SIZE(oxnas_ox820_groups),
1127 .gpio_banks = oxnas_gpio_banks,
1128 .nbanks = ARRAY_SIZE(oxnas_gpio_banks),
1129};
1130
1131static struct pinctrl_desc oxnas_ox820_pinctrl_desc = {
1132 .name = "oxnas-pinctrl",
1133 .pins = oxnas_ox820_pins,
1134 .npins = ARRAY_SIZE(oxnas_ox820_pins),
1135 .pctlops = &oxnas_pinctrl_ops,
1136 .pmxops = &oxnas_ox820_pinmux_ops,
1137 .confops = &oxnas_ox820_pinconf_ops,
1138 .owner = THIS_MODULE,
1139};
1140
93f889b9
NA		 1141static struct oxnas_pinctrl_data oxnas_ox810se_pinctrl_data = {
1142 .desc = &oxnas_ox810se_pinctrl_desc,
1143 .pctl = &ox810se_pinctrl,
1144};
1145
4b0c0c25
NA		 1146static struct oxnas_pinctrl_data oxnas_ox820_pinctrl_data = {
1147 .desc = &oxnas_ox820_pinctrl_desc,
1148 .pctl = &ox820_pinctrl,
1149};
1150
93f889b9
NA		 1151static const struct of_device_id oxnas_pinctrl_of_match[] = {
1152 { .compatible = "oxsemi,ox810se-pinctrl",
1153 .data = &oxnas_ox810se_pinctrl_data
1154 },
4b0c0c25
NA		 1155 { .compatible = "oxsemi,ox820-pinctrl",
1156 .data = &oxnas_ox820_pinctrl_data,
1157 },
93f889b9
NA		 1158 { },
1159};
1160
611dac1e
NA		 1161static int oxnas_pinctrl_probe(struct platform_device *pdev)
1162{
93f889b9
NA		 1163 const struct of_device_id *id;
1164 const struct oxnas_pinctrl_data *data;
611dac1e
NA		 1165 struct oxnas_pinctrl *pctl;
1166
93f889b9
NA		 1167 id = of_match_node(oxnas_pinctrl_of_match, pdev->dev.of_node);
1168 if (!id)
1169 return -ENODEV;
1170
1171 data = id->data;
1172 if (!data || !data->pctl || !data->desc)
1173 return -EINVAL;
1174
611dac1e
NA		 1175 pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
1176 if (!pctl)
1177 return -ENOMEM;
1178 pctl->dev = &pdev->dev;
1179 dev_set_drvdata(&pdev->dev, pctl);
1180
1181 pctl->regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
1182 "oxsemi,sys-ctrl");
1183 if (IS_ERR(pctl->regmap)) {
1184 dev_err(&pdev->dev, "failed to get sys ctrl regmap\n");
1185 return -ENODEV;
1186 }
1187
93f889b9
NA		 1188 pctl->functions = data->pctl->functions;
1189 pctl->nfunctions = data->pctl->nfunctions;
1190 pctl->groups = data->pctl->groups;
1191 pctl->ngroups = data->pctl->ngroups;
1192 pctl->gpio_banks = data->pctl->gpio_banks;
1193 pctl->nbanks = data->pctl->nbanks;
611dac1e 1194
93f889b9 1195 pctl->pctldev = pinctrl_register(data->desc, &pdev->dev, pctl);
611dac1e
NA		 1196 if (IS_ERR(pctl->pctldev)) {
1197 dev_err(&pdev->dev, "Failed to register pinctrl device\n");
1198 return PTR_ERR(pctl->pctldev);
1199 }
1200
1201 return 0;
1202}
1203
1204static int oxnas_gpio_probe(struct platform_device *pdev)
1205{
1206 struct device_node *np = pdev->dev.of_node;
1207 struct of_phandle_args pinspec;
1208 struct oxnas_gpio_bank *bank;
1209 unsigned int id, ngpios;
1210 int irq, ret;
1211 struct resource *res;
1212
1213 if (of_parse_phandle_with_fixed_args(np, "gpio-ranges",
1214 3, 0, &pinspec)) {
1215 dev_err(&pdev->dev, "gpio-ranges property not found\n");
1216 return -EINVAL;
1217 }
1218
1219 id = pinspec.args[1] / PINS_PER_BANK;
1220 ngpios = pinspec.args[2];
1221
1222 if (id >= ARRAY_SIZE(oxnas_gpio_banks)) {
1223 dev_err(&pdev->dev, "invalid gpio-ranges base arg\n");
1224 return -EINVAL;
1225 }
1226
1227 if (ngpios > PINS_PER_BANK) {
1228 dev_err(&pdev->dev, "invalid gpio-ranges count arg\n");
1229 return -EINVAL;
1230 }
1231
1232 bank = &oxnas_gpio_banks[id];
1233
1234 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1235 bank->reg_base = devm_ioremap_resource(&pdev->dev, res);
1236 if (IS_ERR(bank->reg_base))
1237 return PTR_ERR(bank->reg_base);
1238
1239 irq = platform_get_irq(pdev, 0);
1240 if (irq < 0) {
1241 dev_err(&pdev->dev, "irq get failed\n");
1242 return irq;
1243 }
1244
1245 bank->id = id;
1246 bank->gpio_chip.parent = &pdev->dev;
1247 bank->gpio_chip.of_node = np;
1248 bank->gpio_chip.ngpio = ngpios;
1249 ret = gpiochip_add_data(&bank->gpio_chip, bank);
1250 if (ret < 0) {
1251 dev_err(&pdev->dev, "Failed to add GPIO chip %u: %d\n",
1252 id, ret);
1253 return ret;
1254 }
1255
1256 ret = gpiochip_irqchip_add(&bank->gpio_chip, &bank->irq_chip,
1257 0, handle_level_irq, IRQ_TYPE_NONE);
1258 if (ret < 0) {
1259 dev_err(&pdev->dev, "Failed to add IRQ chip %u: %d\n",
1260 id, ret);
1261 gpiochip_remove(&bank->gpio_chip);
1262 return ret;
1263 }
1264
1265 gpiochip_set_chained_irqchip(&bank->gpio_chip, &bank->irq_chip,
1266 irq, oxnas_gpio_irq_handler);
1267
1268 return 0;
1269}
1270
611dac1e
NA		 1271static struct platform_driver oxnas_pinctrl_driver = {
1272 .driver = {
1273 .name = "oxnas-pinctrl",
1274 .of_match_table = oxnas_pinctrl_of_match,
1275 .suppress_bind_attrs = true,
1276 },
1277 .probe = oxnas_pinctrl_probe,
1278};
1279
1280static const struct of_device_id oxnas_gpio_of_match[] = {
1281 { .compatible = "oxsemi,ox810se-gpio", },
4b0c0c25 1282 { .compatible = "oxsemi,ox820-gpio", },
611dac1e
NA		 1283 { },
1284};
1285
1286static struct platform_driver oxnas_gpio_driver = {
1287 .driver = {
1288 .name = "oxnas-gpio",
1289 .of_match_table = oxnas_gpio_of_match,
1290 .suppress_bind_attrs = true,
1291 },
1292 .probe = oxnas_gpio_probe,
1293};
1294
1295static int __init oxnas_gpio_register(void)
1296{
1297 return platform_driver_register(&oxnas_gpio_driver);
1298}
1299arch_initcall(oxnas_gpio_register);
1300
1301static int __init oxnas_pinctrl_register(void)
1302{
1303 return platform_driver_register(&oxnas_pinctrl_driver);
1304}
1305arch_initcall(oxnas_pinctrl_register);
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